Semiconductor structure and preparation method thereof
By placing the core circuitry on a high-level wiring layer and employing optimized wiring design in the semiconductor structure, the problem of poor interconnect reliability in exposure field splicing was solved, thereby improving the reliability and performance of the chip.
Patent Information
- Application Number
- CN202511906666.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-06
AI Technical Summary
Currently, chips stitched together in multiple exposure fields face high challenges in aligning precision, resulting in poor reliability of the interconnect structure and impacting chip quality and performance.
In semiconductor structures, core circuits are placed on higher wiring layers, and measures such as axial routing, increasing the width of metal lines in splicing areas, filling virtual metal structures, setting parallel backup lines and redundant vias are adopted to optimize the wiring layer design and improve interconnect reliability.
By reducing high-frequency signal transmission impairments and long-distance interconnect reliability issues, the overall reliability and performance of the chip are improved, while the cumulative errors and complexity in the manufacturing process are reduced.
Smart Images
Figure CN121620198A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronics technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of technology, in order to achieve better performance and meet more demands, the size of chips is getting larger and larger. Large-size chips are often fabricated using a process of layered exposure stitching.
[0003] Currently, the cutting-edge process technology of multi-exposure field stitching still faces key technical bottlenecks. The core technical challenges mainly lie in the difficulty of controlling the alignment accuracy of multiple exposure fields, which leads to poor reliability of the interconnect structure. Therefore, chips fabricated using multi-exposure field stitching urgently need improved interconnect reliability to ensure chip quality and performance. Summary of the Invention
[0004] In view of the above problems, the present invention is proposed to provide a semiconductor structure and a method for preparing the same that overcomes or at least partially solves the above problems.
[0005] In a first aspect, a semiconductor structure is provided, comprising: An active layer and a multilayer wiring layer located on the active layer; The multi-layer wiring layer includes a bottom wiring layer and a top wiring layer stacked together, with the bottom wiring layer located between the top wiring layer and the active layer. The core circuitry of the semiconductor structure is disposed on the higher layer wiring layer; wherein, the core circuitry includes lines for transmitting high-frequency signals and / or long-distance lines spanning different exposure fields during the fabrication of the wiring layer and whose length meets preset requirements.
[0006] Optionally, the wiring direction of the wiring layer is axial wiring, which is a direction perpendicular to or parallel to the coordinate axis of the exposure field; the wiring line type of the wiring layer includes any one or more combinations of the following: straight, serpentine, toothed, and wavy; for metal lines transmitting the same signal specification, the width of the metal lines within the splicing area of the wiring layer is greater than the width of the metal lines outside the splicing area; the splicing area is the overlapping area and / or edge area of adjacent different exposure fields when the wiring layer is prepared; the area between the metal lines of the wiring layer is filled with a virtual metal structure, and the filling density of the virtual metal structure within the splicing area is greater than the filling density of the virtual metal structure outside the splicing area.
[0007] Optionally, the cross-field lines of the wiring layer are provided with corresponding parallel backup lines, and the cross-field lines are lines that cross different exposure fields when the wiring layer is prepared; the parallel backup lines are connected to the selection structure so as to control whether the parallel backup lines are activated.
[0008] Optionally, the semiconductor structure includes multiple partitions, each partition corresponding to a different exposure field during the fabrication of the semiconductor structure; the semiconductor structure includes multiple functional systems, with modules of the same functional system located in the same partition; the key module of each functional system is located in the central region of the corresponding partition, and the key module includes a core functional module, a high-frequency module, and a sensitive circuit module.
[0009] Optionally, the semiconductor structure includes local alignment marks and interlayer alignment marks; the local alignment marks are used to calibrate the position of each exposure field when fabricating the semiconductor structure; the interlayer alignment marks are used to align the upper and lower metal layers and the vias when fabricating the multilayer wiring layers.
[0010] Optionally, the semiconductor structure includes alignment test bonding and interconnect test bonding; the alignment test bonding is used to evaluate inter-layer alignment error and adjacent exposure field alignment error during the fabrication of the semiconductor structure; the interconnect test bonding is used to evaluate the interconnect status of metal lines and vias in the wiring layer during the fabrication of the semiconductor structure.
[0011] Secondly, a method for fabricating a semiconductor structure is provided, comprising: Provide wafers; An active layer is fabricated on the wafer; A multilayer wiring layer is fabricated on the active layer; wherein the multilayer wiring layer includes a stacked bottom wiring layer and a high-level wiring layer, the bottom wiring layer being located between the high-level wiring layer and the active layer; the core circuit of the semiconductor structure is disposed on the high-level wiring layer; wherein the core circuit includes lines for transmitting high-frequency signals and / or long-distance lines spanning different exposure fields during the fabrication of the wiring layer, the long-distance lines spanning different exposure fields and having a length that meets a preset requirement.
[0012] Optionally, the step of fabricating a multilayer wiring layer on the active layer includes: fabricating a multilayer wiring layer on the active layer, wherein, for metal lines transmitting the same signal specification, the width of the metal lines within the splicing area of the wiring layer is greater than the width of the metal lines outside the splicing area; the splicing area is the overlapping area and / or edge area of adjacent different exposure fields when fabricating the wiring layer; and filling the area between the metal lines of the wiring layer with virtual metal structures, wherein the filling density of the virtual metal structures within the splicing area is greater than the filling density of the virtual metal structures outside the splicing area.
[0013] Optionally, after providing the wafer, the method further includes: preparing global alignment marks, local alignment marks, and interlayer alignment marks; the preparation of multiple wiring layers on the active layer includes: calibrating the position of the wafer according to the global alignment marks; calibrating the position of each exposure field according to the local alignment marks; and aligning and preparing the upper and lower metal layers and vias of the interconnect layer according to the interlayer alignment marks.
[0014] Optionally, after fabricating multiple wiring layers on the active layer, the method further includes: detecting the connectivity of cross-field lines in the wiring layers, wherein the cross-field lines are lines that cross different exposure fields when fabricating the wiring layers; if the cross-field lines fail, then activating the parallel backup lines corresponding to the failed cross-field lines by selecting a structure.
[0015] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: The semiconductor structure and its fabrication method provided in this invention divide the wiring layer into a higher-level wiring layer and a lower-level wiring layer, and place the core lines (lines transmitting high-frequency signals and / or long-distance lines across fields) on the higher-level wiring layer. Since, in multi-layer wiring, for metal lines transmitting the same signal specifications, higher-level wiring layers (wiring layers further from the active area) often have wider metal linewidths and lower impedances, placing the core lines on higher-level wiring layers reduces high-frequency signal transmission impairment and instability by decreasing impedance. Furthermore, the higher linewidth and lower impedance reduce reliability issues related to long-distance interconnects across fields caused by alignment problems during exposure field splicing.
[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description
[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the semiconductor structure in an embodiment of the present invention; Figure 2 This is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0018] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0020] Please see Figure 1 , Figure 1 This is a schematic diagram of the semiconductor structure in an embodiment of this application. The semiconductor structure provided in this embodiment includes: an active layer 1 and a multilayer wiring layer 2 located on the active layer 1. The multilayer wiring layer 2 includes a stacked bottom wiring layer 21 and a top wiring layer 22, with the bottom wiring layer 21 located between the top wiring layer 22 and the active layer 1. The core circuit 3 of the semiconductor structure is disposed on the top wiring layer 22. The core circuit includes lines for transmitting high-frequency signals and / or long-distance lines spanning different exposure fields during the fabrication of the wiring layer, wherein the long-distance lines span different exposure fields and have a length that meets a preset requirement.
[0021] Specifically, the semiconductor structure of this application can be a chip or a wafer. Taking a large-size chip as an example, when fabricating using a process of stitching together different exposure fields, the reliability of interconnect connections and the process fault tolerance are poor because the alignment accuracy between each exposure field is difficult to avoid. Considering that the reliability and performance of a chip are often reflected in its core circuit 3, for example, the high-frequency signal transmission lines in the core circuit 3 have higher requirements for process fault tolerance and are more susceptible to the impact of interconnect reliability, and the long-distance lines across fields in the core circuit 3 are more easily affected by the stitching errors of the different exposure fields, ensuring the reliability and performance of the core circuit 3 can effectively ensure the reliability and performance of the semiconductor structure. Since in the wiring layer 2, the higher wiring layers 22 further away from the active layer 1 often have relatively wider metal line dimensions and relatively lower resistivity, placing the core circuit 3 in the higher wiring layer 22 can reduce the transmission damage and instability of high-frequency signals, reduce the reliability problems of long-distance interconnects across fields caused by the alignment problems of stitching together different exposure fields, and reduce the problem of large impedance changes in interconnects caused by the stitching errors of the exposure fields.
[0022] It should also be noted that the line for transmitting high-frequency signals can be a line for transmitting signals higher than the preset frequency, and the long-distance line across the field can be a line that is longer than the preset distance across the exposure field. The preset frequency and preset distance can be set by the R&D personnel based on experience or based on the simulation structure of the simulation software, and there are no restrictions here.
[0023] In an optional implementation, the core circuit 3 may also include circuits related to the core functions of the semiconductor structure, or other circuits with high requirements for process fault tolerance, without limitation.
[0024] In an optional implementation, the wiring direction in wiring layer 2 can also be set as axial wiring, which is perpendicular or parallel to the exposure field coordinate axis. Specifically, each exposure field has a preset alignment coordinate axis (which is often parallel or perpendicular to the edge of the exposure field). If the wiring is obliquely angled to the coordinate axis, it will cause wiring errors in both the X and Y directions of the coordinate axis, thus increasing the wiring error. Therefore, setting axial wiring can control the wiring error of each line in a single direction, reduce the sensitivity to multi-directional errors, and improve wiring reliability.
[0025] In optional implementations, the wiring pattern of wiring layer 2 may include any one or more combinations of the following: straight, serpentine, toothed, and wavy. By using zigzag and curved wiring patterns, the ductility of the lines can be effectively increased, enabling longer-distance wiring within limited dimensions. Combining this with the wiring direction of axial wiring can further increase ductility while maintaining low error.
[0026] In an optional implementation, for metal lines transmitting the same signal specifications, the width of the metal lines within the splicing area of wiring layer 2 can be set to be greater than the width of the metal lines outside the splicing area. The splicing area is the overlapping region and / or edge region of adjacent exposure fields during the fabrication of the wiring layer. That is, the photolithography process of each layer of the semiconductor structure requires exposure in multiple exposure fields spliced together. During the fabrication of the semiconductor structure, the overlapping region and / or edge region of adjacent exposure fields on each layer is the splicing area. The splicing area can be simply the overlapping region of adjacent exposure fields on the semiconductor structure, or it can include the edge region of each exposure field on the semiconductor structure with a preset size; there is no limitation here.
[0027] Specifically, when fabricating wiring layer 2 of large-size chips, multiple exposure fields are often spliced together due to the exceeding exposure size requirements. Between adjacent exposure fields, overlapping areas may exist due to alignment accuracy issues or setting rules. At the edges of each exposure field, optical diffraction and other effects can easily lead to exposure pattern distortion. Therefore, these overlapping areas and the edges of each exposure field are areas prone to interconnect reliability problems. Therefore, this application sets the width of the metal lines within the splicing area (including overlapping and / or edge areas) for metal lines transmitting the same signal specifications to be relatively larger than the width of the metal lines outside the splicing area. This compensates for the problem of interconnect contact misalignment and linewidth reduction caused by alignment errors and optical effects, improves the process tolerance of the interconnects in the splicing area, and ensures reliability.
[0028] In an optional embodiment, the areas between the metal lines of wiring layer 2 can be filled with virtual metal structures, with the filling density of the virtual metal structures within the splicing area being greater than that outside the splicing area. Specifically, since functional wiring is often not uniformly distributed across each wiring layer, the metal line density at the edge of the exposure field is often lower than that at the center. This uneven distribution of metal lines leads to inconsistent warping at different locations within each layer, resulting in an uneven surface and affecting the yield of subsequent mechanical polishing processes. Therefore, this application fills the blank areas between metal lines with virtual metal structures and balances the metal density differences from the center of each exposure field to the splicing area by setting a gradient in the filling density of the virtual metal structures, reducing defects caused by processes such as chemical mechanical polishing. The shape and size of the virtual metal structures can be set according to the specific shape and size of the wiring gaps and are not limited here.
[0029] In an optional implementation, parallel backup lines can be provided for the cross-field lines of wiring layer 2. Cross-field lines refer to lines that span different exposure fields during the fabrication of wiring layer 2. The parallel backup lines are connected to a selection structure to control whether the parallel backup lines are activated. Specifically, due to the splicing error of the exposure fields, long cross-field lines are more prone to interconnection reliability problems, such as short circuits or open circuits. Therefore, this application provides parallel backup lines for critical cross-field lines, and connects the parallel backup circuit to the selection structure so that the parallel backup circuit is normally inactive. When a cross-field line is determined to be faulty through electrical testing, the parallel backup line corresponding to the faulty line is activated by the selection structure, ensuring reliability through redundancy design. The selection structure can be an integrated fuse or a programmable switch, etc., and is not limited here.
[0030] Furthermore, redundant vias can be set for critical vias, and the risk of interlayer connection failure can be reduced through the design of redundant via arrays. Among them, critical vias can be vias related to critical functions, vias with weak process fault tolerance, or vias in the exposure field splicing area, without any restrictions.
[0031] Specifically, by combining the aforementioned parallel backup lines, redundant vias, virtual metal structures, increased width of metal lines in the splicing area, axial routing, and high-level routing of critical lines, it is possible to construct a highly fault-tolerant multi-exposure field interconnect structure, further enhance the error tolerance capability during the splicing process of each exposure field, ensure the electrical continuity and signal integrity of cross-field interconnects, and accelerate the industrialization process of large-size chips with multiple exposure fields.
[0032] In an optional implementation, the semiconductor structure can be configured to include multiple partitions, each corresponding one-to-one with a different exposure field during the fabrication of the semiconductor structure. The semiconductor structure includes multiple functional systems, with modules of the same functional system located within the same partition. The key modules of each functional system are located in the central region of their corresponding partition; these key modules include core functional modules, high-frequency modules, and sensitive circuit modules. Given the one-to-one correspondence between the fabricated partitions and the exposure fields during the fabrication process, the splicing area is located at the edge of each partition.
[0033] Specifically, to achieve rich functionality, semiconductor structures often include multiple functional systems, such as CPU core circuit systems, memory circuit systems, and sensor systems. The interaction frequency and interaction requirements within the same functional system are often the highest. Therefore, this application tries to place modules of the same functional system within the same partition to minimize interactions between different partitions, reduce signal transmission across exposure field regions, and thus further reduce the number of cross-field lines, minimizing the impact of exposure field alignment issues on the reliability of the semiconductor structure. In this way, by dividing the layout into functional systems, the complexity of stitching together each exposure field is reduced, directly improving the manufacturing yield of large chips.
[0034] Furthermore, to reduce the impact of alignment accuracy issues and optical diffraction distortion on the reliability of the semiconductor structure in the splicing area, this application can also position the key modules of each functional system in the central area of the corresponding partition. This can be achieved by placing densely wired sections and / or key transistor clusters in the central area of each exposure zone's corresponding partition, while placing relatively loose interconnect logic sections in the splicing area. Alternatively, core functional modules, high-frequency modules, and sensitive circuit modules can be placed in the central area of each exposure zone's corresponding partition, while relatively simple interconnect logic sections are placed in the splicing area. In this way, the impact of exposure zone alignment issues and optical diffraction problems on interconnect lines can be minimized, preventing impact on critical functions and ensuring the overall reliability of the semiconductor structure. Thus, by placing critical and sensitive circuits in the center of each exposure zone, the yield rate of core functions is ensured, and only simple circuit structures are placed in the splicing area, minimizing splicing reliability risks.
[0035] In an optional implementation, the semiconductor structure may also include local alignment marks and interlayer alignment marks. Local alignment marks are used to calibrate the position of each exposure field during semiconductor structure fabrication. Interlayer alignment marks are used for the alignment of upper and lower metal layers and vias during the fabrication of the multilayer wiring layer 2.
[0036] Specifically, during semiconductor structure fabrication, triple alignment marks can be used to reduce alignment errors in exposure field separation processes. At the wafer-level fabrication stage, global alignment marks, local alignment marks, and interlayer alignment marks are set. Global alignment marks can be master marks placed at the four corners of the wafer to calibrate the wafer's position and orientation, establishing a global coordinate system for the entire chip. Local alignment marks can be placed at the four corner edges of each exposure field to calibrate the stitching between exposure fields. Interlayer alignment marks are used for the alignment of upper and lower metal layers and vias; these marks can employ a nested cross structure to ensure accurate interlayer overlay alignment. Of course, the position and shape of these three alignment marks can be set as needed and are not limited here. By setting these triple alignment marks and constructing a multi-dimensional alignment deviation model based on them, multi-level deviation information can be used to optimize alignment accuracy during processing. Combined with the detected global, local, and interlayer alignment errors, automatic and precise exposure field alignment can be achieved. In this way, by constructing multi-level alignment marks and a multi-dimensional alignment deviation model, the cumulative error in the multi-exposure field splicing manufacturing process is suppressed, the alignment accuracy is improved, and the manufacturing efficiency and yield of large-size chips prepared by multi-exposure fields are optimized.
[0037] It should be noted that when the semiconductor structure of this application is a wafer, the global alignment mark, local alignment mark, and interlayer alignment mark can all be retained on the wafer. When the semiconductor structure of this application is a chip, the global alignment mark is no longer retained on the chip after chip dicing; only the local alignment mark and interlayer alignment mark can be retained on the chip.
[0038] In optional embodiments, the semiconductor structure may further include alignment test bonds and interconnect test bonds. Alignment test bonds are used to evaluate inter-layer alignment errors and adjacent exposure field alignment errors during semiconductor structure fabrication. Interconnect test bonds are used to evaluate the interconnect status of metal lines and vias in the wiring layers during semiconductor structure fabrication.
[0039] Specifically, alignment test keys are used to monitor and evaluate splicing alignment errors and interlayer alignment errors. Alignment test keys can be via structures used to test the alignment status between layers. If the alignment test key, which is a via structure between two layers, is conductive, the interlayer alignment can be considered to meet the requirements. Interconnect test keys are established by arranging a chain-like structure of vias and metal lines in series at the boundaries of the exposure fields. The quality of interconnect connections can be evaluated by testing the change in cross-boundary resistance using a probe. That is, interconnect test keys can be metal chain structures or via structures. The metal chain structure is used to measure whether the interconnection of a single layer meets the requirements, while the via structure is used to measure whether the interconnection between layers meets the requirements. By setting up the metal chain structure and via structure in series, the interconnection status between any layer and between any layers can be detected. Thus, the combination of alignment test bonding and interconnect test keys can verify the reliability of multi-exposure field interconnects, monitor and evaluate the alignment errors and interconnect reliability of large-size chips, and facilitate rapid diagnosis and yield analysis during large-size chip testing. Through the collection and feedback of detection data from alignment test bonding and interconnect test keys, relevant process models or parameters can be corrected, achieving closed-loop optimization for improving the yield of large-size chips.
[0040] In the embodiments of this application, any improvement schemes provided by the foregoing embodiments can be selected and combined as needed to achieve the effect of improving the reliability and performance of semiconductor structures, and no restrictions are imposed here.
[0041] Based on the same inventive concept, embodiments of this application also provide a method for fabricating a semiconductor structure, such as... Figure 2 As shown, it includes: Step S201: Provide a wafer; Step S202: An active layer is fabricated on the wafer; Step S203: A multilayer wiring layer is fabricated on the active layer; wherein the multilayer wiring layer includes a stacked bottom wiring layer and a high-level wiring layer, the bottom wiring layer being located between the high-level wiring layer and the active layer; the core circuit of the semiconductor structure is disposed on the high-level wiring layer; wherein the core circuit includes lines for transmitting high-frequency signals and / or long-distance lines across fields, the long-distance lines across fields being lines that cross different exposure fields during the fabrication of the wiring layer and whose length meets preset requirements.
[0042] In an optional embodiment, a multilayer wiring layer is fabricated on the active layer, comprising a combination of any one or more of the following steps: Multiple wiring layers are fabricated on the active layer, wherein, for metal lines transmitting the same signal specification, the width of the metal lines within the splicing area of the wiring layer is greater than the width of the metal lines outside the splicing area, and the splicing area is the overlapping area and / or edge area of adjacent different exposure fields when fabricating the wiring layer; Virtual metal structures are filled in the area between the metal lines of the wiring layer, wherein the filling density of the virtual metal structures within the splicing area is greater than the filling density of the virtual metal structures outside the splicing area.
[0043] In an optional embodiment, after providing the wafer, the method further includes: preparing global alignment marks, local alignment marks, and interlayer alignment marks; the preparation of multiple wiring layers on the active layer includes: calibrating the position of the wafer according to the global alignment marks; calibrating the position of each exposure field according to the local alignment marks; and aligning and preparing the upper and lower metal layers and vias of the interconnect layer according to the interlayer alignment marks.
[0044] In an optional implementation, after fabricating multiple wiring layers on the active layer, the method further includes: detecting the connectivity of cross-field lines in the wiring layers, wherein the cross-field lines are lines that cross different exposure fields when fabricating the wiring layers; if the cross-field lines fail, then activating the parallel backup lines corresponding to the failed cross-field lines by selecting a structure.
[0045] Since the semiconductor structure fabrication method described in the embodiments of this application is the same as the semiconductor structure fabrication method described in the foregoing embodiments of this application, and the principle and steps of this fabrication method have been described in detail above, they will not be repeated here. All fabrication methods used to prepare the semiconductor structures of the embodiments of this application fall within the scope of protection of this invention.
[0046] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: The semiconductor structure and its fabrication method provided in this invention divide the wiring layer into a higher-level wiring layer and a lower-level wiring layer, and place the core lines (lines transmitting high-frequency signals and / or long-distance lines across fields) on the higher-level wiring layer. Since, in multi-layer wiring, for metal lines transmitting the same signal specifications, higher-level wiring layers (wiring layers further from the active area) often have wider metal linewidths and lower impedances, placing the core lines on higher-level wiring layers reduces high-frequency signal transmission impairment and instability by decreasing impedance. Furthermore, the higher linewidth and lower impedance reduce reliability issues related to long-distance interconnects across fields caused by alignment problems during exposure field splicing.
[0047] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages is for the purpose of disclosing the best mode of implementation of the invention.
[0048] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0049] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof.
[0050] Those skilled in the art will understand that modules in the apparatus of the embodiments can be adaptively changed and placed in one or more apparatuses different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be employed to combine all features disclosed in this specification (including the abstract and drawings) and all processes or units of any method or apparatus so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying abstract and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0051] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention and form different embodiments.
[0052] It should be noted that the above embodiments are illustrative of the invention and not restrictive. Any reference signs placed between parentheses should not be construed as limiting the invention. The word "comprising" does not exclude the presence of components or steps not listed in the invention. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In embodiments listing several means, several of these means may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.
Claims
1. A semiconductor structure, characterized by, The semiconductor structure comprises: an active layer and a multi-layer wiring layer located on the active layer; the multi-layer wiring layer comprises a bottom wiring layer and a high wiring layer stacked, and the bottom wiring layer is located between the high wiring layer and the active layer; the core circuit of the semiconductor structure is arranged in the high wiring layer; wherein the core circuit comprises a line for transmitting high-frequency signals and / or a cross-field long-distance line, and the cross-field long-distance line is a line that crosses different exposure fields when the wiring layer is prepared and has a length that meets a preset requirement.
2. The semiconductor structure of claim 1, wherein: the wiring direction of the wiring layer is an axial wiring, and the axial wiring is a direction perpendicular or parallel to the coordinate axis of the exposure field; the wiring line type of the wiring layer comprises any one or a combination of the following: straight line, snake shape, tooth shape and wave shape; for metal wires transmitting the same signal specification, the width of the metal wire in the splicing area of the wiring layer is greater than the width of the metal wire outside the splicing area; the splicing area is an overlapping area and / or an edge area of adjacent different exposure fields when the wiring layer is prepared; the area between the metal wires of the wiring layer is filled with a virtual metal structure, and the filling density of the virtual metal structure in the splicing area is greater than the filling density of the virtual metal structure outside the splicing area.
3. The semiconductor structure of claim 1, wherein: the cross-field line of the wiring layer is provided with a corresponding parallel backup line, and the cross-field line is a line that crosses different exposure fields when the wiring layer is prepared; the parallel backup line is connected with a selection structure to control whether to activate the parallel backup line through the selection structure.
4. The semiconductor structure of claim 1, wherein: the semiconductor structure comprises a plurality of partitions, and the plurality of partitions correspond one-to-one to a plurality of exposure fields when the semiconductor structure is prepared; the semiconductor structure comprises a plurality of functional systems, and the modules of the same functional system are arranged in the same partition; the key modules of each functional system are arranged in the center area of the corresponding partition, and the key modules include core functional modules, high-frequency modules and sensitive circuit modules.
5. The semiconductor structure of claim 1, wherein: it comprises local alignment marks and interlayer alignment marks; the local alignment marks are used to calibrate the position of each exposure field when the semiconductor structure is prepared; and the interlayer alignment marks are used to align the upper and lower metal layers and align the through holes when the multi-layer wiring layer is prepared.
6. The semiconductor structure of claim 1, wherein: it comprises alignment test keys and interconnection test keys; the alignment test keys are used to evaluate the interlayer alignment error and the alignment error of adjacent exposure fields when the semiconductor structure is prepared; and the interconnection test keys are used to evaluate the metal wire and through hole interconnection state of the wiring layer when the semiconductor structure is prepared.
7. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a wafer; preparing an active layer on the wafer; Preparation of a multilayer wiring layer on the active layer; wherein the multilayer wiring layer comprises a bottom wiring layer and a high wiring layer stacked, the bottom wiring layer is located between the high wiring layer and the active layer; the core circuit of the semiconductor structure is arranged in the high wiring layer; wherein the core circuit comprises a line for transmitting high-frequency signals and / or a cross-field long-distance line, the cross-field long-distance line is a line that crosses different exposure fields when the wiring layer is prepared and the length meets the preset requirements.
8. The method of producing a semiconductor structure according to claim 7, wherein The preparation of the multilayer wiring layer on the active layer comprises: Preparation of a multilayer wiring layer on the active layer, wherein for metal lines transmitting the same signal specification, the width of the metal lines in the splicing area of the wiring layer is greater than the width of the metal lines outside the splicing area; the splicing area is the overlapping area and / or the edge area of adjacent different exposure fields when the wiring layer is prepared; The area between the metal lines of the wiring layer is filled with a virtual metal structure, wherein the filling density of the virtual metal structure in the splicing area is greater than the filling density of the virtual metal structure outside the splicing area.
9. The preparation method of the semiconductor structure according to claim 7, wherein: After the wafer is provided, the method further comprises: preparation of global alignment marks, local alignment marks and interlayer alignment marks; The preparation of the multilayer wiring layer on the active layer comprises: aligning the position of the wafer according to the global alignment marks; aligning the position of each exposure field according to the local alignment marks; and aligning the upper and lower metal layers and the via of the interconnection layer according to the interlayer alignment marks.
10. The method of producing a semiconductor structure according to claim 7, wherein After the multilayer wiring layer is prepared on the active layer, the method further comprises: Detecting the communication state of the cross-field line of the wiring layer, the cross-field line being a line that crosses different exposure fields when the wiring layer is prepared; If the cross-field line fails, the parallel backup line corresponding to the failed cross-field line is activated through a selection structure.