Display panel and display device

Abstract

The embodiment of the invention provides a display panel which comprises a substrate, a pixel circuit, a pixel unit array and a color film layer, and the pixel circuit, the pixel unit array and the color film layer are sequentially stacked on one side of the substrate; each pixel unit comprises a first sub-pixel and a second sub-pixel, the aperture ratio of the first sub-pixel is larger than that of the second sub-pixel, the number of openings of the first sub-pixel is larger than that of openings of the second sub-pixel, and the number of pixel circuits used for driving the first sub-pixel is equal to that of pixel circuits used for driving the second sub-pixel; the color film layer comprises a first color resistor and a second color resistor, the orthographic projection of the first color resistor on the substrate covers the orthographic projection of the opening of the first sub-pixel on the substrate, and the orthographic projection of the second color resistor on the substrate covers the orthographic projection of the opening of the second sub-pixel on the substrate; the orthographic projection shapes of the first color resistor and the second color resistor on the substrate comprise shapes of which at least part of the edges are arc-shaped.

Description

Display panel and display device Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, brilliant colors, high contrast, and fast response rate. They have become the representative of the next generation of displays and are gradually replacing LCD (Liquid Crystal Display) screens.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display panel, comprising a substrate, a pixel circuit, a pixel unit array, and a color filter layer.

[0005] The pixel circuit, the pixel unit array and the color filter layer are stacked in sequence on one side of the substrate;

[0006] The pixel unit includes a first sub-pixel and a second sub-pixel, the aperture ratio of the first sub-pixel is greater than the aperture ratio of the second sub-pixel, the number of apertures of the first sub-pixel is greater than the number of apertures of the second sub-pixel, and the number of pixel circuits for driving the first sub-pixel is equal to the number of pixel circuits for driving the second sub-pixel;

[0007] The color filter layer includes a first color resist and a second color resist, wherein the orthographic projection of the first color resist on the substrate covers the orthographic projection of the opening of the first sub-pixel on the substrate, and the orthographic projection of the second color resist on the substrate covers the orthographic projection of the opening of the second sub-pixel on the substrate;

[0008] The orthographic projection shapes of the first color resist and the second color resist on the substrate include shapes with at least a portion of edges being arc-shaped.

[0009] In some embodiments, the pixel unit further includes a third sub-pixel,

[0010] The aperture ratio of the first sub-pixel is greater than the aperture ratio of the third sub-pixel, the number of apertures of the first sub-pixel is greater than the number of apertures of the third sub-pixel, and the number of pixel circuits for driving the first sub-pixel is equal to the number of pixel circuits for driving the third sub-pixel;

[0011] The color filter layer further includes a third color resist, wherein the orthographic projection of the third color resist on the substrate covers the orthographic projection of the opening of the third sub-pixel on the substrate;

[0012] The orthographic projection shape of the third color resist on the substrate includes a shape with at least a portion of its edges being arc-shaped.

[0013] In some embodiments, the ratio of the size of the orthographic projection shape of the first color resist on the substrate in the row direction to the column direction of the pixel unit array is in a range of 0.8 to 1.2;

[0014] The ratio of the size of the orthographic projection of the second color resist on the substrate in the row direction to the column direction of the pixel unit array is in a range of 0.8 to 1.2;

[0015] The ratio of the size of the orthographic projection shape of the third color resist on the substrate in the row direction to the size of the column direction of the pixel unit array is in a range of 0.8 to 1.2.

[0016] In some embodiments, the orthographic projection shape of the first color resist on the substrate is a symmetrical shape along the row direction and the column direction of the pixel unit array;

[0017] The orthographic projection shape of the second color resist on the substrate is a symmetrical shape along the row direction and the column direction of the pixel unit array;

[0018] The orthographic projection shape of the third color resist on the substrate is a symmetrical shape along the row direction and the column direction of the pixel unit array.

[0019] In some embodiments, the orthographic projection shape of the opening of the first sub-pixel on the substrate is the same as the orthographic projection shape of the first color resist on the substrate;

[0020] The orthographic projection shape of the opening of the second sub-pixel on the substrate is the same as the orthographic projection shape of the second color resist on the substrate;

[0021] The orthographic projection shape of the opening of the third sub-pixel on the substrate is the same as the orthographic projection shape of the third color resist on the substrate.

[0022] In some embodiments, the first sub-pixel has two openings;

[0023] The second sub-pixel has an opening;

[0024] The third sub-pixel has an opening;

[0025] The second sub-pixel and the third sub-pixel in the pixel unit are arranged along a first direction, the second sub-pixel and the first sub-pixel are arranged along a second direction; the third sub-pixel and the first sub-pixel are arranged along the second direction;

[0026] The two openings of the first sub-pixel in the pixel unit are arranged along the first direction;

[0027] The first direction is a column direction of the pixel unit array, and the second direction is a row direction of the pixel unit array.

[0028] In some embodiments, the second sub-pixel openings and one first sub-pixel opening located in a first row and adjacent to each other, and the third sub-pixel opening and another first sub-pixel opening located in a second row and adjacent to each other constitute one pixel unit;

[0029] The first row and the second row are adjacent to each other, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one first sub-pixel opening and another first sub-pixel opening are located in the same column.

[0030] In some embodiments, the second sub-pixel opening located in the first row, the third sub-pixel opening located in the second row and adjacent thereto, one first sub-pixel opening, and another first sub-pixel opening located in the third row constitute one pixel unit;

[0031] The first row, the second row and the third row are arranged in sequence along the first direction, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one first sub-pixel opening and another first sub-pixel opening are located in the same column.

[0032] In some embodiments, in the odd-numbered columns of the pixel units, the second sub-pixel opening located in the first row, the third sub-pixel opening located in the second row and adjacent thereto, one first sub-pixel opening, and another first sub-pixel opening located in the third row constitute one pixel unit;

[0033] The first row, the second row, and the third row are arranged in sequence along the first direction, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one first sub-pixel opening and another first sub-pixel opening are located in the same column;

[0034] In the pixel units of even columns, the second sub-pixel openings and one first sub-pixel opening located in the first row and adjacent to each other, and the third sub-pixel opening and another first sub-pixel opening located in the second row and adjacent to each other constitute one pixel unit;

[0035] The first row and the second row are adjacent to each other, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one first sub-pixel opening and another first sub-pixel opening are located in the same column.

[0036] In some embodiments, the first subpixel includes a first anode;

[0037] The first anode includes a first main portion and a first connecting portion, the first main portion and the first connecting portion are electrically connected, and the first connecting portion is electrically connected to the pixel circuit of the first sub-pixel;

[0038] The second sub-pixel includes a second anode;

[0039] The second anode includes a second main portion and a second connecting portion, the second main portion and the second connecting portion are electrically connected, and the second connecting portion is electrically connected to the pixel circuit of the second sub-pixel;

[0040] The third sub-pixel includes a third anode;

[0041] The third anode includes a third main portion and a third connecting portion, the third main portion and the third connecting portion are electrically connected, and the third connecting portion is electrically connected to the pixel circuit of the third sub-pixel;

[0042] The orthographic projection shape of the first main body on the substrate is the same as or similar to the orthographic projection shape of the first color resist on the substrate;

[0043] The orthographic projection shape of the second main body on the substrate is the same as or similar to the orthographic projection shape of the second color resist on the substrate;

[0044] The orthographic projection shape of the third main body portion on the substrate is the same as or similar to the orthographic projection shape of the third color resist on the substrate.

[0045] In some embodiments, the first sub-pixel, the second sub-pixel, and the third sub-pixel have different colors.

[0046] The areas of the openings in the first sub-pixel are different;

[0047] The shortest distance between the opening outlines of the adjacent first sub-pixel opening and the second sub-pixel opening in the pixel unit is greater than 10 μm;

[0048] The shortest distance between the opening outlines of the second sub-pixel opening and the third sub-pixel opening adjacent to each other in the pixel unit is greater than 10 μm.

[0049] In some embodiments, the same side contours of the second sub-pixel openings and one of the first sub-pixel openings located in the same row in the pixel unit are located on a first straight line.

[0050] The same side contours of the third sub-pixel opening and another first sub-pixel opening located in the same row in the pixel unit are located on a second straight line,

[0051] The same side contours of the second sub-pixel opening and the third sub-pixel opening located in the same column in the pixel unit are located on a third straight line,

[0052] The same side contours of one first sub-pixel opening and another first sub-pixel opening located in the same column of the pixel unit are located on a fourth straight line,

[0053] The first straight line, the second straight line, the third straight line and the fourth straight line are spliced ​​to form a rectangle,

[0054] The orthographic projections of the two openings of the first sub-pixel, the second sub-pixel opening, and the third sub-pixel opening in the pixel unit on the substrate are located within the orthographic projection of the rectangle on the substrate.

[0055] In some embodiments, centers of the second sub-pixel openings and one first sub-pixel opening located in the same row in the pixel unit are located on a first straight line.

[0056] The centers of the third sub-pixel opening and another first sub-pixel opening located in the same row in the pixel unit are located on a second straight line,

[0057] The centers of the second sub-pixel opening and the third sub-pixel opening located in the same column in the pixel unit are located on a third straight line,

[0058] The centers of one first sub-pixel opening and another first sub-pixel opening in the same column of the pixel unit are located on a fourth straight line.

[0059] The first straight line, the second straight line, the third straight line and the fourth straight line are spliced ​​to form a rectangle.

[0060] In some embodiments, the first subpixel comprises a blue subpixel;

[0061] The second sub-pixel includes a green sub-pixel;

[0062] The third sub-pixel includes a red sub-pixel;

[0063] The opening area of ​​the first sub-pixel is larger than the opening area of ​​the second sub-pixel, and the opening area of ​​the second sub-pixel is larger than the opening area of ​​the third sub-pixel;

[0064] The ratio of the opening area of ​​the second sub-pixel to the opening area of ​​the first sub-pixel in the pixel unit is 1:(1,3];

[0065] The area ratio range of the opening of the third sub-pixel and any opening of the first sub-pixel in the pixel unit is 1:(0, 3).

[0066] In some embodiments, the first subpixel comprises a green subpixel;

[0067] The second sub-pixel includes a blue sub-pixel;

[0068] The third sub-pixel includes a red sub-pixel;

[0069] The opening area of ​​the first sub-pixel is larger than the opening area of ​​the second sub-pixel, and the opening area of ​​the second sub-pixel is larger than the opening area of ​​the third sub-pixel;

[0070] The ratio of the opening area of ​​the second sub-pixel to the opening area of ​​the first sub-pixel in the pixel unit is 1:(1,3];

[0071] The area ratio range of the opening of the third sub-pixel and any opening of the first sub-pixel in the pixel unit is 1:(0, 3).

[0072] In some embodiments, the first subpixel includes a first anode;

[0073] The first anodes corresponding to all openings of the first sub-pixel in the pixel unit are connected as one.

[0074] In some embodiments, the pixel circuit includes a first connection electrode,

[0075] The first connecting electrode is located on a side of the first anode close to the substrate; a first flat layer is provided between the first connecting electrode and the first anode;

[0076] The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first anode on the substrate, the first flat layer is provided with a first via hole in the overlapping region of the orthographic projections, and the first anode is connected to the first connecting electrode through the first via hole;

[0077] An orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate.

[0078] In some embodiments, the first subpixel includes a first anode;

[0079] The first anode includes a plurality of sub-electrodes, and the plurality of sub-electrodes are distributed at intervals;

[0080] The orthographic projections of the openings of the first sub-pixels in the pixel unit on the substrate are respectively located within different orthographic projection regions of the sub-electrodes on the substrate.

[0081] In some embodiments, the pixel circuit includes a first connection electrode and a second connection electrode,

[0082] The first connecting electrode and the second connecting electrode are arranged on the same layer;

[0083] The first connecting electrode and the second connecting electrode are located on a side of the first anode close to the substrate; a first flat layer is provided between the first anode and the first connecting electrode and the second connecting electrode;

[0084] The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of one of the sub-electrodes of the first anode on the substrate, the first flat layer is provided with a first via hole in the overlapping region of the orthographic projections, and one of the sub-electrodes of the first anode is connected to the first connecting electrode through the first via hole;

[0085] An orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate;

[0086] The orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projections of any two adjacent sub-electrodes of the first anode on the substrate, and the first flat layer is further provided with a second via hole in the overlapping region of the orthographic projections, and any two adjacent sub-electrodes of the first anode are respectively connected to the second connecting electrode through the second via hole;

[0087] An orthographic projection of the second via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate.

[0088] In some embodiments, the orthographic projection of the second connecting electrode on the substrate is located between the orthographic projections of any two adjacent sub-electrodes of the first anode on the substrate.

[0089] At least a portion of an orthographic projection of the second connecting electrode on the substrate does not overlap with the orthographic projections of any two adjacent sub-electrodes of the first anode on the substrate.

[0090] In some embodiments, the orthographic projections of the first via hole and the second via hole on the substrate are located within an orthographic projection area of ​​the pixel circuit of the first sub-pixel on the substrate.

[0091] In some embodiments, the pixel circuit further includes a first driving transistor,

[0092] The first driving transistor is located on a side of the first connecting electrode close to the substrate, and a second planar layer is provided between the first driving transistor and the first connecting electrode;

[0093] The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first driving transistor on the substrate, the second flat layer is provided with a third via hole in the overlapping region of the orthographic projections, and the first connecting electrode is connected to the first electrode of the first driving transistor through the third via hole;

[0094] An orthographic projection of the third via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate.

[0095] In some embodiments, the second subpixel includes a second anode;

[0096] The pixel circuit further includes a third connecting electrode,

[0097] The third connecting electrode is provided on the same layer as the first connecting electrode;

[0098] The third connecting electrode is located on a side of the second anode close to the substrate; the first flat layer further extends between the third connecting electrode and the second anode;

[0099] The orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second anode on the substrate, the first flat layer further has a fourth via hole in the overlapping region of the orthographic projections, and the second anode is connected to the third connecting electrode through the fourth via hole;

[0100] An orthographic projection of the fourth via hole on the substrate does not overlap with an orthographic projection of the opening of the second sub-pixel on the substrate;

[0101] The third sub-pixel includes a third anode;

[0102] The pixel circuit further includes a fourth connecting electrode,

[0103] The fourth connecting electrode is provided on the same layer as the first connecting electrode;

[0104] The fourth connecting electrode is located on a side of the third anode close to the substrate; the first flat layer further extends between the fourth connecting electrode and the third anode;

[0105] The orthographic projection of the fourth connection electrode on the substrate at least partially overlaps with the orthographic projection of the third anode on the substrate, the first flat layer further defines a fifth via hole in the overlapping region of the orthographic projections, and the third anode is connected to the fourth connection electrode through the fifth via hole;

[0106] An orthographic projection of the fifth via hole on the substrate does not overlap with an orthographic projection of the opening of the third sub-pixel on the substrate.

[0107] In some embodiments, the orthographic projection of the fourth via hole on the substrate is located within the orthographic projection area of ​​the pixel circuit of the second sub-pixel on the substrate;

[0108] The orthographic projection of the fifth via hole on the substrate is located within the orthographic projection area of ​​the pixel circuit of the third sub-pixel on the substrate.

[0109] In some embodiments, the pixel circuit further includes a second driving transistor,

[0110] The second driving transistor is located on a side of the third connecting electrode close to the substrate, and the second planar layer further extends between the second driving transistor and the third connecting electrode;

[0111] The orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second driving transistor on the substrate, the second planar layer further having a sixth via hole formed in the overlapping region of the orthographic projections, and the third connecting electrode is connected to the first electrode of the second driving transistor through the sixth via hole;

[0112] An orthographic projection of the sixth via hole on the substrate does not overlap with an orthographic projection of an opening of the second sub-pixel on the substrate;

[0113] The pixel circuit further includes a third driving transistor,

[0114] The third driving transistor is located on a side of the fourth connecting electrode close to the substrate, and the second planar layer further extends between the third driving transistor and the fourth connecting electrode;

[0115] The orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the third driving transistor on the substrate, the second flat layer further having a seventh via hole formed in the overlapping region of the orthographic projections, and the fourth connecting electrode is connected to the first electrode of the third driving transistor through the seventh via hole;

[0116] An orthographic projection of the seventh via hole on the substrate does not overlap with an orthographic projection of the opening of the third sub-pixel on the substrate.

[0117] In some embodiments, the orthographic projections of the first color resist, the second color resist, and the third color resist on the substrate do not overlap with each other;

[0118] The color filter layer further includes a black matrix, and a pattern of the black matrix is ​​complementary to the patterns of the first color resist, the second color resist, and the third color resist.

[0119] In some embodiments, it also includes an encapsulation layer, a touch layer and a cover plate.

[0120] The encapsulation layer and the touch layer are located between the pixel unit array and the color filter layer, and the encapsulation layer and the touch layer are sequentially stacked on a side of the pixel unit array close to the color filter layer;

[0121] The cover plate is located on a side of the color filter layer facing away from the substrate.

[0122] An embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0123] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0124] FIG. 1 a is a schematic top view of the structure of a display panel in the disclosed technology.

[0125] FIG1 b is a schematic cross-sectional view of the structure along the AA section line in FIG1 a .

[0126] FIG1c is a schematic cross-sectional view of another structure along the AA section line in FIG1a.

[0127] FIG1d is a schematic cross-sectional view of another structure along the AA section line in FIG1a.

[0128] FIG. 1e is a schematic top view of the structure of a sub-pixel in a display panel according to the disclosed technology.

[0129] FIG2 a is a schematic top view of the structure of a display panel according to an embodiment of the present disclosure.

[0130] FIG. 2 b is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0131] FIG2c is a schematic cross-sectional view of the structure along the BB section line in FIG2b.

[0132] FIG2 d is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0133] FIG2e is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0134] FIG2 f is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0135] FIG2g is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0136] FIG2h is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0137] FIG. 2i is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0138] FIG2j is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0139] FIG2k is a schematic top view of the structure of another display panel according to an embodiment of the present disclosure.

[0140] FIG21 is a schematic cross-sectional view of the structure along the CC cutting line in FIG2k.

[0141] FIG2m is a schematic cross-sectional view of the structure along the DD section line in FIG2b and FIG2k. DETAILED DESCRIPTION

[0142] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display panel and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0143] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0144] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0145] In the disclosed technology, reference is made to FIG1a, which is a schematic top view of the structure of a display panel in the disclosed technology; FIG1b is a schematic cross-sectional view of the structure along the AA section line in FIG1a. The display panel includes a drive substrate, a plurality of light-emitting devices 15 disposed on the drive substrate, and an encapsulation structure 16 for encapsulating the plurality of light-emitting devices 15. The display panel has a plurality of sub-pixel regions, each of which has a plurality of colors. For example, the plurality of sub-pixel regions include a red sub-pixel region Pr, a green sub-pixel region Pg, and a blue sub-pixel region Pb. The plurality of light-emitting devices 15 have a plurality of colors. A light-emitting device 15 of a certain color is located in a corresponding sub-pixel region. For example, a light-emitting device emitting red light is located in the red sub-pixel region Pr, a light-emitting device emitting green light is located in the green sub-pixel region Pg, and a light-emitting device emitting blue light is located in the blue sub-pixel region Pb.

[0146] The drive substrate includes: a substrate 1 and a drive structure layer disposed on the substrate 1; a plurality of light-emitting devices 15 and an encapsulation structure 16 for encapsulating the plurality of light-emitting devices 15, which are sequentially disposed on the drive structure layer. The drive structure layer may include a pixel drive circuit for driving the light-emitting devices 15 to emit light. The light-emitting devices 15 may include a first electrode 151, a second electrode 152, and a light-emitting functional layer 153 located between the first and second electrodes 151, 152. The first electrode 151 may serve as the anode of the light-emitting device 15, and the second electrode 152 may serve as the cathode of the light-emitting device 15. When current is generated between the first and second electrodes 151, 152, the light-emitting functional layer 153 emits light. The light-emitting functional layer 153 may include: a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence. Optionally, the light-emitting device 15 is an OLED (Organic Light-Emitting Diode) device, in which case the light-emitting layer uses an organic light-emitting material.

[0147] In some embodiments, the first electrode 151 is a reflective electrode configured to reflect light irradiating the first electrode 151 ; the second electrode 152 is configured to partially transmit and partially reflect light irradiating the second electrode 152 .

[0148] In some embodiments, referring to FIG. 1 b , the driving structure layer includes multiple pixel driving circuits. Each pixel driving circuit corresponds to a light-emitting device 15 on a one-to-one basis. The pixel driving circuit is used to provide a driving current to each light-emitting device 15 to drive the light-emitting device 15 to emit light. For example, the pixel driving circuit includes multiple thin-film transistors 18. Each thin-film transistor 18 includes a gate 181, an active layer 182, a source electrode 183, and a drain electrode 184. For example, in the case of a top-gate thin-film transistor 18, the active layer 182 is located between the gate 181 and the substrate 1; the gate insulating layer GI is disposed on the side of the active layer 182 away from the substrate 1; the gate 181 is disposed on the side of the gate insulating layer GI away from the substrate 1; and the interlayer insulating layer ILD is disposed on the side of the gate 181 away from the substrate 1. The source electrode 183 and the drain electrode 184 are disposed in the same layer and on the side of the interlayer insulating layer ILD away from the substrate 1. The source electrode 183 and the drain electrode 184 are electrically connected to the active layer 182. The planarization layer PLN is disposed on the side of the source electrode 183 and the drain electrode 184 facing away from the substrate 1. A pixel definition layer (PDL) is located on the side of the planarization layer PLN facing away from the substrate 1 and has multiple pixel openings. Each light-emitting device 15 corresponds to a pixel opening and includes a first electrode 151, a second electrode 152, and a light-emitting functional layer 153 located between the first and second electrodes 151, 152. For example, the first electrode 151 is an anode, and the second electrode 152 is a cathode. The first electrode 151 is located between the pixel definition layer PDL and the planarization layer PLN, with a portion of the first electrode 151 exposed by the pixel opening.

[0149] In some embodiments, the encapsulation structure 16 includes a first inorganic encapsulation layer 161, a second inorganic encapsulation layer 162, and an organic encapsulation layer 163 located therebetween. The first inorganic encapsulation layer 161, the organic encapsulation layer 163, and the second inorganic encapsulation layer 162 are stacked in sequence to encapsulate the plurality of light-emitting devices 15, thereby preventing moisture and / or oxygen from the external environment from corroding the light-emitting devices 15. The first inorganic encapsulation layer 161 and the second inorganic encapsulation layer 162 can both be made of a highly dense inorganic material, and the organic encapsulation layer 163 can be made of an organic polymer resin material.

[0150] In the disclosed technology, the pixel drive circuit in the display panel is relatively complex. To improve the light extraction efficiency of the display panel and reduce power consumption, a cathode and anode combination (a fully reflective electrode and a semi-transmissive and semi-reflective electrode) are used. This results in a high reflectivity of the drive substrate. To reduce the reflectivity, the disclosed technology adopts the method of attaching a polarizer. Referring to Figure 1c, which is a schematic cross-sectional view of another structure along the AA section line in Figure 1a, a polarizer 17 is attached to the side of the packaging structure 16 facing away from the substrate 1, thereby reducing the reflectivity of the drive substrate. However, the attachment of polarizer 17 significantly reduces the transmittance of light from the display panel. In some embodiments, a cover plate 14 is provided on the side of the polarizer 17 facing away from the substrate 1.

[0151] In some embodiments, referring to Figure 1d, which illustrates another cross-sectional view of the structure along line AA in Figure 1a, a color filter layer 4 can be used in place of the polarizer to minimize the light transmittance of the display panel. The color filter layer 4 includes multiple color filters 4r, 4g, and 4b. Each color filter 4r / 4g / 4b corresponds to a light-emitting device 15, and the color filters 4r / 4g / 4b emit the same color as the corresponding light-emitting device 15. For example, color filter 4r corresponds to a red light-emitting device and is red; color filter 4g corresponds to a green light-emitting device and is green; and color filter 4b corresponds to a blue light-emitting device and is blue. The color filter layer also includes a black matrix BM, which is co-located with the multiple color filters 4r, 4g, and 4b, and whose pattern complements that of the multiple color filters 4r, 4g, and 4b. In some embodiments, a cover plate 14 is provided on the side of the color filter layer 4 facing away from the substrate 1.

[0152] In some embodiments, the use of a color filter layer has requirements for the shape of the sub-pixels in the display panel (i.e., the shape of the effective light-emitting area of ​​the light-emitting device, i.e., the shape of the pixel opening area in the pixel definition layer (PDL) where the light-emitting device is located). If the shape of the sub-pixels in the display panel does not meet the requirements, the diffraction of the ambient light by the display panel will be aggravated. Referring to Figure 1e, there is a top view schematic diagram of the structure of the sub-pixels in the disclosed technology display panel, in which the shape and arrangement of the red sub-pixels 302, green sub-pixels 303, and blue sub-pixels 301 in the display panel are rectangular or quasi-rectangular. Under the irradiation of external ambient light, the horizontal and vertical diffraction of the ambient light by the display panel will be very obvious, seriously affecting the appearance of the display panel when the screen is off.

[0153] In order to solve the problem that the color filter layer in the disclosed technology causes the display panel to aggravate the diffraction of ambient light, in the first aspect, the present embodiment provides a display panel, and with reference to FIG2a, it is a schematic diagram of a top view of the structure of a display panel in the disclosed embodiment; FIG2b is a schematic diagram of a top view of the structure of another display panel in the disclosed embodiment; FIG2c is a schematic diagram of a cross-sectional structure along the BB section line in FIG2b; wherein, it includes a substrate 1, a pixel circuit 2, an array of pixel units 3 and a color filter layer 4, and the pixel circuit 2, the array of pixel units 3 and the color filter layer 4 are sequentially stacked on one side of the substrate 1; the pixel unit 3 includes a first sub-pixel 31 and a second sub-pixel 32, and the switch of the first sub-pixel 31 The aperture ratio of the first sub-pixel 31 is greater than the aperture ratio of the second sub-pixel 32, the number of openings of the first sub-pixel 31 is greater than the number of openings of the second sub-pixel 32, and the number of pixel circuits 2 for driving the first sub-pixel 31 is equal to the number of pixel circuits 2 for driving the second sub-pixel 32; the color filter layer 4 includes a first color resist 41 and a second color resist 42, the orthographic projection of the first color resist 41 on the substrate 1 covers the orthographic projection of the opening of the first sub-pixel 31 on the substrate 1, and the orthographic projection of the second color resist 42 on the substrate 1 covers the orthographic projection of the opening of the second sub-pixel 32 on the substrate 1; the orthographic projection shapes of the first color resist 41 and the second color resist 42 on the substrate 1 include shapes with at least partially arc-shaped edges.

[0154] In some embodiments, the pixel unit 3 also includes a third sub-pixel 33, the aperture ratio of the first sub-pixel 31 is greater than the aperture ratio of the third sub-pixel 33, the number of openings of the first sub-pixel 31 is greater than the number of openings of the third sub-pixel 33, and the number of pixel circuits 2 used to drive the first sub-pixel 31 is equal to the number of pixel circuits 2 used to drive the third sub-pixel 33; the color filter layer 4 also includes a third color resist 44, and the orthographic projection of the third color resist 44 on the substrate 1 covers the orthographic projection of the opening of the third sub-pixel 33 on the substrate 1; the orthographic projection shape of the third color resist 44 on the substrate 1 includes a shape with at least part of the edge being arc-shaped.

[0155] In some embodiments, the ratio of the size of the orthographic projection shape of the first color resist 41 on the substrate 1 in the row direction and the column direction of the pixel unit 3 array is in the range of 0.8 to 1.2; the ratio of the size of the orthographic projection shape of the second color resist 42 on the substrate 1 in the row direction and the column direction of the pixel unit 3 array is in the range of 0.8 to 1.2; the ratio of the size of the orthographic projection shape of the third color resist 44 on the substrate 1 in the row direction and the column direction of the pixel unit 3 array is in the range of 0.8 to 1.2.

[0156] In some embodiments, the orthographic projection shape of the first color resist 41 on the substrate 1 is a symmetrical figure along the row direction and the column direction of the pixel unit 3 array; the orthographic projection shape of the second color resist 42 on the substrate 1 is a symmetrical figure along the row direction and the column direction of the pixel unit 3 array; the orthographic projection shape of the third color resist 44 on the substrate 1 is a symmetrical figure along the row direction and the column direction of the pixel unit 3 array.

[0157] In some embodiments, the orthographic projection shape of the opening of the first sub-pixel 31 on the substrate 1 is the same as the orthographic projection shape of the first color resist 41 on the substrate 1; the orthographic projection shape of the opening of the second sub-pixel 32 on the substrate 1 is the same as the orthographic projection shape of the second color resist 42 on the substrate 1; the orthographic projection shape of the opening of the third sub-pixel 33 on the substrate 1 is the same as the orthographic projection shape of the third color resist 44 on the substrate 1.

[0158] In some embodiments, the orthographic projections of the first color resist 41, the second color resist 42, and the third color resist 44 on the substrate 1 include circular or quasi-circular shapes. Quasi-circular shapes include ellipses, regular polygons with eight or more sides, and rounded polygons with eight or more sides.

[0159] In some embodiments, the first sub-pixel 31, the second sub-pixel 32, and the third sub-pixel 33 are OLED (Organic Light-Emitting Diode) devices. The first sub-pixel 31 includes a first anode 310, a first light-emitting functional layer 311, and a first cathode 312. The first anode 310, the first light-emitting functional layer 311, and the first cathode 312 are stacked in sequence away from the substrate 1. When current is generated between the first anode 310 and the first cathode 312, the first light-emitting functional layer 311 emits light. The first light-emitting functional layer 311 may include a hole injection layer, a hole transport layer, a first light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence. The second sub-pixel 32 includes a second anode 320, a second light-emitting functional layer 321, and a second cathode 322. The second anode 320, the second light-emitting functional layer 321, and the second cathode 322 are stacked in sequence away from the substrate 1. When current is generated between the second anode 320 and the second cathode 322, the second light-emitting functional layer 321 emits light. The third subpixel 33 includes a third anode 330, a third light-emitting functional layer, and a third cathode. The third anode, the third light-emitting functional layer, and the third cathode are stacked in sequence away from the substrate 1. When current is generated between the third anode and the third cathode, the third light-emitting functional layer emits light. The second light-emitting functional layer 321 may include: a hole injection layer, a hole transport layer, a second light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence. The third light-emitting functional layer may include: a hole injection layer, a hole transport layer, a third light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence. The first, second, and third light-emitting layers emit different colors. In some embodiments, the first cathode 312 and the second cathode 322 are arranged on the same layer as the third cathode and are laid out as a whole layer. In some embodiments, the hole injection layers of the first sub-pixel 31, the second sub-pixel 32 and the third sub-pixel 33 can be set in the same layer and laid out in the entire layer; the hole transport layers of the first sub-pixel 31, the second sub-pixel 32 and the third sub-pixel 33 can be set in the same layer and laid out in the entire layer; the electron transport layers of the first sub-pixel 31, the second sub-pixel 32 and the third sub-pixel 33 can be set in the same layer and laid out in the entire layer; the electron injection layers of the first sub-pixel 31, the second sub-pixel 32 and the third sub-pixel 33 can be set in the same layer and laid out in the entire layer.

[0160] In some embodiments, the first color resist 41 emits the same color as the first sub-pixel 31, the second color resist 42 emits the same color as the second sub-pixel 32, and the third color resist 44 emits the same color as the third sub-pixel 33. The orthographic projection of the first color resist 41 on the substrate 1 covers the opening of the first sub-pixel 31, so that all light emitted from the first sub-pixel 31 can be emitted through the first color resist 41. The orthographic projection of the second color resist 42 on the substrate 1 covers the opening of the second sub-pixel 32, so that all light emitted from the second sub-pixel 32 can be emitted through the second color resist 42. The orthographic projection of the third color resist 44 on the substrate 1 covers the opening of the third sub-pixel 33, so that all light emitted from the third sub-pixel 33 can be emitted through the third color resist 44, thereby improving the color saturation of the image displayed by the display panel.

[0161] In some embodiments, the orthographic projections of the first color resist 41 , the second color resist 42 , and the third color resist 44 on the substrate 1 do not overlap with each other; the color filter layer 4 further includes a black matrix 43 , the pattern of the black matrix 43 is complementary to the pattern of the first color resist 41 , the second color resist 42 , and the third color resist 44 .

[0162] In this embodiment, the display panel uses a color filter layer 4 in place of the polarizer used in the prior art. This reduces the display panel's reflectivity to light and significantly increases its light transmittance compared to a polarizer, thereby enhancing the display quality. Furthermore, by ensuring that the orthographic projections of the first and second color filters 41, 42 of the color filter layer 4 on the substrate 1 include at least partially curved edges, the display panel's diffraction of ambient light can be reduced, thereby improving the display panel's appearance when the screen is off.

[0163] In some embodiments, the orthographic projection shapes of the openings of the first sub-pixel 31, the second sub-pixel 32, and the third sub-pixel 33 on the substrate 1 include circles or quasi-circles. This configuration can reduce the diffraction of ambient light by the display panel, thereby improving the appearance of the display panel when the screen is off.

[0164] In some embodiments, the center of the orthographic projection of the first color resist 41 on the substrate 1 coincides with the center of the orthographic projection of the opening of the first sub-pixel 31 on the substrate 1; the center of the orthographic projection of the second color resist 42 on the substrate 1 coincides with the center of the orthographic projection of the opening of the second sub-pixel 32 on the substrate 1; the center of the orthographic projection of the third color resist 44 on the substrate 1 coincides with the center of the orthographic projection of the opening of the third sub-pixel 33 on the substrate 1.

[0165] In some embodiments, referring to Figures 2a and 2b, the pixel unit 3 includes at least two second sub-pixels 32 and at least one first sub-pixel 31, the opening area of ​​the first sub-pixel 31 is larger than the opening area of ​​the second sub-pixel 32; each second sub-pixel 32 has an opening; the orthographic projections of the openings of the second sub-pixels 32 on the substrate 1 do not overlap; each first sub-pixel 31 has at least two openings; the orthographic projections of the openings of the first sub-pixels 31 on the substrate 1 do not overlap; the orthographic projections of the openings of the first sub-pixels 31 and the openings of the second sub-pixels 32 on the substrate 1 do not overlap; the second sub-pixels 32 in the pixel unit 3 are arranged along the first direction Y, and the second sub-pixels 32 and the first sub-pixels 31 are arranged along the second direction X; the openings of the first sub-pixels 31 in the pixel unit 3 are arranged along the first direction Y; the first direction Y and the second direction X intersect.

[0166] In some embodiments, referring to Figures 2a and 2b, the first sub-pixel 31 has two openings; the second sub-pixel 32 has one opening; the third sub-pixel 33 has one opening; the second sub-pixel 32 and the third sub-pixel 33 in the pixel unit 3 are arranged along the first direction Y, and the second sub-pixel 32 and the first sub-pixel 31 are arranged along the second direction X; the third sub-pixel 33 and the first sub-pixel 31 are arranged along the second direction X; the two openings of the first sub-pixel 31 in the pixel unit 3 are arranged along the first direction Y; the first direction Y is the column direction of the pixel unit 3 array, and the second direction X is the row direction of the pixel unit 3 array.

[0167] In some embodiments, referring to FIG. 2d , there is shown a schematic top view of another display panel structure according to an embodiment of the present disclosure, wherein a first sub-pixel 31 includes a first anode 310; the orthographic projection of the first anode 310 on substrate 1 is located within the orthographic projection area of ​​the pixel unit 3 to which it belongs on substrate 1; and the orthographic projection of the opening of the first sub-pixel 31 in the pixel unit 3 on substrate 1 is located within the orthographic projection area of ​​the first anode 310 on substrate 1. The arrangement of the first anode 310 can improve the aperture ratio of the pixel unit 3 and enhance the display quality of the display panel.

[0168] In some embodiments, referring to Figure 2d, the second sub-pixel 32 opening and one first sub-pixel 31 opening located in the first row and adjacent to each other and the third sub-pixel 33 opening and another first sub-pixel 31 opening located in the second row and adjacent to each other constitute a pixel unit 3; the first row and the second row are adjacent, and the second sub-pixel 32 opening and the third sub-pixel 33 opening are located in the same column, and one first sub-pixel 31 opening and another first sub-pixel 31 opening are located in the same column.

[0169] In some embodiments, referring to Figure 2e, which is a schematic top view of the structure of another display panel in an embodiment of the present disclosure; wherein, the first sub-pixel 31 includes a first anode 310; the orthographic projection of the first anode 310 on the substrate 1 extends from the first pixel unit 3 of the two pixel units 3 adjacent along the first direction Y to the orthographic projection area of ​​the second pixel unit 3 on the substrate 1; the orthographic projections of the opening of the first sub-pixel 31 in the first pixel unit 3 close to the second pixel unit 3 and the orthographic projections of the opening of the first sub-pixel 31 in the second pixel unit 3 close to the first pixel unit 3 on the substrate 1 are located in the orthographic projection area of ​​the first anode 310 on the substrate 1.

[0170] In some embodiments, referring to FIG. 2e , the first anodes 310 in the pixel unit 3 array have the same size and shape, and are arranged in an array along a first direction Y and a second direction X. The arrangement of the first anodes 310 can improve the aperture ratio of the pixel unit 3 and enhance the display quality of the display panel.

[0171] In some embodiments, referring to Figure 2e, the second sub-pixel 32 opening located in the first row, the third sub-pixel 33 opening located in the second row and adjacent to it, one first sub-pixel 31 opening, and another first sub-pixel 31 opening located in the third row constitute a pixel unit 3; the first row, the second row, and the third row are arranged in sequence along the first direction Y, and the second sub-pixel 32 opening and the third sub-pixel 33 opening are located in the same column, and one first sub-pixel 31 opening and another first sub-pixel 31 opening are located in the same column.

[0172] In some embodiments, referring to FIG. 2f , there is shown a top view of another display panel structure in an embodiment of the present disclosure; wherein, the first sub-pixel 31 includes a first anode 310; the first direction Y is the column direction of the array of pixel units 3, and the second direction X is the row direction of the array of pixel units 3; the orthographic projection of the first anode 310 of at least some of the odd-numbered columns of pixel units 3 on the substrate 1 extends from the first pixel unit 3 of two adjacent pixel units 3 along the first direction Y to the orthographic projection area of ​​the second pixel unit 3 on the substrate 1; accordingly, in at least some of the odd-numbered columns of pixel units 3, the first pixel unit 3 The orthographic projections of the opening of the first sub-pixel 31 in the second pixel unit 3 near the second pixel unit 3 and the opening of the first sub-pixel 31 in the second pixel unit 3 near the first pixel unit 3 on the substrate 1 are located within the orthographic projection area of ​​the first anode 310 on the substrate 1; the orthographic projections of the first anode 310 in at least some of the even-numbered columns of pixel units 3 on the substrate 1 are located within the orthographic projection area of ​​the pixel unit 3 to which they belong on the substrate 1; accordingly, in at least some of the even-numbered columns of pixel units 3, the orthographic projections of the openings of the first sub-pixels 31 on the substrate 1 are located within the orthographic projection area of ​​the corresponding first anode 310 on the substrate 1. The arrangement of the first anodes 310 can, on the one hand, increase the aperture ratio of the pixel unit 3 and, on the other hand, enhance the display quality of the display panel.

[0173] In some embodiments, referring to Figure 2f, in the odd-numbered column pixel units 3, the second sub-pixel 32 opening located in the first row, the third sub-pixel 33 opening located in the second row and adjacent to it, one first sub-pixel 31 opening, and another first sub-pixel 31 opening located in the third row constitute a pixel unit 3; the first row, the second row, and the third row are arranged sequentially along the first direction Y, and the second sub-pixel 32 opening and the third sub-pixel 33 opening are located in the same column, and one first sub-pixel 31 opening and another first sub-pixel 31 opening are located in the same column; in the even-numbered column pixel units 3, the second sub-pixel 32 opening and the first sub-pixel 31 opening located in the first row and adjacent to it, and the third sub-pixel 33 opening and another first sub-pixel 31 opening located in the second row and adjacent to it constitute a pixel unit 3; the first row and the second row are adjacent to each other, and the second sub-pixel 32 opening and the third sub-pixel 33 opening are located in the same column, and one first sub-pixel 31 opening and another first sub-pixel 31 opening are located in the same column.

[0174] In some embodiments, referring to Figures 2d, 2e and 2f, the second sub-pixel 32 includes a second anode 320; the orthographic projections of the second anodes 320 of the second sub-pixels 32 in the pixel unit 3 on the substrate 1 are spaced apart from each other; the orthographic projections of the second anode 320 and the first anode 310 on the substrate 1 are spaced apart from each other; the orthographic projection of the second anode 320 on the substrate 1 is located within the orthographic projection area of ​​the pixel unit 3 to which it belongs on the substrate 1; the orthographic projection of the opening of each second sub-pixel 32 on the substrate 1 is located within the orthographic projection area of ​​the second anode 320 of the second sub-pixel 32 on the substrate 1.

[0175] In some embodiments, referring to Figures 2b and 2k, the first sub-pixel 31 includes a first anode 310; the first anode 310 includes a first main portion 3102 and a first connecting portion 3103, the first main portion 3102 and the first connecting portion 3103 are electrically connected, and the first connecting portion 3103 is electrically connected to the pixel circuit 2 of the first sub-pixel 31.

[0176] In some embodiments, referring to Figures 2b and 2k, the second sub-pixel 32 includes a second anode 320; the second anode 320 includes a second main portion 3201 and a second connecting portion 3202, the second main portion 3201 and the second connecting portion 3202 are electrically connected, and the second connecting portion 3202 is electrically connected to the pixel circuit 2 of the second sub-pixel 32.

[0177] In some embodiments, referring to Figures 2b and 2k, the third sub-pixel 33 includes a third anode 330; the third anode 330 includes a third main portion 3301 and a third connecting portion 3302, the third main portion 3301 and the third connecting portion 3302 are electrically connected, and the third connecting portion 3302 is electrically connected to the pixel circuit 2 of the third sub-pixel 33; the orthographic projection shape of the first main portion 3102 on the substrate 1 is the same as or similar to the orthographic projection shape of the first color resist 41 on the substrate 1; the orthographic projection shape of the second main portion 3201 on the substrate 1 is the same as or similar to the orthographic projection shape of the second color resist 42 on the substrate 1; the orthographic projection shape of the third main portion 3301 on the substrate 1 is the same as or similar to the orthographic projection shape of the third color resist 44 on the substrate 1.

[0178] In some embodiments, the orthographic projection of the first anode 310 on the substrate 1 includes a circular or quasi-circular shape; the orthographic projection of the second anode 320 on the substrate 1 includes a circular or quasi-circular shape. The orthographic projection of the third anode 330 on the substrate 1 includes a circular or quasi-circular shape. This arrangement not only ensures the aperture ratio of the sub-pixels, but also reduces the diffraction of ambient light by the display panel, thereby improving the appearance of the display panel when the screen is off.

[0179] In some embodiments, the orthographic projection of the first color resist 41 on the substrate 1 falls within the orthographic projection area of ​​the first anode 310 on the substrate 1; the orthographic projection of the second color resist 42 on the substrate 1 falls within the orthographic projection area of ​​the second anode 320 on the substrate 1; and the orthographic projection of the third color resist 44 on the substrate 1 falls within the orthographic projection area of ​​the third anode 330 on the substrate 1. This arrangement enables the preparation of the first color resist 41, the second color resist 42, the third color resist 44, and the first anode 310, the second anode 320, and the third anode 330 to meet process requirements.

[0180] In some embodiments, referring to FIG. 2g , there is shown a schematic top view of another display panel structure in an embodiment of the present disclosure; wherein the first sub-pixel 31, the second sub-pixel 32, and the third sub-pixel 33 have different colors, and the areas of the openings in the first sub-pixel 31 are different; the shortest distance s between the opening outlines of adjacent first sub-pixels 31 and second sub-pixels 32 in the pixel unit 3 is greater than 10 μm; and the shortest distance m between the opening outlines of adjacent second sub-pixels 32 and third sub-pixels 33 in the pixel unit 3 is greater than 10 μm. This configuration can, on the one hand, increase the aperture ratio of the pixel unit 3, and on the other hand, enhance the display quality of the display panel.

[0181] In some embodiments, referring to FIG. 2h , there is shown a schematic top view of another display panel structure in accordance with an embodiment of the present disclosure; wherein the orthographic projection of the area where the pixel unit 3 is located on the substrate 1 is a rectangular or quasi-rectangular shape. Quasi-rectangular refers to a shape that is not a regular rectangle but rather resembles a rectangle. This arrangement can better improve the aperture ratio of the pixel unit 3 while also enhancing the display quality of the display panel.

[0182] In some embodiments, referring to Figure 2h, the same side contour of the second sub-pixel 32 opening and the first sub-pixel 31 opening located in the same row in the pixel unit 3 is located on a first straight line, the same side contour of the third sub-pixel 33 opening and the other first sub-pixel 31 opening located in the same row in the pixel unit 3 is located on a second straight line, the same side contour of the second sub-pixel 32 opening and the third sub-pixel 33 opening located in the same column in the pixel unit 3 is located on a third straight line, the same side contour of the first sub-pixel 31 opening and the other first sub-pixel 31 opening located in the same column in the pixel unit 3 is located on a fourth straight line, the first straight line, the second straight line, the third straight line and the fourth straight line are spliced ​​to form a rectangle, and the orthographic projections of the two openings of the first sub-pixel 31, the second sub-pixel 32 opening and the third sub-pixel 33 opening in the pixel unit 3 on the substrate 1 are located within the orthographic projection of the rectangle on the substrate 1.

[0183] In some embodiments, referring to FIG. 2i , which is a schematic top view of another display panel structure in an embodiment of the present disclosure, the centers of the opening patterns of the first sub-pixel 31 and the second sub-pixel 32 in the pixel unit 3 are connected to form a rectangular or quasi-rectangular shape. This arrangement can further enhance the display effect of the display panel and increase the aperture ratio of the pixel unit 3.

[0184] In some embodiments, referring to Figure 2i, the centers of the openings of the second sub-pixel 32 and one first sub-pixel 31 located in the same row in the pixel unit 3 are located on a first straight line, the centers of the openings of the third sub-pixel 33 and another first sub-pixel 31 located in the same row in the pixel unit 3 are located on a second straight line, the centers of the openings of the second sub-pixel 32 and the third sub-pixel 33 located in the same column in the pixel unit 3 are located on a third straight line, the centers of the openings of the first sub-pixel 31 and another first sub-pixel 31 located in the same column in the pixel unit 3 are located on a fourth straight line, and the first straight line, the second straight line, the third straight line and the fourth straight line are spliced ​​to form a rectangle.

[0185] In some embodiments, referring to Figures 2d, 2e, 2f, 2g, 2h and 2i, the first sub-pixel 31 includes a blue sub-pixel, and the blue sub-pixel has two openings; the second sub-pixel 32 includes a green sub-pixel; the third sub-pixel 33 includes a red sub-pixel; the opening area of ​​the first sub-pixel 31 is larger than the opening area of ​​the second sub-pixel 32, and the opening area of ​​the second sub-pixel 32 is larger than the opening area of ​​the third sub-pixel 33; the opening area ratio range of the second sub-pixel 32 and the first sub-pixel 31 in the pixel unit 3 is 1:(1, 3); the area ratio range of the opening of the third sub-pixel 33 and any opening of the first sub-pixel 31 in the pixel unit 3 is 1:(0, 3). With such an arrangement, on the one hand, the aperture ratio of the pixel unit 3 is improved, and on the other hand, it is ensured that the display panel has a better color effect.

[0186] 2d , 2e , 2f , 2g , 2h , and 2i , the first color resist 41 includes a blue color resist, the second color resist 42 includes a green color resist, and the third color resist 44 includes a red color resist.

[0187] In some embodiments, referring to FIG. 2j , a schematic top view of the structure of another display panel in an embodiment of the present disclosure is shown; wherein, the first sub-pixel 31 includes a green sub-pixel, and the green sub-pixel has two openings; the second sub-pixel 32 includes a blue sub-pixel; and the third sub-pixel 33 includes a red sub-pixel; the opening area of ​​the first sub-pixel 31 is larger than the opening area of ​​the second sub-pixel 32, and the opening area of ​​the second sub-pixel 32 is larger than the opening area of ​​the third sub-pixel 33; the opening area ratio range of the second sub-pixel 32 to the first sub-pixel 31 in the pixel unit 3 is 1:(1, 3); the area ratio range of the opening of the third sub-pixel 33 to any opening of the first sub-pixel 31 in the pixel unit 3 is 1:(0, 3). With such an arrangement, on the one hand, the aperture ratio of the pixel unit 3 is improved, and on the other hand, it is ensured that the display panel has a better color effect.

[0188] In some embodiments, referring to FIG. 2 j , the first color resist 41 includes a green color resist, the second color resist 42 includes a blue color resist, and the third color resist 44 includes a red color resist.

[0189] In some embodiments, referring to Figures 2b and 2c, the first sub-pixel 31 includes a first anode 310; the orthographic projections of all openings of the first sub-pixels 31 in the pixel unit 3 on the substrate 1 do not overlap with each other; the first anodes 310 corresponding to all openings of the first sub-pixels 31 in the pixel unit 3 are connected as a whole, and the orthographic projections of all openings of the first sub-pixels 31 on the substrate 1 are located within the orthographic projection area of ​​the first anode 310 on the substrate 1.

[0190] In some embodiments, referring to Figures 2b and 2c, the pixel circuit 2 includes a first connection electrode 21, which is located on a side of the first anode 310 close to the substrate 1; a first planar layer 5 is provided between the first connection electrode 21 and the first anode 310; the orthographic projection of the first connection electrode 21 on the substrate 1 at least partially overlaps with the orthographic projection of the first anode 310 on the substrate 1, and the first planar layer 5 is provided with a first via 50 in the overlapping area of ​​the orthographic projections, and the first anode 310 is connected to the first connection electrode 21 through the first via 50; the orthographic projection of the first via 50 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the first connection electrode 21 and the first anode 310, and the orthographic projection of the first via 50 on the substrate 1 does not overlap with the orthographic projection of the opening of the first sub-pixel 31 on the substrate.

[0191] In some embodiments, referring to Figure 2k, there is shown a schematic top view of the structure of another display panel in the embodiment of the present disclosure; Figure 2l is a schematic cross-sectional view of the structure along the CC cutting line in Figure 2k; wherein, the first sub-pixel 31 includes a first anode 310; the first anode 310 includes a plurality of sub-electrodes 3101, and the plurality of sub-electrodes 3101 are distributed at intervals; the orthographic projections of all openings of the first sub-pixels 31 in the pixel unit 3 on the substrate 1 do not overlap with each other; the orthographic projections of each opening of the first sub-pixel 31 in the pixel unit 3 on the substrate 1 correspond to different sub-electrodes 3101, and the orthographic projections of each opening of the first sub-pixel 31 on the substrate 1 are respectively located within the orthographic projection area of ​​the corresponding sub-electrode 3101 on the substrate 1.

[0192] In some embodiments, referring to FIG. 2 k and FIG. 2 l , the pixel circuit 2 includes a first connection electrode 21 and a second connection electrode 22, which are disposed in the same layer. The first connection electrode 21 and the second connection electrode 22 are located on a side of the first anode 310 close to the substrate 1. A first planar layer 5 is disposed between the first anode 310 and the first connection electrode 21 and the second connection electrode 22. The orthographic projection of the first connection electrode 21 on the substrate 1 at least partially overlaps with the orthographic projection of one of the sub-electrodes 3101 of the first anode 310 on the substrate 1. One of the sub-electrodes 3101 of the first anode 310 is connected to the first connection electrode 21 via a first via hole 50 provided in the first planar layer 5. The orthographic projection of the first via hole 50 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the first connecting electrode 21 and one of the sub-electrodes 3101 of the first anode 310, and the orthographic projection of the first via hole 50 on the substrate 1 does not overlap with the orthographic projection of the opening of the first sub-pixel 31 on the substrate 1; the orthographic projection of the second connecting electrode 22 on the substrate 1 at least partially overlaps with the orthographic projections of any two adjacent sub-electrodes 3101 of the first anode 310 on the substrate 1, and any two adjacent sub-electrodes 3101 of the first anode 310 are respectively connected to the second connecting electrode 22 through the second via hole 51 opened in the first flat layer 5; the orthographic projection of the second via hole 51 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the second connecting electrode 22 and any two adjacent sub-electrodes 3101 of the first anode 310, and the orthographic projection of the second via hole 51 on the substrate 1 does not overlap with the orthographic projection of the opening of the first sub-pixel 31 on the substrate 1.

[0193] In some embodiments, referring to Figures 2k and 2l, the orthographic projection of the second connecting electrode 22 on the substrate 1 is located between the orthographic projections of any two adjacent sub-electrodes 3101 of the first anode 310 on the substrate 1, and at least part of the orthographic projection of the second connecting electrode 22 on the substrate 1 does not overlap with the orthographic projections of any two adjacent sub-electrodes 3101 of the first anode 310 on the substrate 1.

[0194] In some embodiments, referring to FIG. 2 k and FIG. 2 l , the orthographic projections of the first via hole 50 and the second via hole 51 on the substrate 1 are located within the orthographic projection region of the pixel circuit 2 of the first sub-pixel 31 on the substrate 1 .

[0195] In some embodiments, referring to Figures 2b and 2c as well as Figures 2k and 2l, the pixel circuit 2 also includes a first driving transistor 23, which is located on a side of the first connecting electrode 21 close to the substrate 1, and a second flat layer 6 is provided between the first driving transistor 23 and the first connecting electrode 21; the orthographic projection of the first connecting electrode 21 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 231 of the first driving transistor 23 on the substrate 1, and the first connecting electrode 21 is connected to the first electrode 231 of the first driving transistor 23 through a third via 60 provided in the second flat layer 6; the orthographic projection of the third via 60 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the first connecting electrode 21 and the first electrode 231 of the first driving transistor 23, and the orthographic projection of the third via 60 on the substrate 1 does not overlap with the orthographic projection of the opening of the first sub-pixel 31 on the substrate 1.

[0196] In some embodiments, the first driving transistor 23 further includes an active layer 232, a gate 233, and a second electrode 234. The gate 233 is located on the side of the active layer 232 facing away from the substrate 1, and a first gate insulating layer 7 is disposed between the gate 233 and the active layer 232. The second electrode 234 is disposed in the same layer as the first electrode 231, and the second electrode 234 and the first electrode 231 are located on the side of the gate 233 facing away from the substrate 1. A second gate insulating layer 8 and an intermediate dielectric layer 9 are disposed between the gate 233, the first electrode 231, and the second electrode 234. In addition, the pixel circuit 2 further includes a first capacitor 10. The first plate 101 of the first capacitor 10 is disposed in the same layer as the gate 233, and the second plate 102 of the first capacitor 10 is located on the side of the first plate 101 facing away from the substrate 1. The first plate 101 and the second plate 102 are insulated by a second gate insulating layer 8.

[0197] In some embodiments, referring to Figure 2m, which is a schematic cross-sectional view of the structure along the DD section line in Figure 2b and Figure 2k; the second sub-pixel 32 includes a second anode 320; the pixel circuit 2 also includes a third connection electrode 24, which is arranged in the same layer as the first connection electrode 21; the third connection electrode 24 is located on the side of the second anode 320 close to the substrate 1; the first flat layer 5 also extends between the third connection electrode 24 and the second anode 320; the orthographic projection of the third connection electrode 24 on the substrate 1 and the orthographic projection of the second anode 320 on the substrate 1 at least partially overlap, and the second anode 320 is connected to the third connection electrode 24 through a fourth via 52 provided in the first flat layer 5; the orthographic projection of the fourth via 52 on the substrate 1 is located in the overlapping area of ​​the orthographic projection of the third connection electrode 24 and the second anode 320, and the orthographic projection of the fourth via 52 on the substrate 1 does not overlap with the orthographic projection of the opening of the second sub-pixel 32 on the substrate 1.

[0198] In some embodiments, referring to Figures 2b and 2k, the third sub-pixel 33 includes a third anode 330; the pixel circuit also includes a fourth connecting electrode, which is arranged in the same layer as the first connecting electrode; the fourth connecting electrode is located on the side of the third anode 330 close to the substrate; the first flat layer also extends between the fourth connecting electrode and the third anode 330; the orthographic projection of the fourth connecting electrode on the substrate and the orthographic projection of the third anode 330 on the substrate at least partially overlap, and the first flat layer is further provided with a fifth via 53 in the overlapping area of ​​the orthographic projections, and the third anode 330 is connected to the fourth connecting electrode through the fifth via 53; the orthographic projection of the fifth via 53 on the substrate does not overlap with the orthographic projection of the opening of the third sub-pixel 33 on the substrate.

[0199] In some embodiments, referring to Figures 2b and 2k, the orthographic projection of the fourth via 52 on the substrate 1 is located within the orthographic projection area of ​​the pixel circuit 2 of the second sub-pixel 32 on the substrate 1; the orthographic projection of the fifth via 53 on the substrate is located within the orthographic projection area of ​​the pixel circuit 2 of the third sub-pixel 33 on the substrate.

[0200] In some embodiments, referring to Figure 2m, the pixel circuit 2 also includes a second driving transistor 25, which is located on a side of the third connecting electrode 24 close to the substrate 1, and the second flat layer 6 also extends between the second driving transistor 25 and the third connecting electrode 24; the orthographic projection of the third connecting electrode 24 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 251 of the second driving transistor 25 on the substrate 1, and the third connecting electrode 24 is connected to the first electrode 251 of the second driving transistor 25 through a sixth via 61 opened in the second flat layer 6; the orthographic projection of the sixth via 61 on the substrate 1 is located in the overlapping area of ​​the orthographic projection of the third connecting electrode 24 and the first electrode 251 of the second driving transistor 25, and the orthographic projection of the sixth via 61 on the substrate 1 does not overlap with the orthographic projection of the opening of the second sub-pixel 32 on the substrate 1.

[0201] In some embodiments, the pixel circuit also includes a third driving transistor (not shown in the figure), which is located on the side of the fourth connecting electrode close to the substrate, and the second flat layer also extends between the third driving transistor and the fourth connecting electrode; the orthographic projection of the fourth connecting electrode on the substrate and the orthographic projection of the first electrode of the third driving transistor on the substrate at least partially overlap, and the second flat layer is also provided with a seventh via hole in the overlapping area of ​​the orthographic projections, and the fourth connecting electrode is connected to the first electrode of the third driving transistor through the seventh via hole; the orthographic projection of the seventh via hole on the substrate does not overlap with the orthographic projection of the opening of the third sub-pixel on the substrate.

[0202] In some embodiments, the second driving transistor 25 further includes an active layer 252, a gate 253, and a second electrode 254. The gate 253 is located on the side of the active layer 252 facing away from the substrate 1, and a first gate insulating layer 7 is disposed between the gate 253 and the active layer 252. The second electrode 254 is disposed in the same layer as the first electrode 251, and the second electrode 254 and the first electrode 251 are located on the side of the gate 253 facing away from the substrate 1. A second gate insulating layer 8 and an intermediate dielectric layer 9 are disposed between the gate 253, the first electrode 251, and the second electrode 254. In addition, the pixel circuit 2 further includes a second capacitor 11. The first plate 111 of the second capacitor 11 is disposed in the same layer as the gate 253, and the second plate 112 of the second capacitor 11 is located on the side of the first plate 111 facing away from the substrate 1. The first plate 111 and the second plate 112 are insulated by a second gate insulating layer 8.

[0203] In some embodiments, referring to Figures 2b and 2k, the pixel circuit 2 of the third sub-pixel 33, the pixel circuit 2 of the second sub-pixel 32, and the pixel circuit 2 of the first sub-pixel 31 in the pixel unit 3 are distributed sequentially along the second direction X, that is, in this embodiment, the pixel circuits 2 of the red sub-pixel, the green sub-pixel, and the blue sub-pixel in the pixel unit 3 are distributed sequentially along the second direction X.

[0204] In some embodiments, referring to Figures 2c, 2l and 2m, the display panel also includes a pixel defining layer 19, which is located on the side of the first flat layer 5 away from the substrate 1, and the pixel defining layer 19 has a plurality of pixel openings, and the first sub-pixel 31, the second sub-pixel 32 and the third sub-pixel 33 correspond one-to-one to the pixel openings, and the first anode 310, the second anode 320 and the third anode 330 are located between the pixel defining layer 19 and the first flat layer 5, and a portion of the first anode 310, the second anode 320 and the third anode 330 are exposed by the pixel openings.

[0205] In some embodiments, referring to Figures 2c, 2l and 2m, the display panel further includes an encapsulation layer 12, a touch layer 13 and a cover plate 14. The encapsulation layer 12 and the touch layer 13 are located between the pixel unit 3 array and the color filter layer 4, and the encapsulation layer 12 and the touch layer 13 are stacked in sequence on the side of the pixel unit 3 array close to the color filter layer 4; the cover plate 14 is located on the side of the color filter layer 4 facing away from the substrate 1.

[0206] In some embodiments, the encapsulation layer 12 includes a first inorganic encapsulation layer 121, an organic encapsulation layer 122, and a second inorganic encapsulation layer 123, which are stacked in sequence. The encapsulation layer 12 encapsulates the array of pixel units 3, thereby preventing moisture and / or oxygen from the external environment from corroding the sub-pixels. The first inorganic encapsulation layer 121 and the second inorganic encapsulation layer 123 can both be made of highly dense inorganic materials, and the organic encapsulation layer 122 can be made of an organic polymer resin material.

[0207] In some embodiments, the touch layer 13 is directly formed on the side of the encapsulation layer 12 facing away from the substrate 1 for touch control of the display panel. The cover plate 14 can be made of glass or resin material to protect the color filter layer 4 and the entire display panel.

[0208] In this embodiment, the display panel uses a color filter layer 4 instead of the polarizer used in the prior art. This reduces the display panel's reflectivity to light and significantly increases the light transmittance of the display panel compared to the polarizer, thereby enhancing the display quality. Furthermore, by ensuring that the orthographic projections of the first and second color filters 41, 42 of the color filter layer 4 onto the substrate 1 are circular or quasi-circular, the display panel's diffraction of ambient light can be reduced, thereby improving the display panel's appearance when the screen is off.

[0209] An embodiment of the present disclosure further provides a display device, comprising the display panel in any of the above embodiments.

[0210] By using the display panel of any of the above embodiments, the reflectivity of the display device to light can be reduced, while the light transmittance of the display device can be greatly increased, thereby improving the display quality of the display device. Furthermore, the diffraction of ambient light by the display device can be reduced, thereby improving the appearance of the display device when the screen is off.

[0211] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, or a navigation system.

[0212] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, wherein: Including substrate, pixel circuit, pixel unit array and color film layer, The pixel circuit, the pixel unit array and the color filter layer are sequentially stacked on one side of the substrate; The pixel unit includes a first sub-pixel and a second sub-pixel, the aperture ratio of the first sub-pixel is greater than the aperture ratio of the second sub-pixel, the number of openings of the first sub-pixel is greater than the number of openings of the second sub-pixel, and the number of the pixel circuits for driving the first sub-pixel is equal to the number of the pixel circuits for driving the second sub-pixel; The color filter layer includes a first color resist and a second color resist, wherein the orthographic projection of the first color resist on the substrate covers the orthographic projection of the opening of the first sub-pixel on the substrate, and the orthographic projection of the second color resist on the substrate covers the orthographic projection of the opening of the second sub-pixel on the substrate; The orthographic projection shapes of the first color resist and the second color resist on the substrate include shapes with at least a portion of edges being arc-shaped.

2. The display panel according to claim 1, wherein: The pixel unit further includes a third sub-pixel, The aperture ratio of the first sub-pixel is greater than the aperture ratio of the third sub-pixel, the number of openings of the first sub-pixel is greater than the number of openings of the third sub-pixel, and the number of the pixel circuits for driving the first sub-pixel is equal to the number of the pixel circuits for driving the third sub-pixel; The color filter layer further includes a third color resist, and the orthographic projection of the third color resist on the substrate covers the orthographic projection of the opening of the third sub-pixel on the substrate; The orthographic projection shape of the third color barrier on the substrate includes at least a portion of the edges being arc-shaped. shape.

3. The display panel according to claim 2, wherein: The size ratio of the orthographic projection shape of the first color resist on the substrate in the row direction and the column direction of the pixel unit array is in the range of 0.8 to 1.2; The size ratio of the orthographic projection shape of the second color resist on the substrate in the row direction and the column direction of the pixel unit array is in the range of 0.8 to 1.2; The ratio of the dimensions of the orthographic projection shape of the third color resist on the substrate in the row direction and the column direction of the pixel unit array is in the range of 0.8 to 1.

2.

4. The display panel according to claim 2, wherein: The orthographic projection shape of the first color resist on the substrate is a symmetrical shape along the row direction and the column direction of the pixel unit array; The orthographic projection shape of the second color resist on the substrate is a symmetrical shape along the row direction and the column direction of the pixel unit array; The orthographic projection shape of the third color resist on the substrate is a symmetrical shape along the row direction and the column direction of the pixel unit array.

5. The display panel according to any one of claims 2 to 4, wherein: The orthographic projection shape of the opening of the first sub-pixel on the substrate is the same as the orthographic projection shape of the first color resist on the substrate; The orthographic projection shape of the opening of the second sub-pixel on the substrate is the same as the orthographic projection shape of the second color resist on the substrate; The orthographic projection shape of the opening of the third sub-pixel on the substrate is the same as the orthographic projection shape of the third color resist on the substrate.

6. The display panel according to claim 5, wherein: The first sub-pixel has two openings; The second sub-pixel has an opening; The third sub-pixel has an opening; The second sub-pixel and the third sub-pixel in the pixel unit are arranged along a first direction, the second sub-pixel and the first sub-pixel are arranged along a second direction; the third sub-pixel and the first sub-pixel are arranged along the second direction; The two openings of the first sub-pixel in the pixel unit are arranged along the first direction; The first direction is a column direction of the pixel unit array, and the second direction is a row direction of the pixel unit array.

7. The display panel according to claim 6, wherein: The second sub-pixel openings and one of the first sub-pixel openings located in the first row and adjacent to each other, and the third sub-pixel opening and another of the first sub-pixel openings located in the second row and adjacent to each other constitute one of the pixel units; The first row and the second row are adjacent to each other, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one of the first sub-pixel openings and another of the first sub-pixel openings are located in the same column.

8. The display panel according to claim 6, wherein: The second sub-pixel opening located in the first row, the third sub-pixel opening located in the second row and adjacent to each other, one first sub-pixel opening, and another first sub-pixel opening located in the third row constitute one pixel unit; The first row, the second row and the third row are arranged in sequence along the first direction, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one first sub-pixel opening and another first sub-pixel opening are located in the same column.

9. The display panel according to claim 6, wherein: In the pixel units of odd columns, the second sub-pixel opening located in the first row, the third sub-pixel opening located in the second row and adjacent to one of the first sub-pixel openings, and another first sub-pixel opening located in the third row constitute one pixel unit; The first row, the second row and the third row are arranged in sequence along the first direction, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one first sub-pixel opening and another first sub-pixel opening are located in the same column; In the pixel units of even-numbered columns, the second sub-pixel openings and one of the first sub-pixel openings located in the first row and adjacent to each other and the third sub-pixel opening and another of the first sub-pixel openings located in the second row and adjacent to each other constitute one of the pixel units; The first row and the second row are adjacent to each other, and the second sub-pixel opening and the third sub-pixel opening are located in the same column, and one of the first sub-pixel openings and another of the first sub-pixel openings are located in the same column.

10. The display panel according to any one of claims 6 to 9, wherein: The first sub-pixel includes a first anode; The first anode includes a first main body portion and a first connecting portion, the first main body portion and the first connecting portion are electrically connected, and the first connecting portion is electrically connected to the pixel circuit of the first sub-pixel; The second sub-pixel includes a second anode; The second anode includes a second main body portion and a second connecting portion, the second main body portion and the second connecting portion are electrically connected, and the second connecting portion and the pixel circuit of the second sub-pixel are electrically connected; The third sub-pixel includes a third anode; The third anode comprises a third main body portion and a third connecting portion, the third main body portion and the third connecting portion are electrically connected, and the third connecting portion is electrically connected to the pixel circuit of the third sub-pixel; The orthographic projection shape of the first main body on the substrate is the same as or similar to the orthographic projection shape of the first color resist on the substrate; The orthographic projection shape of the second main body on the substrate is the same as or similar to the orthographic projection shape of the second color resist on the substrate; The orthographic projection shape of the third main body portion on the substrate is the same as or similar to the orthographic projection shape of the third color resist on the substrate.

11. The display panel according to claim 2, wherein: The first sub-pixel, the second sub-pixel and the third sub-pixel have different colors, The areas of the openings in the first sub-pixel are different; The shortest distance between the opening outlines of the first sub-pixel opening and the second sub-pixel opening adjacent to each other in the pixel unit is greater than 10 μm; The shortest distance between opening contours of the second sub-pixel opening and the third sub-pixel opening adjacent to each other in the pixel unit is greater than 10 μm.

12. The display panel according to claim 7, wherein: The same side contour of the second sub-pixel opening and one of the first sub-pixel openings located in the same row in the pixel unit is located on a first straight line, The same side contour of the third sub-pixel opening and another first sub-pixel opening located in the same row in the pixel unit is located on a second straight line, The same side contours of the second sub-pixel opening and the third sub-pixel opening located in the same column in the pixel unit are located on a third straight line, The same side contours of one first sub-pixel opening and another first sub-pixel opening in the same column of the pixel unit are located on a fourth straight line, The first straight line, the second straight line, the third straight line and the fourth straight line are spliced ​​to form a rectangle, The orthographic projections of the two openings of the first sub-pixel, the second sub-pixel opening, and the third sub-pixel opening in the pixel unit on the substrate are located within the orthographic projection of the rectangle on the substrate.

13. The display panel according to claim 7, wherein: The centers of the second sub-pixel openings and one first sub-pixel opening located in the same row in the pixel unit are located on a first straight line, The centers of the third sub-pixel opening and another first sub-pixel opening located in the same row in the pixel unit are located on a second straight line, The centers of the second sub-pixel opening and the third sub-pixel opening located in the same column in the pixel unit are located on a third straight line, The centers of one of the first sub-pixel openings and another of the first sub-pixel openings in the same column in the pixel unit are located on a fourth straight line, The first straight line, the second straight line, the third straight line and the fourth straight line are spliced ​​to form a rectangle.

14. The display panel according to any one of claims 2 to 4, wherein: The first sub-pixel comprises a blue sub-pixel; The second sub-pixel includes a green sub-pixel; The third sub-pixel includes a red sub-pixel; The opening area of ​​the first sub-pixel is larger than the opening area of ​​the second sub-pixel, and the opening area of ​​the second sub-pixel is larger than the opening area of ​​the third sub-pixel; The ratio range of the opening area of ​​the second sub-pixel to the first sub-pixel in the pixel unit is 1:(1,3]; The area ratio range of the opening of the third sub-pixel and any opening of the first sub-pixel in the pixel unit is 1:(0, 3].

15. The display panel according to any one of claims 2 to 4, wherein: The first sub-pixel comprises a green sub-pixel; The second sub-pixel includes a blue sub-pixel; The third sub-pixel includes a red sub-pixel; The opening area of ​​the first sub-pixel is larger than the opening area of ​​the second sub-pixel, and the opening area of ​​the second sub-pixel is larger than the opening area of ​​the third sub-pixel; The ratio range of the opening area of ​​the second sub-pixel to the first sub-pixel in the pixel unit is 1:(1,3]; The area ratio range of the opening of the third sub-pixel and any opening of the first sub-pixel in the pixel unit is 1:(0, 3].

16. The display panel according to any one of claims 6 to 9, wherein: The first sub-pixel includes a first anode; The first anodes corresponding to all openings of the first sub-pixel in the pixel unit are connected as one.

17. The display panel according to claim 16, wherein: The pixel circuit comprises a first connection electrode, The first connecting electrode is located on a side of the first anode close to the substrate; a first flat layer is provided between the first connecting electrode and the first anode; The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first anode on the substrate, the first flat layer is provided with a first via hole in the overlapping area of ​​the orthographic projections, and the first anode is connected to the first connecting electrode through the first via hole; An orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate.

18. The display panel according to any one of claims 6 to 9, wherein: The first sub-pixel includes a first anode; The first anode includes a plurality of sub-electrodes, and the plurality of sub-electrodes are distributed at intervals; The orthographic projections of the openings of the first sub-pixels in the pixel unit on the substrate are respectively located within different orthographic projection regions of the sub-electrodes on the substrate.

19. The display panel according to claim 18, wherein: The pixel circuit comprises a first connection electrode and a second connection electrode, The first connecting electrode and the second connecting electrode are arranged in the same layer; The first connecting electrode and the second connecting electrode are located on a side of the first anode close to the substrate; A first planar layer is provided between the first anode and the first connecting electrode and the second connecting electrode; The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of one of the sub-electrodes of the first anode on the substrate, the first flat layer is provided with a first via hole in the overlapping area of ​​the orthographic projections, and one of the sub-electrodes of the first anode is connected to the first connecting electrode through the first via hole; An orthographic projection of the first via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate; The orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projections of any two adjacent sub-electrodes of the first anode on the substrate, and the first flat layer is further provided with a second via hole in the orthographic projection overlapping region, and any two adjacent sub-electrodes of the first anode are respectively connected to the second connecting electrode through the second via hole; An orthographic projection of the second via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate.

20. The display panel according to claim 19, wherein: The orthographic projection of the second connecting electrode on the substrate is located between the orthographic projections of any two adjacent sub-electrodes of the first anode on the substrate, At least a portion of an orthographic projection of the second connecting electrode on the substrate does not overlap with the orthographic projections of any two adjacent sub-electrodes of the first anode on the substrate.

21. The display panel according to claim 19, wherein: The orthographic projections of the first via hole and the second via hole on the substrate are located within an orthographic projection region of the pixel circuit of the first sub-pixel on the substrate.

22. The display panel according to claim 17 or 19, wherein: The pixel circuit further includes a first driving transistor, The first driving transistor is located on a side of the first connecting electrode close to the substrate, and a second planar layer is provided between the first driving transistor and the first connecting electrode; The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first driving transistor on the substrate, the second flat layer is provided with a third via hole in the overlapping area of ​​the orthographic projections, and the first connecting electrode is connected to the first electrode of the first driving transistor through the third via hole; An orthographic projection of the third via hole on the substrate does not overlap with an orthographic projection of the opening of the first sub-pixel on the substrate.

23. The display panel according to claim 22, wherein: The second sub-pixel includes a second anode; The pixel circuit further includes a third connecting electrode, The third connecting electrode is arranged in the same layer as the first connecting electrode; The third connecting electrode is located on a side of the second anode close to the substrate; The said A flat layer also extends between the third connecting electrode and the second anode; The orthographic projection of the third connection electrode on the substrate overlaps at least partially with the orthographic projection of the second anode on the substrate, the first flat layer is further provided with a fourth via hole in the overlapping area of ​​the orthographic projections, and the second anode is connected to the third connection electrode through the fourth via hole; An orthographic projection of the fourth via hole on the substrate does not overlap with an orthographic projection of the opening of the second sub-pixel on the substrate; The third sub-pixel includes a third anode; The pixel circuit further includes a fourth connection electrode, The fourth connecting electrode is arranged in the same layer as the first connecting electrode; The fourth connection electrode is located on a side of the third anode close to the substrate; the first flat layer also extends between the fourth connection electrode and the third anode; The orthographic projection of the fourth connection electrode on the substrate at least partially overlaps with the orthographic projection of the third anode on the substrate, the first flat layer further has a fifth via hole in the orthographic projection overlapping region, and the third anode is connected to the fourth connection electrode through the fifth via hole; An orthographic projection of the fifth via hole on the substrate does not overlap with an orthographic projection of the opening of the third sub-pixel on the substrate.

24. The display panel according to claim 23, wherein: The orthographic projection of the fourth via hole on the substrate is located in the orthographic projection area of ​​the pixel circuit of the second sub-pixel on the substrate; The orthographic projection of the fifth via hole on the substrate is located within the orthographic projection region of the pixel circuit of the third sub-pixel on the substrate.

25. The display panel according to claim 23, wherein: The pixel circuit further includes a second driving transistor, The second driving transistor is located on a side of the third connecting electrode close to the substrate, The second planar layer further extends between the second driving transistor and the third connecting electrode; The orthographic projection of the third connection electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second driving transistor on the substrate, and the second flat layer is further provided with a sixth via hole in the overlapping area of ​​the orthographic projections, and the third connection electrode is connected to the first electrode of the second driving transistor through the sixth via hole; The orthographic projection of the sixth via hole on the substrate does not overlap with the orthographic projection of the opening of the second sub-pixel on the substrate; The pixel circuit further includes a third driving transistor, The third driving transistor is located at a side of the fourth connecting electrode close to the substrate, and the second flat layer further extends between the third driving transistor and the fourth connecting electrode; The orthographic projection of the fourth connection electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the third driving transistor on the substrate, and the second flat layer is further provided with a seventh via hole in the orthographic projection overlapping region, and the fourth connection electrode is connected to the first electrode of the third driving transistor through the seventh via hole; An orthographic projection of the seventh via hole on the substrate does not overlap with an orthographic projection of the opening of the third sub-pixel on the substrate.

26. The display panel according to claim 2, wherein: The orthographic projections of the first color resist, the second color resist and the third color resist on the substrate do not overlap with each other; The color filter layer further includes a black matrix, and a pattern of the black matrix is ​​complementary to patterns of the first color resist, the second color resist, and the third color resist.

27. The display panel according to claim 1, wherein: It also includes a packaging layer, a touch layer and a cover plate. The encapsulation layer and the touch layer are located between the pixel unit array and the color filter layer, and the encapsulation layer and the touch layer are sequentially stacked on the pixel unit array near the color filter layer. one side; The cover plate is located on a side of the color filter layer facing away from the substrate.

28. A display device, wherein: A display panel comprising any one of claims 1-27.

Images