Current detection circuit, monitoring and control chip of optical module, optical module and equipment

Abstract

The invention provides a current detection circuit, a monitoring and control chip of an optical module, the optical module and equipment. The current detection circuit arranged in the optical module comprises a current output module, a current detection module, a level conversion and voltage amplification module and a voltage acquisition and digital calibration module which are sequentially connected in series, the current output module provides load current for the optical module load; the current detection module is used for converting load current into voltage drop on an internal detection resistor; the level conversion and voltage amplification module converts the level of the voltage drop and amplifies the level to obtain a first output voltage; the voltage acquisition and digital calibration module converts the first output voltage into a digital voltage signal, and calibrates the digital voltage signal to obtain a voltage calibration value corresponding to the load current. The load current of the optical module load is detected through the current detection circuit, conversion from a negative voltage domain to a positive voltage domain is achieved, errors introduced by the optical module are calibrated, and the requirements for high reliability and low cost are met while the detection precision is improved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a current detection circuit, a monitoring and control chip for an optical module, an optical module, and related equipment. Background Technology

[0002] With the rapid rise of AI (Artificial Intelligence) and cloud computing technologies, the requirements for optical module systems that convert electrical signals to optical signals are becoming increasingly stringent. Optical modules are developing towards higher speeds, lower power consumption, and lower costs. For optical modules, the internal lasers and detectors are extremely sensitive to temperature. Temperature increases caused by high power consumption can directly lead to decreased performance and reliability, or even permanent damage. As a component of the optical module, the monitoring and control chip needs to strictly monitor the load current of the optical module (laser) to avoid the fatal impact of prolonged high power consumption and heat generation on the optical module system.

[0003] Traditional current detection circuits are typically implemented using off-chip discrete components, which results in relatively high costs. Summary of the Invention

[0004] The technical problem to be solved by this disclosure is to address the aforementioned deficiencies in the prior art, and to provide a current detection circuit, a monitoring and control chip for an optical module, an optical module, and a device.

[0005] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0006] This disclosure provides a current detection circuit, which is disposed inside an optical module. The current detection circuit includes: a current output module, a current detection module, a level conversion and voltage amplification module, and a voltage acquisition and digital calibration module connected in series.

[0007] The current output module is used to provide load current to the optical module load outside the optical module;

[0008] The current detection module includes a detection resistor, and the current detection module is used to convert the load current into a voltage drop across the detection resistor;

[0009] The level conversion and voltage amplification module is used to convert the voltage drop and amplify it to obtain a first output voltage, the first output voltage being matched with the measurement range of the voltage acquisition and digital calibration module;

[0010] The voltage acquisition and digital calibration module is used to convert the first output voltage into a digital voltage signal and calibrate the digital voltage signal to obtain a voltage calibration value; wherein the voltage calibration value corresponds to the current detection value of the load current.

[0011] Optionally, the current output module includes: a first PMOS (P-channel metal-oxide-semiconductor) transistor and a first NMOS (N-channel metal-oxide-semiconductor) transistor;

[0012] The gate of the first PMOS transistor is connected to a first control signal, the gate of the first NMOS transistor is connected to a second control signal, the source of the first PMOS transistor is grounded, and the source of the first NMOS transistor is connected to a negative power supply voltage.

[0013] The drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor and the load of the optical module, respectively.

[0014] The drain of the first PMOS transistor is used as the output terminal of the current output module and connected to the input terminal of the current detection module.

[0015] Optionally, the current detection module includes: a second PMOS transistor, a second NMOS transistor, the detection resistor, a first operational amplifier, a first switch, and a second switch;

[0016] The non-inverting input terminal of the first operational amplifier is used as the input terminal of the current detection module;

[0017] The gate of the second PMOS transistor is connected to the first control signal, the gate of the second NMOS transistor is connected to the second control signal, the source of the second PMOS transistor is grounded, and the source of the second NMOS transistor is connected to the negative voltage of the power supply.

[0018] The drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor, the inverting input terminal of the first operational amplifier, the first terminal of the detection resistor, and the first terminal of the second switch, respectively.

[0019] The second end of the detection resistor is electrically connected to the output terminal of the first operational amplifier and the first end of the first switch, respectively; the second end of the first switch is electrically connected to the second end of the second switch.

[0020] The non-inverting power supply terminal of the first operational amplifier is grounded, and the inverting power supply terminal of the first operational amplifier is connected to the negative voltage of the power supply.

[0021] The second terminal of the first switch is used as the output terminal of the current detection module and connected to the input terminal of the level conversion and voltage amplification module.

[0022] Optionally, the level conversion and voltage amplification module includes: a first capacitor, a second capacitor, a third switch, and a second operational amplifier;

[0023] The first terminal of the first capacitor is used as the input terminal of the level conversion and voltage amplification module, and connected to the output terminal of the current detection module;

[0024] The second terminal of the first capacitor is electrically connected to the first terminal of the second capacitor, the first terminal of the third switch, and the inverting input terminal of the second operational amplifier, respectively.

[0025] The non-inverting input terminal of the second operational amplifier is connected to a reference voltage, the non-inverting power supply terminal of the second operational amplifier is connected to a positive power supply voltage, and the inverting power supply terminal of the second operational amplifier is grounded.

[0026] The output terminal of the second operational amplifier is electrically connected to the second terminal of the second capacitor and the second terminal of the third switch, respectively.

[0027] The output terminal of the second operational amplifier is used as the output terminal of the level conversion and voltage amplification module, and connected to the input terminal of the voltage acquisition and digital calibration module.

[0028] Optionally, the voltage acquisition and digital calibration module includes: an analog-to-digital conversion submodule and a digital calibration submodule;

[0029] The analog-to-digital conversion submodule is used as the input terminal of the voltage acquisition and digital calibration module. The output terminal of the analog-to-digital conversion submodule is electrically connected to the input terminal of the digital calibration submodule, and the output terminal of the digital calibration submodule is used as the output terminal of the voltage acquisition and digital calibration module.

[0030] The analog-to-digital conversion submodule is used to convert the first output voltage into the digital voltage signal;

[0031] The digital calibration submodule is used to calibrate the digital voltage signal to obtain the voltage calibration value.

[0032] Optionally, the digital calibration submodule is used to calculate the voltage calibration value using a first preset functional relationship when the digital voltage signal meets the judgment condition; and to calculate the voltage calibration value using a second preset functional relationship when the digital voltage signal does not meet the judgment condition.

[0033] Optionally, the judgment condition is codex + (2 N-1 The highest bit of the binary calculation result of -code0 is 1;

[0034] The first preset functional relationship is represented by the following formula:

[0035] code_det = (codex+(2 N-1 -code0)-2 N-1)*K2_real+2 N-1 ;

[0036] The second preset functional relationship is expressed by the following formula:

[0037] code_det = ~(~(codex+(2 N-1 -code0))*K2_real);

[0038] Wherein, code_det represents the voltage calibration value, codex represents the digital voltage signal, N represents the number of bits of the digital voltage signal, code0 represents the initial digital voltage signal when there is no optical module load, K2_real represents the gain of the voltage acquisition and digital calibration module, and ~ represents inversion;

[0039] And / or,

[0040] The total gain of the current output module, the current detection module, and the level conversion and voltage amplification module is less than 1, while the gain of the voltage acquisition and digital calibration module is greater than 1.

[0041] This disclosure also provides a monitoring and control chip for an optical module, the monitoring and control chip for the optical module including the aforementioned current detection circuit.

[0042] This disclosure also provides an optical module, the optical module including a processor and the aforementioned monitoring and control chip for the optical module;

[0043] The processor is communicatively connected to the current detection circuit in the monitoring and control chip of the optical module.

[0044] The processor is used to obtain a voltage calibration value from the current detection circuit and obtain a current detection value of the load current based on the voltage calibration value.

[0045] This disclosure also provides an electronic device, which includes the aforementioned optical module.

[0046] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0047] The positive and progressive effects of this disclosure are as follows: by detecting the load current of the optical module load through the current detection circuit inside the chip, a voltage calibration value is obtained. The voltage calibration value corresponds to the current detection value of the load current. Without using high-voltage devices, it can not only realize the conversion from the negative voltage domain to the positive voltage domain, but also use the existing analog-to-digital converter (ADC) submodule inside the chip to collect the error introduced by the current detection circuit itself and perform calibration in a digital way, thereby improving the detection accuracy while meeting the requirements of high reliability and low cost of optical module system. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of a current detection circuit provided in Embodiment 1 of this disclosure;

[0049] Figure 2 The circuit structure diagram of a current detection circuit provided in Embodiment 1 of this disclosure;

[0050] Figure 3 This is a schematic diagram of an optical module provided in Embodiment 3 of this disclosure. Detailed Implementation

[0051] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0052] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0053] Example 1

[0054] This disclosure provides a current detection circuit, with reference to... Figure 1 The current detection circuit is located inside the optical module. The current detection circuit includes: a current output module 1, a current detection module 2, a level conversion and voltage amplification module 3, and a voltage acquisition and digital calibration module 4 connected in series.

[0055] The current output module 1 is used to provide load current to the optical module load outside the optical module.

[0056] The current detection module 2 includes a detection resistor, which is used to convert the load current into a voltage drop across the detection resistor.

[0057] The level conversion and voltage amplification module 3 is used to convert the voltage drop to a level and amplify it to obtain the first output voltage, which is matched with the measurement range of the voltage acquisition and digital calibration module 4.

[0058] The voltage acquisition and digital calibration module 4 is used to convert the first output voltage into a digital voltage signal and calibrate the digital voltage signal to obtain a voltage calibration value. The voltage calibration value corresponds to the current detection value of the load current.

[0059] in, Figure 2 The circuit diagram of the current sensing circuit is shown. The optical module load within the dashed box is not part of the current sensing circuit. The current sensing circuit is located inside the chip within the optical module. Typically, the reference voltage Vref should be less than Vs / 2, where Vs represents the positive power supply voltage.

[0060] Current output module 1 supports both current pull (I1) and current sink (I2). When the external optical module load pulls current from the chip, the load current is I1. M3 is a mirror image of M1, and part of the current flows through the sensing resistor Rs, generating a voltage drop of Rs*I3 across Rs. At this time, V2 > Vo1. When the external optical module load sinks current into the chip, the load current is I2. M4 is a mirror image of M2, and part of the current flows through the sensing resistor Rs, generating a voltage drop of Rs*I4 across the resistor. At this time, Vo1 > V2.

[0061] The current detection module 2 uses operational amplifier A1 to clamp the Vds (voltage difference between drain and source) of M3 and M1, and M4 and M2, improving accuracy while converting the current output I1 / I2 into a voltage drop across the sensing resistor Rs. If a large current flows out when V1 is small or a large current flows in when V1 is large, a large value for the sensing resistor Rs may cause the operational amplifier A1 to malfunction. Therefore, the value of the sensing resistor Rs should not be too large. In this embodiment, the voltage drop across the sensing resistor Rs is around several hundred millivolts. Both the current output and current detection are in the negative voltage domain -Vs, while the chip already has an ADC (analog-to-digital converter submodule 41) and a digital calibration circuit (digital calibration submodule 42) in the positive voltage domain Vs. The existing ADC (analog-to-digital converter submodule 41) can be used to sample other voltage signals within the chip.

[0062] When the voltage range is 0 to Vs, a conventional Vs device can be used for design. When the voltage range is -Vs to +Vs, using a Vs device will result in overvoltage. If a 2*Vs high-voltage device is used for design, it will lead to an increase in cost.

[0063] To save costs, this embodiment does not use a high-voltage tube, therefore a level conversion and voltage amplification module 3 is required to convert the power supply negative voltage -Vs to the power supply positive voltage Vs.

[0064] A2, including circuits such as C1 and C2, mainly realizes the conversion from the negative voltage domain -Vs to the positive voltage domain Vs, while amplifying the voltage drop of the detection resistor Rs so that it falls within the quantization range of the analog-to-digital conversion submodule 41, resulting in higher voltage acquisition accuracy when I1 / I2 is smaller.

[0065] The specific principle of level conversion and voltage amplification module 3 is as follows. When φ1 and φ3 are closed and φ2 is open, Vo2 represents the first output voltage, Vo2 = Vn2. Since A1 is virtually shorted, Vn2 = Vref, therefore Vo2 = Vref. When φ2 is closed and φ1 and φ3 are open, according to the law of charge conservation, the following formula can be derived:

[0066]

[0067]

[0068] Where I3 = K * I1, I4 = K * I2, and the quantization range of the analog-to-digital conversion submodule 41 is 2Vref, K is a scaling factor, and the same scaling factor is used between I3 and I1, and between I4 and I2. If K * I1 * Rs * C1 / C2 or K * I2 * Rs * C1 / C2 = Vref is designed, when current is drawn into the chip, the Vo2 voltage range is 0 ~ Vref, and when current is drawn into the chip, the Vo2 voltage range is Vref ~ 2Vref.

[0069] In the above formula, C1 / C2 can be matched with MIM (metal-insulator-metal capacitor) capacitors, which can not only achieve high-precision matching, but also be used as a voltage-resistant device to convert negative voltage -Vs to positive voltage Vs (Vs does not exceed 6V). However, if the process error of the detection resistor Rs reaches more than 15%, Vo2 will exceed the input range of the analog-to-digital conversion submodule 41, resulting in a loss of detection accuracy.

[0070] In this embodiment, K*I*Rs*C1 / C2 (assuming I1=I2=I) is processed into K*I*Rs*C1 / C2*K1*K2. The total gain K1 (K1<1) of the current output module 1, current detection module 2, and level conversion and voltage amplification module 3, and the gain K2 (K2>1) of the voltage acquisition and digital calibration module 4 not only meet the input range of the analog-to-digital conversion submodule 41 but also achieve process calibration of the detection resistor Rs. In addition, the error of operational amplifier A2 (i.e., the resulting offset voltage) can also be calibrated by the digital calibration circuit.

[0071] Assuming the error (offset) of A2 is Vos2, then the Vo2 formula is updated as follows:

[0072]

[0073]

[0074] According to the input-output conversion formula of the N-bit analog-to-digital converter submodule 41, code = vin / (2Vref / 2 NThe hardware implementation of the analog-to-digital conversion submodule (ADC) is existing technology and will not be described in detail here.

[0075] After being converted by analog-to-digital converter submodule 41, Vo2 is output as a digital voltage signal code:

[0076]

[0077]

[0078] It can be seen from the formula that 2 N-1 *Vos2 / Vref are fixed offsets that can be corrected using the digital calibration submodule 42.

[0079] The digital calibration submodule 42 is implemented using digital circuitry.

[0080] During the pre-shipment testing of the chip, it is necessary to determine the measured value K2_real of the gain coefficient K2 of the digital calibration submodule 42, and substitute the measured value K2_real into K2 for calculation; at the same time, it is also necessary to determine the initial digital voltage signal code0 corresponding to the absence of optical module load.

[0081] Determine K2_real and code0 using the following steps:

[0082] (1) When there is no load outside the chip (i.e., the optical module load), measure the Vo2 voltage and record the output of the analog-to-digital conversion submodule 41 as code0.

[0083] (2) Increase the load on the chip so that the chip pull current reaches the maximum pull current Imax, measure the Vo2 voltage, and record the output of the analog-to-digital conversion submodule 41 as code1.

[0084] (3) Calculate and store K2_real, K2_real=2 N / code1.

[0085] Among them, code0 and code1 only need to be measured once. code0 and K2_real can be stored in the chip's OTP (a one-time programmable memory) or efuse (a one-time programmable memory) for subsequent current detection calculations.

[0086] After the chip leaves the factory, for the digital calibration submodule 42, the relationship between the voltage calibration value code_det and the load current Idet can be obtained, as shown in the following formula:

[0087]

[0088] When the load current Idet is calculated to be a positive number, it represents the sinking current; when the load current Idet is calculated to be a negative number, it represents the sourcing current. The ADC resolution is selected according to the current detection accuracy requirements. A 10-bit ADC can achieve a precision accuracy of less than 1%.

[0089] In this embodiment, the load current of the optical module load is detected by the current detection circuit inside the chip to obtain the voltage calibration value. The voltage calibration value corresponds to the current detection value of the load current. Without using high voltage devices, it can not only realize the conversion from the negative voltage domain to the positive voltage domain, but also use the existing analog-to-digital converter (ADC) submodule inside the chip to collect the error introduced by the current detection circuit itself and perform calibration in a digital way. This improves the detection accuracy while meeting the requirements of high reliability and low cost of the optical module system.

[0090] In an optional embodiment, refer to Figure 2 The current output module 1 includes a first PMOS transistor M1 and a first NMOS transistor M2.

[0091] The gate of the first PMOS transistor M1 is connected to the first control signal Vgp, the gate of the first NMOS transistor M2 is connected to the second control signal Vgn, the source of the first PMOS transistor M1 is grounded, and the source of the first NMOS transistor M2 is connected to the negative power supply voltage -Vs.

[0092] The drain of the first PMOS transistor M1 is electrically connected to the drain of the first NMOS transistor M2 and the load of the optical module, respectively.

[0093] The drain of the first PMOS transistor M1 is used as the output terminal of the current output module 1 and connected to the input terminal of the current detection module 2.

[0094] In this embodiment, the current output module supports both pull-in current I1 and sink current I2. When the external optical module load pulls current from the chip, the load current is I1. M3 is a mirror image of M1, and part of the current flows through the sensing resistor Rs, generating a voltage drop of Rs*I3 across the sensing resistor. At this time, V2 > Vo1. When the external optical module load sinks current into the chip, the load current is I2. M4 is a mirror image of M2, and part of the current flows through the sensing resistor Rs, generating a voltage drop of Rs*I4 across the resistor. At this time, Vo1 > V2.

[0095] In an optional embodiment, refer to Figure 2 The current detection module 2 includes: a second PMOS transistor M3, a second NMOS transistor M4, a detection resistor Rs, a first operational amplifier A1, a first switch φ1, and a second switch φ2.

[0096] The non-inverting input terminal of the first operational amplifier A1 is used as the input terminal of the current detection module 2.

[0097] The gate of the second PMOS transistor M3 is connected to the first control signal Vgp, the gate of the second NMOS transistor M4 is connected to the second control signal Vgn, the source of the second PMOS transistor M3 is grounded, and the source of the second NMOS transistor M4 is connected to the negative power supply voltage -Vs.

[0098] The drain of the second PMOS transistor M3 is electrically connected to the drain of the second NMOS transistor M4, the inverting input terminal of the first operational amplifier A1, the first terminal of the detection resistor Rs, and the first terminal of the second switch φ2.

[0099] The second end of the sensing resistor Rs is electrically connected to the output terminal of the first operational amplifier A1 and the first end of the first switch φ1, respectively. The second end of the first switch φ1 is electrically connected to the second end of the second switch φ2.

[0100] The non-inverting power supply terminal of the first operational amplifier A1 is grounded, and the inverting power supply terminal of the first operational amplifier A1 is connected to the negative power supply voltage -Vs.

[0101] The second end of the first switch φ1 is used as the output end of the current detection module 2 and connected to the input end of the level conversion and voltage amplification module 3.

[0102] In this embodiment, the current detection module uses operational amplifier A1 to clamp Vds (the voltage difference between the drain and source) of M3 and M1, and M4 and M2, improving accuracy while converting the current output I1 / I2 into a voltage drop across the sensing resistor Rs. If a large current flows out when V1 is small or a large current flows in when V1 is large, a large value for the sensing resistor Rs may cause the operational amplifier A1 to malfunction. Therefore, the value of the sensing resistor Rs should not be too large. In this embodiment, the voltage drop across the sensing resistor Rs is around several hundred millivolts.

[0103] In an optional embodiment, refer to Figure 2 The level conversion and voltage amplification module 3 includes: a first capacitor C1, a second capacitor C2, a third switch φ3, and a second operational amplifier A2.

[0104] The first end of the first capacitor C1 is used as the input terminal of the level conversion and voltage amplification module 3, and connected to the output terminal of the current detection module 2.

[0105] The second terminal of the first capacitor C1 is electrically connected to the first terminal of the second capacitor C2, the first terminal of the third switch φ3, and the inverting input terminal of the second operational amplifier A2.

[0106] The non-inverting input terminal of the second operational amplifier A2 is connected to a reference voltage, the non-inverting power supply terminal of the second operational amplifier A2 is connected to a positive power supply voltage Vs, and the inverting power supply terminal of the second operational amplifier A2 is grounded.

[0107] The output terminal of the second operational amplifier A2 is electrically connected to the second terminal of the second capacitor C2 and the second terminal of the third switch φ3, respectively.

[0108] The output of the second operational amplifier A2 is used as the output of the level conversion and voltage amplification module 3, and connected to the input of the voltage acquisition and digital calibration module 4.

[0109] In this embodiment, high-voltage transistors are not used to save costs. The conversion from negative power supply voltage -Vs to positive power supply voltage Vs is achieved through level conversion and voltage amplification modules. At the same time, the voltage drop across the detection resistor Rs is amplified so that it falls within the quantization range of the analog-to-digital conversion submodule 41, resulting in higher voltage acquisition accuracy when I1 / I2 is smaller.

[0110] In an optional embodiment, refer to Figure 2 The voltage acquisition and digital calibration module 4 includes: analog-to-digital conversion submodule 41 and digital calibration submodule 42.

[0111] The analog-to-digital conversion submodule 41 is used as the input terminal of the voltage acquisition and digital calibration module 4. The output terminal of the analog-to-digital conversion submodule 41 is electrically connected to the input terminal of the digital calibration submodule 42, and the output terminal of the digital calibration submodule 42 is used as the output terminal of the voltage acquisition and digital calibration module 4.

[0112] The analog-to-digital converter submodule 41 is used to convert the first output voltage Vo2 into a digital voltage signal codex.

[0113] The digital calibration submodule 42 is used to calibrate the digital voltage signal codex to obtain the voltage calibration value code_det.

[0114] For the digital calibration submodule 42, in codex+(2 N-1 When the highest bit of the binary calculation result of -code0) is 1, the voltage calibration value code_det is obtained using the first preset function relationship:

[0115] code_det =(codex+(2 N-1 -code0)-2 N-1 )*K2_real+2 N-1 .

[0116] In codex+(2) N-1 When the highest bit of the binary calculation result of -code0) is 0, the voltage calibration value code_det is obtained by using the following formula to represent the second preset function relationship:

[0117] code_det = ~(~(codex+(2 N-1 -code0))*K2_real).

[0118] The relationship between the voltage calibration value code_det and the load current Idet can be obtained, as shown in the following formula:

[0119]

[0120] When the load current Idet is calculated to be a positive number, it represents the sinking current; when the load current Idet is calculated to be a negative number, it represents the sourcing current. The ADC resolution is selected according to the current detection accuracy requirements. For example, a 10-bit ADC can achieve a precision accuracy of less than 1%.

[0121] In this embodiment, the gain coefficient K1 (K1<1) designed for the analog-to-digital conversion submodule 41 and the gain coefficient K2 (K2>1) designed for the digital calibration submodule 42 not only meet the input range of the analog-to-digital conversion submodule 41 but also achieve process calibration of the sensing resistor Rs. In addition, the error of the operational amplifier A2 (i.e., the resulting offset voltage) can also be calibrated by the digital calibration circuit.

[0122] In an optional embodiment, the digital calibration submodule 42 is used to calculate the voltage calibration value code_det using a first preset function relationship when the digital voltage signal codex meets the judgment condition; and to calculate the voltage calibration value code_det using a second preset function relationship when the digital voltage signal codex does not meet the judgment condition.

[0123] In this embodiment, the voltage calibration value code_det is calculated using a first preset function relationship or a second preset function relationship, depending on whether the judgment condition is met.

[0124] In an optional embodiment, the determination condition is codex + (2 N-1 The highest bit of the binary calculation result of -code0 is 1.

[0125] The first presupposed functional relationship is expressed by the following formula:

[0126] code_det =(codex+(2 N-1 -code0)-2 N-1 )*K2_real+2 N-1 .

[0127] The second pre-defined functional relationship is expressed by the following formula:

[0128] code_det = ~(~(codex+(2 N-1 -code0))*K2_real).

[0129] Where code_det represents the voltage calibration value, codex represents the digital voltage signal, N represents the number of bits of the digital voltage signal, code0 represents the initial digital voltage signal when there is no optical module load, K2_real represents the gain of the voltage acquisition and digital calibration module 4, and ~ represents inversion.

[0130] This embodiment provides a specific implementation of the judgment conditions and the calculation of the voltage calibration value code_det.

[0131] In an optional embodiment, the total gain K1 of the current output module 1, the current detection module 2, and the level conversion and voltage amplification module 3 is less than 1, and the gain K2_real of the voltage acquisition and digital calibration module 4 is greater than 1.

[0132] In this embodiment, the total gain K1 (K1<1) of the current output module, current detection module, and level conversion and voltage amplification module, and the gain K2 (K2>1) of the voltage acquisition and digital calibration module, not only meet the input range of the voltage acquisition and digital calibration module but also achieve process calibration of the detection resistor Rs. Furthermore, the error of operational amplifier A2 (i.e., the resulting offset voltage) can also be calibrated by the digital calibration circuit.

[0133] Example 2

[0134] This disclosure provides a monitoring and control chip for an optical module, which includes the current detection circuit described in Embodiment 1.

[0135] In this embodiment, the load current of the optical module load is detected by the current detection circuit inside the chip to obtain the voltage calibration value. The voltage calibration value corresponds to the current detection value of the load current. Without using high voltage devices, it can not only realize the conversion from the negative voltage domain to the positive voltage domain, but also use the existing analog-to-digital converter (ADC) submodule inside the chip to collect the error introduced by the current detection circuit itself and perform calibration in a digital way. This improves the detection accuracy while meeting the requirements of high reliability and low cost of the optical module system.

[0136] Example 3

[0137] This disclosure provides an optical module, referring to... Figure 3 The optical module includes a processor 31 and a monitoring and control chip 32 for the optical module in Embodiment 2.

[0138] The processor 31 is communicatively connected to the current detection circuit in the monitoring and control chip 32 of the optical module.

[0139] The processor 31 is used to obtain a voltage calibration value from the current detection circuit and obtain a current detection value of the load current based on the voltage calibration value.

[0140] In this embodiment, the load current of the optical module load is detected by the current detection circuit inside the chip to obtain the voltage calibration value. The voltage calibration value corresponds to the current detection value of the load current. Without using high voltage devices, it can not only realize the conversion from the negative voltage domain to the positive voltage domain, but also use the existing analog-to-digital converter (ADC) submodule inside the chip to collect the error introduced by the current detection circuit itself and perform calibration in a digital way. This improves the detection accuracy while meeting the requirements of high reliability and low cost of the optical module system.

[0141] Example 4

[0142] This disclosure provides an electronic device, which includes the optical module described in embodiment 3.

[0143] In this embodiment, the load current of the optical module load is detected by the current detection circuit inside the chip to obtain the voltage calibration value. The voltage calibration value corresponds to the current detection value of the load current. Without using high voltage devices, it can not only realize the conversion from the negative voltage domain to the positive voltage domain, but also use the existing analog-to-digital converter (ADC) submodule inside the chip to collect the error introduced by the current detection circuit itself and perform calibration in a digital way. This improves the detection accuracy while meeting the requirements of high reliability and low cost of the optical module system.

[0144] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A current detection circuit, characterized by, The current detection circuit is arranged in the interior of the optical module, and comprises: a current output module, a current detection module, a level conversion and voltage amplification module, a voltage acquisition and digital calibration module connected in series. The current output module is configured to provide a load current to a load outside the optical module. The current detection module comprises a detection resistor, and is configured to convert the load current into a voltage drop on the detection resistor. The level conversion and voltage amplification module is configured to perform level conversion and amplification on the voltage drop to obtain a first output voltage, and the first output voltage matches a measurement range of the voltage acquisition and digital calibration module. The voltage acquisition and digital calibration module is configured to convert the first output voltage into a digital voltage signal, and calibrate the digital voltage signal to obtain a voltage calibration value, wherein the voltage calibration value corresponds to a current detection value of the load current.

2. The current sense circuit of claim 1, wherein, The current output module comprises a first PMOS tube and a first NMOS tube. A gate of the first PMOS tube is connected to a first control signal, a gate of the first NMOS tube is connected to a second control signal, a source of the first PMOS tube is grounded, and a source of the first NMOS tube is connected to a power negative voltage. A drain of the first PMOS tube is electrically connected to a drain of the first NMOS tube and the load of the optical module. The drain of the first PMOS tube is used as an output end of the current output module and is connected to an input end of the current detection module.

3. The current sense circuit of claim 2, wherein, The current detection module comprises a second PMOS tube, a second NMOS tube, the detection resistor, a first operational amplifier, a first switch and a second switch. A non-inverting input end of the first operational amplifier is used as an input end of the current detection module. A gate of the second PMOS tube is connected to the first control signal, a gate of the second NMOS tube is connected to the second control signal, a source of the second PMOS tube is grounded, and a source of the second NMOS tube is connected to the power negative voltage. A drain of the second PMOS tube is electrically connected to a drain of the second NMOS tube, a non-inverting input end of the first operational amplifier, a first end of the detection resistor and a first end of the second switch. A second end of the detection resistor is electrically connected to an output end of the first operational amplifier and a first end of the first switch, and a second end of the first switch is electrically connected to a second end of the second switch. A non-inverting power supply end of the first operational amplifier is grounded, and an inverting power supply end of the first operational amplifier is connected to the power negative voltage. The second end of the first switch is used as an output end of the current detection module and is connected to an input end of the level conversion and voltage amplification module.

4. The current sense circuit of any one of claims 1-3, wherein, The level conversion and voltage amplification module comprises a first capacitor, a second capacitor, a third switch and a second operational amplifier. A first end of the first capacitor is used as an input end of the level conversion and voltage amplification module and is connected to an output end of the current detection module. A second end of the first capacitor is electrically connected with a first end of the second capacitor, a first end of the third switch and an inverting input end of the second operational amplifier respectively; A non-inverting input end of the second operational amplifier is connected with a reference voltage, a non-inverting power supply end of the second operational amplifier is connected with a positive voltage of a power supply, and an inverting power supply end of the second operational amplifier is grounded; An output end of the second operational amplifier is electrically connected with a second end of the second capacitor and a second end of the third switch respectively; The output end of the second operational amplifier is used as an output end of the level conversion and voltage amplification module, and an input end of the voltage acquisition and digital calibration module is connected.

5. The current sense circuit of claim 4, wherein, The voltage acquisition and digital calibration module comprises an analog-digital conversion sub-module and a digital calibration sub-module; The analog-digital conversion sub-module is used as the input end of the voltage acquisition and digital calibration module, an output end of the analog-digital conversion sub-module is electrically connected with an input end of the digital calibration sub-module, and an output end of the digital calibration sub-module is used as the output end of the voltage acquisition and digital calibration module; The analog-digital conversion sub-module is configured to convert the first output voltage into the digital voltage signal; The digital calibration sub-module is configured to calibrate the digital voltage signal to obtain the voltage calibration value.

6. The current sense circuit of claim 5, wherein, The digital calibration sub-module is configured to, when the digital voltage signal satisfies a judgment condition, calculate the voltage calibration value by using a first preset function relationship; and when the digital voltage signal does not satisfy the judgment condition, calculate the voltage calibration value by using a second preset function relationship.

7. The current sense circuit of claim 6, wherein, The judgment condition is that the highest bit of the binary calculation result of codex+(2 N-1 -code0) is 1. The first preset function relationship is represented by the following formula: code_det = (codex+(2 N-1 -code0)-2 N-1 )*K2_real+2 N-1 ; The second preset function relationship is represented by the following formula: code_det = ~ (~ (code x + (2 N-1 - code0) * K2_real); Wherein, code_det represents the voltage calibration value, codex represents the digital voltage signal, N represents the bit number of the digital voltage signal, code0 represents an initial digital voltage signal corresponding to no load of the optical module, K2_real represents the gain of the voltage acquisition and digital calibration module, and ~ represents negation; And / or, The total gain of the current output module, the current detection module and the level conversion and voltage amplification module is less than 1, and the gain of the voltage acquisition and digital calibration module is greater than 1.

8. A monitoring and control chip for an optical module, characterized by comprising: The monitoring and control chip of the optical module comprises the current detection circuit according to any one of claims 1 to 7.

9. An optical module characterized by comprising: The optical module comprises a processor and the monitoring and control chip of the optical module according to claim 8; The processor is in communication connection with the current detection circuit in the monitoring and control chip of the optical module; The processor is configured to acquire the voltage calibration value from the current detection circuit, and obtain the current detection value of the load current based on the voltage calibration value.

10. An electronic device, comprising: The electronic device comprises the optical module according to claim 9.

Images