A level shift structure for a super large array ultra-low temperature infrared image sensor

By employing a combination of high and low threshold devices and level conversion clamping matching technology in an ultra-large array ultra-low temperature infrared image sensor, the problem of signal conversion failure was solved, achieving highly reliable level conversion and improving the reliability and stability of the sensor.

CN115694471BActive Publication Date: 2026-05-29XIAN MICROELECTRONICS TECH INST
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Patent Information

Application Number
CN202211339506.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-10-25
Publication Date
2026-05-29
Estimated Expiration
2042-10-25

AI Technical Summary

Technical Problem

In ultra-large array ultra-low temperature infrared image sensors, the traditional low-voltage to high-voltage circuit structure causes the signal to fail to complete level conversion smoothly under ultra-low temperature conditions, resulting in some signals failing to start and causing functional failure.

Method used

By employing a hybrid high- and low-threshold device technology and a level-shifting clamping matching technology, a low-voltage input transistor is added to the high-voltage-domain level-shifting structure. The clamping matching circuit stabilizes the source-drain voltage of the signal input transistor, ensuring that it is within the normal operating voltage range and avoiding the risk of breakdown.

Benefits of technology

It achieves highly reliable level switching under ultra-low temperature conditions, ensuring that the signal can be turned on smoothly in the high voltage domain, thereby improving the reliability and stability of the image sensor.

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Abstract

This invention discloses a level shifting structure for an ultra-large area array ultra-low temperature infrared image sensor, comprising a conversion signal input transistor; a level clamping transistor whose gate receives a level VREF, and whose source is connected to the source of a feedback transistor, the gate of an inverting N-transistor, and the gate of an inverting P-transistor; the drain of the level clamping transistor connected to the source of the conversion signal input transistor; the drain of the conversion signal input transistor grounded; the gate of the conversion signal input transistor connected to IP; the drain of the feedback transistor connected to the source of a pull-up transistor, whose gate is connected to IP, and whose drain is connected to power supply VDD; the source of the inverting P-transistor connected to power supply VDD, whose drain is connected to the source of the inverting N-transistor, and whose drain is grounded; and a level VREF generated by a level VREF clamping matching voltage generation circuit. This ensures that the source-drain voltage of the conversion signal input transistor (low threshold transistor) does not exceed 1.2V, ensuring that the device operates within its normal voltage range and avoiding the risk of breakdown.
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