Crosstalk cancellation via polarity control of differential signal contacts

Abstract

Connectors to a set of differential transmit signal contacts for a plurality of channels of a communication link may generate signal crosstalk between adjacent channels. Similar signal crosstalk at the other end of the communication link may be caused by connectors to a set of differential receive signal contacts. The connector arrangement may provide opposite polarities for signal crosstalk contributions at opposite ends of the link, resulting in significant crosstalk reduction.

Description

Technical Field

[0001] This disclosure relates to interface connections for high-bandwidth multi-channel communication links, and more specifically to integrated circuit contact layouts that reduce crosstalk by arranging differential signal polarities to cause crosstalk cancellation at opposite ends of the link. Background Technology

[0002] Wafer probe testing systems are an essential part of semiconductor manufacturing processes, enabling electrical verification and characterization of integrated circuit (IC) dies at the wafer level. These systems facilitate early defect detection before wafer dicing and packaging. In IC dies with high-density, high-bandwidth contact configurations, probe testing can be affected by far-end crosstalk (FEXT) issues, which most commonly manifest as electromagnetic interference between adjacent channels of a communication link. High-density requirements often preclude arrangements that would be useful for reducing crosstalk, such as including ground (GND) bumps between closely spaced transmit and receive contacts in adjacent channels.

[0003] Wafer probe testers typically rely on long probe tips (which can be several millimeters in length) to attach probe cards to wafer contacts. The probe tips have the same pitch as the contacts on the wafer, which further exacerbates crosstalk problems. Crosstalk caused by the test probe assembly has been observed to significantly degrade the signal quality of the communication link and impair the testing process. Summary of the Invention

[0004] Therefore, this document discloses an integrated circuit, system, and tester that employs polarity control of differential signal contacts to reduce signal crosstalk between channels. An illustrative integrated circuit includes: a first pair of differential transmit signal contacts for a first channel of a communication link; a second pair of differential receive signal contacts for the first channel of the communication link; a first adjacent pair of differential transmit signal contacts for a second channel of the communication link adjacent to the first channel; and a second adjacent pair of differential receive signal contacts for the second channel of the communication link. The first pair and the first adjacent pair cause signal crosstalk with a first polarity, and the second pair and the second adjacent pair cause signal crosstalk with a second polarity opposite to the first polarity.

[0005] An illustrative system includes: a first integrated circuit die having a set of differential transmit signal contacts for a plurality of adjacent channels of a communication link; a second integrated circuit die having a set of differential receive signal contacts for a plurality of adjacent channels; a first set of connectors coupling the differential transmit signal contacts to a set of conductors; and a second set of connectors coupling the set of conductors to corresponding differential receive signal contacts. The first set of connectors introduces signal crosstalk of a first polarity between a first channel in the plurality of adjacent channels and a first adjacent channel in the plurality of adjacent channels, and the second set of connectors introduces signal crosstalk of a second polarity between the first channel and the first adjacent channel, the second polarity being opposite to the first polarity.

[0006] An illustrative wafer tester includes: a substrate; and test probes mounted on the substrate and having tips configured to connect bumps of an integrated circuit on the wafer to traces on the substrate. The bumps include: a first pair of differential transmit signal contacts for a first channel of a communication link; a second pair of differential receive signal contacts for the first channel of the communication link; a first adjacent pair of differential transmit signal contacts for a second channel of the communication link adjacent to the first channel; and a second adjacent pair of differential receive signal contacts for the second channel of the communication link. Contact with the first pair and the first adjacent pair introduces signal crosstalk of a first polarity, contact with the second pair and the second adjacent pair introduces crosstalk of a second polarity, and during reflow testing, the traces on the substrate configure the second polarity to be opposite to the first polarity.

[0007] Each of the foregoing embodiments can be implemented individually or in combination, and can be implemented in any suitable combination with any one or more of the following features: 1. A first pair of differential transmit signal contacts has a signal polarity matching that of a first adjacent pair of differential transmit signal contacts. 2. A second pair of differential receive signal contacts has a signal polarity opposite to that of a second adjacent pair of signal contacts. 3. A first pair of differential transmit signal contacts has a signal polarity opposite to that of a first adjacent pair of differential transmit signal contacts. 4. A second pair of differential receive signal contacts has a signal polarity matching that of a second adjacent pair of signal contacts. 5. Each channel of the communication link has a pair of differential transmit signal contacts, and the pairs of differential transmit signal contacts of adjacent channels have matched signal polarities. 6. Each channel of the communication link has a pair of differential receive signal contacts, and the pairs of receive signal contacts of adjacent channels have opposite signal polarities. 7. Each channel of the communication link has a pair of differential transmit signal contacts, and the pairs of differential transmit signal contacts of adjacent channels have opposite signal polarities. 8. Each channel of the communication link has a pair of differential receive signal contacts, and the paired receive signal contacts of adjacent channels have matched signal polarities. 9. The first integrated circuit die is also the second integrated circuit die. 10. A set of conductors is part of a test probe card configured to provide feedback testing. 11. The first set of connectors and the second set of connectors are probe tips configured to contact bumps on the first integrated circuit die. 12. The first set of connectors and the second set of connectors include bumps or pins that connect the first integrated circuit die and the second different integrated circuit die to printed circuit traces on a substrate. Attached Figure Description

[0008] Figure 1 A top view of an illustrative wafer with multiple integrated circuit dies is shown.

[0009] Figure 2 This is a cross-sectional view of a probe head assembly used for wafer testing.

[0010] Figure 3 This is a layout diagram illustrating the arrangement of the transmit signal contacts, receive signal contacts, and ground signal contacts on the die.

[0011] Figure 4A This is a schematic diagram illustrating the connection between contacts used for differential transmit signals and differential transmit receive signals.

[0012] Figure 4B This is a perspective view illustrating the printed circuit trace connections between the various probe connectors.

[0013] Figure 5A This is a schematic diagram illustrating an interchangeable polarity connection between adjacent channels.

[0014] Figure 5B It is applicable Figure 5A A perspective view illustrating the interconnection of printed circuit traces with alternating polarity arrangements.

[0015] Figure 6 It is a graph of simulated crosstalk between channels that compares the conventional arrangement of differential signal contacts with the switched polarity arrangement.

[0016] Figure 7 It is a layout diagram illustrating the arrangement of differential signal contacts with alternating signal polarities.

[0017] Figure 8 It is a layout diagram illustrating the arrangement of differential signal contacts with alternating transmitted signal polarities.

[0018] Figure 9 This is a functional block diagram of an illustrative integrated circuit that supports multi-channel communication links. Detailed Implementation

[0019] Note that the specific embodiments given in the accompanying drawings and the following description do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternatives, equivalents, and modifications included within the scope of the claims.

[0020] Figure 1 A top view of a wafer 100 comprising multiple dies 102 is shown. Each die 102 represents a separate semiconductor device manufactured within the wafer 100. The arrangement of multiple dies 102 on the wafer 100 facilitates efficient testing and subsequent dicing of the wafer 100 into individual semiconductor units.

[0021] Go to Figure 2 The figure depicts a cross-sectional view of a probe head 202 used in the wafer testing phase of manufacturing. The probe head 202 is mounted to a substrate 204, which may also be referred to as a probe card 204. To support closely spaced printed circuit traces for transmitting high-bandwidth signals, the substrate 204 may be a multilayer organic (MLO) laminate instead of a conventional printed circuit board (PCB) composite material. The probe head 202 includes a set of probe tips 206 configured to contact electrical contacts on the integrated circuit die 212 under test. These electrical contacts may be pads, leads, solder balls, bumps, or other suitable structures for connecting the integrated circuit die to its target substrate or package connector. Each tip connects to a trace or via on the probe card 204 to transmit or exit signals required for the testing process to or from the corresponding contact on the wafer.

[0022] Testing can be performed by aligning the die 212 under test with the probe tip 202 and pressing the die 212 into contact. The probe tip 206 is shaped to accommodate varying degrees of height of the electrical contacts. The probe tip 202 comprises both an upper ceramic portion 210 and a lower ceramic portion 208, which are aligned and hold the probe tip 206 in place, ensuring precise and compliant contact with the die 212 under test. This configuration allows for thorough inspection of the electrical connectivity required for die functionality.

[0023] Figure 3 An enlarged view of the relevant portions of the contact layout for the die under test 212 is shown. The die under test 212 provides contacts for multiple channels of a communication link. Three channels 301, 302, and 303 are shown here, but the actual number of channels may be more or less. The contacts shown are arranged in three groups, with the differential transmit signal contacts 310 separated from the differential receive signal contacts 312 by a set of ground contacts 314. The differential transmit signal contacts 310 of the first channel 301 are labeled TX1+ and TX1-, the differential transmit signal contacts 310 of the second channel 302 are labeled TX2+ and TX2-, and the differential transmit signal contacts 310 of the third channel 303 are labeled TX3+ and TX3-. The differential receiving signal contacts of the first channel 301 are marked as RX1+ and RX1-, the differential receiving signal contacts of the second channel 302 are marked as RX2+ and RX2-, and the differential receiving signal contacts of the third channel 303 are marked as RX3+ and RX3-.

[0024] Figure 4A The diagram illustrates the electrical connections that can be made for two adjacent channels of a communication link. Conductive path 411 connects the transmitter contact TX1- to the receiver contact RX1-. Similarly, conductive path 412 connects TX1+ to RX1+. In adjacent channels, conductive path 421 connects the transmitter contact TX2- to the receiver contact RX2-, and conductive path 422 connects TX2+ to RX2+. This arrangement is sufficient for loopback testing, in which the transmitting terminal of a device is connected to its own receiving terminal. In practical use, each channel will have differential signals transmitting information in each direction (i.e., from the transmitting contact of the local device to the receiving contact of the remote device and from the transmitting contact of the remote device to the receiving contact of the local device). Figure 9 Let's discuss this use further.

[0025] In the test probe assembly configured for feedback testing, Figure 4A The schematic connection can be as follows Figure 4B The physical implementation is shown. (However, note that...) Figure 4B(Based on a simplified simulation model of the needle's shape.) Substrate 204 includes a set of printed circuit traces 430 to provide conductive paths 411 to 422. Needle 432 forms a first set of electrical connections between differential transmit signal contacts TX1+ (abbreviated as 1P), TX1- (1N), TX2+ (2P), TX2- (1N) and the corresponding traces 430. Needle 434 forms a second set of electrical connections between the corresponding traces and differential receive signal contacts RX1+ (1P), RX1- (1N), RX2+ (2P), RX2- (2N). Figure 4B and Figure 5B There is no clear distinction between transmitting and receiving contacts, as their roles can be interchanged.

[0026] Trace 430 includes traces in two different metallization layers of substrate 204. Needle 432 connects to the upper metallization layer. Needle 434 connects to the lower metallization layer. The upper and lower traces are connected via via 436 (for channel 2) and via 438 (for channel 1). Instead of following the shortest path between needles 432 and 434, trace 430 includes additional length to better represent the attenuation and signal degradation typically encountered in real-world applications.

[0027] When the differential transmit signals for channels 1 and 2 pass through pin 432, these signals cause signal crosstalk between channels. When the differential signal passes through pin 434 and reaches the differential receive signal contact, the differential signal causes additional crosstalk. Figures 4A to 4B With this configuration, these crosstalk contributions are cumulative.

[0028] Figure 5A It is similar to Figure 4A The diagram is a simplified representation, but the relative orientation of the differential receiver contacts for the two channels has been adjusted. Probe tip 206 connects transmitter contact TX1- to receiver contact RX1-, and conductive path 512 connects transmitter contact TX1+ to receiver contact RX1+. The contacts and conductive paths of channel 2 are relative to... Figure 4A constant.

[0029] The adjusted layout can be as follows Figure 5B The implementation is shown. Needle 534 is physically identical to needle 434, but the 1P and 1N tags of channel 1 have been swapped. To accommodate this polarity change, trace 530 and conductive path 411 have been adjusted to maintain 1P-to-1P and 1N-to-1N connections.

[0030] As previously described, when the differential transmit signals for channels 1 and 2 pass through needle 432, these signals cause signal crosstalk between channels. When the differential signal passes through needle 534 to reach the differential receive signal contact, the differential signal causes additional crosstalk. However, the receive signal contact of channel 1, which is opposite to the receive signal contact of channel 2, causes this additional crosstalk to have the opposite polarity to the signal crosstalk from needle 432. When combined, these contributions at least partially cancel each other out, thereby reducing signal crosstalk between channels.

[0031] A similar result can be achieved by swapping the signal polarity of the differential receive signal contacts for channel 2 instead of channel 1. Alternatively, the signal polarity of the differential transmit signal contacts for channel 1 or channel 2 can be swapped to ensure that the crosstalk contribution from one end of the link has the opposite sign to the crosstalk contribution from the other end of the link. In the presence of multiple adjacent channels, adjusting the arrangement of the middle channel will reduce crosstalk from adjacent channels on both sides. For four or more channels, adjusting the connection polarity of each of the odd-numbered channels (or alternatively, each of the even-numbered channels) will effectively reduce crosstalk caused by connections between all adjacent channel pairs in the link.

[0032] Figure 6 It is a comparison Figure 4B Signal crosstalk in the layout Figure 5B A graph showing the simulation results of signal crosstalk levels in a switched polarity arrangement. The vertical axis shows far-end crosstalk (FEXT) from 0 to -120 dB. The horizontal axis shows signal frequencies from 0 to 50 GHz. (The region of interest for current communication standards is 0 to 28 GHz.)

[0033] Line 602 shows Figure 4B The relationship between signal crosstalk and frequency is shown in line 604. Figure 5B The relationship between signal crosstalk and frequency for a polarity-switched arrangement is shown. In the region of interest, the polarity-switched arrangement exhibits an improvement ranging from 4 dB at the high end to 20 dB at the low end. In most regions of interest, the improvement exceeds 10 dB. This improvement can be achieved through a signal routing change without increasing manufacturing costs.

[0034] Figure 7 It shows in Figure 3 The image shows a portion of the contact layout for the integrated circuit die 712 with the described polarity-switched configuration, wherein the differential transmit signal contacts for each of channels 301 to 303 have matched signal polarities, and the differential receive contact for channel 302 has an opposite polarity relative to channels 301 and 303 to provide signal crosstalk reduction. A similar effect can be achieved by using polarity switching at the other end of the link, as previously described.

[0035] Figure 8 It shows in Figure 3 The image shows a portion of the contact layout for the integrated circuit die 812 with a polarity-switched configuration, wherein the differential receive contacts for each of channels 301 to 303 have matched signal polarities, and the differential transmit contact for channel 302 has reverse signal polarities relative to channels 301 and 303. This arrangement achieves equal reduction in signal crosstalk between channels.

[0036] Figure 9 This is a functional block diagram of an illustrative integrated circuit device 912 supporting multi-channel communication links. Device 912 may be, for example, a retimer or a link extender. Device 912 includes a serializer / deserializer (SerDes) module with differential signal contacts 920 for transmitting and receiving high-speed serial bit streams on four channels of a first communication link, an additional SerDes module with contacts 922 for transmitting high-speed serial bit streams on four channels of a second communication link, and core logic 924 for buffering bit streams between communication links while implementing a channel communication protocol. It also includes various support modules with corresponding contacts 926 and 928, such as power regulation and distribution, clock generation, digital input / output lines for control signals, and a JTAG module for built-in self-test.

[0037] It is worth noting that the serializer module of device 912 employs differential transmit signal contacts with matched polarity on each channel of the communication link. However, in order to reduce signal crosstalk, the deserializer module of device 912 employs differential receive signal contacts with alternating polarity, which are opposite to those of the adjacent channels of each communication link.

[0038] If the local device 912 is connected to a similar remote device or a remote device that shares a similar interface layout, the crosstalk caused by the connection at the receiving end of each link will have the opposite polarity to the crosstalk caused by the connection at the transmitting end, thus producing reduced signal crosstalk between channels.

[0039] The embodiments described herein provide a favorable solution for mitigating signal crosstalk in high-density, high-bandwidth communication links, such as those commonly encountered in semiconductor wafer probe testing systems. By incorporating polarity-switching techniques, crosstalk contributions from adjacent channels can be effectively reduced, thereby improving signal integrity and reliability. This approach requires minimal changes to existing probe card designs and can be implemented without additional manufacturing costs. Furthermore, the described configuration is compatible with the use of SerDes transceivers and other differential signaling modules, ensuring broad applicability across a wide range of systems. The disclosed embodiments should provide greater accuracy and efficiency in wafer-level integrated circuit characterization.

[0040] Once fully understanding the foregoing disclosure, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. Although the wafer test system is disclosed in an illustrative context, the foregoing disclosure applies to any connection arrangement that may introduce signal crosstalk and interference at opposite ends of a link. Where applicable, the claims are intended to be construed as encompassing all such alternatives, equivalents, and modifications.

Claims

1. A system comprising: a first integrated circuit die having a set of differential transmit signal contacts for a plurality of adjacent lanes of a communication link; a second integrated circuit die having a set of differential receive signal contacts for the plurality of adjacent lanes; a first set of connectors coupling the differential transmit signal contacts to a set of conductors; and a second set of connectors coupling the set of conductors to corresponding differential receive signal contacts, the first set of connectors introducing signal crosstalk of a first polarity between a first lane of the plurality of adjacent lanes and a first adjacent lane of the plurality of adjacent lanes, and the second set of connectors introducing signal crosstalk of a second polarity between the first lane and the first adjacent lane, the second polarity being opposite the first polarity.

2. The system of claim 1, wherein the first lane has a first pair of connectors and the first adjacent lane has a first adjacent pair of connectors, and the first polarity corresponds to the first adjacent pair of connectors, the first adjacent pair of connectors having an orientation that matches an orientation of the first pair of connectors, and wherein the first lane has a second pair of connectors and the first adjacent lane has a second adjacent pair of connectors, and the second polarity corresponds to the second adjacent pair of connectors, the second adjacent pair of connectors having an orientation that is reversed relative to an orientation of the second pair of connectors.

3. The system of claim 1, wherein the first lane has a first pair of connectors and the first adjacent lane has a first adjacent pair of connectors, and the first polarity corresponds to the first adjacent pair of connectors, the first adjacent pair of connectors having an orientation that is reversed relative to an orientation of the first pair of connectors, and wherein the first lane has a second pair of connectors and the first adjacent lane has a second adjacent pair of connectors, and the second polarity corresponds to the second adjacent pair of connectors, the second adjacent pair of connectors having an orientation that matches an orientation of the second pair of connectors.

4. The system of claim 1, wherein the first set of connectors further introduces signal crosstalk of the first polarity between the first lane of the plurality of adjacent lanes and a second adjacent lane of the plurality of adjacent lanes, and wherein the second set of connectors further introduces signal crosstalk of the second polarity between the first lane and the second adjacent lane.

5. The system of claim 1, wherein the first integrated circuit die is also the second integrated circuit die, and wherein the set of conductors is part of a test probe card configured to provide loopback testing.

6. The system of claim 5, wherein the first set of connectors and the second set of connectors are probe needles configured to contact bumps on the first integrated circuit die. ​ 7. The system of claim 1, wherein the first and second sets of connectors comprise bumps or pins that connect the first and second integrated circuit dies to printed circuit traces on a substrate.

8. An integrated circuit die, comprising: a first pair of differential transmit signal contacts for a first lane of a communication link; a second pair of differential receive signal contacts for the first lane of the communication link; a first adjacent pair of differential transmit signal contacts for a second lane of the communication link adjacent to the first lane; and a second adjacent pair of differential receive signal contacts for the second lane of the communication link, the first pair and the first adjacent pair having signal crosstalk of a first polarity, and the second pair and the second adjacent pair having signal crosstalk of a second polarity opposite the first polarity.

9. The integrated circuit die of claim 8, wherein the first pair of differential transmit signal contacts have a signal polarity matching that of the first adjacent pair of differential transmit signal contacts, and wherein the second pair of differential receive signal contacts have a signal polarity reversed relative to that of the second adjacent pair of signal contacts.

10. The integrated circuit die of claim 8, wherein the first pair of differential transmit signal contacts have a signal polarity reversed relative to that of the first adjacent pair of differential transmit signal contacts, and wherein the second pair of differential receive signal contacts have a signal polarity matching that of the second adjacent pair of signal contacts.

11. The integrated circuit die of claim 8, further comprising: a third pair of differential transmit signal contacts for a third lane of the communication link adjacent to the first lane; and a fourth pair of differential receive signal contacts for the third lane of the communication link, the first pair and the third pair having signal crosstalk of the first polarity, and the second pair and the fourth pair having signal crosstalk of the second polarity opposite the first polarity.

12. The integrated circuit die of claim 8, comprising: each lane of the communication link having a pair of differential transmit signal contacts, the pairs of differential transmit signal contacts of adjacent lanes having matching signal polarities; and each lane of the communication link having a pair of differential receive signal contacts, the pairs of receive signal contacts of adjacent lanes having opposite signal polarities.

13. The integrated circuit die of claim 8, comprising: each lane of the communication link having a pair of differential transmit signal contacts, the pairs of differential transmit signal contacts of adjacent lanes having opposite signal polarities; and each lane of the communication link having a pair of differential receive signal contacts, the pairs of receive signal contacts of adjacent lanes having matching signal polarities.

14. A wafer tester, comprising: a substrate; and a test probe head mounted on the substrate and having needles configured to connect bumps of integrated circuits on a wafer to traces on the substrate, the bumps comprising: a first pair of differential transmit signal contacts for a first lane of a communication link; a second pair of differential receive signal contacts for the first lane of the communication link; a first adjacent pair of differential transmit signal contacts for a second lane of the communication link adjacent the first lane; and a second adjacent pair of differential receive signal contacts for the second lane of the communication link, wherein the pins contacting the first pair and the first adjacent pair introduce signal crosstalk of a first polarity, wherein the pins contacting the second pair and the second adjacent pair introduce crosstalk of a second polarity, and wherein during a loopback test, the traces on the substrate configure the second polarity to be opposite the first polarity.

15. The wafer prober of claim 14, wherein the first pair of differential transmit signal contacts have a signal polarity that matches a signal polarity of the first adjacent pair of differential transmit signal contacts, and wherein the second pair of differential receive signal contacts have a signal polarity that is reversed relative to a signal polarity of the second adjacent pair of signal contacts.

16. The wafer prober of claim 14, wherein the first pair of differential transmit signal contacts have a signal polarity that is reversed relative to a signal polarity of the first adjacent pair of differential transmit signal contacts, and wherein the second pair of differential receive signal contacts have a signal polarity that matches a signal polarity of the second adjacent pair of signal contacts.

17. The wafer prober of claim 14, wherein the bump comprises: a pair of differential transmit signal contacts for each lane of the communication link, the pairs of differential transmit signal contacts of adjacent lanes having matching signal polarities; and a pair of differential receive signal contacts for each lane of the communication link, the pairs of differential receive signal contacts of adjacent lanes having opposite signal polarities.

18. The wafer prober of claim 14, wherein the bump comprises: a pair of differential transmit signal contacts for each lane of the communication link, the pairs of differential transmit signal contacts of adjacent lanes having opposite signal polarities; and a pair of differential receive signal contacts for each lane of the communication link, the pairs of differential transmit signal contacts of adjacent lanes having matching signal polarities.

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