Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a substrate body and a pixel layer which are sequentially arranged in the first direction. And a pixel retaining wall electrode structure. In the second direction and the third direction, the pixel layer comprises a plurality of pixel areas arranged in sequence, each pixel area comprises a pixel driving electrode, the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction; wherein the pixel retaining wall electrode structures are located between every two adjacent pixel areas, and the pixel retaining wall electrode structures are connected with the pixel driving electrodes. According to the technical scheme, the aperture opening ratio of the array substrate can be improved, so that the visual field is improved, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] E-ink (Electronic Ink) is increasingly being used in electronic display devices. Compared to other display technologies such as Liquid Crystal Display (LCD) and Cathode Ray Tube (CRT), it offers advantages such as readability, flexibility, low cost, and low power consumption. E-ink has good reflectivity and contrast, resembling ink on paper, and maintains good contrast even under strong light, making reading on E-ink displays comfortable for users.

[0003] Although E-ink e-books offer numerous advantages such as low power consumption, the current manufacturing process limits the aperture ratio of their display panels, resulting in a narrow viewing area and negatively impacting the user experience. Therefore, improving the aperture ratio of e-book display panels is a pressing technical challenge. Summary of the Invention

[0004] In view of the above problems, this application provides an array substrate and a display device that can increase the aperture ratio of the array substrate, thereby improving the field of view and enhancing the user experience.

[0005] In a first aspect, an array substrate is provided, comprising: a substrate and a pixel layer disposed along a first direction; and a pixel barrier electrode structure; wherein, in a second direction and a third direction, the pixel layer comprises a plurality of sequentially disposed pixel regions, each pixel region comprising a pixel driving electrode, the second direction being perpendicular to the first direction, and the third direction being perpendicular to both the first and second directions; wherein, the pixel barrier electrode structure is located between two adjacent pixel regions, and the pixel barrier electrode structure is connected to the pixel driving electrode.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, in the first direction, the size of the pixel barrier electrode structure is larger than the size of the pixel driving electrode.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the size of the pixel barrier electrode structure is greater than or equal to 25 μm in the first direction.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the array substrate includes a plurality of pixel units disposed along the second direction, each pixel unit including a pixel region and a pixel barrier electrode structure; the pixel driving electrode includes a first portion disposed along the second direction.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the pixel driving electrode further includes a second portion disposed along the first direction, the second portion being connected to the first portion; in the second direction, a plurality of the second portions are connected to the same side of a plurality of the pixel barrier electrode structures.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the pixel driving electrode further includes a second portion and a third portion disposed along the first direction, the second portion and the third portion being connected to the first portion; in the second direction, the first portion has a first end close to the pixel barrier electrode structure and a second end away from the pixel barrier electrode structure; the second portion is disposed at the first end and connected to the pixel barrier electrode structure, and the third portion is disposed at the second end and connected to an adjacent pixel barrier electrode structure.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, in the first direction, the size of the first part is smaller than the size of the second part, and the size of the first part is smaller than the size of the third part; in the second direction, the size of the first part is larger than the size of the second part, and the size of the first part is larger than the size of the third part.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the array substrate includes a plurality of pixel units disposed along the second direction, the pixel unit including two pixel driving electrodes and two pixel barrier electrode structures; the pixel driving electrode includes a first portion disposed along the second direction and a second portion disposed along the first direction, the second portion being connected to the first portion; wherein, the two second portions are connected to the same pixel barrier electrode structure in the pixel unit.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, in the first direction, the size of the first part is smaller than the size of the second part; in the second direction, the size of the first part is larger than the size of the second part.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the array substrate further includes a light-shielding layer, wherein in the first direction, the pixel barrier electrode structure is located between the substrate and the light-shielding layer; and in the second direction, the size of the light-shielding layer is the same as the size of the pixel barrier.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the pixel region further includes ink particles; and in the first direction, the number of layers of the ink particles is greater than or equal to two.

[0016] In a second aspect, a display device is provided, comprising the array substrate described in any implementation of the first aspect of this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0018] Figure 1 A schematic diagram of the structure of an Eink display device according to an embodiment of the related technology;

[0019] Figure 2 This is a schematic diagram of the EPD display principle of one embodiment of the related technology;

[0020] Figure 3 A schematic diagram of the structure of an Eink display panel according to an embodiment of the related technology;

[0021] Figure 4 This is a schematic diagram of the structure of an array substrate according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application;

[0024] Figure 7 This is a wide-viewing-angle schematic diagram of an array substrate according to an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application;

[0027] Figure 10 This is a wide-viewing-angle schematic diagram of an array substrate according to another embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application;

[0029] Figure 12 This is a schematic diagram of the fabrication process of an array substrate according to an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a specific range. Ranges defined in this way include endpoint values ​​and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is also expected that ranges of 60-110 and 80-120 are also included. Furthermore, if the minimum range values ​​are listed as 1 and 2, and the maximum range values ​​are listed as 3, 4, and 5, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" means that all real numbers between "0-5" have been listed herein; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is described as an integer greater than or equal to 2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0032] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined with each other to form new technical solutions.

[0033] Unless otherwise specified, all technical features and optional technical features of this application may be combined to form new technical solutions.

[0034] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one” and “one or more” refer to one, two, or more than two. The term “and / or” is used to describe the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0035] References to "one embodiment," "some embodiments," "one example," or "some examples" used in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0036] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different descriptive objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0037] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0038] E-ink technology uses an electric field to control the movement and distribution of black and white particles within an "electronic ink" capsule material, displaying different shades of gray on an E-ink screen to achieve the function of displaying grayscale images. It's worth noting that when the electric field at both ends of the capsule is removed, the black and white particles remain in their original positions, sometimes for a very long time (at least a month), achieving the "bistable state" of electronic ink. This characteristic allows E-ink screens to maintain their display content for extended periods after power is off. Combined with their clear, sharp, and smooth display effect, E-ink screens look very much like a piece of paper, hence the name "e-book."

[0039] Figure 1 This is a schematic diagram of the structure of an E-ink display device according to an embodiment of related technology. For example... Figure 1 As shown, microcapsules are added to the Eink display device. Each capsule contains black and white microparticles; the black microparticles are negatively charged, and the white microparticles are positively charged. The entire microcapsule is in a point equilibrium state. When a positive charge is applied to the display backplane, the black microparticles move towards the backplane electrodes, while the white microparticles are distributed above the microcapsules. Ambient light incident from above is reflected at the white microparticles in the microcapsules, making the display device bright. When a negative charge is applied to the display backplane, the white microparticles move towards the backplane electrodes, while the black microparticles are distributed above the microcapsules. Ambient light incident from above is absorbed at the black microparticles in the microcapsules, making the display device dark.

[0040] Figure 2 This is a schematic diagram of an EPD display principle according to an embodiment of a related technology. For example... Figure 2 As shown, in the current field of electronic display paper (EPD), electronic ink film is the core raw material. This material currently mainly adopts an electrophoretic technology approach, meaning that only black particles exist in the pixel electrophoretic solution. When displaying in a black state, the black particles are spread evenly in the pixel, and their spreading position is not restricted; when displaying in a white state, the black particles gather on both sides of the pixel, and the white state display is achieved through the reflective metal under the electrodes.

[0041] Figure 3 This is a schematic diagram of the structure of an Eink display panel according to an embodiment of the related technology. In current EPD fabrication processes, most employ an active matrix (AM) thin film transistor (TFT) driving method. However, in the AM TFT driving structure, the pixel wall (PW) electrode structure overlaps with the pixel driving electrode in the vertical direction, which to some extent affects the aperture ratio of the display panel. Furthermore, the pixel wall generally exhibits a foot effect during fabrication, meaning it is prone to residue, which also affects the vertical electric field distribution, impacting the aperture ratio and resulting in a poor user experience.

[0042] In view of the above problems, embodiments of this application provide an array substrate and a display device. By connecting the pixel barrier electrode structure and the pixel driving electrode without overlapping them, the aperture ratio of the display device can be improved, thereby increasing the field of view and enhancing the user experience.

[0043] If mentioned below, AM TFT driving method refers to a method that mainly uses a glass substrate and utilizes TFT driving control to achieve single-area control of the backlight. Each pixel can be driven to emit light continuously and independently. It can use low-temperature polysilicon or oxide TFT driving and has the advantages of low driving voltage and long life of light-emitting elements.

[0044] If mentioned below, the footing effect refers to the phenomenon in photolithography where the bottom of the photoresist pattern is wide due to insufficient development or other reasons.

[0045] The array substrate and display device according to the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0046] Figure 4 This is a schematic diagram of the structure of an array substrate according to an embodiment of this application. Figure 4 As shown, the array substrate 100 includes a substrate 110 and a pixel layer 120 arranged sequentially along the first direction X.

[0047] For example, the first direction X is as follows Figure 4 As shown, the first direction X can also be referred to as the thickness direction or height direction of the array substrate 100 or the display device.

[0048] Along the first direction X, the substrate 110 and the pixel layer 120 are arranged sequentially. Therefore, it can also be said that the pixel layer 120 and the substrate 110 are arranged sequentially from top to bottom, or the substrate 110 and the pixel layer 120 are arranged sequentially from bottom to top.

[0049] The array substrate 100 also includes a pixel barrier electrode structure 121.

[0050] It should be noted that the array substrate 100 also includes conventional film layers such as buffer layer, interlayer dielectric layer and source / drain electrode, which will not be described in detail here.

[0051] Figure 5 This is a schematic diagram of the array substrate according to another embodiment of this application. Please refer to... Figure 4 and Figure 5 In the second direction Y and the third direction Z, the pixel layer 120 includes a plurality of pixel regions 300 arranged sequentially, and the pixel region 300 includes a pixel driving electrode 111. The second direction Y is perpendicular to the first direction X, and the third direction Z is perpendicular to the first direction X and the second direction Y.

[0052] For example, the second direction Y is as follows Figure 4 As shown, the second direction Y can also be referred to as the length direction of the array substrate 100 or the display device.

[0053] For example, a third party provides Z with... Figure 5 As shown, the third direction Z can also be referred to as the width direction of the array substrate 100 or the display device.

[0054] like Figure 5 As shown, the pixel region 300 is arrayed in the second direction Y and the third direction Z. It should be noted that the distribution of the pixel region 300 in the second direction Y and the third direction Z can be exactly the same or different, and this application does not limit this.

[0055] It should be noted that, Figure 4 This is a cross-sectional view of the array substrate 100. Figure 5 This is a top view of the array substrate 100.

[0056] The pixel barrier electrode structure 121 is located between two adjacent pixel regions 300, and the pixel barrier electrode structure 121 is connected to the pixel driving electrode 111.

[0057] The connection between the pixel driving electrode 111 and the pixel barrier electrode structure 121 means that the pixel driving electrode 111 is in close contact with the pixel barrier electrode structure 121, but there is no overlapping area between them; or it can be interpreted as the pixel driving electrode 111 is close to the pixel barrier electrode structure 121, but there is no overlapping area between them, that is, they are in a contiguous relationship.

[0058] Furthermore, the pixel barrier electrode structure 121 is disposed between two adjacent pixel regions 300, that is, the pixel barrier electrode structure 121 is disposed between adjacent pixel driving electrodes 111. Therefore, the connection between the pixel driving electrode 111 and the pixel barrier electrode structure 121 means that both ends of the pixel driving electrode 111 are close to the pixel barrier electrode structure 121, but there is no overlapping area.

[0059] The pixel driving electrode 111 defines a pixel unit; that is, the exposed size of the pixel driving electrode 111 affects the aperture ratio of the array substrate 100, thus determining the display field of view of the display device. For example... Figure 3 As shown, Figure 3 Region A in the diagram shows that, in the relevant technology, there is an overlap between the two ends of the pixel driving electrode 111 and the pixel barrier electrode structure 121, which affects the aperture ratio of the array substrate 100; while... Figure 4 As shown, in the embodiment of this application, the two ends of the pixel driving electrode 111 do not overlap with the pixel barrier electrode structure. Therefore, this can improve the aperture ratio of the array substrate 100 to a certain extent.

[0060] In the above scheme, the array substrate 100 includes a substrate 110 and a pixel layer 120 disposed along a first direction X; further, the pixel layer 120 includes pixel regions 300 distributed in an array, and each pixel region 300 includes a pixel driving electrode 111; the array substrate 100 also includes a pixel barrier electrode structure 121, which is disposed between adjacent pixel regions 300. By connecting the pixel driving electrode 111 and the pixel barrier electrode structure 121 without overlapping areas between them, the aperture ratio of the array substrate 100 can be increased, thereby improving the field of view and enhancing the user experience.

[0061] It should be noted that if the size of the pixel driving electrode 111 is 50μm in the second direction Y, and the size of the overlapping area between the pixel barrier electrode structure 121 and the pixel driving electrode 111 is generally not less than 2μm, then the aperture ratio will be increased by at least 4%.

[0062] In some implementations, in the first direction X, the size h2 of the pixel barrier electrode structure 121 is larger than the size h1 of the pixel driving electrode 111.

[0063] In other words, the height of the pixel barrier electrode structure 121 is greater than the height of the pixel driving electrode 111.

[0064] In the above scheme, in the first direction X, by making the size of the pixel barrier electrode structure 121 larger than the size of the pixel driving electrode 111, it is possible to prevent the pixel driving electrode 111 from breaking down with other structures, and at the same time, it is possible to prevent crosstalk caused by particle movement between pixels. Furthermore, it is possible to adsorb black particles onto the sidewall of the pixel barrier electrode structure 121, thereby further improving the aperture ratio.

[0065] In one possible implementation, in the first direction X, the size h2 of the pixel barrier electrode structure 121 is greater than or equal to 25 μm.

[0066] According to theoretical calculations, when the cell gap is not less than 25μm, the black state is close to saturation. The cell gap refers to the thickness of the cavity where the ink particles are located, which corresponds to the height h2 of the pixel barrier electrode structure 121 in the embodiment of this application.

[0067] In the above scheme, by making the size of the pixel barrier electrode structure 121 in the first direction X not less than 25μm, the black state saturation can be achieved with the fewest particles, which is beneficial to improving the display effect of the array substrate 100.

[0068] Specifically, in the first direction X, the size of the pixel barrier electrode structure 121 can be 25μm, 28μm, 30μm, 32μm, 35μm or any value within the above range, as long as it meets the manufacturing process requirements.

[0069] Specifically, in the first direction X, the size h1 of the pixel driving electrode 111 can be smaller than the size h2 of the pixel barrier electrode structure 121. This application does not limit its specific size.

[0070] Please continue to refer to Figure 4 .like Figure 4 As shown, in some embodiments, the array substrate 100 includes a plurality of pixel units 140 disposed along the second direction Y, each pixel unit 140 including a pixel region 300 and a pixel barrier electrode structure 121; the pixel driving electrode 111 includes a first portion 1111 disposed along the second direction Y.

[0071] like Figure 4 As shown, when the pixel driving electrode 111 includes a first portion 1111 extending along the second direction Y, the two ends of the first portion 1111 are connected to two adjacent pixel barrier electrode structures 121.

[0072] Pixel unit 140 includes a pixel region 300 and a pixel barrier electrode structure 121. Therefore, it can be said that in each pixel unit 140, each pixel driving electrode 111 has a left end and a right end in the second direction Y. Unless otherwise specified below, in each pixel unit 140, the pixel barrier electrode structure 121 is always located at the left end of the pixel driving electrode 111. Of course, the pixel barrier electrode structure 121 can also be located at the right end of the pixel driving electrode 111, as long as the relative position of the pixel barrier electrode structure 121 and the pixel driving electrode 111 in each pixel unit 140 remains consistent.

[0073] Figure 6 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application. Figure 6 As shown, in some embodiments, the pixel driving electrode 111 further includes a second portion 1112 extending along a first direction X, the second portion 1112 being connected to the first portion 1111; in the second direction Y, a plurality of second portions 1112 are connected to the same side of a plurality of pixel barrier electrode structures 121.

[0074] The array substrate 100 includes a plurality of pixel units 140 disposed along the second direction Y. Each pixel unit 140 includes a pixel region 300 and a pixel barrier electrode structure 121. Thus, the plurality of pixel units 140 include a plurality of pixel regions 300 and a plurality of pixel barrier electrode structures 121.

[0075] In the second direction Y, multiple second portions 1112 are connected to the same side of multiple pixel barrier electrode structures 121. This means that in each pixel unit 140, the second portion 1112 is always adjacent to the pixel barrier electrode structure 121 located to the left of the first portion 1111, or always adjacent to the pixel barrier electrode structure 121 located to the right of the first portion 1111. In other words, the second portions 1112 can all be located at the right end of the first portion 1111, or... Figure 6 All of them are set at the left end of the first part 1111.

[0076] It should be understood that when the second part 1112 is connected to the pixel barrier electrode structure 121 on the left side of the first part 1111, that is, as described above, in each pixel unit 140, each pixel barrier electrode structure 121 is disposed at the left end of each pixel driving electrode 111; when the second part 1112 is connected to the pixel barrier electrode structure 121 on the right side of the first part 1111, that is, as described above, in each pixel unit 140, each pixel barrier electrode structure 121 is disposed at the right end of each pixel driving electrode 111.

[0077] It should be understood that in this embodiment, each pixel unit 140 includes a pixel region 300 and a pixel barrier electrode structure 121, each pixel region 300 includes a pixel driving electrode 111, and each pixel driving electrode 111 also includes a first portion 1111 and a second portion 1112.

[0078] In the above scheme, by providing a second part 1112 in the array substrate 100 that is close to the pixel barrier electrode structure 121, it is beneficial to adsorb black particles onto the sidewall of the pixel barrier electrode structure 121, thereby further improving the aperture ratio.

[0079] Figure 7 This is a wide-viewing-angle schematic diagram of an array substrate according to one embodiment of this application. For example... Figure 7 As shown, α1 is the entry point of the related technology, and α2 is... Figure 6 The array substrate 100 shown has an entrance viewing angle. By comparison, the embodiments of this application can increase the entrance viewing angle and expand the field of view.

[0080] Figure 8 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application. Figure 8As shown, the pixel driving electrode 111 further includes a second portion 1112 and a third portion 1113 disposed along the first direction X, and the second portion 1112 and the third portion 1113 are both connected to the first portion 1111; in the second direction Y, the first portion 1111 has a first end close to the pixel barrier electrode structure 121 and a second end away from the pixel barrier electrode structure 121; the second portion 1112 is disposed at the first end and connected to the pixel barrier electrode structure 121, and the third portion 1113 is disposed at the second end and connected to the adjacent pixel barrier electrode structure 121.

[0081] The second part 1112 and the third part 1113 are both connected to the first part 1111, meaning that the second part 1112 is connected to the first part 1111 and the third part 1113 is connected to the first part 1111, but the second part 1112 and the third part 1113 are not connected.

[0082] As described above, after the pixel units 140 are divided, the pixel driving electrodes 111 in each pixel unit 140 have a relative left and right side. More specifically, the first part 1111 of the pixel driving electrodes 111 has a relative left and right side.

[0083] Specifically, the first end of the first part 1111 near the pixel barrier electrode structure 121 corresponds to the left end mentioned above, and the second end of the first part 1111 near the pixel barrier electrode structure 121 corresponds to the right end mentioned above.

[0084] It should be noted that the division between the first end and the second end mentioned above refers to the situation where the pixel barrier electrode structure 121 is always located at the left end of the pixel driving electrode 111 in the pixel unit 140. If the pixel barrier electrode structure 121 is always located at the right end of the pixel driving electrode 111 in the pixel unit 140, the first end can be the end of the first part 1111 that is away from the pixel barrier electrode structure 121.

[0085] In addition, if the structures of the second part 1112 and the third part 1113 are exactly the same, it can be said that the structures of the second part 1112 and the third part 1113 can be set at both ends of the first part 1111 respectively; however, when the structures of the second part 1112 and the third part 1113 are different, they should be set at the corresponding positions according to the requirements of the production process.

[0086] It should also be noted that both the second part 1112 and the third part 1113 must be in contact with the pixel barrier electrode structure 121. When the second part 1112 is provided at the first end, the second part 1112 is in contact with the pixel barrier electrode structure 121 in the pixel unit 140 where the second part 1112 is located. The third part 1113 provided at the second end can be said to be in contact with the pixel barrier electrode structure 121 in the adjacent pixel unit 140.

[0087] In the above scheme, by setting a second part 1112 and a third part 1113 at both ends of the first part 1111 of the pixel driving electrode 111, a "U-shaped" pixel driving electrode 111 is formed. The second part 1112 and the third part 1113 are adjacent to the pixel barrier electrode structure 121, which is beneficial to adsorb black particles on the side wall of the pixel barrier electrode structure 121, further improving the aperture ratio and also improving the viewing angle in the left and right directions.

[0088] In some embodiments, in the first direction X, the size L1 of the first part 1111 is smaller than the size L2 of the second part 1112, and the size L1 of the first part 1111 is smaller than the size L3 of the third part 1113. In the second direction Y, the size L4 of the first part 1111 is larger than the size L5 of the second part 1112, and the size L4 of the first part 1111 is larger than the size L6 of the third part 1113.

[0089] In the above scheme, by limiting the dimensions of the first part 1111, the second part 1112 and the third part 1113 in two directions, sufficient space can be left to accommodate black particles, so as to ensure the normal display function of the array substrate 100.

[0090] Figure 9 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application. Figure 9 As shown, the array substrate 100 includes a plurality of pixel units 140 disposed along the second direction Y. Each pixel unit 140 includes two pixel regions 300 and two pixel barrier electrode structures 121. The pixel driving electrode 111 includes a first portion 1111 disposed along the second direction Y and a second portion 1112 disposed along the first direction X. The second portion 1112 is connected to the first portion 1111. The two second portions 1112 are adjacent to the same pixel barrier electrode structure 121 in the pixel unit 140.

[0091] Specifically, in the pixel unit 140 of this embodiment, the second part 1112 is disposed on the same pixel barrier electrode structure 121 in a back-to-back manner.

[0092] In the above solution, by arranging the driving pixels driving electrodes 111 back to back, the viewing angles in both the left and right directions can be improved, and the manufacturing difficulty can be reduced.

[0093] Similarly, in this embodiment, in the first direction X, the size L7 of the first portion 1111 is smaller than the size L8 of the second portion 1112, and in the second direction Y, the size L7 of the first portion 1111 is smaller than the size L8 of the second portion 1112. 10 It is larger than the size L9 of the second part 1112.

[0094] Figure 10 This is a wide-viewing-angle schematic diagram of an array substrate according to another embodiment of this application. (See attached diagram.) Figure 10 As shown, when the pixel driving electrodes 111 are arranged back to back, a viewing angle in another direction can be increased.

[0095] Please continue to refer to Figure 6 or Figure 9 In some embodiments, the array substrate 100 further includes a light-shielding layer 150, wherein in the first direction X, the pixel barrier electrode structure 121 is located between the substrate 110 and the light-shielding layer 150, and in the second direction Y, the size W2 of the light-shielding layer 150 is the same as the size W1 of the pixel barrier electrode structure 121.

[0096] In other words, the light-shielding layer 150 is only disposed above the pixel barrier electrode structure 121.

[0097] In the above solution, by setting an LS light-shielding layer 150 above the pixel barrier electrode structure 121 and replacing the black matrix in the related technology with the LS light-shielding layer 150, the display effect of the array substrate 100 can be further improved; and in the second direction Y, the size of the light-shielding layer 150 is the same as the size of the pixel barrier electrode structure 121, which can ensure that the pixel barrier electrode structure 121 has the largest opening area size, thereby improving the pixel opening.

[0098] Figure 11 This is a schematic diagram of the structure of an array substrate according to another embodiment of this application. Figure 11 As shown, the pixel area 300 also includes ink particles 310; in the first direction X, the number of layers of ink particles 310 is greater than or equal to two.

[0099] like Figure 11 As shown in the figure, the black particles represent ink particles 310, which ensure the normal display function of the array substrate 100.

[0100] In the above scheme, by limiting the number of ink particles 310 arranged in the pixel area 300 to no less than two layers, the display effect of the array substrate 100 can be improved.

[0101] This application also provides a display device, including the array substrate 100 in any of the above possible implementations.

[0102] The display device can be an OLED display or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, or tablet computer that includes such display devices.

[0103] The fabrication process of the array substrate described in the embodiments of this application will be briefly described below with reference to the accompanying drawings. It should be noted that the following fabrication process only specifically describes the fabrication process related to the embodiments of this application, and fabrication processes consistent with related technologies will not be described again.

[0104] Figure 12 This is a schematic diagram of the fabrication process of an array substrate according to an embodiment of this application.

[0105] First, there is the general fabrication process of TFTs, including the fabrication of the ACT active layer, Gate, source / drain electrodes (SD), and PVX protective layer.

[0106] Then PW Coating: forming a film of the pixel barrier electrode structure on the TFT;

[0107] Then HM photo: Set a light-shielding layer on some pixel barrier electrode structures;

[0108] Next, PW ETCH: Through HardMask metal patterning, the pixel barrier electrode structure pattern is formed after etching;

[0109] Finally, ITO MASK: Indium tin oxide is deposited, and the image definition of the pixel driving electrode is achieved through the MASK process (corresponding to 4 in the figure).

[0110] It should be noted that in this embodiment, indium tin oxide follows the pixel barrier electrode structure pattern, that is, the pixel driving electrode is defined by the pixel barrier electrode structure pattern, and the ITO mask is simply the removal of ITO in the non-pixel area by etching, thereby forming the array substrate structure described in the above embodiment.

[0111] It should be noted that when the array substrate 100 is fabricated using the above-mentioned fabrication process, not only can a structure in which the pixel driving electrode and the pixel barrier electrode structures are only adjacent and do not overlap be obtained, but the footing phenomenon of the pixel barrier electrode structure can also be improved, thereby further increasing the aperture ratio.

[0112] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.

Claims

1. An array substrate, characterized by, Comprising: a substrate and a pixel layer arranged along a first direction; and a pixel barrier electrode structure; in a second direction and a third direction, the pixel layer comprises a plurality of pixel regions arranged in sequence, the pixel regions comprising a pixel driving electrode, the second direction being perpendicular to the first direction, and the third direction being perpendicular to the first direction and the second direction; wherein the pixel barrier electrode structure is located between two adjacent pixel regions, and the pixel barrier electrode structure is connected to the pixel driving electrode.

2. The array substrate of claim 1, wherein, In the first direction, the size of the pixel barrier electrode structure is greater than the size of the pixel driving electrode.

3. The array substrate of claim 2, wherein, In the first direction, the size of the pixel barrier electrode structure is greater than or equal to 25 μm.

4. The array substrate according to any one of claims 1-3, wherein, The array substrate comprises a plurality of pixel units arranged along the second direction, each of the pixel units comprising one of the pixel regions and one of the pixel barrier electrode structures; The pixel driving electrode comprises a first portion arranged along the second direction.

5. The array substrate of claim 4, wherein, The pixel driving electrode further comprises a second portion arranged along the first direction, and the second portion is connected to the first portion; In the second direction, a plurality of the second portions are connected to the same side of a plurality of the pixel barrier electrode structures.

6. The array substrate of claim 4, wherein, The pixel driving electrode further comprises a second portion and a third portion arranged along the first direction, and the second portion and the third portion are both connected to the first portion; In the second direction, the first portion has a first end close to the pixel barrier electrode structure and a second end away from the pixel barrier electrode structure; The second portion is arranged at the first end and connected to the pixel barrier electrode structure, and the third portion is arranged at the second end and connected to an adjacent pixel barrier electrode structure.

7. The array substrate of claim 6, wherein, In the first direction, the size of the first portion is smaller than the size of the second portion, and the size of the first portion is smaller than the size of the third portion; In the second direction, the size of the first portion is greater than the size of the second portion, and the size of the first portion is greater than the size of the third portion.

8. The array substrate according to any one of claims 1-3, wherein, The array substrate comprises a plurality of pixel units arranged along the second direction, each of the pixel units comprising two of the pixel regions and two of the pixel barrier electrode structures; The pixel driving electrode comprises a first portion arranged along the second direction and a second portion arranged along the first direction, and the second portion is connected to the first portion; wherein two of the second portions are connected to the same one of the pixel barrier electrode structures in the pixel unit.

9. The array substrate according to claim 5 or 8, wherein, In the first direction, the size of the first portion is smaller than the size of the second portion; In the second direction, the size of the first portion is greater than the size of the second portion.

10. The array substrate according to any one of claims 1-3, wherein, The array substrate further comprises a light shielding layer, and in the first direction, the pixel barrier electrode structure is located between the substrate and the light shielding layer; In the second direction, the size of the light shielding layer is the same as the size of the pixel barrier electrode structure.

11. The array substrate of any one of claims 1-3, wherein, The pixel region further comprises ink particles; In the first direction, the number of layers of the ink particles is greater than or equal to two.

12. A display device comprising: An array substrate including any of the array substrate as claimed in any of claims 1-11.

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