A control circuit, chip, power supply, electronic device, and control method.

Abstract

This application provides a control circuit, a chip, a power supply, an electronic device, and a control method. The control circuit includes: a first digital error signal determination circuit that determines an initial error signal and obtains a first digital error signal based on the initial error signal; a second digital error signal determination circuit that determines an initial analog error signal and obtains a second digital error signal based on the initial analog error signal; a comprehensive error determination circuit that determines a comprehensive error signal based on the first and second digital error signals; when the value of the second digital error signal is a second left endpoint or a second right endpoint, the comprehensive error signal is equal to the first digital error signal; when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal; a digital controller is connected to the target circuit and performs feedback control on the target circuit based on the comprehensive error signal to control the target circuit, which is beneficial for balancing control accuracy and ease of maintenance.

Description

Technical Field

[0001] This application relates to the field of circuits, and more particularly to a control circuit, a chip, a power supply, an electronic device, and a control method. Background Technology

[0002] Analog control uses continuous analog quantities (such as output voltage and output current signals) for control. These signals change continuously in both time and value, without quantization error, and can accurately represent the true state of physical quantities. Therefore, analog control can theoretically achieve infinitely fine control and has the advantage of high precision. However, because analog control controllers are built using circuits such as operational amplifiers, they are limited by the arrangement of circuit components. When the control algorithm changes, it is necessary to disassemble or even redraw the printed circuit board (PCB), making maintenance difficult.

[0003] Digital control uses digital signals to represent information. These signals change discontinuously in time and value. Continuously changing analog signals are converted into digital signals for processing through sampling and quantization. Digital control controllers can implement various complex algorithms through software programming, are easy to maintain, and have strong anti-interference capabilities. However, digital control requires sampling analog signals to obtain digital signals. Digital signals can only approximate analog signals, and this process introduces quantization errors. Therefore, the accuracy of digital control is affected by sampling errors. In scenarios with extremely high control accuracy requirements (such as high-voltage power supplies), traditional digital control is inaccurate, resulting in large voltage signal ripple (i.e., fluctuations in output voltage caused by noise and interference). Therefore, to reduce voltage signal ripple, analog control is usually used to ensure control accuracy. However, analog control suffers from the aforementioned maintenance difficulties. Summary of the Invention

[0004] This application discloses a control circuit, chip, power supply, electronic device, and control method to solve the problem that the prior art cannot balance control accuracy and ease of maintenance when reducing voltage signal ripple.

[0005] In a first aspect, this application provides a control circuit, including:

[0006] A first digital error signal determination circuit is configured to determine an initial error signal and obtain a first digital error signal based on the initial error signal. The threshold range of the first digital error signal has a first left endpoint and a first right endpoint. Specifically, when the initial error signal is the initial analog error signal of both the analog signal of the reference signal and the analog signal of the output signal of the target circuit, the first digital error signal is obtained by uniformly mapping the initial analog error signal with a threshold range equal to the initial threshold range to a threshold range from the first left endpoint to the first right endpoint. Alternatively, when the initial error signal is the initial digital error signal of both the digital signal of the reference signal and the digital signal of the output signal, the first digital error signal is equal to the initial digital error signal.

[0007] A second digital error signal determination circuit is configured to determine the initial analog error signal and map a second digital error signal based on the initial analog error signal. The threshold range of the second digital error signal has a second left endpoint and a second right endpoint. The initial threshold range contains a sub-threshold range, which has a third left endpoint and a third right endpoint. Initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second digital error signals greater than the second left endpoint and less than the second right endpoint. Initial analog error signals less than or equal to the third left endpoint are mapped to second digital error signals located at one of the second left endpoint and the second right endpoint. Initial analog error signals greater than or equal to the third right endpoint are mapped to second digital error signals located at the other endpoint of the second left endpoint and the second right endpoint.

[0008] A comprehensive error determination circuit is used to determine a comprehensive error signal based on a first digital error signal and a second digital error signal; wherein, when the value of the second digital error signal is the second left endpoint or the second right endpoint, the comprehensive error signal is equal to the first digital error signal; when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal.

[0009] A digital controller, connected to the target circuit, is used to perform feedback control on the target circuit based on the comprehensive error signal, so as to control the output signal of the target circuit.

[0010] In the above embodiments, firstly, to address the problem of difficult maintenance of analog control, the above embodiments utilize digital controllers for control. Digital controllers mainly use software to implement control logic, making maintenance easier when the control algorithm changes, and also making it easier to implement complex algorithms; in addition, they have advantages such as strong anti-interference ability.

[0011] Second, this application non-uniformly maps the initial analog error signal to a second digital error signal (for example, an initial analog error signal greater than the third left endpoint and less than the third right endpoint is uniformly mapped to a second digital error signal greater than the second left endpoint and less than the second right endpoint; an initial analog error signal less than or equal to the third left endpoint is mapped to a second digital error signal located at one of the second left endpoint and the second right endpoint; an initial analog error signal greater than or equal to the third right endpoint is mapped to a second digital error signal located at the other of the second left endpoint and the second right endpoint). When the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal, and the comprehensive error signal is used to perform feedback control on the target circuit, which is beneficial to ensuring control accuracy.

[0012] Specifically, considering that digital sampling circuits are needed to sample the signal during the digital signal acquisition process, the representation range of these circuits is typically limited, for example, integers between 0 and 4096. In the above embodiment, during the mapping of the initial analog error signal to the second digital error signal, the initial analog error signal within the sub-threshold range is uniformly mapped to the threshold range of the second digital error signal. The initial analog error signal outside the sub-threshold range is mapped to the endpoints of the second digital error signal, so that the range of the second digital error signal is primarily used to represent the initial analog error signal within the sub-threshold range. Since the sub-threshold range is a subset of the threshold range of the initial analog error signal, it can be considered that the initial analog error signal within the sub-threshold range represents the case where the difference between the output signal of the target circuit and the reference signal is small. Therefore, the range of the second digital error signal is primarily used to represent the case where the difference between the output signal of the target circuit and the reference signal is small; that is, integers other than the endpoints 0 and 4096 within the range of 0 can, for example, be used to represent the initial analog error signal being in the range of -100V to 100V (excluding the endpoints), rather than representing the range of -5000V to 5000V. In other words, integers from 0 to 4096, excluding the endpoints, only need to represent a range of 200V, and do not need to represent a range of 10000V. Taking a sampling error rate of 0.024% as an example, the sampling error is 200... 0.024% = 0.048V. If a traditional digital control method is used to uniformly map the initial analog error signal to the second digital error signal, the sampling error will be 10000. 0.024% = 2.4V. It is clear that 0.048V is much smaller than 2.4V. Therefore, when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint (for example, when the second digital error signal belongs to 0~4096 and does not include endpoints), this application effectively reduces the sampling error caused by the analog-to-digital sampling circuit, ensuring high sampling accuracy. At this time, determining the comprehensive error signal based on the second digital error signal enables more precise feedback control.

[0013] Third, this application uniformly maps the initial analog error signal to a first digital error signal, or uses the initial digital error signal as the first digital error signal, and when the second digital error signal takes the value of the second left endpoint or the second right endpoint, uses the first digital error signal as the comprehensive error signal. Compared to using the second digital error signal for feedback control, this application maintains higher control accuracy even when the second digital error signal takes the value of the second left endpoint or the second right endpoint. As mentioned earlier, when the second digital error signal takes the value of the second left endpoint or the second right endpoint, it can represent a wide range of -5000V to -100V or 100V to 5000V. Therefore, the second digital error signal cannot accurately reflect the difference between the output signal and the reference signal of the target circuit, and the feedback control error using the second digital error signal will be large. Since the first digital error signal has a sampling error when the second digital error signal takes the value of the second left endpoint or the second right endpoint, the difference between the reference signal and the output signal is large. In comparison, the sampling error can be ignored. In other words, the impact of the sampling error on the control accuracy is very limited, and this application still has high control accuracy. Furthermore, this application facilitates rapid adjustment and reduces output signal fluctuations in scenarios involving sudden changes in the target circuit's output signal, such as ignition or jitter. Taking the aforementioned data as an example, when the second digital error signal is located at either the second left or right endpoint, regardless of whether the output signal is 1000V or 4000V, the second digital error signal reaches its endpoint (e.g., 0). In this case, the second digital error signal cannot accurately reflect the difference between the output signal and the reference signal. During the initialization phase of feedback control, such as when the output signal increases from 0V to 4900V, the first digital error signal accurately reflects the difference between the output signal and the reference signal. Therefore, this application can quickly adjust the output signal from 0V to 4900V. If the second digital error signal were used, it would take a much longer to adjust to 4900V. This difference in adjustment efficiency also contributes to the application's ability to reduce output signal fluctuations in the target circuit during scenarios with sudden changes in the output signal.

[0014] In summary, this application, while ensuring control accuracy, can implement complex algorithms, is easy to maintain, and helps reduce power supply ripple. It is applicable to both low-voltage and high-voltage scenarios, and is particularly advantageous for high-voltage, low-ripple applications.

[0015] In one possible implementation, a fourth left endpoint and a fourth right endpoint are provided between the second left endpoint and the second right endpoint; the determination of the comprehensive error signal based on the second digital error signal when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint includes: when the second digital error signal is greater than the second left endpoint and less than the fourth left endpoint, or greater than the fourth right endpoint and less than the second right endpoint, the comprehensive error signal is a weighted sum of the first digital error signal and the second digital error signal; and / or when the second digital error signal is greater than or equal to the fourth left endpoint and less than or equal to the fourth right endpoint, the comprehensive error signal is equal to the second digital error signal.

[0016] In the above embodiments, considering the fluctuation of the output signal, when the output signal and the reference signal are just approaching each other, the second digital error signal may be within the second threshold range at one moment and at the endpoint of the second threshold range at the next moment. If the comprehensive error signal is set to be equal to the second digital error signal when the second digital error signal is within the second threshold range, it may lead to control using the second digital error signal at one moment and the first digital error signal at the next moment (i.e., switching back and forth). The values ​​of the second digital error signal and the first digital error signal are often different, which may cause disturbances. By setting a fourth threshold range with endpoints at the fourth left endpoint and the fourth right endpoint respectively within the second threshold range, the fourth threshold range is smaller than the second threshold range. Therefore, when the second digital error signal is outside the fourth threshold range but within the second digital threshold range, the switching back and forth situation is likely to occur. Setting the signal used for feedback control as a weighted sum of the first digital error signal and the second digital error signal helps to avoid the back and forth jump of the signal used for feedback control, reduce disturbances, and improve control stability. When the second digital error signal is within the fourth threshold range, it means that the output signal and the reference signal are closer. At this time, the second digital error signal is more accurate. Therefore, using the second digital error signal for feedback control can ensure control accuracy.

[0017] In one possible implementation, the distance from the fourth left endpoint to the second left endpoint is greater than or equal to 1% and less than or equal to 15% of the distance from the second left endpoint to the second right endpoint; and / or the distance from the fourth right endpoint to the second right endpoint is greater than or equal to 1% and less than or equal to 15% of the distance from the second left endpoint to the second right endpoint. This sets a relatively reasonable range, making it less likely for the second digital error signal to switch back and forth when it is located between the fourth left endpoint and the fourth right endpoint, which helps to ensure control accuracy.

[0018] In one possible implementation, the comprehensive error signal is a weighted sum of the first digital error signal and the second digital error signal, including: the weighting coefficient of the first digital error signal is positively correlated with the distance of the first digital error signal to the midpoint between the first left endpoint and the first right endpoint.

[0019] In the above embodiments, when the distance from the first digital error signal to the midpoint is large, it can be considered that the difference between the output signal and the reference signal is large. In this case, the first digital error signal is more accurate than the second digital error signal. Since the weighting coefficient of the first digital error signal is positively correlated with the distance from the first digital error signal to the midpoint, when the distance from the first digital error signal to the midpoint is large, the weight of the first digital error signal is also large. This is beneficial to making the comprehensive error signal determined based on the weighted sum of the first and second digital error signals more accurate. Furthermore, when the distance from the first digital error signal to the midpoint is small, it can be considered that the difference between the output signal and the reference signal is small. In this case, the second digital error signal is more accurate than the first digital error signal. Since the weighting coefficient of the first digital error signal is positively correlated with the distance from the first digital error signal to the midpoint, when the distance from the first digital error signal to the midpoint is small, the weight of the first digital error signal is also small. Relatively speaking, the weight of the second digital error signal is larger. This is beneficial to making the comprehensive error signal determined based on the weighted sum of the first and second digital error signals more accurate.

[0020] In one possible implementation, the second digital error signal determination circuit includes: a second operational amplifier circuit for mapping the initial analog error signal to a second analog error signal, wherein the threshold range of the second analog error signal has a fifth left endpoint and a fifth right endpoint, wherein an initial analog error signal greater than the third left endpoint and less than the third right endpoint is uniformly mapped to a second analog error signal greater than the fifth left endpoint and less than the fifth right endpoint; an initial analog error signal less than or equal to the third left endpoint is mapped to a second analog error signal located at one of the fifth left endpoint and the fifth right endpoint; and an initial analog error signal greater than or equal to the third right endpoint is mapped to a second analog error signal located at the other endpoint of the fifth left endpoint and the fifth right endpoint; and a second analog-to-digital sampling circuit for sampling the second analog error signal to obtain the second digital error signal. Wherein, the second analog error signal located at the fifth left endpoint corresponds to the second digital error signal located at the second left endpoint, the second analog error signal located at the fifth right endpoint corresponds to the second digital error signal located at the second right endpoint, and the second analog error signal greater than the third left endpoint and less than the third right endpoint corresponds to the second digital error signal greater than the second left endpoint and less than the second right endpoint.

[0021] The above embodiment constructs a second digital error signal determination circuit through a second operational amplifier circuit and a second analog-to-digital sampling circuit. The structure is simple and easy to implement. The initial analog error signal is mapped to a second analog error signal using a second operational amplifier circuit. (Initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second analog error signals greater than the fifth left endpoint and less than the fifth right endpoint; initial analog error signals less than or equal to the third left endpoint are mapped to a second analog error signal located at one of the fifth left and fifth right endpoints; initial analog error signals greater than or equal to the third right endpoint are mapped to the other of the fifth left and fifth right endpoints.) The initial analog error signal is divided into three parts and mapped to obtain the second analog error signal. The two sides (corresponding to larger initial analog error signals) are mapped to the endpoints of the second analog error signal, and the middle part (corresponding to smaller initial analog error signals) is mapped to the part of the second analog error signal excluding the endpoints. In this way, when the subsequent second analog-to-digital sampling circuit samples the second analog error signal to obtain the second digital error signal, the two sides of the initial analog error signal also correspond to the endpoints of the second digital error signal, and the middle part corresponds to the part of the second digital error signal excluding the endpoints. This makes the range of the second digital error signal mainly used to represent the case of smaller errors.

[0022] In one possible implementation, the second digital error signal determination circuit further includes: a second subtractor connected between the target circuit and the second operational amplifier circuit, for determining the initial analog error signal based on the analog signal of the output signal and the analog signal of the reference signal, and sending it to the second operational amplifier circuit.

[0023] The above embodiment uses a subtractor to determine the initial analog error signal, which is simple in structure and easy to implement.

[0024] In one possible implementation, the initial error signal is the initial analog error signal; the first digital error signal determination circuit includes: a first operational amplifier circuit for uniformly mapping the initial analog error signal into a first analog error signal; and a first analog-to-digital sampling circuit for sampling the first analog error signal to obtain the first digital error signal.

[0025] The above embodiment constructs a first digital error signal determination circuit through a first operational amplifier circuit and a first analog-to-digital sampling circuit. The structure is simple and easy to implement.

[0026] In one possible implementation, the first digital error signal determination circuit further includes: a first subtractor connected between the target circuit and the first operational amplifier circuit, for determining the initial analog error signal based on the analog signal of the output signal and the analog signal of the reference signal, and sending it to the first operational amplifier circuit.

[0027] The above embodiment uses a subtractor to determine the initial analog error signal, which is simple in structure and easy to implement.

[0028] In one possible implementation, the initial error signal is the initial digital error signal, and the first digital error signal determination circuit further includes:

[0029] The third analog-to-digital sampling circuit is used to sample the output signal to obtain the digital signal of the output signal;

[0030] The third subtractor, connected between the third analog-to-digital sampling circuit and the comprehensive error determination circuit, is used to determine the initial digital error signal based on the digital signal of the reference signal and the digital signal of the output signal, and send it to the comprehensive error determination circuit.

[0031] In the above embodiments, a circuit for determining the first digital error signal is constructed using a third analog-to-digital sampling circuit and a third subtractor. The circuit has a simple structure and is easy to implement.

[0032] In one possible implementation, the control circuit further includes a digital-to-analog converter connected between the digital controller and the target circuit, for converting digital control signals emitted by the digital controller into analog control signals, the analog control signals being used to control the target circuit.

[0033] As one implementation approach, the digital controller can be integrated within the chip, while the analog-to-digital converter (ADC) is located externally. It should be understood that if the target circuit is directly controlled via the chip, the on-chip digital controller outputs control signals to the on-chip conditioning circuitry. The conditioning circuitry generates a pulse-width modulation (PWM) waveform, and the accuracy of this circuitry is limited by the accuracy of the carrier wave used in the conditioning process, which in turn is constrained by the chip's clock frequency. By placing the ADC externally, the generated analog control signal is not constrained by the chip's clock frequency but rather by the accuracy of the ADC itself. Compared to using a chip, the ADC typically suffers less loss, resulting in higher control accuracy.

[0034] Secondly, this application provides a chip including the control circuit described in any of the above embodiments.

[0035] Thirdly, this application provides a power supply whose output voltage is controlled by a control circuit as described in any of the above embodiments.

[0036] Fourthly, this application provides an electronic device including a power supply as described in any of the above embodiments.

[0037] Fifthly, this application provides a control method, comprising: determining an initial error signal and obtaining a first digital error signal based on the initial error signal, wherein the threshold range of the first digital error signal has a first left endpoint and a first right endpoint; wherein, when the initial error signal is the initial analog error signal of both an analog signal of a reference signal and an analog signal of an output signal of a target circuit, the first digital error signal is obtained by uniformly mapping the initial analog error signal with a threshold range equal to the initial threshold range to a threshold range from the first left endpoint to the first right endpoint; or, when the initial error signal is the initial digital error signal of both a digital signal of a reference signal and a digital signal of an output signal, the first digital error signal is equal to the initial digital error signal; determining the initial analog error signal and mapping a second digital error signal based on the initial analog error signal, wherein the threshold range of the second digital error signal has a second left endpoint and a second right endpoint; wherein, the initial threshold range contains a sub-threshold range, and the sub-threshold range has a third left endpoint and a third right endpoint. An initial analog error signal greater than the third left endpoint and less than the third right endpoint is uniformly mapped to a second digital error signal greater than the second left endpoint and less than the second right endpoint; an initial analog error signal less than or equal to the third left endpoint is mapped to a second digital error signal located at one of the second left endpoint and the second right endpoint; and an initial analog error signal greater than or equal to the third right endpoint is mapped to a second digital error signal located at the other endpoint of the second left endpoint and the second right endpoint; a comprehensive error signal is determined based on the first digital error signal and the second digital error signal; wherein, when the value of the second digital error signal is the second left endpoint or the second right endpoint, the comprehensive error signal is equal to the first digital error signal; when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal; and feedback control is performed on the target circuit based on the comprehensive error signal to control the output signal. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 and Figure 2 This is a schematic diagram of a control circuit according to different embodiments of the present disclosure.

[0040] Figure 3 This is a schematic diagram illustrating the mapping relationship between an initial analog error signal and a first digital error signal according to some embodiments of the present disclosure.

[0041] Figure 4 This is a schematic diagram illustrating the mapping relationship between an initial analog error signal and a second digital error signal according to some embodiments of this disclosure.

[0042] Figure 5 This is a schematic diagram illustrating the mapping relationship between an initial analog error signal, a second analog error signal, and a second digital error signal according to some embodiments of this disclosure.

[0043] Figure 6 This is a flowchart illustrating a control method according to some embodiments of the present disclosure.

[0044] Explanation of reference numerals in the attached figures:

[0045] 100 - First digital error signal determination circuit; 110 - First subtractor; 120 - First operational amplifier circuit; 130 - First analog-to-digital sampling circuit;

[0046] 200 - Second digital error signal determination circuit; 210 - Second subtractor; 220 - Second operational amplifier circuit; 230 - Second analog-to-digital sampling circuit;

[0047] 310 - Third subtractor; 320 - Third operational amplifier circuit; 330 - Third analog-to-digital sampling circuit;

[0048] 400 - Comprehensive Error Determination Circuit;

[0049] 500-Digital Controller;

[0050] 600-Digital-to-Analog Converter;

[0051] 700 - Target Circuit;

[0052] 800 - Fourth op-amp circuit. Detailed Implementation

[0053] Power supplies are widely used in scientific research, industrial manufacturing, medical fields, and other areas. Electronic devices typically use power supplies to provide voltage. Power supplies can include high-voltage power supplies and ordinary power supplies. High-voltage power supplies refer to power supplies with voltages greater than 1KV (e.g., 5KV, 10KV, 45KV, or 100KV).

[0054] As described in the background section, traditional digital control suffers from relatively large sampling errors. Traditional digital control typically first performs analog-to-digital (AD) sampling on the output voltage of the target circuit 700, then determines the digital error based on the difference between the reference voltage and the output voltage of the target circuit 700, and finally performs feedback control based on this digital error. AD sampling maps continuous analog values ​​to discrete values, which cannot accurately reflect continuous analog values, thus introducing errors. Taking a common AD sampling circuit as an example, the mapping range is typically 0~4096, and it can only map to integer values, not smaller values; its error ratio reaches 1 / 4096 = 0.024%. Taking a target circuit 700 output voltage of 5000V as an example, without considering other factors, the AD sampling error is 5000V. 0.024% = 1.22V.

[0055] Because a large error is introduced during the AD sampling process of the output voltage of the target circuit 700, the digital error determined based on the reference voltage and the output voltage of the target circuit 700 also contains a large error. Furthermore, when feedback control is performed based on traditional digital errors, it will affect the control accuracy of the target circuit 700, causing large ripple in the output voltage of the target circuit 700.

[0056] The power supply control specifications are, for example, a voltage of 5000V and ripple control within ±5ppm. This means the ripple should be controlled within 5000V. Within 0.000005 = 0.025V. Because the sampling error (e.g., 1.22V) is much larger than the ripple value (e.g., 0.025V), traditional digital control methods in related technologies cannot collect the ripple when it occurs, and the controller cannot control the ripple. This makes it impossible for traditional digital control accuracy to meet the technical requirements.

[0057] Therefore, analog control is commonly used in related technologies to reduce ripple. However, since analog controllers cannot implement control logic through software programming like digital controllers (e.g., 500), they rely on a combination of hardware such as operational amplifiers. This hardware layout limitations make it difficult to replace hardware when the control algorithm changes, requiring board disassembly or even PCB redesign, resulting in maintenance difficulties.

[0058] Example 1

[0059] Figure 1 and Figure 2 This is a schematic diagram of a control circuit according to different embodiments of the present disclosure. Figure 3 This is a schematic diagram illustrating the mapping relationship between an initial analog error signal and a first digital error signal according to some embodiments of the present disclosure. Figure 4This is a schematic diagram illustrating the mapping relationship between an initial analog error signal and a second digital error signal according to some embodiments of this disclosure.

[0060] like Figure 1 and Figure 2 As shown, this application provides a control circuit, which includes a first digital error signal determination circuit 100, a second digital error signal determination circuit 200, a comprehensive error determination circuit 400, and a digital controller 500.

[0061] The first digital error signal determination circuit 100 is used to determine an initial error signal and obtain a first digital error signal based on the initial error signal. Here, the threshold range (i.e., the initial threshold range) of the initial error signal has an initial left endpoint (e.g., -5000V) and an initial right endpoint (e.g., 5000V). The threshold range of the first digital error signal has a first left endpoint (e.g., 0) and a first right endpoint (e.g., 4096). It should be understood that the first digital error signal is a digital signal, and the first digital error signal can, for example, be represented as an integer value in the range of 0 to 4096. The first digital error signal determination circuit 100 includes, for example, […]. Figure 1 One or more of the first subtractor 110, the first operational amplifier circuit 120, and the first analog-to-digital sampling circuit 130 shown, for example including Figure 2 The first digital error signal determination circuit 100, which includes one or more of the third subtractor 310, the third operational amplifier circuit 320, and the third analog-to-digital sampling circuit 330 shown, will be further described later with reference to some embodiments.

[0062] Specifically, such as Figure 1 As shown, when the initial error signal is the initial analog error signal of both the reference signal (e.g., fluctuating between 0 and 5000V) and the output signal of the target circuit 700 (e.g., fluctuating between 0 and 5000V), the first digital error signal is obtained by uniformly mapping the initial analog error signal with a threshold range of the initial threshold range (e.g., -5000V to 5000V) to a threshold range (e.g., 0 to 4096) from the first left endpoint to the first right endpoint. That is, as... Figure 3 As shown, when the initial error signal is an initial analog error, it corresponds to a continuous value from -5000V to 5000V, and the first digital error signal corresponds to an integer value from 0 to 4096. The mapping between the initial analog error signal and the first digital error signal is uniform. It should be understood that this uniformity ignores the non-uniformity caused by mapping continuous values ​​to discrete values. Ignoring the non-uniformity caused by mapping continuous values ​​to discrete values, the mapping from the initial analog error signal to the first digital error signal can be considered linear.

[0063] like Figure 2As shown, when the initial error signal is the initial digital error signal of both the reference signal and the output signal (e.g., 0~4096, used to reflect voltage error of -5000V~5000V), the first digital error signal is equal to the initial digital error signal.

[0064] like Figure 1 and Figure 2 As shown, the second digital error signal determination circuit 200 is used to determine the initial analog error signal and map the second digital error signal based on the initial analog error signal. Here, the threshold range of the second digital error signal (i.e., the second threshold range) has a second left endpoint (e.g., 0) and a second right endpoint (e.g., 4096). The second digital error signal determination circuit 200 includes, for example, […]. Figure 1 and Figure 2 One or more of the second subtractor 210, the second operational amplifier circuit 220, and the second analog-to-digital sampling circuit 230 shown.

[0065] Specifically, such as Figure 4 As shown, the initial threshold range contains sub-threshold ranges (e.g., -100V to 100V), each sub-threshold range having a third left endpoint (e.g., -100V) and a third right endpoint (e.g., 100V). Initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second digital error signals greater than the second left endpoint (e.g., 0) and less than the second right endpoint (e.g., 4096). For example, initial analog error signals in the range of -100V to 100V are uniformly mapped to second digital error signals of 0 to 4096. Initial analog error signals less than or equal to the third left endpoint are mapped to second digital error signals located at one of the second left and second right endpoints. For example, initial analog error signals less than -100V, i.e., -5000V to -100V, are mapped to one of 0 and 4096. Initial analog error signals greater than or equal to the third right endpoint are mapped to second digital error signals located at the other endpoint of the second left and second right endpoints. For example, an initial analog error signal greater than 100V, i.e., 100V~500V, is mapped to either 0 or 4096. It can be seen that here, the initial analog error signal is not uniformly mapped to the second digital error signal. Instead, the initial analog error signal is divided into three parts: the parts on the left and right are mapped to the endpoints of the second digital error signal, and only the sub-threshold range in the middle is uniformly mapped to the second digital error signal.

[0066] It should be understood that, as some implementation methods, such as Figure 4As shown, the initial analog error signal less than or equal to the third left endpoint is mapped to the second digital error signal located at the second left endpoint. The initial analog error signal greater than or equal to the third right endpoint is mapped to the second digital error signal located at the second right endpoint; this is not intended to limit the scope of this application.

[0067] The comprehensive error determination circuit 400 is used to determine a comprehensive error signal based on a first digital error signal and a second digital error signal. Here, when the value of the second digital error signal is either the second left endpoint or the second right endpoint, the comprehensive error signal is equal to the first digital error signal. When the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal. For example, when the value of the second digital error signal is 0 or 4096, the comprehensive error signal is equal to the first digital error signal. When the value of the second digital error signal is greater than 0 and less than 4096, the comprehensive error signal is determined based on the second digital error signal.

[0068] A digital controller 500, connected to the target circuit 700, is used to perform feedback control on the target circuit 700 based on a comprehensive error signal, thereby controlling the output signal of the target circuit 700. For example, it can control the voltage of the output signal of the target circuit 700, i.e., control the output voltage of the target circuit 700. The digital controller 500 may be, for example, a proportional-integral (PI) controller, a proportional-integral-derivative (PID) controller, etc., and this application is not limited thereto.

[0069] First, in response to the problems of analog control being difficult to implement complex algorithms and difficult to maintain, the above embodiment uses a digital controller 500 for control. The digital controller 500 mainly uses software to implement the control logic. When the control algorithm changes, it is easy to maintain and easier to implement complex algorithms. In addition, it also has the advantages of strong anti-interference ability.

[0070] Second, this application non-uniformly maps the initial analog error signal to a second digital error signal (for example, an initial analog error signal greater than the third left endpoint and less than the third right endpoint is uniformly mapped to a second digital error signal greater than the second left endpoint and less than the second right endpoint; an initial analog error signal less than or equal to the third left endpoint is mapped to a second digital error signal located at one of the second left endpoint and the second right endpoint; an initial analog error signal greater than or equal to the third right endpoint is mapped to a second digital error signal located at the other of the second left endpoint and the second right endpoint). When the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, a comprehensive error signal is determined based on the second digital error signal, and the comprehensive error signal is used to perform feedback control on the target circuit 700, which is beneficial to ensuring control accuracy.

[0071] Specifically, considering that digital sampling circuits are needed to sample the data during the process of obtaining digital signals, the representation range of digital sampling circuits is usually limited, for example, integers between 0 and 4096. In the above embodiment, during the process of mapping the initial analog error signal to the second digital error signal, the initial analog error signal within the sub-threshold range is uniformly mapped to the threshold range of the second digital error signal, while the initial analog error signal outside the sub-threshold range is mapped to the endpoints of the second digital error signal. This ensures that the range of the second digital error signal is primarily used to represent the initial analog error signal within the sub-threshold range. Since the sub-threshold range is a subset of the threshold range of the initial analog error signal, the initial analog error signal within the sub-threshold range can be considered to represent the case where the difference between the output signal of the target circuit 700 and the reference signal is small. Therefore, the range of the second digital error signal is mainly used to represent cases where the difference between the output signal of the target circuit 700 and the reference signal is small. That is, integers within the range of 0 to 4096, excluding the endpoints 0 and 4096, can be used to represent the initial analog error signal being in the range of -100V to 100V (excluding the endpoints), rather than representing the range of -5000V to 5000V. In other words, the integers from 0 to 4096, excluding the endpoints, only need to represent a range of 200V, not a range of 10000V. For example, with a sampling error rate of 0.024%, the sampling error is 200V. 0.024% = 0.048V. If a traditional digital control method is used to uniformly map the initial analog error signal to the second digital error signal, the sampling error will be 10000. 0.024% = 2.4V. It is clear that 0.048V is much smaller than 2.4V. Therefore, when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint (for example, when the second digital error signal belongs to 0~4096 and does not include endpoints), this application effectively reduces the sampling error caused by the analog-to-digital sampling circuit, ensuring high sampling accuracy. At this time, determining the comprehensive error signal based on the second digital error signal enables more precise feedback control.

[0072] Third, this application uniformly maps the initial analog error signal to a first digital error signal, or uses the initial digital error signal as the first digital error signal, and when the second digital error signal takes the value of the second left endpoint or the second right endpoint, uses the first digital error signal as the comprehensive error signal. Compared to using the second digital error signal for feedback control, this maintains higher control accuracy. As mentioned earlier, when the second digital error takes the value of the second left endpoint or the second right endpoint, it can represent a wide range of -5000V to -100V or 100V to 5000V. Therefore, the second digital error signal cannot accurately reflect the difference between the output signal and the reference signal of the target circuit 700, and the feedback control error using the second digital error signal will be large. Since the second digital error takes the value of the second left endpoint or the second right endpoint, although the first digital error signal has a sampling error, the difference between the reference signal and the output signal is large. In comparison, the sampling error can be ignored. In other words, the sampling error has a very limited impact on the control accuracy, and this application still has high control accuracy. Furthermore, it facilitates rapid adjustment and reduces output signal fluctuations in scenarios involving sudden changes in the output signal of the target circuit 700, such as ignition or jitter. Taking the aforementioned data as an example, when the second digital error signal is located at either the second left or right endpoint, regardless of whether the output signal is 1000V or 4000V, the second digital error signal reaches the endpoint (e.g., 0). In this case, the second digital error signal cannot accurately reflect the difference between the output signal and the reference signal. During the initialization phase of feedback control, such as when the output signal increases from 0V to 4900V, the first digital error signal accurately reflects the difference between the output signal and the reference signal. Therefore, this application can quickly adjust the output signal from 0V to 4900V. If the second digital error signal were used, it would take a much longer to adjust to 4900V. This difference in adjustment efficiency also contributes to the ability of this application to reduce output signal fluctuations in the target circuit 700 in scenarios with sudden output signal changes.

[0073] In summary, this application, while ensuring control accuracy, can implement complex algorithms, is easy to maintain, and helps reduce power supply ripple. It is applicable to both low-voltage and high-voltage scenarios, and is particularly advantageous for high-voltage, low-ripple applications. High-voltage, low-ripple scenarios include those with voltages greater than or equal to 1000V (e.g., 5000V, 10000V, 45000V, 100000V, etc.) and ripple controlled within a certain threshold range (e.g., ±5ppm, ±10ppm, etc.).

[0074] In some embodiments, a fourth left endpoint (e.g., 400) and a fourth right endpoint (e.g., 3696) are provided between the second left endpoint and the second right endpoint. When the second digital error signal is greater than the second left endpoint and less than the fourth left endpoint (e.g., within 0~400 excluding endpoints), or greater than the fourth right endpoint and less than the second right endpoint (e.g., within 3696~4096 excluding endpoints), the composite error signal is a weighted sum of the first digital error signal and the second digital error signal. When the second digital error signal is greater than or equal to the fourth left endpoint and less than or equal to the fourth right endpoint, the composite error signal is equal to the second digital error signal.

[0075] In the above embodiments, considering the fluctuation of the output signal, when the output signal and the reference signal are just approaching each other, the second digital error signal may be within the second threshold range at one moment and at the endpoint of the second threshold range at the next moment. If the comprehensive error signal is set to be equal to the second digital error signal when the second digital error signal is within the second threshold range, it may lead to control using the second digital error signal at one moment and the first digital error signal at the next moment (i.e., switching back and forth). The values ​​of the second digital error signal and the first digital error signal are often different, which will cause disturbances. By setting the fourth threshold range with endpoints at the fourth left endpoint and the fourth right endpoint respectively within the second threshold range, the fourth threshold range is smaller than the second threshold range. Therefore, when the second digital error signal is outside the fourth threshold range but within the second digital threshold range, the switching back and forth situation is likely to occur. Setting the signal used for feedback control as a weighted sum of the first digital error signal and the second digital error signal helps to avoid the back and forth jump of the signal used for feedback control, reduce disturbances, and improve control stability. When the second digital error signal is within the fourth threshold range, it means that the output signal and the reference signal are closer. At this time, the second digital error signal is more accurate. Therefore, using the second digital error signal for feedback control can ensure control accuracy.

[0076] In other embodiments, when the second digital error signal is at the second left endpoint or the second right endpoint, the combined error signal is equal to the first digital error signal. When the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the combined error signal is equal to the second digital error signal. This control logic is simple and easy to implement.

[0077] In some embodiments, the distance from the fourth left endpoint to the second left endpoint is greater than or equal to 1% and less than or equal to 15% of the distance from the second left endpoint to the second right endpoint (e.g., 5%, 10%, or other values ​​within the range). In some embodiments, the distance from the fourth right endpoint to the second right endpoint is greater than or equal to 1% and less than or equal to 15% of the distance from the second left endpoint to the second right endpoint (e.g., 5% or 10%). This sets a reasonable range, making it less likely for the second digital error signal to switch back and forth when it is located between the fourth left endpoint and the fourth right endpoint, which helps to ensure control accuracy.

[0078] In some embodiments, the weighting coefficient of the first digital error signal is positively correlated with the distance of the first digital error signal to the midpoint between the first left endpoint and the first right endpoint (hereinafter referred to as the midpoint).

[0079] In the above embodiments, when the distance from the first digital error signal to the midpoint is large, it can be considered that the difference between the output signal and the reference signal is large. In this case, the first digital error signal is more accurate than the second digital error signal. Since the weighting coefficient of the first digital error signal is positively correlated with the distance from the first digital error signal to the midpoint, when the distance from the first digital error signal to the midpoint is large, the weight of the first digital error signal is also large. This is beneficial to making the comprehensive error signal determined based on the weighted sum of the first and second digital error signals more accurate. Furthermore, when the distance from the first digital error signal to the midpoint is small, it can be considered that the difference between the output signal and the reference signal is small. In this case, the second digital error signal is more accurate than the first digital error signal. Since the weighting coefficient of the first digital error signal is positively correlated with the distance from the first digital error signal to the midpoint, when the distance from the first digital error signal to the midpoint is small, the weight of the first digital error signal is also small. Relatively speaking, the weight of the second digital error signal is larger. This is beneficial to making the comprehensive error signal determined based on the weighted sum of the first and second digital error signals more accurate.

[0080] In some implementations, the weighting coefficients of the first digital error signal are linearly or non-linearly related to the distance from the first digital error signal to the midpoint.

[0081] Figure 5This is a schematic diagram illustrating the mapping relationship between an initial analog error signal, a second analog error signal, and a second digital error signal according to some embodiments of this disclosure.

[0082] The following is combined Figure 1 , Figure 2 , Figure 5 and one Some embodiments describe a second digital error signal determination circuit 200.

[0083] In some embodiments, the second digital error signal determination circuit 200 includes a second operational amplifier circuit 220 and a second analog-to-digital sampling circuit 230.

[0084] The second operational amplifier circuit 220 is used to map the initial analog error signal to a second analog error signal. The threshold range of the second analog error signal has a fifth left endpoint and a fifth right endpoint. The initial analog error signal greater than the third left endpoint and less than the third right endpoint is uniformly mapped to a second analog error signal greater than the fifth left endpoint and less than the fifth right endpoint; the initial analog error signal less than or equal to the third left endpoint is mapped to a second analog error signal located at one of the fifth left endpoint and the fifth right endpoint; the initial analog error signal greater than or equal to the third right endpoint is mapped to a second analog error signal located at the other endpoint of the fifth left endpoint and the fifth right endpoint.

[0085] The second analog-to-digital sampling circuit 230 is used to sample the second analog error signal to obtain a second digital error signal. The second analog-to-digital sampling circuit 230 is used to sample the second analog error signal to obtain a second digital error signal, wherein the second analog error signal located at the fifth left endpoint corresponds to the second digital error signal located at the second left endpoint, the second analog error signal located at the fifth right endpoint corresponds to the second digital error signal located at the second right endpoint, and the second analog error signal greater than the fifth left endpoint and less than the fifth right endpoint corresponds to the second digital error signal greater than the second left endpoint and less than the second right endpoint.

[0086] The above embodiment constructs a second digital error signal determination circuit 200 through a second operational amplifier circuit 220 and a second analog-to-digital sampling circuit 230. The structure is simple and easy to implement. The second operational amplifier circuit 220 maps the initial analog error signal to a second analog error signal (initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second analog error signals greater than the fifth left endpoint and less than the fifth right endpoint; initial analog error signals less than or equal to the third left endpoint are mapped to second analog error signals located at one of the fifth left and fifth right endpoints; initial analog error signals greater than or equal to the third right endpoint are mapped to second analog error signals located at the other of the fifth left and fifth right endpoints). The initial analog error signal is divided into three parts and mapped to obtain the second analog error signal. The two sides (corresponding to the case where the initial analog error signal is larger) are mapped to the endpoints of the second analog error signal, and the middle part (corresponding to the case where the initial analog error signal is smaller) is mapped to the part of the second analog error signal excluding the endpoints. In this way, when the second analog-to-digital sampling circuit 230 samples the second analog error signal to obtain the second digital error signal, the two sides of the initial analog error signal also correspond to the endpoints of the second digital error signal, and the middle part corresponds to the part of the second digital error signal excluding the endpoints, so that the range of the second digital error signal is mainly used to represent the case where the error is smaller.

[0087] In addition, the threshold range of the second analog error signal can be less than or equal to the sampling range of the second analog-to-digital sampling circuit 230, which helps to ensure the normal operation of the second analog-to-digital sampling circuit 230 and avoids the situation where the sampling voltage exceeds the sampling range of the second analog-to-digital sampling circuit 230, which may affect the service life or sampling accuracy of the second analog-to-digital sampling circuit 230.

[0088] In some embodiments, the second digital error signal determination circuit 200 further includes a second subtractor 210. The second subtractor 210 is connected between the target circuit 700 and the second operational amplifier circuit 220, and is used to determine an initial analog error signal based on the analog signal of the output signal and the analog signal of the reference signal, and send it to the second operational amplifier circuit 220.

[0089] The above embodiment uses a subtractor to determine the initial analog error signal, which is simple in structure and easy to implement.

[0090] In some embodiments, a fourth operational amplifier circuit 800 may be included between the target circuit 700 and the second subtractor 210. The fourth operational amplifier circuit 800 can be used to scale the output signal, for example, scaling the output signal from 5000V to 10V (this is just an example; the degree of scaling can be selected according to actual conditions). Considering that the subtractor's lifespan may be affected if it operates under high voltage, scaling the output voltage of the target circuit 700 by setting the fourth operational amplifier circuit 800 helps protect the second subtractor 210. It should be understood that this scaling is scaling an analog signal to an analog signal, which theoretically can be considered error-free.

[0091] The first digital error signal determination circuit 100 is described below with reference to some embodiments.

[0092] In some embodiments, such as Figure 1 As shown, the initial error signal is an initial analog error signal. In this case, the first digital error signal determination circuit 100 includes a first operational amplifier circuit 120 and a first analog-to-digital sampling circuit 130.

[0093] The first operational amplifier circuit 120 is used to uniformly map the initial analog error signal to the first analog error signal.

[0094] The first analog-to-digital sampling circuit 130 is used to sample the first analog error signal to obtain the first digital error signal.

[0095] The above embodiment constructs a first digital error signal determination circuit 100 through a first operational amplifier circuit 120 and a first analog-to-digital sampling circuit 130. The structure is simple and easy to implement.

[0096] In some embodiments, the threshold range of the first analog error signal may be less than or equal to the sampling range of the first analog-to-digital sampling circuit 130. Mapping the first analog error signal to a first analog error signal with a threshold range less than or equal to the sampling range of the first analog-to-digital sampling circuit 130 helps ensure the normal operation of the first analog-to-digital sampling circuit 130 and avoids situations where the lifespan or sampling accuracy of the first analog-to-digital sampling circuit 130 is affected due to the sampling voltage exceeding the sampling range of the first analog-to-digital sampling circuit 130.

[0097] In some embodiments, such as Figure 1 As shown, the first digital error signal determination circuit 100 also includes a first subtractor 110. The first subtractor 110 is connected between the target circuit 700 and the first operational amplifier circuit 120, and is used to determine an initial analog error signal based on the analog signal of the output signal and the analog signal of the reference signal, and send it to the first operational amplifier circuit 120.

[0098] The above embodiment uses a subtractor to determine the initial analog error signal, which is simple in structure and easy to implement.

[0099] As one implementation, a fourth operational amplifier circuit 800 may be included between the target circuit 700 and the first subtractor 110. The fourth operational amplifier circuit 800 can be used to scale the output signal, for example, scaling the output signal from 5000V to 10V. Considering that the subtractor's lifespan may be affected if it operates under high voltage, scaling the output voltage of the target circuit 700 by setting the fourth operational amplifier circuit 800 helps protect the second subtractor 210.

[0100] In other embodiments, such as Figure 2 As shown, the initial error signal is the initial digital error signal. In this case, the first digital error signal determination circuit 100 includes a third analog-to-digital sampling circuit 330 and a third subtractor 310.

[0101] The third analog-to-digital sampling circuit 330 is used to sample the output signal to obtain the digital signal of the output signal;

[0102] The third subtractor 310 is connected between the third analog-to-digital sampling circuit 330 and the comprehensive error determination circuit 400. It is used to determine the initial digital error signal based on the digital signal of the reference signal and the digital signal of the output signal, and then send it to the comprehensive error determination circuit 400.

[0103] In the above embodiments, the first digital error signal determination circuit 100 is constructed using the third analog-to-digital sampling circuit 330 and the third subtractor 310. The structure is simple and easy to implement.

[0104] As one implementation, a third operational amplifier circuit 320 may also be included between the third analog-to-digital sampling circuit 330 and the target circuit 700. Considering that the third analog-to-digital sampling circuit 330 may have requirements for operating voltage, and operating under high voltage may affect its service life or even cause failure, setting the third operational amplifier circuit 320 to scale the output signal of the target circuit 700 is beneficial to protecting the third analog-to-digital sampling circuit 330.

[0105] In some embodiments, such as Figure 1 and Figure 2 As shown, the control circuit also includes a digital-to-analog converter (DAC) 600. The DAC 600 is connected between the digital controller 500 and the target circuit 700, and is used to convert the digital control signals issued by the digital controller 500 into analog control signals, which are used to control the target circuit 700.

[0106] As one implementation, the digital controller 500 can be integrated within the chip, while the analog-to-digital converter (ADC) is located externally. It should be understood that if the target circuit 700 is directly controlled via the chip, the on-chip digital controller 500 outputs control signals to the on-chip conditioning circuit. The conditioning circuit generates a pulse-width modulation (PWM) waveform. The accuracy of the conditioning circuit is limited by the accuracy of the carrier wave used in the conditioning process, and the carrier wave's accuracy is constrained by the chip's clock frequency. By placing the ADC externally, the generated analog control signal is not constrained by the chip's clock frequency, but rather by the ADC's accuracy. Compared to using a chip, the ADC typically suffers less loss, resulting in higher control accuracy.

[0107] The following descriptions of Examples 2 to 5 can be referenced from the description of Example 1 above, and the same or similar parts will not be repeated.

[0108] Example 2

[0109] According to a second aspect of this application, a chip is provided, including the control circuitry described in any of the above embodiments. The chip is, for example, a Field Programmable Gate Array (FPGA) chip or an Application-Specific Integrated Circuit (ASIC) chip.

[0110] Example 3

[0111] According to a third aspect of this application, a power supply is provided, the output voltage of which is controlled by the control circuit described in any embodiment.

[0112] In some embodiments, the power supply is, for example, a chuck power supply or a high-voltage voltage source.

[0113] Example 4

[0114] According to a fourth aspect of this application, an electronic device is provided, comprising a power supply and a load as described in any of the embodiments, wherein the power supply is used to supply power to the load. The electronic device may be a semiconductor device, such as an etching device or a deposition device.

[0115] Example 5

[0116] According to the fifth aspect of this application, such as Figure 6 As shown, a control method is provided, including steps S100, S200, S300 and S400.

[0117] In step S100, an initial error signal is determined and a first digital error signal is obtained based on the initial error signal. Here, the threshold range of the first digital error signal has a first left endpoint and a first right endpoint. Specifically, when the initial error signal is the initial analog error signal of both the analog signal of the reference signal and the analog signal of the output signal of the target circuit 700, the first digital error signal is obtained by uniformly mapping the initial analog error signal with a threshold range equal to the initial threshold range to a threshold range from the first left endpoint to the first right endpoint; or, when the initial error signal is the initial digital error signal of both the digital signal of the reference signal and the digital signal of the output signal, the first digital error signal is equal to the initial digital error signal.

[0118] In step S200, an initial analog error signal is determined, and a second digital error signal is obtained by mapping based on the initial analog error signal. Here, the threshold range of the second digital error signal has a second left endpoint and a second right endpoint. The initial threshold range contains a sub-threshold range, which has a third left endpoint and a third right endpoint. Initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second digital error signals greater than the second left endpoint and less than the second right endpoint; initial analog error signals less than or equal to the third left endpoint are mapped to second digital error signals located at one of the second left and second right endpoints; and initial analog error signals greater than or equal to the third right endpoint are mapped to second digital error signals located at the other endpoint of the second left and second right endpoints.

[0119] It should be understood that the execution order of steps S100 and S200 is not limited, and can be as follows: Figure 6 As shown, step S100 can be executed first, followed by step S200; alternatively, step S200 can be executed first, followed by step S100; or steps S100 and S200 can be executed in parallel. Executing steps S100 and S200 in parallel improves computational efficiency, thereby enhancing control accuracy.

[0120] In step S300, a comprehensive error signal is determined based on the first digital error signal and the second digital error signal. Specifically, if the value of the second digital error signal is either the second left endpoint or the second right endpoint, the comprehensive error signal is equal to the first digital error signal; if the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal.

[0121] In step S400, feedback control is performed on the target circuit based on the comprehensive error signal to control the output voltage of the target circuit.

[0122] The above-described preferred embodiments have further detailed the purpose, technical solutions, and advantages of this application. It should be understood that the above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A control circuit, characterized by include: A first digital error signal determination circuit (100) is used to determine an initial error signal and obtain a first digital error signal based on the initial error signal. The threshold range of the first digital error signal has a first left endpoint and a first right endpoint. Wherein, when the initial error signal is the initial analog error signal of both the analog signal of the reference signal and the analog signal of the output signal of the target circuit (700), the first digital error signal is obtained by uniformly mapping the initial analog error signal with a threshold range equal to the initial threshold range to a threshold range from the first left endpoint to the first right endpoint; or, when the initial error signal is the initial digital error signal of both the digital signal of the reference signal and the digital signal of the output signal, the first digital error signal is equal to the initial digital error signal. A second digital error signal determination circuit (200) is configured to determine the initial analog error signal and map a second digital error signal based on the initial analog error signal. The threshold range of the second digital error signal has a second left endpoint and a second right endpoint. The initial threshold range contains a sub-threshold range, which has a third left endpoint and a third right endpoint. Initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second digital error signals greater than the second left endpoint and less than the second right endpoint. Initial analog error signals less than or equal to the third left endpoint are mapped to second digital error signals located at one of the second left endpoint and the second right endpoint. Initial analog error signals greater than or equal to the third right endpoint are mapped to second digital error signals located at the other endpoint of the second left endpoint and the second right endpoint. A comprehensive error determination circuit (400) is used to determine a comprehensive error signal based on the first digital error signal and the second digital error signal; wherein, when the value of the second digital error signal is the second left endpoint or the second right endpoint, the comprehensive error signal is equal to the first digital error signal; when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal. A digital controller (500) is connected to the target circuit (700) and is used to perform feedback control on the target circuit (700) based on the comprehensive error signal, so as to control the output signal of the target circuit (700).

2. The control circuit of claim 1, wherein, Between the second left endpoint and the second right endpoint, there are a fourth left endpoint and a fourth right endpoint; When the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal, including: When the second digital error signal is greater than the second left endpoint and less than the fourth left endpoint, or greater than the fourth right endpoint and less than the second right endpoint, the combined error signal is a weighted sum of the first digital error signal and the second digital error signal; and / or When the second digital error signal is greater than or equal to the fourth left endpoint and less than or equal to the fourth right endpoint, the composite error signal is equal to the second digital error signal.

3. The control circuit according to claim 2, characterized in that, The distance from the fourth left endpoint to the second left endpoint is greater than or equal to 1% and less than or equal to 15% of the distance from the second left endpoint to the second right endpoint; and / or The distance from the fourth right endpoint to the second right endpoint is greater than or equal to 1% and less than or equal to 15% of the distance from the second left endpoint to the second right endpoint.

4. The control circuit of claim 2, wherein, The comprehensive error signal is a weighted sum of the first digital error signal and the second digital error signal, including: The weighting coefficient of the first digital error signal is positively correlated with the distance from the first digital error signal to the midpoint between the first left endpoint and the first right endpoint.

5. The control circuit according to any one of claims 1 to 4, characterized in that, The second digital error signal determination circuit (200) includes: A second operational amplifier circuit (220) is used to map the initial analog error signal to a second analog error signal, wherein the threshold range of the second analog error signal is less than or equal to the sampling range of the second analog-to-digital sampling circuit (230), and has a fifth left endpoint and a fifth right endpoint, wherein an initial analog error signal greater than the third left endpoint and less than the third right endpoint is uniformly mapped to a second analog error signal greater than the fifth left endpoint and less than the fifth right endpoint; an initial analog error signal less than or equal to the third left endpoint is mapped to a second analog error signal located at one of the fifth left endpoint and the fifth right endpoint; an initial analog error signal greater than or equal to the third right endpoint is mapped to a second analog error signal located at the other endpoint of the fifth left endpoint and the fifth right endpoint; and The second analog-to-digital sampling circuit (230) is used to sample the second analog error signal to obtain the second digital error signal, wherein the second analog error signal located at the fifth left endpoint corresponds to the second digital error signal located at the second left endpoint, the second analog error signal located at the fifth right endpoint corresponds to the second digital error signal located at the second right endpoint, and the second analog error signal greater than the third left endpoint and less than the third right endpoint corresponds to the second digital error signal greater than the second left endpoint and less than the second right endpoint.

6. The control circuit according to claim 5, characterized in that, The second digital error signal determination circuit (200) further includes: The second subtractor (210), connected between the target circuit (700) and the second operational amplifier circuit (220), is used to determine the initial analog error signal based on the analog signal of the output signal and the analog signal of the reference signal, and send it to the second operational amplifier circuit (220).

7. The control circuit according to any one of claims 1-4, characterized in that, The initial error signal is the initial analog error signal; the first digital error signal determination circuit (100) includes: The first operational amplifier circuit (120) is used to uniformly map the initial analog error signal into a first analog error signal; The first analog-to-digital sampling circuit (130) is used to sample the first analog error signal to obtain the first digital error signal.

8. The control circuit according to claim 7, characterized in that, The first digital error signal determination circuit (100) further includes: The first subtractor (110) is connected between the target circuit (700) and the first operational amplifier circuit (120) to determine the initial analog error signal based on the analog signal of the output signal and the analog signal of the reference signal, and send it to the first operational amplifier circuit (120).

9. The control circuit according to any one of claims 1-4, characterized in that, The initial error signal is the initial digital error signal, and the first digital error signal determining circuit (100) includes: The third analog-to-digital sampling circuit (330) is used to sample the output signal to obtain the digital signal of the output signal; The third subtractor (310) is connected between the third analog-to-digital sampling circuit (330) and the comprehensive error determination circuit (400) to determine the initial digital error signal based on the digital signal of the reference signal and the digital signal of the output signal, and send it to the comprehensive error determination circuit (400).

10. The control circuit according to any one of claims 1-4, characterized in that, The control circuit also includes: A digital-to-analog converter (600) is connected between the digital controller (500) and the target circuit (700) to convert digital control signals issued by the digital controller (500) into analog control signals, which are used to control the target circuit (700).

11. A chip, characterized in that, include: The control circuit as described in any one of claims 1-10.

12. A power supply, characterized in that, The output voltage of the power supply is controlled by the control circuit as described in any one of claims 1-10.

13. An electronic device, characterized in that, include: The power supply as described in claim 12.

14. A control method, characterized in that, include: An initial error signal is determined and a first digital error signal is obtained based on the initial error signal. The threshold range of the first digital error signal has a first left endpoint and a first right endpoint. Wherein, when the initial error signal is the initial analog error signal of both the analog signal of the reference signal and the analog signal of the output signal of the target circuit (700), the first digital error signal is obtained by uniformly mapping the initial analog error signal with a threshold range equal to the initial threshold range to a threshold range from the first left endpoint to the first right endpoint; or, when the initial error signal is the initial digital error signal of both the digital signal of the reference signal and the digital signal of the output signal, the first digital error signal is equal to the initial digital error signal. An initial analog error signal is determined, and a second digital error signal is obtained by mapping based on the initial analog error signal. The threshold range of the second digital error signal has a second left endpoint and a second right endpoint. The initial threshold range contains a sub-threshold range, which has a third left endpoint and a third right endpoint. Initial analog error signals greater than the third left endpoint and less than the third right endpoint are uniformly mapped to second digital error signals greater than the second left endpoint and less than the second right endpoint. Initial analog error signals less than or equal to the third left endpoint are mapped to second digital error signals located at one of the second left endpoint and the second right endpoint. Initial analog error signals greater than or equal to the third right endpoint are mapped to second digital error signals located at the other endpoint of the second left endpoint and the second right endpoint. A comprehensive error signal is determined based on the first digital error signal and the second digital error signal; wherein, when the value of the second digital error signal is the second left endpoint or the second right endpoint, the comprehensive error signal is equal to the first digital error signal; when the value of the second digital error signal is greater than the second left endpoint and less than the second right endpoint, the comprehensive error signal is determined based on the second digital error signal; and Feedback control is performed on the target circuit (700) based on the comprehensive error signal to control the output signal of the target circuit (700).

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