Power management method
By employing a dynamic power management method for multi-chip systems, the problems of long control cycles and high costs in existing PoE systems are solved. This method enables the expansion of the number of communication ports, shortens the control cycle, and reduces costs, thus meeting the needs of system expansion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2026-03-10
AI Technical Summary
In existing PoE systems with multiple communication ports, the system control cycle is long and the cost is high, including MCUs and multiple PSE chips. Systems with only a single PSE chip and memory have a limited number of connection ports, cannot be expanded, and cannot simultaneously meet the goals of security and efficiency.
Employing a multi-chip system, each chip has a priority. The processing unit executes initialization and power supply procedures to dynamically manage power allocation, including reading mode values, calculating remaining usable power values, detecting and classifying communication port requirements, and supplying or de-supplying power based on priority and remaining power, thus reducing reliance on the MCU.
It enables the expansion of the number of communication ports, significantly shortens the control cycle, reduces costs, reduces communication consumption, and makes power management more efficient, thus meeting the needs of system expansion.
Smart Images
Figure CN121635648A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a power management technology, and more particularly to a power management method and a multi-chip system. Background Technology
[0002] Power over Ethernet (PoE) technology can transmit data signals and provide DC power to IP-based terminals. This technology offers numerous advantages, including high cabling compatibility, low power supply cost, flexible deployment, high support for powered devices (PDs), and centralized and flexible power management. For PoE systems with multiple communication ports, security, efficiency, accuracy, and configurability are key objectives of power management strategies. A deep understanding of the relationships and differences between these objectives, and maximizing the consideration of all goals, is the starting point for designing a power management strategy.
[0003] Security involves controlling the power supply capacity, quantity, and rhythm of each communication port in the system, as well as timely and effective handling of abnormal situations. Efficiency aims to maximize the utilization of system resources and provide rapid and efficient power to the PD. Accuracy ensures that communication ports requiring removal and power supply can be identified at the earliest possible time during each stage of system power management. Configurability provides multiple optional combinations in the power management strategy to meet diverse user needs. Security and efficiency are two opposing goals; security emphasizes conservative use of system power, while efficiency aims to maximize system power utilization.
[0004] There are two common types of multi-port PoE systems. One type includes a microcontroller unit (MCU) and multiple power sourcing equipment (PSE) chips. The system's host and MCU communicate via a universal asynchronous receiver / transmitter (UART) or an integrated bus circuit (I2C). 2 C) Interface messages are exchanged to capture various configuration and status information, including power management programs, while the MCU accesses each PSE chip via the I2C interface. Another approach involves only a single PSE chip and memory (e.g., electrically erasable programmable read-only memory, EEPROM), with the power management program executed independently by a single PSE chip.
[0005] However, in systems that include an MCU and multiple PSE chips, the MCU needs to periodically poll the PSE chips. The MCU needs to collect all information before making a decision, resulting in a control cycle that often takes tens or hundreds of milliseconds (ms), which is a very long time. Furthermore, the number of connection ports is limited by the MCU software and cannot be expanded. In addition, the inclusion of an MCU increases the system's cost. As for systems that only include a single PSE chip and memory, the number of connection ports is limited to the number of connection ports of that single PSE chip and cannot be expanded. Summary of the Invention
[0006] A power management method is applicable to a multi-chip system. The multi-chip system includes multiple chips. Each chip has a priority. Each chip includes a processing unit, a storage unit, and multiple communication ports. The storage unit stores a mode value and a used power value. The mode value is either a static mode value or a dynamic mode value. The power management method includes: the processing unit executing an initialization procedure to obtain a remaining usable power value; the initialization procedure including: the processing unit reading the mode value to determine whether the mode value is a dynamic mode value or a static mode value; the processing unit reading the used power value from the storage unit of the chip with the previous priority; and the processing unit subtracting the used power value from the storage unit of the chip with the previous priority from the total power value to obtain a remaining usable power value; the processing unit executing a power supply procedure for each communication port in a time-sharing manner; the power supply procedure including: the processing unit detecting and classifying the communication ports to obtain the required power value of the communication ports; the processing unit comparing the remaining usable power value with the required power value; and when the remaining usable power value is greater than or equal to the required power value, the processing unit supplies power to the communication port and allocates the remaining usable power. The processing unit subtracts the required power value from the power value to obtain the updated remaining usable power value; the processing unit calculates the power consumed by each powered-on communication port. When the mode value is the static mode value, the power consumed by each communication port is the required power value of each communication port; the processing unit sums the power consumed by all powered-on communication ports to obtain the local used power value; the processing unit subtracts the used power value of the storage unit of the chip with the previous priority and the local used power value from the total power value to obtain the second remaining usable power value; and when the second remaining usable power value is greater than or equal to 0, the processing unit adds the used power value of the storage unit of the chip with the previous priority to the local used power value to obtain the used power value and stores the used power value in the storage unit.
[0007] In some embodiments, when the processing unit calculates the power consumed by each powered-on communication port, when the mode value is the dynamic mode value, the power consumed by each communication port is the real-time voltage value of each communication port multiplied by the real-time current value of each communication port.
[0008] In some embodiments, the power management method further includes: when the second remaining usable power value is less than 0, the processing unit stops supplying power to one of the plurality of powered communication ports, and recalculates the local usage power value and the second remaining usable power value.
[0009] In some embodiments, the power supply procedure further includes: after the processing unit supplies power to the communication port, the processing unit waits for a stabilization period to confirm that the power-on state of the communication port is stable.
[0010] In some embodiments, the initialization procedure further includes: the processing unit checking whether the chip of the previous priority is faulty according to the priority; and when the chip of the previous priority is not faulty, the processing unit reading the power used value of the storage unit of the chip of the previous priority.
[0011] In some embodiments, the priority of each chip is determined by its address.
[0012] In some embodiments, each communication port has a second priority. When the second remaining usable power value is less than 0, the processing unit stops supplying power to one of the plurality of powered communication ports according to the second priority of each communication port.
[0013] In some embodiments, the processing unit performs a power supply procedure for each communication port in a time-division manner according to the second priority of each communication port.
[0014] In some embodiments, the initialization procedure further includes: the processing unit storing the mode value to the storage unit based on firmware setting information.
[0015] In some embodiments, the multi-chip system further includes a processor. The initialization procedure further includes: the processor storing a mode value to a storage unit based on firmware setting information.
[0016] In some embodiments, a multi-chip system includes multiple chips. Each chip has a priority. Each chip includes a storage unit, multiple communication ports, and a processing unit. The storage unit stores a mode value and a power consumption value. The mode value is either a static mode value or a dynamic mode value. The processing unit executes a power management method. The power management method includes: executing an initialization procedure to obtain a remaining usable power value. The initialization procedure includes: reading the mode value to determine whether the mode value is a dynamic mode value or a static mode value; reading the power consumption value stored in the storage unit of the chip with the previous priority; subtracting the power consumption value stored in the storage unit of the chip with the previous priority from the total power value to obtain a remaining usable power value; and performing a power supply procedure for each communication port in a time-sharing manner. The power supply procedure includes: detecting and classifying communication ports to obtain the required power value of the communication ports; comparing the remaining usable power value with the required power value; and when the remaining usable power value is greater than or equal to the required power value, supplying power to the communication ports and subtracting the required power value from the remaining usable power value to obtain an updated remaining usable power value; calculating the power consumed by each powered-on communication port, where the power consumed by each communication port is the required power value when the mode value is a static mode value; summing the power consumed by all powered-on communication ports to obtain a local power consumption value; subtracting the used power value of the storage unit of the previous priority chip and the local power consumption value from the total power value to obtain a second remaining usable power value; and when the second remaining usable power value is greater than or equal to 0, adding the used power value of the storage unit of the previous priority chip to the local power consumption value to obtain a used power value and storing the used power value in the storage unit.
[0017] The detailed features and advantages of this disclosure are described below in the embodiments, the content of which is sufficient to enable those skilled in the art to understand the technical content of this disclosure and to implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the claims, and the drawings, those skilled in the art can easily understand the related purposes and advantages of this disclosure. Attached Figure Description
[0018] Figure 1 This is a schematic block diagram of an embodiment of a multi-chip system.
[0019] Figure 2 This is a flowchart of an embodiment of a power management method.
[0020] Figure 3 A flowchart of an embodiment of the initialization procedure.
[0021] Figure 4 A flowchart of an embodiment of the power supply procedure.
[0022] Figure 5 A flowchart of another embodiment of the initialization procedure.
[0023] Figure 6 This is a flowchart of yet another embodiment of the initialization procedure.
[0024] Figure 7 This is a schematic block diagram of another embodiment of a multi-chip system.
[0025] Figure 8 A flowchart for yet another embodiment of the initialization procedure. Detailed Implementation
[0026] Figure 1 This is a schematic block diagram illustrating an embodiment of a multi-chip system. Please refer to [link / reference]. Figure 1 The multi-chip system 1 includes multiple chips 10. Each chip 10 includes a storage unit 102, multiple communication ports 103, and a processing unit 101. The storage unit 102 stores mode values and power consumption values. The mode values are either static mode values or dynamic mode values. The processing unit 101 executes power management methods. In some embodiments, the chip 10 may be, but is not limited to, a PSE chip.
[0027] In some embodiments, the chips 10 are interconnected via a bus 11. In some embodiments, the bus 11 may be, but is not limited to, an inter-integrated circuit (I-ICB). 2 C).
[0028] In some embodiments, each chip 10 has a priority. In some embodiments, the priority of each chip 10 is determined by its address. In some embodiments, the priority of each chip 10 decreases from the chip 10 with the lower address to the chip 10 with the higher address. That is, the chip 10 with the lower address has a higher priority. Here, we use... Figure 1 Taking a multi-chip system as an example, for ease of explanation, here... Figure 1 The multiple chips 10 are referred to as chip 110, chip 120, and chip 130. Assume the address of chip 110 is A, the address of chip 120 is A+1, the address of chip 130 is A+2, and the address of chip 140 is A+n. Chip 110 has the highest priority due to its lowest address. Chip 120 has the second highest priority due to its second lowest address. That is, chip 120 is the chip 10 with the next highest priority after chip 110; in other words, chip 110 is the chip 10 with the next highest priority after chip 120. Chip 130 has the third highest priority due to its third lowest address. Chip 140 has the lowest priority due to its highest address.
[0029] In some embodiments, the multi-chip system 1 supplies power to each chip 10 according to priority; the higher the priority of a chip 10, the earlier it is powered on. Figure 1 Taking the multi-chip system 1 as an example, chip 110 will be powered on first, followed by chip 120, then chip 130, and chip 140 will only be powered on after all the chips 10 ahead of it have been powered on.
[0030] In some embodiments, the used power value stored in storage unit 102 is the sum of the used power value of the chip 10 with the highest priority preceding the chip 10 where storage unit 102 is located, and the local used power value of the chip 10 where storage unit 102 is located. That is, the used power value stored in storage unit 102 is the sum of the local used power values of all chips 10 with priorities preceding the chip 10 where storage unit 102 is located, plus the local used power value of the chip 10 where storage unit 102 is located. Figure 1 Taking a multi-chip system 1 as an example, the used power value stored in storage unit 102 of chip 110 is only the local used power value of chip 110 because chip 110 is the highest priority chip 10. The used power value stored in storage unit 102 of chip 120 is the used power value of chip 110 plus the local used power value of chip 120, that is, the used power value stored in storage unit 102 of chip 120 is the local used power value of chip 110 plus the local used power value of chip 120. The used power value stored in storage unit 102 of chip 130 is the used power value stored in storage unit 102 of chip 120 plus the local used power value of chip 130, that is, the used power value stored in storage unit 102 of chip 130 is the local used power value of chip 110 plus the local used power value of chip 120 plus the local used power value of chip 130. The power used value stored in the storage unit 102 of chip 140 is the sum of the local power used values of all chips 10 with priorities preceding chip 140, plus the local power used value of chip 140.
[0031] In some embodiments, all chips 10 included in the multi-chip system 1 share a total power. In some embodiments, the total power shared by all chips 10 included in the multi-chip system 1 is the total power supply of the multi-chip system 1, but this disclosure is not limited thereto. In some embodiments, the magnitude of the total power that can be shared by all chips 10 included in the multi-chip system 1 is set by the user rather than the total power supply of the multi-chip system 1. In some embodiments, the total power value shared by all chips 10 included in the multi-chip system 1 is stored in the storage unit 102 of each chip 10, but this disclosure is not limited thereto.
[0032] Figure 2 This is a flowchart illustrating an embodiment of the power management method. Please refer to [link / reference]. Figure 2First, the processing unit 101 executes an initialization procedure to obtain the remaining usable power value (step S01). Figure 3 A flowchart illustrating an embodiment of the initialization procedure. See also... Figure 3 First, processing unit 101 reads the mode value to determine whether the mode value is a dynamic mode value or a static mode value (step S011). Next, processing unit 101 reads the used power value of the storage unit 102 of the chip 10 with the previous priority (step S012). Finally, processing unit 101 subtracts the used power value of the storage unit 102 of the chip 10 with the previous priority from the total power value to obtain the remaining usable power value (step S013). In step S013, since all chips 10 share the total power, and the multi-chip system 1 supplies power to each chip 10 according to priority, and the used power value stored in storage unit 102 is the sum of the local used power values of all chips 10 with priorities preceding the chip 10 where storage unit 102 is located, plus the local used power value of the chip 10 where storage unit 102 is located. Therefore, processing unit 101 only needs to subtract the used power value of the storage unit 102 of the chip 10 with the previous priority from the total power value to obtain the remaining usable power value representing how much power the chip 10 where processing unit 101 is located still has.
[0033] Next, the processing unit 101 performs a power supply procedure for each communication port 103 in a time-sharing manner, that is, the processing unit 101 performs a power supply procedure for only one communication port 103 in one cycle (step S02). Figure 4 A flowchart illustrating an embodiment of the power supply procedure. Please refer to [link / reference]. Figure 4 First, the processing unit 101 detects and classifies the communication port 103 to obtain the power demand value of the communication port 103 (step S021). Next, the processing unit 101 compares the remaining usable power value with the demand power value (step S022). When the remaining usable power value is greater than or equal to the demand power value, the processing unit 101 supplies power to the communication port 103 and subtracts the demand power value from the remaining usable power value to obtain an updated remaining usable power value (step S023). When the remaining usable power value is less than the demand power value, the processing unit 101 does not supply power to the communication port 103 (step S024).
[0034] In some embodiments, after the processing unit 101 supplies power to the communication port 103, the processing unit 101 also waits for a settling time to confirm that the power-on state of the communication port 103 is stable (step S025). In some embodiments, the settling time may be, but is not limited to, 250 milliseconds (ms).
[0035] In some embodiments, each communication port 103 has a second priority. In some embodiments, the processing unit 101 performs a power supply procedure on each communication port 103 in a time-division manner according to the second priority of each communication port 103. The higher the second priority of a communication port 103, the earlier the processing unit 101 performs the power supply procedure on it. In some embodiments, each communication port 103 includes a number, and the second priority of each communication port 103 may be determined by, but is not limited to, the number of each communication port 103. In some embodiments, the smaller the number, the higher the second priority, but this disclosure is not limited thereto.
[0036] In some embodiments, in step S021, the processing unit 101 detects and classifies the communication port 103 according to the IEEE 802.3at and IEEE 802.3bt standards to obtain the required power value of the communication port 103.
[0037] Then, the processing unit 101 calculates the power consumed by each powered-on communication port 103 (step S03). When the mode value is static mode, the power consumed by each communication port 103 is the power requirement of each communication port 103 (step S04). When the mode value is dynamic mode, the power consumed by each communication port 103 is the real-time voltage value of each communication port 103 multiplied by the real-time current value of each communication port 103 (step S08).
[0038] In some embodiments, when the processing unit 101 calculates the power consumed by each powered-on communication port 103 (step S03), when the mode value is a static mode value or the power-on time of each communication port 103 is less than the settling time, the power consumed by each communication port 103 is the required power value of each communication port 103 (step S04). When the mode value is a dynamic mode value and the power-on time of each communication port 103 is greater than or equal to the settling time, the power consumed by each communication port 103 is the real-time voltage value of each communication port 103 multiplied by the real-time current value of each communication port 103 (step S08).
[0039] Then, the processing unit 101 sums the power consumed by all powered-on communication ports 103 to obtain a local power consumption value (step S05). Next, the processing unit 101 subtracts the used power value of the storage unit 102 of the previous priority chip 10 and the local power consumption value from the total power value to obtain a second remaining usable power value (step S06). When the second remaining usable power value is greater than or equal to 0, the processing unit 101 adds the used power value of the storage unit 102 of the previous priority chip 10 to the local power consumption value to obtain a used power value and stores the used power value in the storage unit 102 (step S07). When the second remaining usable power value is less than 0, the processing unit 101 stops supplying power to one of the multiple powered-on communication ports 103, recalculates the local power consumption value and the second remaining usable power value (step S09), and then again determines whether the second remaining usable power value is greater than or equal to 0 or less than 0.
[0040] In some embodiments, in step S09, when the second remaining usable power value is less than 0, the processing unit 101 stops supplying power to one of the multiple powered communication ports 103 according to the second priority of each communication port 103. In some embodiments, the processing unit 101 will preferentially stop supplying power to the communication port 103 with the lowest second priority. That is, in some embodiments, the processing unit 101 will preferentially stop supplying power to the communication port 103 with the highest number.
[0041] It should be specifically noted that when the mode value is static, the power consumed by each communication port 103 is the power demand of each communication port 103. The power demand of each communication port 103 is checked in the power supply procedure (step S02). The processing unit 101 will only supply power to the communication port 103 when the remaining usable power is greater than or equal to the power demand. Therefore, when the mode value is static, the sum of the used power value in the storage unit 102 of the previous priority chip 10 and the local used power value (i.e., the sum of the power consumed by all powered-on communication ports 103) will not exceed the total power value. In other words, when the mode value is static, the second remaining usable power value will not be less than 0. In other words, the second remaining usable power value being less than 0 can only occur when the mode value is dynamic.
[0042] In step S07, the used power value stored by the processing unit 101 in the storage unit 102 is the used power value that the processing unit 101 of the next priority chip 10 reads in step S012.
[0043] Since the multi-chip system 1 does not include an MCU, the number of communication ports 103 of each chip 10 is not limited by the MCU software and can be expanded as needed. The number of communication ports 103 of the multi-chip system 1 is only limited by the address limit of the bus 11. Furthermore, since the multi-chip system 1 does not include an MCU, its cost is significantly reduced. Moreover, in the multi-chip system 1, each chip 10 determines whether its communication port 103 is powered on or off, rather than relying on MCU instructions, thus significantly shortening the control cycle. In some embodiments, the control cycle of the multi-chip system 1 can be, but is not limited to, 1 ms. In addition, since each chip 10 only needs to obtain its power data from the chip 10 with the next higher priority, the communication consumption of the multi-chip system 1 is also significantly reduced.
[0044] Figure 5 A flowchart of another embodiment of the initialization procedure. See also... Figure 5 In some embodiments, after step S011, the processing unit 101 further checks whether the chip 10 of the previous priority is faulty (step S014). If the chip 10 of the previous priority is not faulty, the processing unit 101 reads the used power value of the storage unit 102 of the chip 10 of the previous priority (step S012). If the chip 10 of the previous priority is faulty, the processing unit 101 checks whether the chip 10 of the next higher priority is faulty until the checked chip 10 is not faulty before continuing to execute step S012.
[0045] Figure 6 This is a flowchart of yet another embodiment of the initialization procedure. Please refer to [link / reference]. Figure 6 In some embodiments, prior to step S011, the processing unit 101 further stores the mode value in the storage unit 102 according to the firmware setting information (step S015). In some embodiments, the firmware setting information is stored in the storage unit 102 of each chip 10, but this disclosure is not limited thereto.
[0046] Figure 7 This is a schematic block diagram of another embodiment of a multi-chip system. Please refer to [link / reference]. Figure 7 In some embodiments, the multi-chip system 1 further includes a processor 12. The processor 12 is interconnected with each chip 10 via a bus 11. In some embodiments, the processor 12 may act as an observer, acquiring real-time information from each chip 10 via the bus 11, but this disclosure is not limited thereto. In some embodiments, the processor 12 may also be configured to switch from a peer-to-peer mode to a master-slave mode to manage each chip 10.
[0047] Figure 8 A flowchart illustrating another embodiment of the initialization procedure. Please refer to [link / reference]. Figure 8In some embodiments, prior to step S011, the processor 12 further stores the mode value to the storage unit 102 based on firmware setting information (step S016). In some embodiments, the processor 12 further includes a second storage unit. In some embodiments, the firmware setting information is stored in the second storage unit of the processor 12, but this disclosure is not limited thereto.
[0048] In summary, in some embodiments, the multi-chip system 1 does not include an MCU, and the number of communication ports 103 of each chip 10 is therefore not limited by the MCU software and can be expanded as needed. Furthermore, since the multi-chip system 1 does not include an MCU, its cost is significantly reduced. Moreover, in the multi-chip system 1, each chip 10 determines whether its communication port 103 is powered on or off, rather than relying on MCU instructions, thus significantly shortening the control cycle of the multi-chip system 1. In addition, since each chip 10 only needs to obtain its power data from the chip 10 with the next higher priority, the communication power consumption of the multi-chip system 1 is also significantly reduced.
[0049] Although the technical content of this disclosure has been disclosed above with reference to preferred embodiments, it is not intended to limit this disclosure. Any changes and modifications made by those skilled in the art without departing from the spirit of this disclosure should be included within the scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.
[0050] [Symbol Explanation]
[0051] 1: Multi-chip system
[0052] 10, 110, 120, 130, 140: Chips
[0053] 101: Processing Unit
[0054] 102: Storage Unit
[0055] 103: Communication Port
[0056] 11: Bus
[0057] S01~S09, S011~S016, S021~S025: Steps
[0058] 12: Processor
Claims
1. A power management method for a multi-chip system, the multi-chip system comprising a plurality of chips, each of the chips having a priority, each of the chips comprising a processing unit, a storage unit, and a plurality of communication ports, the storage unit being configured to store a mode value and a used power value, the mode value being a static mode value or a dynamic mode value, the power management method comprising: the processing unit executing an initialization procedure to obtain a remaining available power value, the initialization procedure comprising: the processing unit reading the mode value to determine whether the mode value is the dynamic mode value or the static mode value; the processing unit reading the used power value of the storage unit of the chip of the previous priority; and the processing unit subtracting the used power value of the storage unit of the chip of the previous priority from a total power value to obtain the remaining available power value; the processing unit executing a power supply procedure to each of the communication ports in time division, the power supply procedure comprising: the processing unit detecting and ranking the communication ports to obtain a required power value of the communication ports; the processing unit comparing the remaining available power value and the required power value; and when the remaining available power value is greater than or equal to the required power value, the processing unit supplying power to the communication ports and subtracting the required power value from the remaining available power value to obtain an updated remaining available power value; the processing unit calculating a power consumed by each of the communication ports that has been powered on, when the mode value is the static mode value, the power consumed by each of the communication ports being the required power value of each of the communication ports; the processing unit summing the power consumed by all of the communication ports that have been powered on to obtain a local used power value; the processing unit subtracting the used power value of the storage unit of the chip of the previous priority and the local used power value from the total power value to obtain a second remaining available power value; and when the second remaining available power value is greater than or equal to zero, the processing unit adding the used power value of the storage unit of the chip of the previous priority and the local used power value to obtain the used power value and storing the used power value to the storage unit.
2. The power management method of claim 1, wherein when the processing unit calculates the power consumed by each of the communication ports that has been powered on, when the mode value is the dynamic mode value, the power consumed by each of the communication ports is a real-time voltage value of each of the communication ports multiplied by a real-time current value of each of the communication ports.
3. The power management method of claim 2, further comprising: when the second remaining available power value is less than zero, the processing unit stopping power supply to one of all of the communication ports that have been powered on and recalculating the local used power value and the second remaining available power value.
4. The power management method of claim 3, wherein the power supply procedure further comprises: when the processing unit supplies power to the communication ports, the processing unit waiting for a stabilization time to confirm that a powered-on state of the communication ports is stable.
5. The power management method of claim 4, wherein the initialization procedure further comprises: The processing unit checks whether the chip of the previous priority is failed according to the priority; and When the chip of the previous priority is not failed, the processing unit reads the used power value of the storage unit of the chip of the previous priority.
6. The power management method of claim 5, wherein the priority of each chip is determined by an address of each chip.
7. The power management method of claim 6, wherein each communication port has a second priority, and when the second remaining available power value is less than 0, the processing unit stops power supply to one of all the communication ports that have been powered on according to the second priority of each communication port.
8. The power management method of claim 7, wherein the processing unit performs the power supply procedure to each communication port according to the second priority of each communication port in time division.
9. The power management method of claim 8, wherein the initialization procedure further comprises: The processing unit stores the mode value to the storage unit according to firmware setting information.
10. The power management method of claim 8, wherein the multi-chip system further comprises a processor, and the initialization procedure further comprises: The processor stores the mode value to the storage unit according to firmware setting information.