Address management method, data access method, memory and storage control board

Abstract

The invention discloses an address management method, a data access method, a memory and a storage control board, and belongs to the technical field of storage. According to the method, a traditional FTL mapping table is divided into a first mapping table and a plurality of second mapping tables for a storage control board and a plurality of storage medium boards in a memory, the first mapping table describes a logic address range corresponding to each storage medium board, and the second mapping table describes a logic address range corresponding to each storage medium board. Each second mapping table describes the physical address corresponding to each logic address in the logic address range corresponding to one storage medium board, the first mapping table is managed through the storage control board, the respective second mapping table is managed through each storage medium board, and compared with a traditional FTL mapping table, the first mapping table does not need to describe the physical address, so that the mapping efficiency is improved. The data size of the first mapping table is smaller, and when the storage control board caches the first mapping table, the first mapping table occupies less cache space of the storage control board.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to an address management method, a data access method, a memory, and a storage control board. Background Technology

[0002] For the massive data storage needs of scenarios such as artificial intelligence (AI), cloud computing, and the Internet, high-capacity solid-state drives (SSDs) can meet customers' demands for higher density, lower energy efficiency, and reduced total cost of ownership (TCO) of storage devices in storage systems.

[0003] Currently, storage systems store data using high-capacity SSDs. A high-capacity SSD includes an SSD controller and multiple storage media. The SSD controller has a flash translation layer (FTL) function. The FTL function is used to map the host's logical address space to the physical address space of the entire SSD. Based on this mapping, data is accessed through the storage space provided by the storage media in the SSD. For the FTL function, the SSD controller maintains an FTL mapping table. The FTL mapping table includes the physical addresses of the data written to each storage media in the SSD and the logical addresses corresponding to each physical address. The SSD controller manages and caches the FTL mapping table.

[0004] In scenarios requiring storage of massive amounts of data, a large number of physical addresses in a large-capacity SSD will be occupied by writing data. Since the FTL mapping table includes each physical address in the SSD where data is written and the logical address corresponding to each physical address, the data volume of the FTL mapping table is relatively large. When the SSD controller caches the FTL mapping table, the FTL mapping table occupies a large amount of the SSD controller's cache space. Summary of the Invention

[0005] This application provides an address management method, a data access method, a memory, and a memory controller board, which can reduce the cache space occupied by the FTL mapping table on the memory controller board. The memory here is, for example, an SSD, and the memory controller board is, for example, an SSD controller. The technical solution is as follows:

[0006] In a first aspect, an address management method is provided, which is applied to a first memory, the first memory including a first memory control board and a plurality of first memory media boards connected to the first memory control board. For example, the first memory may be an SSD, the first memory control board may be an SSD controller, and the first media boards may be media modules in the SSD, including at least one memory medium.

[0007] The method includes: a first storage control board managing a first mapping table, and each first storage medium board managing its own second mapping table, wherein the first mapping table describes the logical address range corresponding to each first storage medium board, and each second mapping table describes the physical address corresponding to each logical address within the logical address range of its respective storage medium board.

[0008] This method targets the memory controller board and multiple memory media boards in a memory system. It splits the traditional FTL mapping table into a first mapping table and multiple second mapping tables. The first mapping table describes the logical address range corresponding to each memory media board, and each second mapping table describes the physical address corresponding to each logical address within the logical address range of a memory media board. The first mapping table is managed by the memory controller board, and each memory media board manages its own second mapping table. Compared to the traditional FTL mapping table, the first mapping table does not need to describe physical addresses; therefore, its data volume is smaller. Taking an SSD as the memory and an SSD controller as the memory controller board as an example, because the data volume of the first mapping table is smaller than that of the traditional FTL mapping table, the SSD controller replaces the traditional FTL mapping table with the first mapping table. When caching the first mapping table, its cache space usage on the SSD controller is less.

[0009] In one possible implementation, the method further includes: a first storage control board responding to a first access request, selecting a first target storage medium board from a plurality of first storage medium boards based on a first mapping table, and sending a first access request to the first target storage medium board; and the first target storage medium board responding to the first access request sent by the first storage control board, performing data access on the storage space corresponding to the physical address in the first target storage medium board based on a managed second mapping table.

[0010] Based on the above possible implementations, by offloading a portion of the physical address access capabilities of the memory control board to the storage medium board, for each access request, the memory control board only needs to determine the target storage medium board from the storage medium boards of the memory based on the logical address range of each first memory, without needing to determine the specific physical address corresponding to the access request. The target storage medium board then accesses data in its internal storage space based on its own logical address range.

[0011] Taking an SSD as the storage device and an SSD controller as the storage control board as an example, compared to the traditional SSD controller determining the physical address to be accessed by an access request based on the traditional FTL mapping, this method reduces the computing power of the SSD controller, enabling it to handle more access requests concurrently, thereby improving the data read and write efficiency of the SSD. Furthermore, the SSD controller does not need to maintain a massive FTL mapping table; it only needs to maintain a mapping table between address ranges and storage devices (the first mapping table), distributing the mapping table between physical addresses (the second mapping table) across the various storage devices for maintenance, thus reducing the pressure on the access request management system to maintain the massive FTL mapping table.

[0012] In one possible implementation, the first storage control board, in response to a first access request, selects a first target storage medium board from a plurality of first storage medium boards based on a first mapping table, and sends a first access request to the first target storage medium board, including: in response to the first access request being a write request, the first storage control board allocates a first target storage medium board for the first access request from the plurality of first storage medium boards, sends a first access request to the first target storage medium board, and establishes a first mapping relationship between a first target logical address and a first target storage medium board in the first mapping table, wherein the first target logical address is the logical address carried in the first access request; or, in response to the first access request being a read request, the first storage control board, based on the first mapping table, queries the storage medium board corresponding to the first target logical address, and sends a first access request to the storage medium board corresponding to the first target logical address, wherein the storage medium board corresponding to the first target logical address is the first target storage medium board;

[0013] In response to a first access request sent by a first storage control board, the first target storage medium board performs data access on the storage space corresponding to the physical address in the first target storage medium board based on a managed second mapping table. This includes: in response to the first access request being a write request, the first target storage medium board allocates a target physical address for the first data carried by the first access request from a physical address in at least one storage medium within the first target storage medium board, writes the first data to the storage space corresponding to the target physical address, and establishes a second mapping relationship between the first target logical address and the target physical address in the managed second mapping table; or, in response to the first access request being a read request, the first target storage medium board queries the target physical address corresponding to the first target logical address based on the managed second mapping table and reads the data stored in the storage space corresponding to the target physical address.

[0014] In one possible implementation, the first storage control board responds to the first access request by selecting a first target storage medium board from a plurality of first storage medium boards based on a first mapping table, and sending the first access request to the first target storage medium board includes: the first storage control board responds to the first access request by querying the storage medium board corresponding to the first target logical address based on the first mapping table, and sending the first access request to the storage medium board corresponding to the first target logical address, wherein the first target logical address is the logical address carried in the first access request, and the storage medium board corresponding to the first target logical address is the first target storage medium board;

[0015] In response to a first access request sent by a first storage control board, the first target storage medium board performs data access on the storage space corresponding to the physical address in the first target storage medium board based on a managed second mapping table. This includes: in response to the first access request being a write request, the first target storage medium board allocates a target physical address for the first data carried by the first access request from a physical address in at least one storage medium within the first target storage medium board, writes the first data to the storage space corresponding to the target physical address, and establishes a second mapping relationship between the first target logical address and the target physical address in the managed second mapping table; or, in response to the first access request being a read request, the first target storage medium board queries the target physical address corresponding to the first target logical address based on the managed second mapping table and reads the data stored in the storage space corresponding to the target physical address.

[0016] In one possible implementation, a first memory and a second memory are connected, the second memory including a plurality of second storage media boards, and the method further includes: a first storage control board obtaining a third mapping table, responding to a second access request, selecting a second target storage media board from the plurality of second storage media boards based on the third mapping table, and sending a second access request to the second target storage media board, wherein the third mapping table describes the logical address range corresponding to each second storage media board.

[0017] Based on the above possible implementation methods, the storage control board in one memory can access data from the storage media boards in other memories based on the logical address range corresponding to each storage media board in other memories, which can reduce the data access pressure of other memories and achieve load balancing between memories.

[0018] In one possible implementation, the first memory further includes a second memory control board for managing a first mapping table and multiple first memory media boards; the method further includes: the first memory control board acquiring the first mapping table managed by the second memory control board.

[0019] Based on the above possible implementation methods, the storage control board can obtain the first mapping table managed by other storage control boards in the memory, and then access the storage media boards managed by other storage control boards in the memory based on the first mapping table managed by other storage control boards. This can reduce the data access pressure on other storage control boards and achieve load balancing among storage control boards in the memory.

[0020] Secondly, a data access method is provided, which is applied to a storage control board connected to a plurality of first storage media boards. The method includes: receiving a first access request; responding to the first access request; selecting a first target storage media board from the plurality of first storage media boards based on a first mapping table; and sending a first access request to the first target storage media board. The first access request indicates data access to a first target logical address, and the first mapping table describes the logical address range corresponding to each first storage media board.

[0021] In one possible implementation, the above-mentioned response to a first access request, selecting a first target storage medium from a plurality of first storage mediums based on a first mapping table, and sending a first access request to the first target storage medium includes: in response to a write request, allocating a first target storage medium from the plurality of first storage mediums for the first access request, sending a first access request to the first target storage medium, and establishing a first mapping relationship between a first target logical address and a first target storage medium in the first mapping table; or, in response to a read request, querying the storage medium corresponding to the first target logical address based on the first mapping table, and sending a first access request to the storage medium corresponding to the first target logical address, wherein the storage medium corresponding to the first target logical address is the first target storage medium.

[0022] In one possible implementation, the above-mentioned response to the first access request, selecting a first target storage medium board from a plurality of first storage medium boards based on a first mapping table, and sending a first access request to the first target storage medium board includes: responding to the first access request, querying the storage medium board corresponding to the first target logical address based on the first mapping table, and sending a first access request to the storage medium board corresponding to the first target logical address, wherein the storage medium board corresponding to the first target logical address is the first target storage medium board.

[0023] In one possible implementation, the aforementioned storage control board and multiple first storage media boards are located in a first memory, the first memory and a second memory are connected, the second memory includes multiple second storage media boards, and the method further includes: obtaining a third mapping table, responding to a second access request, selecting a second target storage media board from the multiple second storage media boards based on the third mapping table, and sending a second access request to the second target storage media board, wherein the second access request indicates data access to a second target logical address, and the third mapping table describes the logical address range corresponding to each second storage media board.

[0024] In one possible implementation, the aforementioned storage control board and multiple first storage media boards are located in a first memory, and the first memory further includes a second storage control board for managing a first mapping table and multiple first storage media boards; the method further includes: obtaining the first mapping table managed by the second storage control board.

[0025] Thirdly, a memory is provided for performing the method provided in the first aspect or any alternative manner of the first aspect.

[0026] Fourthly, a storage control board is provided for performing the method provided in the second aspect or any alternative manner of the second aspect.

[0027] Fifthly, a storage control board is provided, the storage control board including a processor for performing the method provided as described in the second aspect above or any alternative method of the second aspect above.

[0028] In a sixth aspect, a storage medium board is provided, the storage medium board including a processor and a storage medium, the processor being configured to perform method steps performed by the storage medium board in the method provided in the first aspect or any alternative method of the first aspect.

[0029] A seventh aspect provides a computer-readable storage medium storing at least one piece of program code that is read by a processor in a storage control board to cause the storage control board to perform the method provided in the second aspect above or any alternative method of the second aspect above.

[0030] Eighthly, a computer-readable storage medium is provided, the storage medium storing at least one piece of program code, the program code being read by a processor in the storage medium board to cause the storage medium board to perform the method steps performed by the storage medium board in the method provided in the first aspect above or any alternative mode of the first aspect above.

[0031] In a ninth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor in a storage control board reading the program code from the computer-readable storage medium, the processor executing the program code, causing the storage control board to perform the method provided by the second aspect or various optional implementations of the second aspect described above.

[0032] In a tenth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor in the storage medium board reading the program code from the computer-readable storage medium, the processor executing the program code, causing the storage medium board to perform the method steps performed by the storage medium board as provided in the first aspect or any alternative method of the first aspect. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of another storage system provided in an embodiment of this application;

[0035] Figure 3 This is a comparative schematic diagram of an FTL mapping table provided in an embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram illustrating an interface change of a storage medium provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0039] Figure 7 This is a flowchart of an address management method provided in an embodiment of this application;

[0040] Figure 8 This is a flowchart of a data access method provided in an embodiment of this application;

[0041] Figure 9 This is a flowchart illustrating a data writing process applied to a memory, as provided in an embodiment of this application.

[0042] Figure 10 This is a data reading flowchart for a memory provided in an embodiment of this application;

[0043] Figure 11This is a flowchart of another data access method provided in an embodiment of this application;

[0044] Figure 12 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0045] Figure 13 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0046] Figure 14 This is a schematic diagram illustrating the switching of a primary and backup storage control board according to an embodiment of this application;

[0047] Figure 15 This is a flowchart of another data access method provided in an embodiment of this application;

[0048] Figure 16 This is a schematic diagram illustrating the switching of another primary / standby storage control board provided in an embodiment of this application;

[0049] Figure 17 This is a schematic diagram illustrating communication between two memory devices according to an embodiment of this application;

[0050] Figure 18 This is a flowchart of another data access method provided in an embodiment of this application;

[0051] Figure 19 This is a flowchart of a data reconstruction method provided in an embodiment of this application. Detailed Implementation

[0052] To facilitate understanding of the specific embodiments of this application, the embodiments of this application will be further described in detail with reference to the accompanying drawings.

[0053] Combination Figure 1 This paper introduces the implementation environment of the data access method provided in this application.

[0054] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application, such as... Figure 1 As shown, the storage system includes a compute node cluster and a storage node cluster. The compute node cluster includes one or more compute nodes 110. The compute nodes 110 in the compute node cluster can communicate with each other. Figure 1 The diagram shows three computing nodes 110, but the number of computing nodes 110 in the computing node cluster is not limited to three. In this embodiment of the application, the number of computing nodes 110 in the computing node cluster is not limited.

[0055] Computing node 110 is an electronic device, such as a server, desktop computer, storage controller of a storage array, mobile phone, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, or any other suitable electronic device capable of connecting to memory 122. This application embodiment does not limit the device type of computing node 110. Figure 2 Taking the storage system shown as an example, the computing node 110 can be a large-scale supernode, or a third-party computing node in the cloud or the Internet. Here, the application scenarios of the computing node 110 are not limited in this embodiment.

[0056] In terms of hardware, such as Figure 1 As shown, compute node 110 includes at least a processor 111, a cache 112, and a network interface 113. The processor 111 is a CPU used to process requests from outside the compute node 110 or requests generated internally within the compute node 110. For example, when the processor 111 receives a write request from a user, it temporarily stores the data in the cache 112. When the total amount of data in the cache 112 reaches a certain threshold, the processor 111 sends the data stored in the cache 112 to the storage node 120 for persistent storage. In addition, the processor 111 is also used for data computation or processing, such as metadata management, deduplication, data compression, virtualization of storage space, and address translation. Figure 1 Only one CPU111 is shown in this embodiment. In practical applications, there are often multiple CPUs111, and each CPU111 has one or more CPU cores. This embodiment does not limit the number of CPUs or the number of CPU cores.

[0057] Cache 112 refers to the internal memory that directly exchanges data with processor 111. It can read and write data at any time at a very fast speed, serving as temporary data storage for the operating system or other running programs. For example, processor 111 temporarily stores data to be written in cache 112. When the total amount of data in cache 112 reaches a certain threshold, processor 111 then stores the data stored in cache 112 into memory 122.

[0058] Cache 112 includes at least two types of memory, such as random access memory (RAM) or read-only memory (ROM). For example, RAM can be dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), or storage class memory (SCM). DDR SDRAM can also be simply referred to as DDR. DRAM is a semiconductor memory, and like most random access memory (RAM), it is a type of volatile memory device. SCM is a hybrid storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard drives, but its access speed is slower than DRAM, and it is also cheaper than DRAM. However, DRAM and SCM are only illustrative examples in this embodiment; the cache may also include other random access memories, such as static random access memory (SRAM). For read-only memory, examples include programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM). Additionally, cache 112 can also be a dual in-line memory module (DIMM), i.e., a module composed of DRAM, or an SSD. In practical applications, multiple caches 112 and different types of caches 112 can be configured in the compute node 110. This application embodiment does not limit the number or type of caches 112 in the compute node 110. Furthermore, cache 112 can be configured to have a power-saving function. The power-saving function means that when the system experiences a power outage and then power is restored, the data stored in the cache will not be lost.

[0059] Network interface 113 is used to communicate with storage node 120. For example, when the total amount of data in cache 112 reaches a certain threshold, compute node 110 can send a request to storage node 120 via network interface 113 to persistently store the data. Additionally, compute node 110 may also include a bus for communication between components within compute node 110. Functionally, since... Figure 1 The primary function of compute node 110 is computing operations. When storing data, it can utilize remote storage for persistent storage, thus requiring less local storage than a conventional server, resulting in cost and space savings. However, this does not mean that compute node 110 cannot have local storage. In practice, compute node 110 can also have a small amount of built-in storage or external storage.

[0060] Any compute node 110 can communicate with storage nodes 120 in the storage node cluster through network 130. For example, network interface 113 in compute node 110 is connected to network 130, and compute node 110 can access any storage node 120 in the storage node cluster through network interface 113.

[0061] Network 130 supports a memory consistency protocol, which enables fast and reliable data transfer between different components connected to network 130. Therefore, network 130 can also be called a high-speed interconnect network. The memory consistency protocol is also used to share the storage space of multiple storage nodes 120 in a storage node cluster with multiple compute nodes 110, allowing multiple compute nodes 110 to access the storage space of multiple storage nodes 120 simultaneously.

[0062] like Figure 2As shown, the memory coherence protocols supported by network 130 include Compute Express Link (CXL) or Remote Direct Memory Access over Converged Ethernet (ROCE). However, the types of memory coherence protocols are not limited to CXL and ROCE. For example, memory coherence protocols also include the common high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe), Fibre Channel (FC), Small Computer System Interface (SCSI) protocol, Ethernet protocol, or Remote Direct Memory Access (RDMA), etc., among which the RDMA protocol includes InfiniBand (IB). Here, this application embodiment does not limit the memory coherence protocol. The memory coherence protocol allows multiple computing nodes 110 outside of memory 122 to access the storage space of memory 122 simultaneously, which can improve the memory access efficiency.

[0063] Network interface 113 also supports memory coherence protocols so that any component in compute node 110 (such as processor 111 or cache 112) can connect to network 130 via network interface 113, thereby enabling the component to communicate with memory 122 in storage node 120 via network 130.

[0064] The storage node cluster is used to provide storage space for the compute node cluster. The storage node cluster includes at least one storage node 120. Each storage node 120 is connected to the network 130. Different storage nodes 120 can communicate with each other through the network 130. Compute nodes 110 and storage nodes 120 can also communicate with each other through the network 130. Figure 1 The diagram shows three storage nodes 120, but the number of storage nodes 120 in a storage node cluster is not limited to three. This embodiment of the application does not limit the number of storage nodes 120 in the storage node cluster. Storage node 120 can be any device capable of increasing storage space, such as a server, desktop computer, or storage controller or hard disk enclosure of a storage array. This embodiment of the application does not limit the type of device for storage node 120.

[0065] like Figure 1 As shown, each storage node 120 includes a network interface 121 and at least one memory 122, wherein the memory 122 is used to provide storage space. Figure 1The memory 122 shown is a flash memory, such as an SSD. However, memory 122 is not limited to SSDs; it can be any other type of memory, as long as it is accessed based on an FTL address mapping mechanism (not limited to the current FTL mapping, but also including other memories with address translation mechanisms between logical and physical addresses). Here, this application embodiment does not limit the device type of memory 122. Figure 1 The diagram shows three memory units 122, but the number of memory units 122 in storage node 120 is not limited to three. Therefore, this embodiment does not limit the number of memory units 122 in storage node 120. In this embodiment, when the memory is directly connected to the computing node 110, it communicates with the computing node 110 via, for example, an M.2 interface or a Serial Advanced Technology Attachment (SATA) interface. The M.2 interface is also known as a Next Generation Form Factor (NGFF) interface. The communication protocol between the memory and the computing node 110 is, for example, a PCIe or SATA bus.

[0066] Each memory 122 in storage node 120 is connected to a network interface 121 in its respective storage node 120. Network interface 121 is used for communication with other devices outside storage node 120. For example, network interface 121 and network interface 113 are both connected to network 130 to connect storage node 120 and compute node 110 to network 130. Both network interface 121 and network interface 113 support memory coherence protocols, enabling any component in compute node 110 (such as processor 111 or cache 112) to communicate with any component in storage node 120 (such as memory 122 or control device of storage node 120) through the communication link formed by network interface 113, network 130, and network interface 121. Each network interface 121 in storage node 120 is connected to network 130, allowing different components in different storage nodes 120 to communicate through network 130. Therefore, through network interface 101 in each compute node 101, network 130, and network interface 121 in each storage node 120, [the following is possible:] Figure 1 The storage system shown is a fully switched, fully pass-through cluster architecture. The memory 122 supports direct network output and end-to-end data pass-through, meaning storage is available wherever data is accessed, resulting in a multi-fold increase in storage capacity. In traditional storage systems, when any network-connected component (such as a compute node) needs to access components on other network-connected hosts (such as storage nodes), the CPU of those hosts must be interrupted, and the system must wait for CPU scheduling before accessing those components. This wastes CPU computing power and results in significant access latency. Figure 1The storage system shown is a fully switched, fully pass-through cluster architecture. Any component connected to network 130 (such as compute node 110) can directly access other components (such as storage node 120) connected to network 130 without waiting for CPU scheduling of other components. This avoids wasting the CPU computing power of other components and also reduces access latency.

[0067] exist Figure 1 In this embodiment, the storage system includes one storage node cluster, which is used by the computing node cluster to provide data storage services. In other embodiments, the storage system may also include two storage node clusters, namely a first storage node cluster and a second storage node cluster, such as... Figure 2 As shown, both the first storage node cluster and the second storage node cluster consist of at least one storage node. The first storage node cluster is used to provide data storage services to the computing node cluster. Figure 1 The storage node cluster shown can serve as the first storage node cluster. The second storage node cluster is used to provide metadata storage services for the compute node cluster. The compute nodes can store user data in storage nodes 120 of the first storage node cluster. The data stored in the first storage node cluster also has metadata, which describes the storage location of the data in the storage system. Storage nodes 120 in the second storage node cluster are used to store the metadata. The second storage node cluster is connected to network 130 so that the second storage node cluster can communicate with storage nodes 120 in the first storage node cluster and compute nodes 110 in the compute cluster through network 130. For example, when a compute node 110 finishes storing a piece of data in a storage node 120 in the first storage cluster, storage node 120 stores at least one of the following as metadata: the logical address corresponding to the physical address of the data, the identifier of the memory where it is located, and the identifier of the memory 122 where it is located. This metadata is stored in a storage node in the second storage node cluster. In this way, before the compute node 110 reads the data, it can first query the metadata of the data from the storage node in the second storage node cluster, and then read the data from the physical address of the data based on the queried metadata.

[0068] In traditional SSDs, the storage media within the SSD are controlled by an SSD controller. This controller typically features a flash translation layer (FTL) function. For ease of description, we will refer to the SSD controller in a traditional SSD as a traditional SSD controller, and its FTL function as a traditional FTL function. The traditional FTL function maps the host's logical address space to the entire physical address space of the SSD. Based on this mapping, it performs data access to the storage control provided by the storage media within the SSD. The logical address space includes multiple logical addresses (LAs), which are cache addresses generated by the host's CPU. The entire physical address space of the SSD includes the physical addresses (PAs) of all the storage media within the SSD.

[0069] For traditional FTL functionality, traditional SSD controllers store an FTL mapping table. This FTL mapping table, referred to as the traditional FTL mapping table, records the mapping relationships between physical addresses (PAs) that have been written to the SSD. Traditional SSD controllers uniformly address the physical addresses within all storage media of the SSD. For example... Figure 3 As shown, taking a traditional SSD as an example, assuming the physical address space of the traditional SSD includes PA0-PA15 and the logical address space of the host includes LA0-LA15, whenever data is written to a physical address in this physical address space, the traditional SSD controller records the mapping relationship between that physical address and a logical address in the traditional FTL mapping table. Assuming that data has been written to PA0-PA15, the traditional SSD controller's FTL mapping table will record 16 mapping relationships between LA0-LA15 and PA0-PA15. Each LA in LA0-LA15 is mapped to one PA in PA0-PA15, and different LAs are mapped to different PAs. For example, there is a mapping relationship between LA0 and PA7 to indicate that LA0 is mapped to PA7, there is a mapping relationship between LA5 and PA3 to indicate that LA5 is mapped to PA3, and there is a mapping relationship between LA8 and PA15 to indicate that LA8 is mapped to PA15.

[0070] Since every time data is written to a physical address in the physical address space, the traditional SSD controller records the mapping relationship between the physical address and a logical address in the traditional FTL mapping table, as the amount of data written increases, the number of mapping relationships recorded in the traditional FTL mapping table increases, the cache space required by the traditional FTL mapping table increases, which reduces the cache space of the traditional SSD controller. This makes it impossible for the SSD controller to cache more data to be written or data that has already been read, resulting in a decrease in the data read and write efficiency of the SSD.

[0071] Based on this, this application provides a memory, in which the controller is referred to as a memory control board. This application also improves upon the traditional FIT (Functional Threading) function by designing a two-level FTL (Functional Threading Table) mapping table: a primary FTL mapping table and a secondary FTL mapping table. The primary FTL mapping table describes the logical address range corresponding to each storage medium board in the memory, and the secondary mapping table describes the physical address corresponding to each logical address within the logical address range of its respective storage medium board. In this application, the traditional FTL mapping table is replaced by a primary FTL mapping table, which is managed by the memory control board. The secondary FTL mapping table is then located within the memory and managed by the storage medium boards of the memory control board, with the storage medium boards managing the secondary FTL mapping table. The memory control board selects storage medium boards for data access based on the primary FTL mapping table, and the storage medium boards access data based on the secondary FTL mapping table. This memory can be configured as an SSD, the memory control board can be configured as an SSD controller, and the storage medium boards can be configured as media modules within an SSD.

[0072] The memory provided in this application can be used in... Figure 1 and Figure 2 The storage system shown is, for example, the memory 122 described above. The memory provided in this application is based on a two-level FTL mapping table, and data access is accomplished through the data access method provided in this application.

[0073] Figure 4 This is a schematic diagram of the structure of a memory provided in an embodiment of this application, such as... Figure 4 As shown, the memory 122 includes a network interface 21, a memory control board 22, multiple memory media boards 23, a cache area 24, and an interface circuit 25, wherein the memory control board 22, the network interface 21, and the memory media boards 23 are connected.

[0074] For example, the storage control board 22 and the storage medium board 23 are connected via hot-swapping. For instance, the memory 122 also includes an interface circuit 25, which is used to connect to the storage medium board 23 and the storage control board 22 in the memory 122 via hot-swapping, so that the storage control board 22 and the multiple storage medium boards 23 can communicate through the interface circuit 25.

[0075] In one possible implementation, the interface circuit 25 is located within the storage medium board 23, and the interface circuit 25 serves as the external interface of the storage medium board 23. For example, each storage medium board 23 includes the interface circuit 25, and the storage control board 22 is connected to the interface circuits 25 of multiple storage medium boards 23 via hot-swapping. For instance, the storage control board 22 includes multiple hot-swappable interfaces, each supporting hot-swappable connection, and each hot-swappable interface is plugged into the interface circuit 25 of one storage medium board 23.

[0076] In another possible implementation, the interface circuit 25 is not located on the storage medium board 23, but in a component outside the storage medium board 23 within the memory 122. For example, Figure 4 As shown, the memory 122 also includes a connector 2x, which includes an interface circuit 25. The connector 2x is connected to the storage medium board 23 and the storage control board 22 via the interface circuit 25. For example, the connector 2x also includes multiple hot-swappable interfaces 26, which support hot-swappable connections. Each hot-swappable interface 26 is connected to the interface circuit 25 and is used to connect to the storage control board 22 or the storage medium board 23 via hot-swapping.

[0077] According to the different connected objects, the multiple hot-swappable interfaces 26 are divided into hot-swappable control interfaces and hot-swappable storage interfaces.

[0078] A hot-swappable storage interface is used to connect storage media board 23. There are multiple hot-swappable storage interfaces, and each storage media board 23 is hot-swappably connected to the interface circuit 25 in connector 2x through the hot-swappable storage interface. For example, each storage media board 23 includes a gold finger area, which includes multiple gold fingers. The gold finger area of ​​the storage media board 23 is inserted into the hot-swappable storage interface to achieve a hot-swappable connection between the storage media board 23 and the interface circuit 25 in connector 2x.

[0079] Optionally, at least one hot-swappable storage interface on connector 2x is idle. An idle hot-swappable storage interface means that no storage medium board 23 is plugged into the hot-swappable storage interface. In this way, if the storage capacity of memory 122 needs to be expanded, a new storage medium board 23 can be plugged into the idle hot-swappable storage interface to achieve the expansion.

[0080] Optionally, the hot-swappable storage interface is a serializer-deserializer (serdes) interface. Figure 5 Taking the storage medium board 23 as an example, the control circuit 232 in the storage medium board 23 is connected to the serdes interface on the connector 2x.

[0081] In traditional SSDs, the SSD storage controller connects to NAND chips through an open NAND flash interface (ONFI). ONFI is a parallel interface, and the traces from ONFI tend to be crowded together, resulting in traces that can only extend to a few centimeters at most. The extension range of the traces is relatively small, and the number of NAND chips connected to the traces is small, thus limiting the number of NAND chips in a traditional SSD, and consequently limiting the storage capacity of the traditional SSD. Even for large-capacity traditional SSDs, the storage capacity of traditional SSDs can only reach the terabyte (TB) level, and cannot reach higher capacity levels.

[0082] Compared to the routing range of the parallel interface, the routing range of the SERDE interface is larger. When the SERDE interface is used as a hot-swappable storage interface, the connector 2x can connect a large number of storage media boards 23 within the routing range of the SERDE interface, thereby increasing the number of storage media 231 in the memory 122 and increasing the storage capacity of the memory 122, so that the storage capacity of the memory 122 can reach the petabyte (PB) level or higher.

[0083] A hot-swap control interface is used to connect the storage control board 22. There is at least one hot-swap control interface, and each storage control board 22 is hot-swap connected to the interface circuit 25 in the connector 2x via one hot-swap control interface. For example, each storage control board 22 has a gold finger area comprising multiple gold fingers. The gold finger area of ​​each storage control board 22 is inserted into the hot-swap control interface to achieve a hot-swap connection between the storage control board 22 and the interface circuit 25 in the connector 2x. The gold finger area of ​​each storage control board 22 may or may not be located on the storage control board 22. Taking an example where the gold finger area is not located on the storage control board 22... Figure 4 As shown, the storage control board 22 and other components are packaged into a control module 27. The control module 27 includes a gold finger area, which is connected to the storage control board 22. The gold finger area connected to the storage control board 22 is the gold finger area that the storage control board 22 has. The gold finger area on the control module 27 is inserted into the hot-swappable control interface to realize the hot-swappable connection between the storage control board 22 and the interface circuit 25 in the connector 2x.

[0084] Other components in the control module 27 can be the cache 24, or other hardware besides the cache 24. This application embodiment does not limit the type of other components. The cache 24 includes at least two types of storage media boards. For example, the cache 24 can be random access memory (RAM) or read-only memory (ROM). For instance, RAM can be dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), or storage class memory (SCM). DDR SDRAM can also be simply referred to as DDR. DRAM is a semiconductor memory, and like most random access memory (RAM), it is a type of volatile memory device. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard drives, but its access speed is slower than DRAM, and it is also cheaper than DRAM. However, DRAM and SCM are only illustrative examples in this embodiment. Cache 24 may also include other random access memories, such as static random access memory (SRAM). For read-only memory, for example, it may be programmable read-only memory (PROM) or erasable programmable read-only memory (EPROM). Additionally, cache 24 may be a dual in-line memory module (DIMM), i.e., a module composed of DRAM, or it may be an SSD. In practical applications, multiple caches 24 and different types of caches 24 can be configured in memory 122. This application embodiment does not limit the number and type of caches 24 in memory 122. Furthermore, cache 24 can be configured to have a power-saving function. The power-saving function means that when the system experiences a power outage and then power is restored, the data stored in the cache will not be lost.

[0085] Taking the other components in the control module 27 as the cache area 24 as an example, the memory 122 also includes at least one cache area 24. When the memory 122 includes a storage control board 22, the at least one cache area 24 is associated with the storage control board 22. When the memory 122 includes multiple storage control boards 22, each storage control board 22 is associated with at least one cache area 24. For any storage control board 22, any storage control board 22 and the associated cache area 24 are encapsulated into a control module 27. That is, the memory 122 includes at least one control module 27, and each control module 27 includes a storage control board 22 and at least one cache area 24.

[0086] Figure 4 This example illustrates a memory 122 comprising two cache areas 24, but the number of cache areas 24 in the memory 122 is not limited to two. Figure 4 The example shown is that the storage control board 22 is associated with two cache areas 24, but the number of cache areas 24 associated with the storage control board 22 is not limited to two. In this embodiment of the application, the number of cache areas 24 in the memory 122 and the number of cache areas 24 associated with the storage control board 22 are not limited. Figure 4 The example shown uses DDR as the cache area 24, but the type of cache area 24 is not limited to DDR and can be any type of cache area described above.

[0087] The storage control board 22 is connected to its associated cache areas 24. The cache areas 24 provide data caching services for the associated storage control board 22. The cache areas 24 are internal storage media boards for direct data exchange between the storage control board 22 and the storage control board 22. They can read and write data at any time at high speed, serving as temporary data storage media boards for running software programs. For example, when the storage control board 22 receives a write request from outside the memory, it temporarily stores the data to be written in the associated cache area 24. When the total amount of data in the cache area 24 reaches a certain threshold, the storage control board 22 then sends the data stored in the cache area 24 to the storage module for persistent storage.

[0088] Figure 4 The example described is based on the cache area 24 being located outside the storage control board 22 in the memory 122. In other embodiments, the cache area 24 is located in the storage control board 22, that is, the storage control board 22 also includes the cache area 24. The cache area 24 is connected to the control chip in the storage control board 22. The cache area 24 is used to provide data caching services for the control chip. The cache area 24 is used to cache the first-level FTL mapping table.

[0089] Network interface 21 is the external communication interface of memory 122, used to communicate with devices outside of memory 122. For example, network interface 21 connects to network 130 in the storage system via network interface 121 in storage node 120. Storage control board 22 receives access requests from compute node 110 via network interface 21, and after processing the access request, returns a response to the access request to compute node 110 via network interface 21. Network interface 21 is connected to connector 2x. For example, network interface 21 is hot-swappable to connector 2x. Figure 4 For example, the hot-swappable interface 26 of connector 2x also includes a hot-swappable network interface, into which the gold finger area on network interface 21 is inserted to achieve a hot-swappable connection between network interface 21 and connector 2x.

[0090] Figure 4 The example shown is that the network interface 21 is indirectly connected to the storage control board 22 through the connector 2x. In other embodiments, the network interface 21 is directly connected to the storage control board 22 so that the network interface 21 and the storage control board 22 can communicate directly. In this case, the network interface 21 is not connected to the connector 2x.

[0091] For any component in memory 122 other than connector 2x (such as memory control board 22, network interface 21, or memory medium board 23), since the component supports hot-swappable connection with connector 2x, in the event of a component failure, the faulty component can be replaced during the operation of memory 122. This allows components in memory 122 to be replaced independently online without affecting the normal operation of memory 122. Thus, when memory 122 is used in a storage system, if a component in a memory 122 fails, only the faulty component needs to be replaced, without replacing the entire memory 122, reducing the maintenance cost of the storage system.

[0092] Multiple components of the memory 122, excluding connector 2x (such as the memory control board 22, network interface 21, and storage medium board 23), are connected to connector 2x to mount (access) these components. This allows any one of these components to communicate with the others via connector 2x. For example, any memory control board 22 can read and write data to any storage medium board 23 via connector 2x. Different storage medium boards 23 can also communicate via connector 2x; for instance, different storage medium boards 23 can exchange stored data with each other. Any memory control board 22 can also communicate via network interface 21 via connector 2x. In other words, different components in the memory 122 connected to connector 2x can communicate.

[0093] Therefore, connector 2x provides a communication link for other components in memory 122, enabling different components in memory 122 to communicate through connector 2x. Thus, different components among these multiple components can communicate and connect through connector 2x. Communication connection refers to the connection method in which different components communicate through a communication link.

[0094] The storage control board 22 manages the storage media boards 23 in the memory 122 and / or other memories. The storage control board 22 manages a first-level FTL mapping table. In response to an access request, it selects a target storage media board from multiple storage media boards 23 based on the first-level FTL mapping table to access data. The first-level FTL mapping table records the mapping relationship (referred to as a first mapping relationship) between logical addresses and multiple storage media boards 23 in the memory. For example, the first-level FTL mapping table includes multiple entries, each entry representing a first mapping relationship. Each mapping entry includes at least one LA in the logical address space and an identifier of a storage media board 23. The identifier of any storage media board 23 is used to represent that storage media board 23 and may be the number of that storage media board 23. Here, the identifier of the storage media board 23 is not limited in this embodiment.

[0095] Still with Figure 3 For example, assuming the memory includes storage media boards 1-4 and the logical address space includes LA0-LA15, the memory control board records the first mapping relationship between LA0-LA15 and storage media boards 1-4 through the first-level FTL mapping table shown in Table 1 below.

[0096] Table 1

[0097] Logical address Identification of storage media boards LA0-LA3 Storage media board 1 LA4-LA7 Storage media board 2 LA8-LA11 Storage media board 3 LA12-LA15 Storage media board 4

[0098] The logical addresses mapped to each storage medium 23 constitute the logical address range of each storage 23. As shown in Table 1 above, the logical address range of storage medium 1 is LA0-LA3.

[0099] Since traditional FTL mapping tables record the mapping relationship between the physical address space and logical address of the entire SSD, the first-level FTL mapping table in this application records the mapping relationship between the identifiers of multiple storage media boards and logical addresses. Since the amount of data for the identifiers of storage media boards is less than that for physical addresses, the first-level FTL mapping table records less information compared to traditional FTL mapping tables. Storing a first-level FTL mapping table can reduce the cache space occupied by the storage controller board 22, so that the storage controller board 22 has enough cache space to process more data to be written or read.

[0100] The memory 122 has at least one storage medium board 23, each storage medium board 23 providing storage space for storing data. The storage space is indicated by a physical address; exemplarily, each storage medium board 23 includes at least one storage medium 231. The storage medium 231 provides a physical address space addressed by a physical address, and at least one storage medium 231 is encapsulated in each storage medium board 23. Each storage medium 231 may be a NAND flash memory chip (NAND chip), a 3D NAND chip, or other types of storage medium. In this embodiment, the number of storage medium boards 23 in the memory 122, the number of storage media 231 in each storage medium board 23, and the type of storage medium are not limited.

[0101] Each storage medium board 23 manages a second-level FTL mapping table. Based on the managed second mapping table, it accesses data to the storage space corresponding to the physical address in the storage medium board. The second mapping table describes the physical address corresponding to each logical address within the logical address range of its respective storage medium board. For example, the second-level FTL mapping table records the mapping relationship (referred to as the second mapping relationship) between a logical address and the physical address in the storage medium 231 within the storage medium board 23. This logical address is a logical address in the first-level FTL mapping table. The physical addresses of the storage spaces within all storage media 231 in any storage medium board 23 are uniformly addressed. The physical addresses of the storage spaces within any storage medium 231 constitute the physical address space of that storage medium 231. The physical addresses in the physical address space of the storage medium 231 are the physical addresses within the storage medium 231. The physical address spaces of all storage media 231 in any storage medium board 23 constitute the physical address space of that storage medium board 23. In other words, the physical address space of any storage medium board 23 includes the physical addresses of all storage media 231 within that storage medium board 23.

[0102] It should be understood that the memory 122 stores multiple second-level FTL mapping tables, each corresponding to a storage medium board 23, and each second-level FTL mapping table is managed by the corresponding storage medium board 23. For any second-level FTL mapping table corresponding to any storage medium board 23, the second-level FTL mapping table includes multiple mapping table entries, each mapping table entry represents a second mapping relationship, and each mapping table entry includes a logical address and a physical address in the physical address space of the storage medium board 23. The logical address corresponds to the storage medium board 23 in the first-level FTL mapping table.

[0103] Still with Figure 3For example, after the storage control board uniformly addresses the physical addresses of all storage media within each of the storage media boards 1-4, the physical address space of each storage media board includes four physical addresses: PA0-PA3. Storage media boards 1-4 provide a total of 16 PAs, which constitute the physical address space of the storage control board 101. Assuming the host's logical address space includes LA0-LA16, LA0-LA15 in the logical address space are mapped to these 16 PAs through a first-level FTL mapping table and four second-level FTL mapping tables. The first-level FTL mapping table is shown in Table 1 above. Each storage media board 1-4 stores a second-level FTL mapping table. The second-level FTL mapping table in any storage media board includes four second-level mapping relationships. Taking storage media board 1 as an example, the second-level FTL mapping table stored in storage media board 1 is shown in Table 2 below.

[0104] Table 2

[0105] Logical address physical address LA0 PA2 LA1 PA0 LA2 PA1 LA3 PA3

[0106] The overall architecture of memory 122 has been described above. Next, based on... Figure 6 Combining the following two parts (1) and (2), the internal structure of the storage control board 22 and the internal structure of the storage medium board 23 will be introduced respectively.

[0107] Figure 6 The image shown is a simplified version of the memory 122, with emphasis on the internal structure of the memory control board 22 and the memory medium board 23. Figure 4 In the illustrated memory 122, each memory control board 22 is communicatively connected to each memory medium board 23 in the memory 122 via a connector 2x. Figure 6 The connector 2x is not shown; the communication connection between the storage control board 22 and the storage medium board 23 is represented by the connection line between them.

[0108] (1) Storage control board 22

[0109] like Figure 6 As shown, the storage control board 22 includes a host interface 221, a first hot-swappable interface 222, and a control chip 223. The host interface 221 is used to connect to a host so that requests from the host can be sent to the control chip 223 through the host interface 221.

[0110] Optionally, the host interface 221, connector 2x, and network interface 21 support the same communication protocol so that they can communicate with each other, such as... Figure 6As shown, the communication protocol can be the memory coherence protocol described above. The memory coherence protocol allows multiple hosts outside of memory 122 to access the physical address space of memory 122 simultaneously, thereby improving memory access efficiency.

[0111] Optionally, the host interface 221 is connected to the connector 2x. For example, the host interface 221 is connected to the gold finger area of ​​the storage control board 22, so as to connect to the connector 2x through the gold finger area. The host interface 221 communicates with the network interface 21 in the storage via the connector 2x. For example, the control chip 223 can communicate with other devices through the communication link formed by the host interface 221, the connector 2x, and the network interface 21. These other devices can be any device other than the storage 122.

[0112] A first hot-swappable interface 222 is used to connect to an interface circuit 25 that connects to multiple storage media boards 23 via hot-swapping. For example, the first hot-swappable interface 222 is hot-swappably connected to a connector 2x, which includes the interface circuit 25 that connects to multiple storage media boards 23. Exemplarily, the first hot-swappable interface 222 is connected to the gold finger area of ​​a storage control board 22 to connect to the connector 2x via the gold finger area. The first hot-swappable interface 222 communicates with multiple storage media boards 23 via the connector 2x, so that the control chip 223 can access these multiple storage media boards 23 through the first hot-swappable interface 222.

[0113] Alternatively, the first hot-swappable interface 222 is used to directly connect to the interface circuits 25 of multiple storage media boards 23 via hot-swapping. For example, each storage media board 23 includes an interface circuit 25, and there may be multiple first hot-swappable interfaces 222, each connected to the interface circuit 25 of one storage media board 23.

[0114] Since the first hot-swappable interface 222 is connected to the interface circuit 25 of multiple storage media boards 23 by hot-swapping, or directly connected to the interface circuit 25 of multiple storage media boards 23 by hot-swapping, if the storage control board 22 fails during the operation of the memory 122, the faulty storage control board 22 can be directly replaced by hot-swapping without replacing the entire memory 122. When the memory 122 is used in a storage system, the maintenance cost of the storage system can be reduced.

[0115] The control chip 223 is a programmable electronic component, such as a central processing unit (CPU) or a data processing unit (DPU). A DPU possesses the versatility and programmability of a CPU, but is more specialized, capable of efficiently operating on network packets, storage requests, or analysis requests. A DPU differs from a CPU in its high degree of parallelism (requiring the processing of a large number of requests). When the control chip 223 is a CPU, the CPU includes one or more cores; however, this embodiment does not limit the number of CPU cores. Optionally, the control chip 223 can also be a graphics processing unit (GPU), an embedded neural network processing unit (NPU), or other processing chips. This embodiment does not limit the type of control chip 223. The number of control chips 223 in the storage control board 22 can be one, two, or more. As the storage capacity of the memory 122 increases and / or the number of devices communicating with the memory 122 increases, the computing power required by the storage control board 22 increases, and the number of control chips 223 can increase accordingly.

[0116] The control chip 223 is used to connect to the host interface 221 and the first hot-swappable interface 222, so that the control chip 223 can communicate with other devices outside the memory 122 through the host interface 221, and communicate with each storage medium board 23 in the memory 122 through the first hot-swappable interface 222.

[0117] The control chip 223 is the control center of the storage control board 22, used to manage the storage media 231 in multiple storage media boards 23. For example, the control chip 223 manages the primary FTL mapping table (e.g., ...). Figure 6 The FTL1 shown responds to an access request by selecting a target storage medium from multiple storage mediums 23 based on the first-level FTL mapping table to access data.

[0118] For example, the control chip 223 has a flash translation layer (FTL) function, which is used to read and write data between the host and the storage media in multiple storage media boards 23 based on a first-level FTL mapping table.

[0119] The control chip 223 can also store the first-level FTL mapping table through the cache area 24, which can reduce the occupation of the first-level FTL mapping table on the internal storage space of the control chip 223, and make it easier for the control chip 223 to quickly query the target storage medium board to be accessed from the stored first-level FTL mapping table when performing data reading and writing, thereby improving data reading and writing efficiency.

[0120] Optionally, the control chip 223 also has other functions for managing the storage medium besides the FTL function, such as erasure coding (EC) / catchup and reBalance (CRB) offloading, garbage collection (GC), and triple parity redundant RAID-TP. The various functions of the control chip 223 can be implemented in hardware, software, or a combination of both. This application does not limit the implementation method of these functions. In the case of any function implemented in hardware, that function may not be integrated into the control chip 223, but may reside outside of it, such as the RAID-TP function.

[0121] (2) Storage medium board 23

[0122] like Figure 4 and Figure 6 As shown, each storage medium board 23 includes at least one storage medium 231, a control circuit 232, and a second hot-swappable interface 233.

[0123] The second hot-swappable interface 233 is used to connect to the interface circuit 25 of the storage control board 22 via hot-swapping, enabling other components in the storage medium board 23 to communicate with the storage control board 22 through the second hot-swappable interface 233. For example, the second hot-swappable interface 233 is hot-swappably connected to the interface circuit 25 within the connector 2x in the memory 122. Exemplarily, the second hot-swappable interface 233 is the gold finger area of ​​the storage medium board 23, and the second hot-swappable interface 233 is plugged into the connector 2x to hot-swappably connect with the interface circuit 25 in the connector 2x. In other embodiments, the storage control board 22 includes the interface circuit 25, and the second hot-swappable interface 233 is used to directly connect to the interface circuit 25 of the storage control board 22 via hot-swapping.

[0124] Since the second hot-swappable interface 233 is connected to the interface circuit 25 of the storage control board 22 via hot-swapping, or directly to the interface circuit 25 of the storage control board 22 via hot-swapping, if the storage medium board 23 fails during the operation of the memory 122, the faulty storage medium board 23 can be directly replaced via hot-swapping without replacing the entire memory 122. When the memory 122 is used in a storage system, the maintenance cost of the storage system can be reduced.

[0125] The control circuit 232 is used to connect to the second hot-swap interface 233 and each storage medium 231 in the storage medium board 23. The control circuit 232 is also used to manage each storage medium 231 in the storage medium board 23. For example, the control circuit 232 manages a second-level FTL mapping table (such as FTL2) and accesses data in the storage space corresponding to the physical address in the storage medium board 23 based on the managed second mapping table.

[0126] Optionally, such as Figure 6 As shown, the control circuit 232 includes a front-end interface 2321, a back-end interface 2322, and a processor 2323. Both the front-end interface 2321 and the back-end interface 2322 are connected to the processor 2323. The processor 2323 communicates with the storage control board 22 through the front-end interface 2321, and communicates with each storage medium 231 in the storage medium board 23 through the back-end interface 2322.

[0127] The front-end interface 2321 is connected to the storage control board 22 via the second hot-swappable interface 233, enabling communication between the front-end interface 2321 and the storage control board 22. The front-end interface 2321, the second hot-swappable storage interface 233, and the first hot-swappable interface 222 in the storage control board 22 have the same interface type, allowing them to communicate. All three are ONFI, SERDES, or other types of interfaces.

[0128] The back-end interface 2322 is connected to each storage medium 231 in the storage medium board 23, so that the processor 2323 can access each storage medium 231 in the storage medium board 23 through the back-end interface 2322. The back-end interface 2322 can be an ONFI interface, a SERDES interface, or other types of interfaces supported by the storage medium 231. Here, the interface type of the back-end interface 2322 is not limited in this embodiment.

[0129] The implementation of processor 2323 is similar to that of control chip 223, and will not be described in detail here. Processor 2323 is the control center of its respective control circuit 232, used to manage the various storage media 231 connected to the back-end interface 2322. For example, it manages a secondary FTL mapping table (such as FTL2) and accesses data to the storage space corresponding to the physical address in the storage medium board 23 based on the managed secondary mapping table. In other words, processor 2323 has FTL functionality, which is used to manage the secondary mapping table.

[0130] Optionally, the processor 2323 can cache the second-level FTL mapping table in its internal cache, or store the second-level FTL mapping table on the connected storage medium 231 for persistent storage. Alternatively, as... Figure 4 As shown, each storage medium board 23 also includes at least one cache area 233, which is connected to the control circuit 232 in the storage medium board 23. The cache area 233 is used to provide data caching services for the connected control circuit 232. For example, the cache area 233 is used to store a secondary FTL mapping table. The cache area 233 is an internal storage medium board in the storage medium board 23 that directly exchanges data with the control circuit 232. The processor 2323 can store the secondary FTL mapping table in the cache area 233. When the amount of data in the secondary FTL mapping table reaches a certain threshold, the processor 2323 will then permanently store the secondary FTL mapping table in the cache area 233 to the storage medium 231. When the processor 2323 receives a write request, it can also temporarily store the data to be written carried by these write requests in the cache area 233. When the total amount of data in the cache area 233 reaches a certain threshold, the processor 2323 will then send the data stored in the cache area 233 to the storage medium 231 for persistent storage. Alternatively, when the total amount of data in the secondary FTL mapping table and the data to be written in the cache 233 reaches a certain threshold, the secondary FTL mapping table and the data to be written in the cache 233 are permanently stored in the storage medium 231.

[0131] By storing the secondary FTL mapping table in the cache area 233, the space occupied by the secondary FTL mapping table in the internal storage of the control circuit 232 can be reduced, and the control circuit 232 can quickly find the physical address to be accessed from the stored secondary FTL mapping table when performing data reading and writing, thereby improving the data reading and writing efficiency.

[0132] Optionally, buffer 233 can be configured to have a power-saving function. When buffer 233 has a power-saving function, data (such as secondary FTL mapping tables or data to be written) in buffer 233 can be prevented from being lost when the system sends a power failure.

[0133] Figure 4 This example uses cache 233 as an example of DDR, but it is not limited to DDR. Cache 233 can be any type of cache described above. Figure 4 This example illustrates that each storage medium 23 includes one cache area 233. However, the number of cache areas 233 in the storage medium 23 is not limited to one; it can be two or more. This embodiment of the application does not limit the number or type of cache areas 233 in the storage medium 23. Optionally, the storage medium 23 may also not include a cache area 233. This embodiment of the application does not limit whether the storage medium 23 includes a cache area 233.

[0134] It should be understood that, compared to a traditional SSD storage controller board, in this application, some functions of the FTL are offloaded to the control circuit 232 in the storage medium board 23, so that the control circuit 232 can manage the storage medium 231 in the storage medium board 23 by means of this part of the FTL function.

[0135] Optionally, the processor 2323 also has other functions for managing the storage medium besides the FTL function, such as low density parity-check codes (LDPC) function. Compared with the traditional SSD storage controller board, in this application, these functions are offloaded to the processor 2323 in the storage medium board 23. Optionally, the processor 2323 may not have these functions, and these functions are provided by the control chip 223 in the storage controller board 22. Here, this application embodiment does not limit whether the processor 2323 has these functions.

[0136] The various functions in the processor 2323 can be implemented by hardware, software, or a combination of both. This application does not limit the implementation method of these functions.

[0137] Figure 1 and Figure 2 The storage systems shown are illustrated with memory 122 remotely connected to computing nodes as an example. In other embodiments, memory 122 can also be directly plugged into a host for direct connection. The host can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, server, or any other suitable electronic device capable of connecting to memory 122.

[0138] For ease of description, both the computing nodes remotely connected to the memory 122 and the host directly connected to it are referred to as external devices connected to the memory 122, which are devices outside the memory 122.

[0139] During initialization, the storage control board 22 uniformly addresses the physical addresses of the storage media 231 in the memory 122 to the physical address space. Based on the physical address space, the storage control board 22 determines the logical address space to establish logical addresses. The storage control board 22 formats the storage space corresponding to this physical address space, thereby formatting the physical addresses in each storage medium 231 of the memory 122, making the storage space corresponding to each physical address empty, so that data can be written to the storage space corresponding to each physical address later.

[0140] When an application is installed and run on an external device connected to memory 122, the external device requests storage space for the application. The storage control board 22 within memory 122, based on this request, provides the external device with a logical address space or a logical address segment within that space, thus allocating storage space for the application. During the execution of the application, the external device reads and writes data to the storage medium 231 within memory 122 based on the logical address space or logical address segment provided by the storage control board 22.

[0141] For ease of description, the first-level FTL mapping table managed by the memory control board 22 in the memory 122 is referred to as the first mapping table, and the second-level FTL mapping table managed by the memory medium board 23 in the memory 122 is referred to as the second mapping table. Based on the memory 122, the first mapping table, and the second mapping table, this application provides an address management method. Next, in conjunction with... Figure 7 The method is described below. This method is applied to a memory, which includes a memory control board and multiple memory media boards connected to the memory control board. The memory, memory control board, and memory media boards can be the memory 122, memory control board 22, and memory media board 23 described above, respectively. The method includes the following steps.

[0142] 701. The storage control board manages the first mapping table, which describes the logical address range corresponding to each storage medium board in the memory.

[0143] The storage control board can manage the first mapping table in various ways. For example, in response to an access request from an external device, the storage control board manages the first mapping table while processing the access request. For instance, in response to a write access request, the storage control board manages the first mapping table while processing the access request. This implementation will be described later with reference to specific embodiments. The access request indicates data access to a target logical address, which is the logical address to be accessed in the access request. The access request carries the target logical address. The access request can be a read request or a write request. In the case of a write access request, the data access method includes writing data or reading data. Accordingly, the access request may be a write request or a read request. In the case of a write access request, the access request indicates writing data to the target logical address, and the access request also carries the data to be written. In the case of a read access request, the access request indicates reading data from the target logical address.

[0144] For example, the first mapping relationship in the first mapping table is fixed. During initialization, the storage control board allocates a logical address range to each first storage medium board and establishes a mapping relationship between each first storage medium board and the allocated logical address range in the first mapping table, as shown in Table 1, the first-level FTL mapping table. Subsequently, whenever the storage control board receives an access request, it looks up the storage medium board corresponding to the target logical address carried in the access request in the first mapping table and sends the access request to the storage medium board corresponding to the target logical address.

[0145] 702. Each storage medium board in the memory manages its own second mapping table, wherein each second mapping table describes the physical address corresponding to each logical address within the logical address range of its respective storage medium board.

[0146] Each storage medium board responds to an access request sent by the storage controller board and manages its own second mapping table during the processing of the access request. For example, each storage medium board responds to a write request sent by the storage controller board and manages its own second mapping table during the processing of the access request. This implementation will be described in detail later with reference to specific embodiments.

[0147] This method targets the storage controller board and multiple storage media boards in a memory. It splits the traditional FTL mapping table into a first mapping table and multiple second mapping tables. The first mapping table describes the logical address range corresponding to each storage media board, and each second mapping table describes the physical address corresponding to each logical address within the logical address range of a storage media board. The storage controller board manages the first mapping table, and each storage media board manages its own second mapping table. Compared to the traditional FTL mapping table, the first mapping table does not need to describe physical addresses. Therefore, the data volume of the first mapping table is smaller. Taking the memory as an SSD and the storage controller board as an SSD controller as an example, since the data volume of the first mapping table is smaller than that of the traditional FTL mapping table, the SSD controller replaces the traditional FTL mapping table with the first mapping table. When caching the first mapping table, the first mapping table occupies less cache space on the SSD controller.

[0148] In traditional SSDs, when a traditional SSD controller responds to an access request and accesses data based on a traditional FTL mapping table, it must first perform address translation on the logical address in the access request to convert it into a physical address. Then, it performs read and write operations on that physical address on the storage medium of the traditional SSD to achieve data access. Because the SSD controller not only needs to complete address translation but also needs to perform read and write operations on the storage medium during the above data access process, it cannot handle a large number of access requests concurrently, resulting in poor data access efficiency for the SSD.

[0149] Based on this, and in conjunction with the memory provided in this application, this application also provides a data access method. In this method, a storage control board in the memory responds to an access request and, based on a first mapping table, selects a target storage medium board from multiple storage medium boards to achieve data access. Next, in conjunction with... Figure 8 The process of this data access method will be introduced.

[0150] Figure 8 This is a flowchart of a data access method provided in an embodiment of this application, such as... Figure 8 As shown, the method is applied to a memory (such as memory 122), which includes a memory control board and a plurality of memory medium boards connected to the memory control board, and the method includes the following steps.

[0151] 801. The memory control board in the memory receives a first access request, which indicates data access to a first target logical address.

[0152] The memory can be any of the memory 122 described above, and the storage control board can be any storage control board 22 within the memory 122. The first access request is any access request received by the storage control board, and the first target logical address is the target logical address to be accessed by the first access request. The first access request carries the first target logical address. The first access request may be a write request or a read request. If the first access request is a write request, it also carries first data, which is the data to be written in this instance.

[0153] The first access request is generated by an external device. Assuming the external device is any computing node 110 remotely connected to the memory, the external device sends an access request to the memory via network 130. The network interface in the memory (e.g., network interface 21) receives the access request and forwards it to the storage control board in the memory. The storage control board receives the access request to obtain the first access request. In this case, the first access request is the access request received by the storage control board, and the first target logical address is the target logical address carried in the received access request. Alternatively, assuming the external device is a host directly connected to the memory (e.g., the memory is plugged into the host's motherboard via an M.2 interface), the host sends an access request to an interface in the memory (e.g., the M.2 interface). The interface forwards the access request to the storage control board in the memory, and the storage control board receives the access request to obtain the first access request. In this case, the first access request is the access request received by the storage control board, and the first target logical address is the target logical address carried in the received access request.

[0154] In some embodiments, this step 801 is performed by the control chip in the storage control board.

[0155] 802. In response to the first access request, the storage control board selects a first target storage medium board from multiple first storage medium boards based on the first mapping table, and sends the first access request to the first target storage medium board. The first mapping table describes the logical address range corresponding to each first storage medium board.

[0156] The first mapping table can be a first-level FTL mapping table managed by the storage control board. The plurality of first storage media boards are storage media boards (e.g., storage media board 23) in the memory where the storage control board is located. The storage media board to be accessed by the access request is called the target storage media board. The first target storage media board is the storage media board to be accessed by the first access request. The first target storage media board is the storage media board mapped to the first target logical address, and the storage media board where the physical address corresponding to the first target logical address is located.

[0157] The implementation of step 802 varies depending on the different methods of storage controller management. The following is just an example.

[0158] When the storage control board responds to an access request from an external device and manages the first mapping table during the process of processing the access request, the storage control board implements step 802 through the following steps A1 to A2. The storage control board implements the process of managing the first mapping table in response to a write request and during the process of processing the access request through the following steps A1 to A3.

[0159] Step A1: In response to the first access request being a write request, the storage control board allocates a first target storage medium board from among a plurality of first storage medium boards for the first access request.

[0160] If the first access request is a write request, when the first access request is received, the first mapping relationship between the first target logical address and the first target storage medium has not yet been established in the first mapping table. Therefore, the storage control board allocates the first target storage medium for the access request through step A1.

[0161] In this context, allocating a first target storage medium board for an access request means allocating a storage medium board for the first data carried by the first access request. The storage control board can allocate a storage medium board for the first data in various ways. For example, the storage control board can allocate a storage medium board for the first data from a pool of free storage medium boards. A free storage medium board refers to a storage medium board with available storage space, which is the storage space corresponding to a physical address that does not have a second mapping relationship with a logical address. The storage control board can allocate at least one free storage medium board for the first data. The total amount of data that can be stored in the free storage space of the allocated at least one free storage control board is greater than or equal to the amount of the first data. The at least one free storage control board allocated for the first data is the first target storage medium board. When multiple first target storage medium boards are allocated for the first data, the first data is divided into multiple parts, each part corresponding to a first target storage medium board. For any part of the data, a write request is generated based on the first target logical address and that part of the data. The storage control board then sends the write request to the corresponding first target storage medium board.

[0162] For example, suppose a storage control board stores data in stripes across multiple first storage media boards. For the first data to be written, the storage control board divides the first data into multiple data blocks, performs erasure coding (EC) calculations on these data blocks to obtain at least one parity block. The storage control board allocates stripes to the first data; each stripe includes multiple stripe units, and each stripe unit is a storage space on a storage media board used to store either a data block or a parity block. For any of the multiple data blocks or at least one parity block, the storage control board allocates a stripe unit from the multiple stripe units of the stripe, identifies the storage media board containing the allocated stripe unit as the first target storage media board, generates a write request based on the first target logical address, the block, and the identifier of the allocated stripe unit, and sends the write request to the first target storage media board.

[0163] Of course, if the amount of the first data is less than the amount of data that the stripe can store, the storage control board can also suspend the first access request and store the first data in the storage control board's cache (such as cache 24) to wait for other write requests. When the total amount of data to be written carried by multiple write requests is greater than or equal to the amount of data that the stripe can store, this step A1 will be executed for the data to be written carried by the multiple write requests.

[0164] Step A2: The storage control board sends a first access request to the first target storage medium board.

[0165] If a first target storage medium is allocated for the first access request, the storage control board executes step A2. If the first access request is a write request, there may be multiple first target storage mediums. The storage control board may generate multiple write requests based on the first data carried in the first access request and the first target logical address. Each of the multiple write requests carries a portion of the data to be written, and each write request corresponds to a first target storage medium. The storage control board then sends the corresponding write request to each first target storage medium.

[0166] After sending a first access request to the first target storage medium, the first target storage medium responds to the first access request as a write request, stores the first data carried in the first access request in the first target storage medium, and notifies the storage control board that the first data has been successfully written. Based on this notification, the storage control board performs the following step A3.

[0167] Step A3: The storage control board establishes a first mapping relationship between the first target logical address and the first target storage medium board in the first mapping table.

[0168] The storage controller adds a new entry to the first mapping table, which includes the first target logical address and the identifier of the storage medium board allocated for the data to be written.

[0169] When the storage control board responds to an access request from an external device and manages the first mapping table during the processing of that access request, if the first access request is a read request, a first mapping relationship between the first target logical address and the first target storage medium board has already been established in the first mapping table upon receiving the first access request. Based on this, as follows: Figure 10 As shown, step 802 can be achieved through the following steps B1 and B2.

[0170] Step B1: In response to the first access request being a read request, the storage control board queries the storage medium board corresponding to the first target logical address based on the first mapping table.

[0171] For example, the storage control board queries the first mapping table for entries that include the first target logical address. If any entry in the first mapping table includes the first target logical address, the storage medium board indicated by the identifier of the storage medium board in that entry is determined as the first target storage medium board.

[0172] Step B2: The storage control board sends a first access request to the storage medium board corresponding to the first target logical address, so that the storage medium board can read data based on the first access request.

[0173] When the storage control board manages the first mapping table during the initialization process, the first mapping relationship in the first mapping table is fixed. This step 802 is implemented through the following steps C1 and C2.

[0174] Step C1: In response to the first access request, the storage control board queries the storage medium board corresponding to the first target logical address based on the first mapping table, wherein the storage medium board corresponding to the first target logical address is the first target storage medium board.

[0175] For example, the storage control board queries the first mapping table for entries that include the first target logical address. If any entry in the first mapping table includes the first target logical address, the storage medium board indicated by the identifier of the storage medium board in that entry is determined as the first target storage medium board.

[0176] Step C2: The storage control board sends a first access request to the storage medium board corresponding to the first target logical address, so that the storage medium board can read data based on the first access request.

[0177] In steps C1 and C2 above, the first access request may be a write request or a read request. Here, this embodiment of the application does not limit the request type of the first access request.

[0178] In some embodiments, this step 802 is performed by the control chip in the storage control board.

[0179] 803. In response to the first access request sent by the storage control board, the first target storage medium board accesses the storage space corresponding to the physical address in the first target storage medium board based on the managed second mapping table.

[0180] The second mapping table can be a secondary FTL mapping table managed by the first target storage medium board.

[0181] like Figure 9 and Figure 10 As shown, step 803 includes steps D1 to D4 as described below.

[0182] Step D1: The first target storage medium receives the first access request.

[0183] The first access request is an access request sent by the storage control board.

[0184] Step D2: In response to the first access request being a write request, the first target storage medium board allocates a target physical address for the first data carried by the first access request from the physical address in at least one storage medium within the first target storage medium board, writes the first data to the storage space corresponding to the target physical address, establishes a second mapping relationship between the first target logical address and the target physical address in the managed second mapping table, and executes the following step D4.

[0185] When the first access request is a write request, the second mapping table managed by the first target storage medium has not yet established a mapping relationship between the first target logical address and the target physical address. Therefore, the first target storage medium first allocates a physical address for the first data from the physical addresses in the storage medium within the first target storage medium. For example, any unused physical address in the physical address space of the first target storage medium is allocated to the first data; the allocated physical address is the target physical address. Here, any unused physical address is a physical address that does not have a second mapping relationship with the logical address.

[0186] After allocating a target physical address for the first data, the first data is written to the storage space corresponding to the target physical address in the storage medium of the first target storage control board. Upon successful writing of the first data, a second mapping relationship between the first target logical address and the target physical address is established in the managed second mapping table. For example, a new entry is added to the second mapping table, which includes both the first target logical address and the target physical address. If the first data writing fails, the step of establishing the second mapping relationship between the first target logical address and the target physical address in the managed second mapping table is not executed.

[0187] It should be understood that steps D1 and D2 above are one possible implementation of step 702 above.

[0188] Step D3: In response to the first access request being a read request, the first target storage medium board queries the target physical address corresponding to the first target logical address based on the managed second mapping table, reads the data stored in the storage space corresponding to the target physical address, and executes the following step D4.

[0189] When the first access request is a read request, a second mapping relationship between the first target logical address and the target physical address has already been established in the second mapping table. Based on this, the first target storage medium queries the target physical address mapped to the first target logical address in the second mapping table. For example, it queries the second mapping table for entries that include the first target logical address. If any entry in the second mapping table includes the first target logical address, the physical address in that entry is determined as the target physical address. The data stored in the storage space corresponding to the target physical address is then read.

[0190] Step D4: The first target storage medium board sends a first access response to the storage control board. The first access response is the access result of the physical address corresponding to the first target logical address.

[0191] When the first access request is a write request, the first access response is a write response, indicating whether data was successfully written to the first target logical address. When the first access request is a read request, the first access response is a read response, indicating whether data was successfully read from the physical address corresponding to the first target logical address. If successfully read, the first access response includes the data read from the physical address corresponding to the first target logical address.

[0192] The storage control board receives a first access response. Upon receiving the first access response, it outputs the first access response to an external device, which is any external device that sent the first access request to the storage. Additionally, as... Figure 9As shown, if the first access response is a write response, the storage control board responds to the first access response indicating that data has been successfully written to the first target logical address, and the storage control board also executes step A3.

[0193] In some embodiments, step 803 may be performed by a control circuit in the first target storage medium board.

[0194] To further understand the above data access process, Figure 11 For example, during the initialization process, the FTL function in the memory control board assigns an identifier to each storage medium board in the memory to establish the first-level logical address (i.e., the identifier of the storage medium board is the first-level logical address) and formats the physical addresses in each storage medium board in the memory. After receiving an access request, the system parses the request to determine whether it is a write or read request. If it is a write request, the storage controller obtains the logical address carried in the access request as the target logical address that the host needs to write to. It receives the host data (i.e., the data to be written) carried in the write request, performs EC calculation on the host data, and obtains data blocks and parity blocks (e.g., 20 data blocks and 2 parity blocks). It allocates storage media boards to each data block and parity block. In the first-level FTL mapping table, it establishes a mapping relationship between the target logical address on the host side and the first-level logical address of the allocated storage media board to ensure that different blocks are mapped to different storage media boards. According to the mapping relationship between the target logical address and the first-level logical address, it sends each block and the target logical address to the corresponding storage media board. After receiving the block, the storage media board allocates an unused physical address for the block and establishes a mapping relationship between the target logical address and the allocated physical address in the second-level FTL mapping table. The target logical address is equivalent to the second-level logical address. The storage medium board writes data in blocks to the corresponding physical addresses. Once the data writing is complete, it returns a write access response to indicate successful writing. When the access request is a read request, the storage controller board obtains the target logical address that the host needs to read from the logical address carried in the access request. It then looks up the storage medium board identifier corresponding to the target logical address in the first-level FTL mapping table, obtains this identifier as the second-level logical address, and sends a read request to the corresponding storage medium board based on the found second-level logical address. After receiving the read request, the storage medium board looks up the physical address corresponding to the target logical address in the second-level FTL mapping table, returns the read data based on the physical address, and returns a success message, indicating the data reading is complete.

[0195] The method provided in this application offloads a portion of the physical address access capability of the memory's storage control board to the storage media board. For an access request to be processed, the storage control board only needs to determine the target storage media board from the memory's storage media boards based on the logical address range of each storage media board, without needing to determine the specific physical address corresponding to the access request. Taking an SSD as the memory and an SSD controller as the storage control board as an example, compared to the traditional SSD controller determining the physical address to be accessed based on the traditional FTL mapping, this method reduces the computing power of the SSD controller, enabling it to concurrently process more access requests, thereby improving the SSD's data read and write efficiency. Furthermore, the SSD controller does not need to maintain a large FTL mapping table; it only needs to maintain a mapping table between address ranges and memory (a first mapping table), distributing the mapping table between address ranges and physical addresses (a second mapping table) among the various memory systems for separate maintenance, reducing the pressure of maintaining a large FTL mapping table for each access request.

[0196] The above describes the structure of the memory and the data access process within it, using the example of a memory 122 including a memory control board 22. In other embodiments, the memory 122 includes multiple memory control boards 22, which will be discussed later. Figure 12 and Figure 13 The structure of this type of memory will be introduced.

[0197] Figure 12 This is a schematic diagram of another memory structure provided in an embodiment of this application, such as... Figure 12 As shown, the memory 122 includes multiple memory control boards 22 and multiple memory media boards 23, with the multiple memory control boards 22 connected to each memory media board 23. Figure 12 The memory 122 shown is Figure 4 The difference between the memory 122 shown is that, Figure 12 The memory 122 shown includes two memory control boards 22. Figure 12 Each storage medium board 23 in the memory 122 shown includes multiple second hot-swappable interfaces 233, and the control circuitry 232 in each storage medium board 23 includes multiple front-end interfaces 2321, such as... Figure 13As shown, each second hot-swappable interface 233 corresponds to a storage control board 22 and a front-end interface 2321. Each second hot-swappable interface 233 is connected to the corresponding storage control board 22 and the corresponding front-end interface 2321, so that each second hot-swappable interface 233, the corresponding storage control board 22, and the corresponding front-end interface 2321 form a communication link, enabling the control chip 233 in the corresponding storage control board 22 to communicate with the processor 2323 through this communication link. The connection method between each second hot-swappable interface 233 and the storage control board 22 has been described above and will not be repeated here. Figure 12 The internal structure and connection method of other components in the memory 122 shown are similar to those in the memory 122. Figure 4 The memory 122 shown is similar, and can be specifically described as follows: Figure 13 As shown, it will not be elaborated further here.

[0198] For any storage control board 22 in the memory 122, the storage control board 22 may have control over all storage media boards 23 in the memory 122, or it may have control over some of the storage media boards 23 in the memory 122. The storage media boards recorded in the first-level FTL mapping table managed by the storage control board 22 are the storage media boards 23 that the storage control board 22 has control over. That is, when the storage control board 22 has control over any storage media board 23, the first mapping relationship between this storage media board 23 and its logical address is recorded in the first-level FTL mapping table of the storage control board 22.

[0199] for Figure 3 and Figure 12 In any of the memory types 122 involved, each memory control board 22 in the memory 122 can communicate with each memory medium board 23 in the memory 122. Based on this, for any memory control board 22 of the memory 122, control permissions for memory medium boards 23 can be configured in any memory control board 22. When the memory control board 22 has control permissions for at least one memory medium board 23, the memory control board 22 manages the storage media in the at least one memory medium board 23. For example, the memory control board 22 records the mapping address corresponding to the at least one memory medium board 23 through a first-level FTL mapping table, and performs data access on the storage media in the at least one memory medium board 23 based on the first-level FTL mapping table.

[0200] For example, when the memory 122 includes a memory control board 22, the memory control board 22 is configured with control permissions for each memory medium board 23 in the memory 122, so that the memory control board 22 can control each memory medium board 23 in the memory 122. At this time, the first-level FTL mapping table managed by the memory control board 22 records the first mapping relationship between logical addresses and each memory medium board 23 in the memory 122.

[0201] When the memory 122 includes multiple memory control boards 22, each memory control board 22 can be configured with control permissions for each memory medium board 23 in the memory, so that each memory control board 22 controls each memory medium board 23 in the memory. In this case, the first-level FTL mapping table managed by each memory control board 22 records the first mapping relationship between logical addresses and each memory medium board 23 in the memory. Alternatively, each memory control board 22 can be configured with control permissions for at least one memory medium board 23 in the memory 122, and each memory control board 22 controls the configured at least one memory medium board 23. For example, a memory includes memory control board 1, memory control board 2, and memory medium boards 1-6. Memory control board 1 has control permissions for memory medium boards 1-3, and memory control board 2 has control permissions for memory medium boards 4-6. Memory control board 1 manages memory medium boards 1-3, and memory control board 2 manages memory medium boards 4-6. In this case, the first-level FTL mapping table in each memory control board 22 is used to record the first mapping relationship between logical addresses and the configured at least one memory medium board 23.

[0202] For ease of description, any one of the multiple storage control boards 22 in the memory 122 is referred to as the first storage control board, and any other storage control board 22 in the memory 122 besides the first storage control board is referred to as the second storage control board.

[0203] Optionally, the first storage control board can be configured as a backup storage control board for the second storage control board. In the event of a failure of the second storage control board, the second storage control board can take over the control of each storage medium board 23 in the memory 122 and manage each storage medium board 23.

[0204] by Figure 14For example, assuming that storage control board 141, storage control board 142, and multiple storage media boards 143 are located in the same memory, storage control board 141 and storage control board 142 are the second storage control board and the first storage control board, respectively. Each storage media board 143 has two second hot-swappable interfaces (i.e., dual ports), and each storage media board 143 communicates with storage control board 141 and storage control board 142 through these two second hot-swappable interfaces. Initially, storage control board 142 serves as a backup storage control board for storage control board 141. Storage control board 141 has control over each storage media board 143. When storage control board 141 is functioning correctly, it manages each storage media board 143, while storage control board 142 either does not operate or distributes workload evenly. When storage control board 141 fails, storage control board 142 takes over the control over each storage media board 143 and manages it. After the storage control board 141 recovers from the fault, it can regain control of each storage medium board 143 and manage each storage medium board 143. Alternatively, it can take over control of each storage medium board 143 and manage each storage medium board 143 after the storage control board 142 fails.

[0205] In memory 122, the second memory control board acts as the main memory control board, managing a first-level FTL mapping table. This table stores the first mapping relationship between logical addresses and multiple memory media boards 23 within memory 122. The first memory control board retrieves this first-level FTL mapping table from the second memory control board. In response to an access request, based on the retrieved first mapping table, it selects a target memory media board from the multiple first memory media boards to access the data.

[0206] Furthermore, if the second storage control board recovers from a failure while the first storage control board is managing the storage medium board 23, the second storage control board can immediately regain control of the first storage control board and manage the storage medium board 23 in the memory 122 to avoid excessive consumption of the first storage control board's computing power. Alternatively, after the first storage control board fails, the second storage control board can regain control of the first storage control board and manage the storage medium board 23 in the memory 122.

[0207] Alternatively, the second storage control board can be configured as a backup storage control board for the first storage control board. In this case, the second storage control board and the first storage control board serve as backup storage control boards for each other. If either the first storage control board or the second storage control board fails, the other storage control board will manage the various storage media boards 23 in the memory 122.

[0208] Next, combined Figure 15 The flowchart of another data access method provided in the embodiments of this application introduces the process of the second storage control board synchronizing a first mapping table to the first storage control board, and the first storage control board accessing data on the storage medium in the storage medium board based on the synchronized first mapping table.

[0209] 1501. The second storage control board in the memory synchronizes the first mapping table with the first storage control board. The first mapping table describes the logical address range corresponding to each first storage medium board.

[0210] The first storage control board and the second storage control board are located in the same memory, the plurality of first storage medium boards are storage medium boards in the memory, and the first mapping table is the first-level FTL mapping table of the memory.

[0211] by Figure 14 For example, assuming that storage control board 141, storage control board 142 and multiple storage media boards 143 are located in the same memory, storage control board 142 is the first storage control board, storage control board 141 is the second storage control board, and each storage media board 143 is the first storage media board.

[0212] The second storage control board records the logical address range of each first storage medium board through the first mapping table. The second storage control board can synchronize the first mapping table it manages with the backup storage control board (i.e., the first storage control board) to realize the synchronization of the first mapping table with the backup storage control board.

[0213] by Figure 16 For example, assume that LA0-LA15 in the logical address space are mapped to the physical address space provided by storage media boards 1-4, and the physical address space provided by each storage media board 1-4 includes PA0-PA3. Storage control board 161 has control over storage media boards 1 and 2, and storage control board 162 has control over storage media boards 3 and 4. Storage control board 161 records the first mapping relationship between LA0-LA7 and storage media boards 1-2 through a first mapping table (i.e., a first-level FTL mapping table) 163, and storage control board 162 records the first mapping relationship between LA8-LA15 and storage media boards 3-4 through a first mapping table 164. For example, the first mapping table 163 and the first mapping table 164 are shown in Tables 3 and 4 below, respectively.

[0214] Table 3

[0215] Logical address Identification of storage media boards LA0-LA3 Storage media board 1 LA4-LA7 Storage media board 2

[0216] Table 4

[0217] Logical address Identification of storage media boards LA8-LA11 Storage media board 3 LA12-LA15 Storage media board 4

[0218] Each storage medium board in storage medium boards 1-4 records a second mapping relationship between its corresponding LA (logic address) and its respective PA (physical address) in its physical address space through a second mapping table 165. For example, each second mapping table 165 can be as shown in Table 2 above.

[0219] If storage control board 162 is the first storage control board, then storage control board 161 synchronizes the first mapping table 163 to storage control board 162. Storage control board 162 uses the first-level FTL mapping table 163 synchronized by storage control board 161 as a backup table for the first mapping table 163. If storage control board 161 fails, storage control board 162 can access the physical addresses in storage media boards 1-2 through the backup table to control and manage storage media boards 1-2. If storage control board 161 is the first storage control board, then storage control board 162 synchronizes the first mapping table 164 to storage control board 161. Storage control board 161 uses the first mapping table 164 synchronized by storage control board 162 as a backup table for the first mapping table 164. If storage control board 162 fails, storage control board 161 can access the physical addresses in storage media boards 3-4 through the backup table to control and manage storage media boards 3-4.

[0220] The second storage control board synchronizes the first mapping table managed by the second storage medium board to the first storage control board. The first storage control board receives the synchronized first mapping table from the second storage control board, thus enabling the first storage control board to access the first mapping table managed by the second storage control board. After receiving the synchronized first mapping table, the first storage control board stores the first mapping table, for example, through its cache. The first storage control board can also associate the first mapping table with the identifier of the second storage control board to indicate that the first mapping table is a backup table of the second storage control board.

[0221] The second storage control board can periodically synchronize the first mapping table with the first storage control board, for example, by synchronizing the first mapping table with the first storage control board after a certain period of time. Alternatively, it can synchronize the first mapping table with the first storage control board when there is an update to the first mapping table managed by the second storage control board. Updates to the first mapping table include an increase or decrease in the number of first mapping relationships, or a change in the logical address or storage medium board identifier in the first mapping relationship.

[0222] Step 1501 is an optional step. In some embodiments, it is not necessary for the second storage control board to synchronize the first mapping table with the first storage control board. Alternatively, the first mapping table managed by the second storage control board can be configured manually or by other devices on the first storage control board. In some embodiments, step 1501 is performed by the control chip in the second storage control board.

[0223] 1502. If the second storage control board fails, the first storage control board responds to the first access request by selecting a first target storage medium board from multiple first storage medium boards based on the first mapping table and sending a first access request to the first target storage medium board.

[0224] Taking an access request originating from an external device as an example, the memory also includes a distributor. The distributor distributes the access request sent by the external device. The distributor can be a network interface in the memory or a network interface card (NIC) containing the network interface. Upon receiving the first access request, the distributor checks if the second storage control board is faulty. If the second storage control board is faulty, the distributor sends the first access request to the first storage control board. The first storage control board responds to the first access request by selecting a first target storage medium board from multiple first storage medium boards based on a first mapping table and sending the first access request to the first target storage medium board. If the second storage control board is not faulty, the distributor sends the first access request to the second storage control board, so that the second storage control board responds to the first access request by selecting a first target storage medium board from multiple first storage medium boards based on the first mapping table and sending the first access request to the first target storage medium board.

[0225] In other embodiments, the first storage control board is used to provide load balancing services for the second storage control board. When the second storage control board is not faulty, the first storage control board can also obtain a first access request. In response to the first access request, based on the first mapping table, the first target storage medium board is selected from multiple first storage medium boards to access data, so as to share the load of the second storage control board.

[0226] Specifically, for any one of the first storage control board and the second storage control board, in response to the first access request, the storage control board selects a first target storage medium board from a plurality of first storage medium boards based on the first mapping table, and sends the first access request to the first target storage medium board. The process can be referred to step 802 above, and will not be repeated here.

[0227] In some embodiments, this step 1502 is performed by a control chip in the first storage control board.

[0228] 1503. In response to the first access request sent by the first storage control board, the first target storage medium board accesses the storage space corresponding to the physical address in the first target storage medium board based on the managed second mapping table.

[0229] Step 1503 is similar to step 803 described above, and will not be repeated here. In some embodiments, step 1503 is executed by a control circuit in the first target storage medium.

[0230] The method provided in this application embodiment, in addition to being able to achieve Figure 8 In addition to the beneficial effects of the illustrated method embodiment, the logical address range of each storage medium board managed by the storage control board is synchronized with the backup storage control board. This allows the backup storage control board to access data on the storage medium boards managed by the storage control board in the event of a failure of the storage control board, based on the synchronized logical address range of each storage medium board. External devices do not need to wait for the storage control board to recover, thus improving the efficiency of external devices accessing the storage medium boards. Furthermore, in the event of a failure of a single storage control board in the memory, the backup storage control board manages the storage medium boards in the memory without affecting the operation of the memory.

[0231] In other embodiments, any two memories provided in this application can communicate, and the memory control board in one memory can be a backup controller for the memory control board in the other memory. For ease of description, these two memories are referred to as the first memory and the second memory, respectively. Any memory control board in the first memory is referred to as the first memory control board, and the memory medium board in the first memory is referred to as the first memory medium board. The first memory may or may not include a second memory control board. Any memory control board in the second memory is referred to as the third memory control board, and the memory medium board in the second memory is referred to as the second memory medium board.

[0232] The second memory and the first memory are connected via a bus, enabling components in the first memory to communicate with components in the second memory, thus realizing communication connections between different components in the second memory and the first memory. For example, the network interfaces of both the first and second memories are connected to the same bus. Since these two network interfaces are each connected to a connector of their respective memory, and the connectors of each memory are connected to various storage control boards within that memory, the connectors and network interfaces of the second memory, the bus, and the network interfaces and connectors of the first memory together form a communication link between the third and first storage control boards. Through this communication link, the first and third storage control boards can communicate, and the first and second storage media boards can communicate.

[0233] The first storage control board is configured as a backup storage control board for the third storage control board. This allows the first storage control board to take over control of the second storage media boards in the second memory in the event of a failure of the third storage control board, and to manage these second storage media boards. For example, the first storage control board can access a first mapping table managed by the third storage control board, which describes the logical address range of each second storage media board in the second memory, and then perform data access on multiple second storage media boards in the second memory.

[0234] by Figure 17 For example, memory 171 and memory 172 are communicatively connected. Memory 171 and memory 172 are the first memory and the second memory, respectively. Storage control board 1711 and storage control board 1721 are the first storage control board and the third storage control board, respectively. Each storage medium board 1712 in memory 171 is the first storage medium board, and each storage medium board 1722 in memory 172 is the second storage medium board.

[0235] Because the different components in the second memory and the first memory are interconnected, when the third storage control board has control over the second storage medium board, if the third storage control board is not faulty, it will manage the second storage medium board. If the third storage control board fails, the first storage control board can take over control of the second storage medium board while managing the first storage medium board, and manage the second storage medium board. After the fault of the third storage control board is resolved, the third storage control board will take over control of the second storage medium board again and manage the second storage medium board to prevent the second storage medium board from consuming too much computing power of the first storage control board and affecting the control efficiency of the first storage medium board.

[0236] In other embodiments, the third storage control board can be configured as a backup storage control board for the first storage control board. The third and first storage control boards serve as backups for each other. If the first storage control board fails, the third storage control board can take over control of the first storage medium board and manage it. Subsequently, after the first storage control board recovers, the first storage control board regains control of the first storage medium board and manages it again, preventing the first storage medium board from excessively consuming the computing power of the third storage control board and affecting the control efficiency of the second storage medium board. In this application, managing the storage medium board refers to managing the storage media within the storage medium board.

[0237] Still with Figure 17For example, storage control board 1711 has control over each storage medium board 1712, and storage control board 1721 has control over each storage medium board 1722. Storage control board 1711 and storage control board 1721 serve as backup storage control boards for each other. When either storage control board 1711 or storage control board 1721 fails, the other storage control board takes over the control of the other and manages each storage medium board 1712 and each storage medium board 1722.

[0238] Next, combined Figure 18 The flowchart shown in this application embodiment illustrates another data access method provided, describing the process of a first storage control board accessing data from a storage medium in a second storage medium board.

[0239] 1801. The third storage control board in the second memory synchronizes the third mapping table with the first storage control board in the first memory. The third mapping table describes the logical address range corresponding to each second storage medium board.

[0240] The third storage control board and the second storage medium board are located in the second memory. The first storage control board and the first storage medium board are located in the first memory. The third mapping table is the first mapping table managed by the third storage control board.

[0241] by Figure 16 For example, assuming storage control board 161 is the third storage control board, storage media board 1 and storage media board 2 are the second storage media boards, storage control board 162 is the first storage control board, and storage media board 3 and storage media board 4 are the first storage media boards, storage control board 161 synchronizes the first mapping table 163 to storage control board 102. At this time, the first mapping table 163 is the third mapping table. Assuming storage control board 162 is the third storage control board and storage control board 161 is the first storage control board, then storage media board 3 and storage media board 4 are the second storage media boards, and storage media board 1 and storage media board 2 are the first storage media boards. Storage control board 162 synchronizes the first mapping table 164 to storage control board 161. At this time, the first mapping table 164 is the third mapping table.

[0242] The third storage control board sends a third mapping table to the first storage control board in the first memory via the bus between the first and second memories. The third mapping table is then sent to the first storage control board in the first memory, allowing the first storage control board to access the third mapping table managed by the third storage control board. After receiving the synchronized third mapping table, the first storage control board stores it, for example, through its cache. The first storage control board also associates the third mapping table with its own identifier to indicate that it is a backup table for the third storage control board.

[0243] Step 1801 is an optional step. In some embodiments, it is not necessary for the third storage control board to synchronize the third mapping table with the first storage control board. Alternatively, the third mapping table managed by the third storage control board can be configured manually or by other devices in the first storage control board. In some embodiments, step 1801 is performed by the control chip in the third storage control board.

[0244] 1802. If the third storage control board fails, the first storage control board responds to the second access request by selecting a second target storage medium board from multiple second storage medium boards based on the third mapping table and sending a second access request to the second target storage medium board.

[0245] The second access request indicates data access to a second target logical address. The second target logical address is the logical address to be accessed in the second access request, and the second access request carries the second target logical address. The second target storage medium is the second storage medium to be accessed by the second access request, that is, the second storage medium where the physical address corresponding to the second target logical address is located. The second access request may be a write request or a read request. If the second access request is a write request, it indicates writing data to the second target logical address, and in this case, the second access request also carries the data to be written (referred to as the second data). If the second access request is a read request, it indicates reading data from the second target logical address.

[0246] Taking the second access request generated by an external device as an example, assuming the external device is a computing node, the bus between the first memory and the second memory is also connected to a control device, which is used to distribute the access requests sent by the computing node. After receiving an access request from a computing node, the control device determines the second memory as the memory to be accessed based on the identifier of the second memory carried in the access request. It then checks whether the third storage control board in the second memory is faulty. If the third storage control board is faulty, the control device sends an access request to the first memory. The first storage control board in the first memory receives the access request, identifies it as a second access request based on the identifier of the second memory carried in the access request, and, in response to the second access request, selects a second target storage medium board from multiple second storage medium boards based on a third mapping table, and sends a second access request to the second target storage medium board. If the third storage control board is not faulty, the control device sends the access request to the second memory. The second storage control board in the second storage control device receives the access request, identifies it as a second access request based on the identifier of the second memory carried in the access request, and, in response to the second access request, selects a second target storage medium board from multiple second storage medium boards based on the third mapping table, and sends a second access request to the second target storage medium board. Assuming the external device is a host or computing node connected to the second memory, the external device generates an access request carrying the identifier of the second memory and checks whether the third storage control board in the second memory is faulty. If the third storage control board is faulty, the external device sends an access request to the first memory. The first storage control board in the first memory receives the access request, identifies the access request as a second access request based on the identifier of the second memory carried in the access request, and in response to the second access request, selects a second target storage medium board from multiple second storage medium boards based on a third mapping table, and sends a second access request to the second target storage medium board. If the third storage control board is not faulty, the external device sends an access request to the second memory, the second storage control board in the second memory receives the access request, identifies the access request as a second access request based on the identifier of the second memory carried in the access request, and in response to the second access request, selects a second target storage medium board from multiple second storage medium boards based on a third mapping table, and sends a second access request to the second target storage medium board.

[0247] In other embodiments, the first storage control board is used to provide load balancing services for the third storage control board. When the third storage control board is not faulty, the first storage control board can also obtain a second access request. In response to the second access request, based on the third mapping table, the first storage control board selects a second target storage medium board from the plurality of second storage medium boards to access data, so as to share the load of the third storage control board.

[0248] For any of the first and second storage control boards, in response to the second access request, the storage control board selects a second target storage medium board from a plurality of second storage medium boards based on the third mapping table, and sends the second access request to the second target storage medium board. The process can be referred to step 802 above, and will not be repeated here.

[0249] In some embodiments, this step 1802 is performed by a control chip in the first storage control board.

[0250] 1803. In response to the second access request, the second target storage medium board performs data access on the storage space corresponding to the physical address in the second target storage medium board based on the managed second mapping table.

[0251] For example, the second target storage medium receives the second access request and, in response to the second access request, performs data access on the storage space corresponding to the physical address in the second target storage medium based on the second mapping table. This process is the same as the process shown in steps D1 to D4 above. Here, this application embodiment will not describe this process again.

[0252] In some embodiments, this step 1803 is performed by a control circuit in the second target storage medium board.

[0253] The method provided in this application embodiment, in addition to being able to achieve Figure 8 In addition to the beneficial effects of the method embodiment shown, the logical address range of each storage medium board in the second memory is synchronized from the third storage control board in the second memory to the first storage control board in the first memory. This allows the first storage control board to access data on the second storage medium board in the second memory based on the synchronized logical address range of each storage medium board in the second memory in the event of a failure of the third storage control board. This eliminates the need for external devices to wait for the third storage control board to recover from the failure, thus improving the efficiency of external devices accessing the storage medium board.

[0254] Based on the memory and storage system described above, embodiments of this application provide a data reconstruction method, combined with... Figure 19 This method will be introduced.

[0255] Figure 19 This is a flowchart of a data reconstruction method provided in an embodiment of this application. The method is applied to any of the memory described above. The method is applied to a memory (such as memory 122). The memory includes a memory control board and a plurality of memory medium boards. Each memory medium board includes at least one memory medium. The method includes the following steps.

[0256] 1901. The memory control board in the memory performs fault detection on multiple memory media boards.

[0257] The smallest area in memory that requires data reconstruction in the event of a single point of failure is called the fault domain. A single point of failure is a failure of a component in the memory, such as a failure in the control circuitry or the memory control board. The fault domain is not a region in the memory that is already faulty, but rather the smallest area in memory that requires data reconstruction in the event of a single point of failure.

[0258] The storage medium board can be used as a fault domain within the memory. Figure 14 For example, assuming the storage control board is either storage control board 141 or storage control board 142, and each storage medium board 143 represents a fault domain. Then... Figure 17 For example, the storage control board can be either storage control board 1711 or storage control board 1721, and each storage medium board 1712 and 1722 is an independent fault domain.

[0259] In the case where the storage media board is the fault domain, the storage control board detects faults in multiple storage media boards through heartbeat communication, so as to reconstruct the data of the faulty storage media board (as in step 1902 below).

[0260] 1902. If a fault is detected in any of the multiple storage media boards, the storage control board reconstructs the data stored in the storage medium of that storage media board.

[0261] The memory used in the storage system, where the storage control board is located, is applied (e.g.) Figure 1 or Figure 2 In the case of the storage system shown, each memory in the storage system stores data in the form of stripes. Assuming that the data blocks and parity blocks in the stripes are distributed in different storage media boards in different memory boards, when any storage media board fails, for any block (data block or parity block) stored in the storage medium of that storage media board, the storage control board obtains other blocks in the stripe where the block is located in the storage system, and reconstructs the data in the block based on the other blocks in the stripe to recover the block.

[0262] The storage control board can also store the various blocks of the recovered faulty storage media board into other fault-free storage media boards in the storage system for subsequent access by computing nodes. These other fault-free storage media boards can be located in the memory where the storage control board is located, or in other memory outside the memory where the storage control board is located. This application embodiment does not limit the location of the other fault-free storage media boards.

[0263] The above description uses the example of a storage control board reconstructing data on a faulty storage medium board among multiple storage medium boards. If the storage control board has a backup storage control board (such as the first storage control board), and that storage control board fails, the backup storage control board will reconstruct data on the faulty storage medium board among the multiple storage medium boards by executing the above steps 1901 and 1902.

[0264] For example, the backup storage control board will detect whether the first storage control board is faulty, for example, by using heartbeat detection. If the storage control board is detected to be faulty, the backup storage control board will take over the control of the multiple storage media boards and perform data reconstruction on the faulty storage media board by executing the above steps 1901 and 1902.

[0265] by Figure 14 For example, storage control board 141 and storage control board 142 are each other's backup storage control boards. Initially, either storage control board 141 or storage control board 142 is the primary storage control board, and the other storage control board 141 or storage control board 142 is the backup storage control board. During the process of the primary storage control board managing multiple storage media boards 143, if the backup storage control board detects a failure of the primary storage control board, the backup storage control board takes over the control of the multiple storage media boards 143, making the original primary storage control board the backup storage control board and the original backup storage control board the new primary storage control board. The new primary storage control board manages the multiple storage media boards 143 in ways such as fault detection of the multiple storage media boards 143, data reconstruction of the faulty storage media board 143, and data access to the storage media in the storage media board 143.

[0266] The method provided in this application uses the storage media boards in the memory as the fault domain. It performs individual fault tests on each storage media board within the memory through a storage control board, and reconstructs the data on the faulty storage media board. This eliminates the need to reconstruct the data on all storage media in the memory, reducing the amount of data to be reconstructed and improving the efficiency of data reconstruction. In traditional SSD applications in storage systems, if the NAND chip in a traditional SSD fails, the software in the computing node controls the traditional SSD storage control board to reconstruct the data on the NAND chip. This requires upper-layer software support for data reconstruction, which may not be supported in general software ecosystems, limiting the applicability of traditional SSDs. However, the storage control board in this application can reconstruct the data on the storage media boards in its memory without the need for upper-layer software support, enabling the memory to be used in general software ecosystems and broadening its applicability. The storage capacity of the memory provided in this application is far greater than that of traditional SSDs. For example, the storage capacity of the memory provided in this application can reach the petabyte (PB) level or higher. Through the method provided in the embodiments of this application, the memory provided in this application can support data reconstruction at the petabyte level or higher. Furthermore, the embodiments of this application use the storage medium board as the fault domain, rather than the entire memory as the fault domain. According to calculations, the single point of failure of the memory provided in this application is 10% of that when the entire memory is used as the fault domain. Compared with traditional SSDs, the fault domain in the memory provided in this application can be reduced by more than 90%. In data reconstruction scenarios, the data reconstruction efficiency of the memory provided in this application will be higher. Moreover, in the event of a failure of a storage medium board in the memory provided in this application, the storage control board can reconstruct the data on the failed storage medium board. Other unfailed storage medium boards in the memory can still be accessed normally, without affecting the operation of the entire memory.

[0267] When traditional SSDs are used in storage systems, a failure in a traditional SSD renders the entire SSD unusable. Therefore, reconstructing the data stored in all NAND chips within the entire SSD, treating the entire SSD as the fault domain, is a data reconstruction process. Furthermore, as the SSD capacity increases, the amount of data reconstructed increases linearly with the single-chip storage capacity, severely reducing the availability of the storage system. In this embodiment, a backup storage control board is provided for the storage control board in the memory. In the event of a storage control board failure, the system switches to the backup storage control board to manage the storage media boards in the memory. This enables second-level switching without data reconstruction, avoiding the linear increase in reconstructed data with single-chip storage capacity and thus preventing the reduction in storage system availability caused by data reconstruction. As shown in Table 5 below, when the 1PB storage capacity provided in this application is used in a storage system, the availability of the storage system can reach five nines.

[0268] Table 5

[0269]

[0270] MTTR is the mean time to repair of the storage system, and MTBF is the mean time between failures. Unit availability is one of the metrics for measuring system performance; it represents the probability that the system is in a normal state at any given time. Switchover success rate refers to the probability that the backup controller will successfully take over in the event of a failure.

[0271] Equivalent to a traditional SSD controller, the storage control board in any of the memories provided in this application offloads some functions of the FTL to the control circuit in the storage medium board. For example, the control circuit stores the second mapping relationship between logical addresses and storage media. However, the storage control board in the memory can also have other functions of managing storage media in a traditional SSD controller, such as garbage collection.

[0272] For example, a storage control board (or a control chip within the storage control board) is used to determine a first physical address space, which is the physical address space within the memory that needs to be garbage collected, located among multiple storage media boards. Regarding garbage collection, there are generally two scenarios: one is that an external device specifies the release of data in the physical address space corresponding to a certain logical address segment in the memory, and the storage control board uses the physical address space corresponding to that logical address segment as the first physical address space. The other scenario is that the storage control board periodically determines the physical address space within its memory that needs garbage collection and uses the determined physical address space as the first physical address space.

[0273] The storage control board (or the control chip within the storage control board) is also used to copy valid data stored in the first physical address space to the second physical address space in the plurality of storage media boards. The second physical address space and the first physical address space are different physical address spaces. For example, after determining the first physical address space, the control chip reads valid data from the storage media board where the first physical address space is located, and writes the read valid data into the second physical address space in the plurality of storage media boards.

[0274] The storage control board (or the control chip in the storage control board) is also used to delete all data stored in the first physical address space in order to release the first physical address space and complete garbage collection for the first physical address space.

[0275] The data reconstruction method and / or the garbage collection process of the storage control board described above can also be combined with any of the data access methods provided above to obtain more implementation options.

[0276] In an exemplary embodiment, a storage control board is also provided, the storage control board including a processor for executing program code, causing the storage control board to perform the method steps performed by any of the storage control boards in the above-described method embodiments.

[0277] In an exemplary embodiment, a storage medium board is also provided, the storage medium board including a processor (such as a processor in a control circuit) for executing program code, causing the storage medium board to perform the method steps performed by any of the storage medium boards in the above-described method embodiments.

[0278] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code that can be executed by a processor in a storage control board to perform the method steps performed by any of the storage control boards in the various method embodiments described above.

[0279] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code that can be executed by a processor in the storage medium to perform the method steps performed by any of the storage mediums in the various method embodiments described above.

[0280] The computer-readable storage media provided above are non-transitory computer-readable storage media, such as read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0281] In an exemplary embodiment, a computer program product or computer program is also provided, which includes program code and computer instructions stored in a computer-readable storage medium. A processor in a storage control board reads the program code from the computer-readable storage medium and executes the program code, causing the storage control board to perform the method steps performed by any of the storage control boards in the above-described method embodiments.

[0282] In an exemplary embodiment, a computer program product or computer program is also provided, which includes program code and computer instructions stored in a computer-readable storage medium. A processor in the storage medium reads the program code from the computer-readable storage medium and executes the program code, causing the storage medium to perform the method steps performed by any of the storage mediums in the above-described method embodiments.

[0283] In the description of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the number or order of execution, and "first," "second," etc., do not necessarily imply that they are different.

[0284] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0285] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, all access requests involved in this application were obtained under fully authorized conditions.

[0286] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0287] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An address management method characterized by comprising: The method is applied to a first memory including a first memory control board and a plurality of first memory medium boards connected to the first memory control board, and the method includes: The first memory control board manages a first mapping table describing a respective logical address range of each of the first memory medium boards; Each of the first memory medium boards manages a second mapping table thereof, wherein each of the second mapping tables describes a physical address corresponding to each logical address in a corresponding logical address range of the memory medium board.

2. The method of claim 1, wherein, The method further includes: The first memory control board selects a first target memory medium board from the plurality of first memory medium boards based on the first mapping table in response to a first access request, and sends the first access request to the first target memory medium board; The first target memory medium board performs data access on a storage space corresponding to a physical address in the first target memory medium board based on the managed second mapping table in response to the first access request sent by the first memory control board.

3. The method of claim 2, wherein: The first memory control board selects a first target memory medium board from the plurality of first memory medium boards based on the first mapping table in response to a first access request, and sends the first access request to the first target memory medium board includes: The first memory control board allocates the first target memory medium board for the first access request from the plurality of first memory medium boards in response to the first access request being a write request, sends the first access request to the first target memory medium board, and establishes a first mapping relationship between a first target logical address and the first target memory medium board in the first mapping table, the first target logical address being a logical address carried by the first access request; or, the first memory control board queries a storage medium board corresponding to the first target logical address based on the first mapping table in response to the first access request being a read request, sends the first access request to the storage medium board corresponding to the first target logical address, and the storage medium board corresponding to the first target logical address is the first target memory medium board; The first target memory medium board performs data access on a storage space corresponding to a physical address in the first target memory medium board based on the managed second mapping table in response to the first access request sent by the first memory control board includes: The first target storage medium board allocates a target physical address for the first data carried by the first access request from a physical address in at least one storage medium in the first target storage medium board, writes the first data into a storage space corresponding to the target physical address, and establishes a second mapping relationship between the first target logical address and the target physical address in the second mapping table managed by the first target storage medium board in response to the first access request being a write request; or the first target storage medium board queries a target physical address corresponding to the first target logical address based on the second mapping table managed by the first target storage medium board, and reads data stored in a storage space corresponding to the target physical address in response to the first access request being a read request.

4. The method of claim 2, wherein, The first storage control board selects a first target storage medium board from the plurality of first storage medium boards based on the first mapping table in response to a first access request, and sends the first access request to the first target storage medium board, including: The first storage control board queries a storage medium board corresponding to a first target logical address based on the first mapping table in response to the first access request, and sends the first access request to the storage medium board corresponding to the first target logical address, wherein the first target logical address is a logical address carried by the first access request, and the storage medium board corresponding to the first target logical address is the first target storage medium board; The first target storage medium board performs data access on a storage space corresponding to a physical address in the first target storage medium board based on the second mapping table managed by the first target storage medium board in response to the first access request sent by the first storage control board, including: The first target storage medium board allocates a target physical address for the first data carried by the first access request from a physical address in at least one storage medium in the first target storage medium board, writes the first data into a storage space corresponding to the target physical address, and establishes a second mapping relationship between the first target logical address and the target physical address in the second mapping table managed by the first target storage medium board in response to the first access request being a write request; or the first target storage medium board queries a target physical address corresponding to the first target logical address based on the second mapping table managed by the first target storage medium board, and reads data stored in a storage space corresponding to the target physical address in response to the first access request being a read request.

5. The method according to any one of claims 1-4, characterized in that, The first storage control board acquires a third mapping table, and the third mapping table describes a logical address range corresponding to each of the second storage medium boards; The first storage control board selects a second target storage medium board from the plurality of second storage medium boards based on the third mapping table in response to a second access request, and sends the second access request to the second target storage medium board. ​ 6. The method according to any one of claims 1-5, characterized in that, The first memory further comprises a second storage control board for managing the first mapping table and the plurality of first storage medium boards; and the method further comprises: The first storage control board acquires the first mapping table managed by the second storage control board.

7. A data access method, characterized by, The method is applied to a storage control board connected with a plurality of first storage medium boards, and comprises: receiving a first access request indicating data access to a first target logical address; in response to the first access request, selecting a first target storage medium board from the plurality of first storage medium boards based on a first mapping table, and sending the first access request to the first target storage medium board, the first mapping table describing a logical address range corresponding to each of the first storage medium boards.

8. The method of claim 7, wherein: in response to the first access request, selecting a first target storage medium board from the plurality of first storage medium boards based on a first mapping table, and sending the first access request to the first target storage medium board, the first mapping table describing a logical address range corresponding to each of the first storage medium boards. in response to the first access request being a read request, querying a storage medium board corresponding to the first target logical address based on the first mapping table, and sending the first access request to the storage medium board corresponding to the first target logical address, the storage medium board corresponding to the first target logical address being the first target storage medium board. in response to the first access request, selecting a first target storage medium board from the plurality of first storage medium boards based on a first mapping table, and sending the first access request to the first target storage medium board, the first mapping table describing a logical address range corresponding to each of the first storage medium boards.

9. The method of claim 7, wherein, The storage control board and the plurality of first storage medium boards are located in a first memory, the first memory and a second memory are connected, the second memory comprises a plurality of second storage medium boards, and the method further comprises: acquiring a third mapping table describing a logical address range corresponding to each of the second storage medium boards; 10. The method according to any one of claims 8-9, characterized in that, in response to a second access request indicating data access to a second target logical address, selecting a second target storage medium board from the plurality of second storage medium boards based on the third mapping table, and sending the second access request to the second target storage medium board. ​ ​ 11. The method according to any one of claims 8-10, characterized in that, The storage control board and the plurality of first storage medium boards are located in a first storage, and the first storage further comprises a second storage control board configured to manage the first mapping table and the plurality of first storage medium boards; The method further comprises: obtaining the first mapping table managed by the second storage control board.

12. A memory, comprising: The storage comprises a first storage control board and a plurality of first storage medium boards connected to the first storage control board; The first storage control board is configured to manage a first mapping table, and the first mapping table describes a logical address range corresponding to each of the first storage medium boards; Each of the first storage medium boards comprises: a storage medium configured to provide a physical storage space, and the physical storage space is addressed by a physical address; a control circuit configured to manage a second mapping table, and the second mapping table is configured to describe a physical address corresponding to each logical address in a logical address range corresponding to the first storage medium board where the control circuit is located.

13. The memory of claim 12, wherein, The first storage control board comprises a hot plug interface and a control chip connected to the hot plug interface; The hot plug interface is configured to be connected to an interface circuit of the plurality of first storage medium boards in a hot plug manner, or directly connected to the interface circuit of the plurality of first storage medium boards in a hot plug manner; The control chip is configured to manage the first mapping table.

14. The storage according to claim 13, wherein the control chip is further configured to, in response to a first access request, select a first target storage medium board from the plurality of first storage medium boards based on the first mapping table, and send the first access request to the first target storage medium board; the control circuit in the first target storage medium is further configured to, in response to the first access request sent by the first storage control board, perform data access on a storage space corresponding to a physical address in the first target storage medium board based on the managed second mapping table.

15. The storage according to claim 14, wherein the control chip is further configured to, in response to the first access request being a write request, allocate the first target storage medium board for the first access request from the plurality of first storage medium boards, send the first access request to the first target storage medium board, and establish a first mapping relationship between a first target logical address and the first target storage medium board in the first mapping table, the first target logical address being a logical address carried by the first access request; or, in response to the first access request being a read request, query a storage medium board corresponding to the first target logical address based on the first mapping table, and send the first access request to the storage medium board corresponding to the first target logical address, the storage medium board corresponding to the first target logical address being the first target storage medium board. The control circuit in the first target storage medium board is further configured to, in response to the first access request being a write request, allocate a target physical address for first data carried by the first access request from a physical address in at least one storage medium in the first target storage medium board, write the first data into a storage space corresponding to the target physical address, and establish a second mapping relationship between the first target logical address and the target physical address in the second mapping table managed by the control circuit; or, in response to the first access request being a read request, query a target physical address corresponding to the first target logical address based on the second mapping table managed by the control circuit, and read data stored in a storage space corresponding to the target physical address. Or, in response to the first access request being a read request, query a target physical address corresponding to the first target logical address based on the second mapping table managed by the control circuit, and read data stored in a storage space corresponding to the target physical address.

16. The memory according to claim 14, wherein The control chip is further configured to, in response to the first access request, query a storage medium board corresponding to a first target logical address based on the first mapping table, and send the first access request to the storage medium board corresponding to the first target logical address, wherein the first target logical address is a logical address carried by the first access request, and the storage medium board corresponding to the first target logical address is the first target storage medium board. The control circuit in the first target storage medium board is further configured to, in response to the first access request being a write request, allocate a target physical address for first data carried by the first access request from a physical address in at least one storage medium in the first target storage medium board, write the first data into a storage space corresponding to the target physical address, and establish a second mapping relationship between the first target logical address and the target physical address in the second mapping table managed by the control circuit; or, in response to the first access request being a read request, query a target physical address corresponding to the first target logical address based on the second mapping table managed by the control circuit, and read data stored in a storage space corresponding to the target physical address.

17. The memory of any one of claims 14-16, wherein, The memory is connected with a second memory, the second memory includes a plurality of second storage medium boards, and the control chip is further configured to: obtain a third mapping table, the third mapping table describing a logical address range corresponding to each of the second storage medium boards; in response to a second access request, select a second target storage medium board from the plurality of second storage medium boards based on the third mapping table, and send the second access request to the second target storage medium board.

18. The memory of any of claims 14-17, wherein, The memory further includes a second storage control board, and the second storage control board is connected with the plurality of first storage medium boards; The second storage control board is configured to manage the first mapping table and the plurality of first storage medium boards. The control chip is further configured to obtain the first mapping table managed by the second storage control board.

19. The memory of any of claims 12-18, wherein, The memory is a solid state disk (SSD), the first storage control board is an SSD controller in the solid state disk, and the first storage medium board is a medium module in the solid state disk.

20. A memory control board, characterized by The storage control board is connected with a plurality of first storage control boards, and each of the first storage control boards includes: The control chip is configured to manage a first mapping table, the first mapping table describing a respective logical address range corresponding to each of the first storage medium boards.

21. The storage control panel of claim 20, wherein, The storage control board further comprises: A hot plug interface configured to connect to an interface circuit of the first storage control board via hot plug, or directly connect to the interface circuit of the first storage control board via hot plug.

22. The storage control board of claim 20 or 21, wherein, The control chip is further configured to: In response to a first access request, select a first target storage medium board from the plurality of first storage medium boards based on the first mapping table, and send the first access request to the first target storage medium board.

23. The storage control board of any of claims 20-22, wherein, The storage control board and the plurality of first storage medium boards are located in a first storage, the first storage is connected to a second storage, the second storage comprises a plurality of second storage medium boards, and the control chip is further configured to: Obtain a third mapping table, the third mapping table describing a respective logical address range corresponding to each of the second storage medium boards; In response to a second access request, select a second target storage medium board from the plurality of second storage medium boards based on the third mapping table, and send the second access request to the second target storage medium board.

24. The storage control board of any of claims 20-23, wherein, The storage control board and the plurality of first storage medium boards are located in a first storage, the first storage further comprises a second storage control board, and the second storage control board is connected to the storage control board and the plurality of first storage medium boards; The second storage control board is configured to manage the first mapping table and the plurality of first storage medium boards. The control chip is further configured to obtain the first mapping table managed by the second storage control board.

25. The storage control board of any of claims 20-24, wherein, The storage control board is an SSD controller in a solid state drive (SSD), and the plurality of first storage medium boards are medium modules in the SSD.

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