Divider based on shift multiplication and power reduction

Abstract

The invention discloses a divider based on shift multiplication and power reduction, relates to the field of digital logic circuits and embedded computing, and completes operation through three steps of symbol preprocessing, power shift multiplication power locking and cross-magnitude bit-by-bit weight coefficient reduction. Dynamic precision pre-scaling and median prejudgment bidirectional search is introduced, a quotient coefficient is tested from a cardinal number intermediate value, up-down search is performed according to a residual error, and iteration is greatly reduced. Compared with the prior art, the method does not need a hardware multiplier and a huge lookup table, only depends on displacement, addition and subtraction and small-amount comparison, is suitable for a small MCU with limited resources, solves the problems that a traditional software division method is low in efficiency and an SRT algorithm is large in resource consumption, and achieves high cost-performance balance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital logic circuit and embedded computing technology, and particularly to a divider based on shift multiplication and weight bit reduction. BACKGROUND

[0002] In the arithmetic operation of embedded systems and digital circuits, division operation is a common arithmetic operation. However, due to the complexity of the algorithm and circuit structure of the traditional divider, it is impossible to deploy a hardware divider in a low-power, low-resource single-chip microcomputer. For example, the general C51 series, STM8 series and STM32 M0 / M3 below series of single-chip microcomputers usually do not integrate hardware dividers. This results in the fact that these low-power single-chip microcomputers must rely on software algorithms to implement division when processing division, resulting in extremely low efficiency and long time delay. Therefore, in the scenarios of real-time sensor detection, PID control, motor FOC control, edge computing monitoring and the like, it is often difficult to use the low-cost single-chip microcomputers without hardware dividers mentioned above.

[0003] The traditional software division algorithm mainly includes the restoration remainder method and the non-restoration remainder method. These two methods are classical binary integer division based on subtraction and shift, which are widely used in early CPU design. The working principle is similar to the cycle subtraction until the final result is obtained. Although the implementation is simple, the operation period is long, the efficiency is low, and the entire bit width of the dividend must be traversed.

[0004] In order to improve the speed, modern high-performance processors often use SRT (Sweeney, Robertson, and Tocher) algorithm. The SRT algorithm generates redundant quotient numbers through table lookup or recursion, which can reduce the time complexity from O(n) to O(n / k). However, the SRT algorithm needs to store a large quotient lookup table (the space complexity increases exponentially O(2^k) with the increase of the base), and the hardware logic is complex, which is not suitable for resource-constrained low-power single-chip microcomputer (MCU) platforms at all.

[0005] In addition, the traditional Radix-2 bit-by-bit division can also run on small resource CPUs, but it generates quotient bits fixedly from the highest bit to the lowest bit of the dividend, even if the high-bit quotient is 0, it must also participate in the operation, and there is a lot of "empty" calculation of leading zeros, so the efficiency is still not ideal.

[0006] In summary, the prior art lacks a general mechanism that balances the operation speed and hardware resources. The existing solutions are either too slow (traditional long division) or too resource-consuming (SRT algorithm), resulting in a technical gap in the application of low-cost MCUs in high-performance operation.

[0007] Furthermore, binary has an inherent disadvantage in precision in financial calculations and high-precision calculations, such as its inability to represent precise values ​​like 0.1 or 0.2.

[0008] In summary, there is a gap between "extremely low resource consumption" and "high computational efficiency" in existing technologies, and there is a lack of a universal division scheme that can run efficiently on 8 / 16 / 32-bit microcontrollers. Summary of the Invention

[0009] The purpose of this invention is to provide a divider based on shift doubling and weight reduction, aiming to resolve the contradiction between slow operation speed and high resource consumption in existing technologies. This invention reconstructs the quotient generation order by quickly and actively determining the boundary, eliminating the shortcomings of leading zero iteration, negative remainder recovery, and fixed full-width loops in existing algorithms without increasing arithmetic complexity, thereby achieving shorter average latency and higher energy efficiency.

[0010] The divider based on shift multiplication and weight reduction of this invention is implemented as follows, including the following steps: A - dividend, B - divisor; (1) Sign preprocessing: Detect the sign bits of the dividend A and the divisor B, and determine the final sign of the quotient S' = Sign(A) ⊕ Sign(B) according to the XOR logic; then convert the dividend and divisor to their corresponding absolute values ​​|A| and |B| for subsequent operations; (2) Weight detection and locking: The absolute value of the divisor |B| is detected by power shift multiplication in base M. By comparing the magnitude relationship between |A| and the multiplication result (|B| × M^t), the highest effective weight t of the quotient is quickly locked, where M is the base (such as binary, decimal, hexadecimal, etc.). This step can effectively skip all leading zeros and directly locate the highest effective weight of the quotient, avoiding invalid iterations. (3) Cross-order weight coefficient reduction (core approach): The initial residual value R is |A|; iterate from the highest weight t to the lowest weight, and for each weight i (t ≥ i ≥ 0), perform the quotient coefficient S. i The search determines and updates the residual R. Calculate the trial value V = S i × M^i × |B| (Since the number of multiplications here is small, it can be implemented using continuous addition or existing binary shift combination algorithms within the arithmetic unit). S i Given a integer R = 0, 1, ..., M-1, find the maximum quotient coefficient S that satisfies R ≥ V. i Value, determine the quotient coefficient S iAfter that, update the residual R as R - S i × M^i × |B|, (4) Result synthesis and sign restoration: Arrange the weight quotient coefficients S of each digit in sequence i Generate the digital sequence S of the quotient, and add the positive or negative sign to the result according to the sign S' determined in step (1).

[0011] Preferably, the present invention further includes a dynamic precision pre-scaling step (1-2): After step (1), receive the specified precision digit N by the user, perform bit weight expansion on the absolute value of the dividend, calculate the preprocessed dividend A' = |A| × M^N, replace A with A', and after calculating S, insert a decimal point according to the precision N to obtain the final value of S.

[0012] Preferably, in the quotient digit coefficient S of step (3) i During the search for the value, adopt the "median prediction two-way search strategy": Preset an intermediate value K in the M number system (for example, K = 5 in decimal and K = 8 in hexadecimal) as the first trial quotient digit coefficient S i , Calculate the trial value V = K × M^i × |B|. (For this multiplication, there is no need to call a multiplier, and it can be implemented using the ready-made binary shift in the arithmetic unit. For example, when searching in decimal, if a number needs to be multiplied by 5: it is equal to shifting the binary number of this number left by 2 bits (equivalent to multiplying by 4) and then adding itself once. When searching in hexadecimal, if a number needs to be multiplied by 8: it is equal to shifting the binary number of this number left by 3 bits (equivalent to multiplying by 8)) If the current residual R ≥ V: It means that the quotient digit coefficient S of the current digit i is at least K, so only search upward (or binary search) in the large value interval of [K, M-1] to find the largest quotient digit coefficient S that meets the conditions i , If the current residual R < V: It means that the quotient digit coefficient S of the current digit i is less than K, so only search downward (or binary search) in the small value interval of [0, K-1] to find the largest quotient digit coefficient S that meets the conditions i .

[0013] The beneficial effects of the present invention are as follows: High energy efficiency and low latency: Compared with traditional algorithms, the present invention skips leading zeros and uses "median prediction" to reduce the search range by half when determining each digit of the quotient, significantly reducing the average number of loops.

[0014] Extremely low resource consumption: The algorithm is based entirely on shifting, addition, comparison and subtraction. It does not require hardware multipliers or lookup tables. Its space complexity is only O(n), making it very suitable for 8 / 16 / 32-bit microcontrollers with only a few KB of Flash memory.

[0015] High versatility: The unified architecture supports binary, decimal, and hexadecimal arithmetic, and dynamic precision adjustment. It also supports decimal arithmetic with specified precision, filling the gap in high-performance dividers for low-end MCUs. In decimal, shifting and searching calculations can be performed directly on the BCD code without conversion to binary; in hexadecimal, a single 4-bit HEX unit can be used for shifting and searching, also without binary conversion. High-efficiency computation is achieved by utilizing the barrel shifting technology within the ALU. Attached Figure Description

[0016] Figure 1 This is a flowchart of the overall operation process; Figure 2 is a flowchart (subroutine) of the bidirectional search strategy for median prediction. Detailed Implementation

[0017] The divider based on shift multiplication and weight reduction of the present invention will now be described in further detail with reference to the embodiments: The divider based on shift multiplication and weight reduction in this invention is implemented as follows: Example 1: Basic Binary Division (M=2) Scenario: Calculate 17 ÷ 3, 8-bit width. (1) Symbol preprocessing: The dividend 17 (00010001) and the divisor 3 (00000011) are both positive numbers, the quotient symbol S' is positive, and the absolute values ​​are |A|=17, |B|=3; (2) Position detection and locking: Shift-multiply detection with divisor B=3: t=0: B × 2^0 = 3 ≤ 17, which satisfies the condition. t=1: B × 2^1 = 6 ≤ 17, which satisfies the condition. t=2: B × 2^2 = 12 ≤ 17, which satisfies the condition. t=3: B × 2^3 = 24>17, exceeding the limit, stop. Conclusion: The highest effective position weight of the locked quotient is t=2; (3) Reduction of place value coefficients across orders of magnitude: Initial residual R=17, self-position weight i=2, iterating towards 0. Position weight i=2: Trial quotient coefficient S2=1, The trial value V = 1 × 2^2 × B = 12, Comparison: R(17) ≥ 12, sufficient for subtraction. Action: Determine S2=1, update residual R = 17 - 12 = 5. Position weight i=1: Trial quotient coefficient S1=1, The trial value V = 1 × 2^1 × 3 = 6. Comparison: R(5) < 6, not enough to subtract. Action: Determine S1=0, and keep the residual R=5 unchanged. Position weight i=0: Trial quotient coefficient S0=1, The trial value V = 1 × 2^0 × 3 = 3. Comparison: R(5) ≥ 3, sufficient for reduction. Action: Determine S0=1, update residual R = 5 - 3 = 2; (4) Result synthesis and symbol recovery: Arrange the quotient coefficients S2S1S0 to obtain the binary quotient 00000101 (decimal 5), with a remainder of 2.

[0018] Example 2: Precision binary division (M=2, N=2) Scenario: Calculate -17 ÷ 3, keeping 2 decimal places (N=2). (1) Symbol preprocessing (with dynamic precision scaling): Sign determination: Since the dividend (-17) and divisor (3) have opposite signs, the quotient sign S' is negative. Calculate the absolute values: |A|=17, which is binary 00010001; |B|=3, which is binary 00000011. Precision prescaling: Based on N=2, shift the dividend to the left by 2 bits (equivalent to multiplying by 4). A' = 17 × 2^2 = 68 Binary demonstration: A (00010001)<<2 → A' (01000100); (2) Position detection and locking: Perform a shift-multiplication probe on the divisor B=3 (00000011) and compare it with A'=68 (01000100). t=0: B × 2^0 = 3 ≤ 68, which satisfies the condition. t=1: B × 2^1 = 6 ≤ 68, which satisfies the condition. t=2: B × 2^2 = 12 ≤ 68, which satisfies the condition. t=3: B × 2^3 = 24 ≤ 68, which satisfies the condition. t=4: B × 2^4 = 48 (00110000) ≤ 68 (01000100), which meets the requirement. t=5: B × 2^5 = 96 (01100000)>68 (01000100), exceeding the limit, stop. Conclusion: The highest effective bit weight is locked at t=4; (3) Reduction of place value coefficients across orders of magnitude: The initial residual R = 68 (01000100), and the positional weight i = 4 iterates towards 0 (corresponding to the original decimal places). Position weight i=4: Trial quotient coefficient S4=1 The trial value V = 1 × 2^4 × B = 48. Comparison: R(01000100) ≥ trial value V(00110000) ? is (R(68) ≥ 47, enough to subtract,), Action: Determine S4=1, update residual: R = 68 - 48 = 20, Binary arithmetic: 01000100 - 00110000 = 00010100 (20), Position weight i=3: Trial quotient coefficient S3=1 The trial value V = 1 × 2^3 × B = 24 (B << 3 = 00011000 (24)). Comparison: R(00010100) ≥ Trial value V(00011000) ? No (R(20) < 24, not enough to subtract), Action: Set quotient coefficient S3 to 0, update residuals: R remains unchanged: R = 20 - 0 = 20(00010100), Position weight i=2: Trial quotient coefficient S2=1 The trial value V = 1 × 2^2 × B = 12 (B << 2 = 00001100 (12)). Comparison: R(00010100) ≥ trial value V(00001100) ? is (R(20) ≥ 12, enough to subtract), Action: Set quotient coefficient S2 = 1, update residual: R = 20 - 12 = 8, Binary arithmetic: 00010100 - 00001100 = 00001000 (8), Position weight i=1: Trial quotient coefficient S1=1 The trial value V = 1 × 2^1 × B = 6 (B << 1 = 00000110 (6)). Comparison: R(00001000) ≥ trial value V(00000110) ? is (R(8) ≥ 6, enough to subtract), Action: Set quotient coefficient S1=1, update residual: R = 8 - 6 = 2, Binary arithmetic: 00001000 - 00000110 = 00000010 (2), Position weight i=0: Trial quotient coefficient S0=1. The trial value V = 1 × 2^1 × B = 6 (B << 0 = 00000011 (3)). Comparison: R(00000010) ≥ Trial value V(00000011) ? No (R(2)<3, not enough to subtract), Action: Set the quotient coefficient S0=0, update the residual: R remains unchanged: R = 2 - 0 = 2 (00000010); (4) Result synthesis and symbol recovery: The generating sequence of numbers S is: S4S3S2S1S0 = 10110. Inserting a decimal point: Based on a precision N=2, insert a decimal point in the second-to-last place of the quotient sequence S → 101.10. (Corresponding decimal: 1×4 + 0×2 + 1×1 + 1×0.5 + 0×0.25 = 5.5. In binary, the first 1 after the decimal point is equivalent to 0.5 in decimal, and the second 1 after the decimal point is equivalent to 0.25 in decimal.) Sign restoration: Since the quotient sign S' is negative, add a negative sign, and the final quotient is -101.10 (corresponding to -5.5 in decimal). Remainder processing: The final residual is 00000010 (2), and the actual remainder needs to be shifted right by N (2) bits to become 000000.10 (corresponding to decimal: 2 × 2^-2 = 0.5). Sign recovery: Since the quotient sign S' is negative, add a negative sign, and the residual is -000000.10 (corresponding to decimal: -0.5).

[0019] Example 3: Bidirectional search of decimal median (M=10) Scenario: Calculate 328 ÷ 6, with a precision of N=1. (1) Symbol preprocessing (with precision scaling): With a positive sign, the preprocessed dividend A' = 328 × 10^1 = 3280. (2) Position detection and locking: t=0, 6 × 10^0 = 6 ≤ 3280; t=1, 6 × 10^2 = 60 ≤ 3280; t=2, 6 × 10^3 = 600 ≤ 3280, t=3, 6 × 10^3 = 6000>3280, Conclusion: The highest position weight t=2. (3) Reduction of weight coefficients across magnitudes (with median prediction): Initial residual R = 3280, Place value i=2 (hundreds digit): Median prediction: Let the trial quotient coefficient S2 = 5 (median value). The trial value V is calculated to be 5 × 10^2 × 6 = 3000. Comparison and Decision: R(3280) ≥ 3000, indicating that S2 is at least 5, and we should search upwards for {5, 6, 7, 8, 9}. Upward probe: Trial quotient coefficient S2=6 → Val=3600, since 3280<3600, it indicates that 6 is too large. Determination coefficient: Backward determination quotient coefficient S2=5, Update residuals: R = 3280 - 3000 = 280, Place value i=1 (tens digit): Median prediction: Let the trial quotient coefficient S1 = 5, The trial value V is calculated as V = 5 × 10^1 × 6 = 300. Comparison and Decision: R(280) < 300, indicating that S1 is less than 5, and the search should proceed downwards to {4, 3, 2, 1, 0}. Downward probe: Trial quotient coefficient S1=4 → Val = 4 × 60 = 240, since 280 ≥ 240, the condition is met. Coefficient of determination: S1 = 4.

[0020] Update residuals: R = 280 - 240 = 40, Place weight i=0 (units digit): Median prediction: Let the trial quotient coefficient S0 = 5, The trial value V = 5 × 6 = 30. Comparison and Decision Making: If 40 ≥ 30, search upwards. Detect upwards: If the initial quotient coefficient S0=6 → Val=36, and 40 ≥ 36, continue upwards. The initial quotient coefficient S0=7 → Val=42, 40<42, too large. Coefficient of determination: Backtracking determination S0=6, Update residuals: R = 40 - 36 = 4, (4) Result synthesis and symbol recovery: The quotient sequence S is generated as S2S1S0 = 546. The quotient sequence S is then adjusted by inserting a decimal point according to N=1, resulting in a final quotient of 54.6 and a remainder of 0.4.

[0021] Example 4: Bidirectional hexadecimal median search (M=16) Scenario: Calculate 0xABCD ÷ 0x12 (decimal 43981 ÷ 18). Symbol preprocessing: Since both the dividend 0xABCD and the divisor 0x12 are positive, the quotient sign S' is positive, and the absolute values ​​are |A|=0xABCD, |B|=0x12; (2) Position detection and locking: t=0, 0x12 × 16^0 = 0x12 ≤ 0xABCD; t=1,0x12 × 16^1 = 0x120 ≤ 0xABCD, t=2, 0x12 × 16^2 = 0x1200 ≤ 0xABCD; t=3, 0x12 × 16^3 = 0x12000>0xABCD, Conclusion: The highest position weight t=2. (3) Reduction of weight coefficients across magnitudes (with median prediction): The initial residual is R = 0xABCD. Position weight i=2: Median prediction: Let the quotient coefficient S2 = 8, Val = 8 × 16^2 × 0x12 = 0x9000. Comparison: 0xABCD ≥ 0x9000, search upwards within the range {9, A, B, C, D, E, F}. Detection: Quotient coefficient S2=9 → 9 ×16^2 × 0x12 = 0xA200, 0xABCD ≥ 0xA200 (continue). The quotient coefficient S2=A (10) → A × 16^2 ×0x12 = 0xB400, 0xABCD<0xB400 (too large). Confirmed: S2=9, Update residual: R = 0xABCD - 0xA200 = 0x09CD, Position weight i=1: Median prediction: Let the quotient coefficient S1=8, Val = 8 × 16^1 × 0x12 = 0x900.

[0022] Comparison: 0x09CD ≥ 0x900, search upwards within the range {9, A, B, C, D, E, F}. Detection: Quotient coefficient S1=9 → 9 × 16^1 × 0x12 = 0xA20, 0x09CD<0xA20 (too large). Confirmed: S1=8, Update residual: R = 0x09CD - 0x900 = 0xCD, Position weight i=0: Median prediction: Let the quotient coefficient S0 = 8, Val = 8 × 0x12 = 0x90, Comparison: 0xCD ≥ 0x90, search upwards within the range {9, A, B, C, D, E, F}. Detection: The quotient coefficient S0=9, and A and B both satisfy (where S0=B → B × 16^0 × 0x12 = 0xC6 ≤0xCD). The quotient coefficient S0 = C → C × 16^0 × 0x12 = 0xD8 > 0xCD (too large). Confirmed: S0 = B.

[0023] Update residuals: R = 0xCD - 0xC6 = 0x7, (4) Result synthesis and symbol recovery: The final quotient sequence S: S2S1S0 = 98B (hexadecimal), with a remainder of 0x7.

Claims

1. A divider based on shift and multiply and bit reduction, characterized by, Comprising the following steps: (1) Symbol pre-processing: detecting the sign bits of the dividend A and the divisor B, determining the final sign of the quotient S' = Sign(A) ⊕ Sign(B) according to the exclusive or logic; then converting the dividend and the divisor into their corresponding absolute values |A| and |B| for subsequent operations; (2) Weight bit detection and locking: performing power shift multiplication detection on the absolute value |B| of the divisor in base M, locking the most significant bit weight t of the quotient by comparing the order relationship between |A| and the multiplication result (|B| × M^t), wherein M is the base; (3) Cross-order weight coefficient reduction: Initialize residual R = |A|; iterate from the highest weight t to the lowest weight; for each weight i, perform quotient coefficient S i The search decision is made and the residual R is updated; the search decision satisfies: 0 ≤ S i Find the quotient coefficient S of the largest integer within the range M. i such that R ≥ S i If the equation × M^i × |B| holds true, then the quotient coefficient S is determined. i Then, update the residual R to R - S i × M^i × |B|; (4) Result synthesis and sign recovery: sequentially arrange the bit weight quotient coefficient S i The digital sequence S of the quotient is generated, and the sign S' determined according to step (1) is added to the result to add a positive or negative sign. The digital sequence S after the addition of the positive or negative sign is the quotient of the dividend A divided by the divisor B.

2. The shift-and-multiply and guard-bit reduction based divider of claim 1, wherein, Between step (1) and step (2), there is also step (1-2) dynamic precision pre-scaling: Receiving the precision bit number N specified by the user, expanding the bit weight of the absolute value of the dividend, calculating the pre-processed dividend A' = |A| × M^N, and replacing A with A'; After generating the digital sequence S of the quotient in step (4), the digital sequence S is inserted with a decimal point according to the precision N.

3. The shift-and-multiply and guard-bit reduction based divider according to claim 1 or 2, characterized in that, The step (3) "searching decision of quotient bit coefficient S i uses "median pre-decision bidirectional searching strategy". presetting an intermediate quotient bit coefficient S i = K (where K ≈ M / 2) as the first tentative quotient bit coefficient; Calculating the trial value V = K × M^i × |B|; If the current residual R ≥ V: determine the target quotient coefficient S i Falls in the interval [K, M-1], perform an upward incremental search until the largest quotient coefficient S satisfying the condition is found i ; If the current residual R < V: determine the target quotient coefficient S i Falls in the interval [0, K-1], perform a down search until the largest quotient coefficient S satisfying the condition is found i .

4. The divider based on shift multiplication and weight bit reduction according to claim 3, characterized in that: When M = 10, the preset intermediate value quotient bit coefficient S i = K = 5; if R ≥ 5 * 10^i * |B|, search the quotient bit coefficient S in the {5, 6, 7, 8, 9} set i ; if R < 5 * 10^i * |B|, search the quotient bit coefficient S in the {4, 3, 2, 1, 0} set i ; When M = 16 (hexadecimal), the preset intermediate quotient bit coefficient S i = K = 8; if R ≥ 8 x 16^i x |B|, search the quotient bit coefficient S in the {8, 9, 10, 11, 12, 13, 14, 15} set i ; if R < 8 x 16^i x |B|, search the quotient bit coefficient S in the {7, 6, 5, 4, 3, 2, 1, 0} set i .

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