Multi-core processor utilization rate scheduling method and device, equipment, medium and product

Abstract

The invention discloses a multi-core processor utilization rate scheduling method and device, equipment, a medium and a product. The method comprises the following steps: acquiring a task utilization rate corresponding to each task in a plurality of processors at a plurality of historical moments; determining the total task utilization rate of each processor at a plurality of historical moments and the total task utilization rate of the target processor at the current moment; determining a processor target usage rate; determining a target compensation amount of the target processor based on the processor utilization rate deviation of the target processor at the current moment, the total processor utilization rate deviation amount at the plurality of historical moments and the change rate; and scheduling the tasks in the target processor according to the target compensation amount. According to the embodiment of the invention, through introduction of the multi-dimensional compensation amount and cross-core time-sharing operation, accurate adjustment is realized, and the purpose of load balancing is achieved; and parameters are optimized and adjusted in real time through an online self-learning mechanism, and the system stability is improved.

Description

Technical Field

[0001] This application belongs to the field of processor task scheduling technology, and particularly relates to a method, apparatus, device, medium and product for multi-core processor utilization scheduling. Background Technology

[0002] In multi-core processors, multitasking is an important and fundamental capability. To improve the system's CPU utilization, it is necessary to flexibly control the current CPU utilization. For example, load balancing controls CPU utilization to make the load on each core as similar as possible.

[0003] Existing multi-core processor task scheduling schemes employ static adjustment strategies that do not consider the impact of historical data; fixed migration strategies use a single task migration method that does not consider task priority, latency sensitivity, or other characteristics; and they lack adaptive optimization, with fixed adjustment parameters that cannot be dynamically adjusted according to system load fluctuations, resulting in poor performance during sudden high loads. Summary of the Invention

[0004] This application provides a method, apparatus, device, medium, and product for scheduling the utilization of multi-core processors, which can achieve precise adjustment, load balancing, and improved system stability.

[0005] In a first aspect, embodiments of this application provide a multi-core processor utilization scheduling method, comprising: obtaining the task utilization rate of each task in multiple processors at multiple historical time points, and obtaining the task utilization rate of each task in a target processor at the current time, wherein the target processor is any processor among the multiple processors; determining the total task utilization rate of each processor at multiple historical time points and the total task utilization rate of the target processor at the current time based on the task utilization rate of each task; determining the target utilization rate of the processor based on the total task utilization rate of the multiple processors at multiple historical time points; calculating the processor utilization deviation of the target processor at the current time and the total processor utilization deviation at multiple historical time points based on the target utilization rate of the processor and the total task utilization rate of the target processor at multiple historical time points and at the current time; calculating the rate of change of the processor utilization deviation of the target processor at the current time relative to the processor utilization deviation of the previous time point; determining the target compensation amount of the target processor based on the processor utilization deviation of the target processor at the current time, the total processor utilization deviation at multiple historical time points, and the rate of change; and scheduling the tasks in the target processor according to the target compensation amount.

[0006] In one possible implementation, determining the target processor utilization rate based on the total task utilization rate of multiple processors at the current moment includes: summing the total task utilization rate of multiple processors at multiple historical moments to obtain the total task utilization rate of multiple processors; and using the ratio of the total task utilization rate of multiple processors to the total number of processors as the target processor utilization rate.

[0007] In one possible implementation, based on the target processor utilization rate and the total task utilization rate of the target processor at multiple historical times and at the current time, the processor utilization rate deviation of the target processor at the current time and the total processor utilization rate deviation at multiple historical times are calculated. This includes: taking the difference between the total task utilization rate of the target processor at the current time and the target processor utilization rate as the processor utilization rate deviation of the target processor at the current time; obtaining the processor utilization rate deviation of the target processor at multiple historical times based on the difference between the total task utilization rate of the target processor at multiple historical times; and summing the processor utilization rate deviations of the target processor at multiple historical times to obtain the total processor utilization rate deviation of the target processor at multiple historical times.

[0008] In one possible implementation, calculating the rate of change of the processor utilization deviation of the target processor at the current moment relative to the processor utilization deviation of the previous moment includes: using the difference between the processor utilization deviation of the target processor at the current moment and the processor utilization deviation of the previous moment as the rate of change.

[0009] In one possible implementation, the target compensation amount for the target processor is determined based on the processor utilization deviation of the target processor at the current moment, the total processor utilization deviation at multiple historical moments, and the rate of change. This includes: calculating the load standard deviation of the target processor at multiple historical moments as the dynamic adjustment compensation coefficient for the target processor; determining a set of adjustment coefficients for the target processor using an online parameter self-learning mechanism based on a pre-set target scheduling time. The set of adjustment coefficients includes a first adjustment coefficient for adjusting the processor utilization deviation at the current moment, a second adjustment coefficient for adjusting the total processor utilization deviation, a third adjustment coefficient for adjusting the rate of change, and a fourth adjustment coefficient for adjusting the dynamic adjustment compensation coefficient; calculating the product of the dynamic adjustment compensation coefficient and the fourth adjustment coefficient, and summing the resulting product with the first adjustment coefficient; summing the summed value with the product of the processor utilization deviation, the product of the total processor utilization deviation and the second adjustment coefficient, and the product of the rate of change and the third adjustment coefficient to obtain the target compensation amount for the target processor.

[0010] In one possible implementation, a set of adjustment coefficients for the target processor is determined using an online parameter self-learning mechanism based on a pre-set target scheduling time. This includes: constructing an online parameter self-learning training model based on the target processor's scheduling time and a first, second, third, and fourth adjustment coefficient in the adjustment coefficient set; training and validating the online parameter self-learning training model using pre-acquired training data to obtain a trained online parameter self-learning model; using the square of the difference between the predicted value output by the online parameter self-learning model and the target scheduling time as the target optimization function; and performing gradient and iterative update processing on the target optimization function based on the initial value of the online parameter self-learning model and the pre-set learning coefficients to obtain the first, second, third, and fourth adjustment coefficients in the optimized adjustment coefficient set.

[0011] In one possible implementation, the target compensation amount is determined in the following way: Where comp represents the target compensation amount, k1 represents the first adjustment coefficient, k2 represents the second adjustment coefficient, k3 represents the third adjustment coefficient, k4 represents the fourth adjustment coefficient, and volatility represents the dynamic adjustment compensation coefficient. This represents the total processor task utilization at the current moment. Indicates the target processor utilization. This represents the total task utilization of the processor at a given historical moment. The total processor task utilization is represented by n, where n represents the number of historical moments within the historical time period, and t represents each historical moment within the historical time period. This indicates the processor utilization deviation at the current moment. This indicates the total deviation in processor utilization. Indicates the rate of change.

[0012] In one possible implementation, before scheduling the task utilization rate in the target processor according to the target compensation amount, the method further includes: determining whether the target compensation amount corresponding to the target processor is equal to zero in each preset time interval; if the target compensation amount is equal to zero, controlling the task utilization rate of the target processor to remain unchanged; if the target compensation amount is not equal to zero, determining to perform the step of scheduling the tasks in the target processor according to the target compensation amount.

[0013] In one possible implementation, when the target compensation amount is not equal to zero, determining the step of scheduling tasks in the target processor according to the target compensation amount includes: when the target compensation amount is greater than zero, determining the scheduling type of the target processor as a migration-out core type; determining the migration amount based on the processor utilization deviation of the target processor, and taking the maximum value of the migration amount among processors of the migration-out core type as the maximum migration-out compensation amount; when the target compensation amount is less than zero, determining the scheduling type of the target processor as a migration-in core type; determining the migration amount corresponding to the processor of the migration-in core type based on the processor utilization deviation of the processor of the migration-in core type, and taking the minimum value of the migration amount among processors of the migration-in core type as the minimum migration-in compensation amount; and initiating scheduling control for tasks of each processor of the migration-out core type based on the maximum migration-out compensation amount and the minimum migration-in compensation amount.

[0014] In one possible implementation, scheduling control is initiated for tasks of each processor of the outgoing core type based on the maximum outgoing compensation amount and the minimum ingoing compensation amount, including: sorting the task utilization rates of the processors of the outgoing core type from smallest to largest to obtain a target task utilization rate sequence; using the minimum of the absolute values ​​of the maximum outgoing compensation amount and the minimum ingoing compensation amount as a coarse adjustment threshold; determining the tasks of the first n items in the target task utilization rate sequence as the target outgoing task set if the sum of the first n items in the target task utilization rate sequence is less than the coarse adjustment threshold, and if the sum of the first n+1 items in the target task utilization rate sequence is greater than the coarse adjustment threshold; performing coarse outgoing control on the tasks in the target outgoing task set; and performing cross-core fine-tuning control on the (n+1)th task in the target task utilization rate sequence if the total remaining task utilization rate of the processors of the outgoing core type meets a preset fine-tuning threshold.

[0015] In one possible implementation, when the total remaining task utilization of the processor of the migrated core type meets a preset fine-tuning threshold, cross-core fine-tuning control is performed on the (n+1)th task in the target task utilization sequence, including: using the difference between the total remaining task utilization of the processor of the migrated core type and the target utilization of the processor as a fine-tuning deviation value; determining whether the fine-tuning deviation value is greater than the fine-tuning threshold; if the fine-tuning deviation value is greater than the fine-tuning threshold, designating the (n+1)th task in the target task utilization sequence corresponding to the processor of the migrated core type as a cross-core fine-tuning task; after the cross-core fine-tuning task is migrated out of the corresponding processor of the migrated core type, calculating the difference between the total remaining task utilization of the processor of the migrated core type and the target utilization of the processor, calculating the difference between the total task utilization of each processor of the migrated core type and the target utilization of the processor, comparing the calculated differences to determine the running time ratio of the cross-core fine-tuning task; and performing segmented execution of the cross-core fine-tuning task according to the running time ratio.

[0016] In one possible implementation, after the cross-core fine-tuning task is sliced ​​and run according to the running time ratio, the method further includes: determining whether the processor of the migrated core type has a latency-sensitive requirement; if the processor of the migrated core type has a latency-sensitive requirement, increasing the running time ratio of the processor of the migrated core type using a pre-set latency-sensitive factor.

[0017] Secondly, embodiments of this application provide a multi-core processor utilization scheduling device, the device comprising: The system comprises the following modules: an acquisition module for acquiring the task utilization rate of each task across multiple processors at multiple historical time points, and the task utilization rate of each task in the target processor at the current time (the target processor being any one of the multiple processors); a determination module for determining the total task utilization rate of each processor across multiple historical time points and the total task utilization rate of the target processor at the current time, based on the task utilization rate of each task; a determination module for determining the target processor utilization rate based on the total task utilization rate of multiple processors across multiple historical time points; a parameter calculation module for calculating the processor utilization deviation of the target processor at the current time and the total processor utilization deviation across multiple historical time points, based on the target processor utilization rate and the total task utilization rate of the target processor at multiple historical time points and at the current time; a parameter calculation module for calculating the rate of change of the processor utilization deviation of the target processor at the current time relative to the processor utilization deviation of the previous time point; a compensation determination module for determining the target compensation amount of the target processor based on the processor utilization deviation of the target processor at the current time, the total processor utilization deviation across multiple historical time points, and the rate of change; and a scheduling module for scheduling tasks in the target processor according to the target compensation amount.

[0018] Thirdly, embodiments of this application provide a multi-core processor utilization scheduling device, the device comprising: a processor and a memory storing computer program instructions; the processor, when executing the computer program instructions, implements the multi-core processor utilization scheduling method as described in any one of the first aspects.

[0019] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the multi-core processor utilization scheduling method as described in any one of the first aspects.

[0020] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a multi-core processor utilization scheduling method as described in any one of the first aspects.

[0021] The multi-core processor utilization scheduling method, apparatus, device, medium, and product of this application embodiments obtain the task utilization rate corresponding to each task in multiple processors at multiple historical time points, and obtain the task utilization rate corresponding to each task in a target processor at the current time, where the target processor is any one of the multiple processors; based on the task utilization rate corresponding to each task, determine the total task utilization rate of each processor at multiple historical time points, and the total task utilization rate of the target processor at the current time; determine the target processor utilization rate based on the total task utilization rate of multiple processors at multiple historical time points; and determine the target processor utilization rate based on the target processor utilization rate and the task utilization rate corresponding to the target processor at multiple historical time points and at the current time. The system calculates the processor utilization deviation of the target processor at the current moment and the total processor utilization deviation over multiple historical moments; it also calculates the rate of change of the processor utilization deviation of the target processor at the current moment relative to the processor utilization deviation of the previous moment; based on the processor utilization deviation of the target processor at the current moment, the total processor utilization deviation over multiple historical moments, and the rate of change, it determines the target compensation amount for the target processor; it schedules the task utilization of the target processor according to the target compensation amount; it can achieve precise adjustment and load balancing by introducing multi-dimensional compensation amounts and cross-core time-sharing operation; and it improves system stability by optimizing adjustment parameters in real time through an online self-learning mechanism. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a multi-core processor utilization scheduling method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a process for determining the target utilization rate of a processor, provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a process for determining processor utilization deviation, total processor utilization deviation, and rate of change, provided in an embodiment of this application. Figure 4 This is a schematic diagram of a process for determining a target compensation amount provided in an embodiment of this application; Figure 5 This is a schematic diagram of a process for determining a set of adjustment coefficients provided in an embodiment of this application; Figure 6 This is a flowchart illustrating another multi-core processor utilization scheduling method provided in an embodiment of this application; Figure 7This is a flowchart illustrating another multi-core processor utilization scheduling method provided in the embodiments of this application; Figure 8 This is a flowchart illustrating a coarse adjustment migration process provided in an embodiment of this application; Figure 9 This is a flowchart illustrating a cross-core fine-tuning process provided in an embodiment of this application; Figure 10 This application provides a schematic flowchart of another cross-core fine-tuning process; Figure 11 A flowchart illustrating another multi-core processor utilization scheduling method provided in this application embodiment; Figure 12 This is a schematic diagram of the structure of a multi-core processor utilization scheduling device provided in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of a multi-core processor utilization scheduling device provided in an embodiment of this application. Detailed Implementation

[0024] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0026] For task scheduling in multi-core processors, the current approach involves obtaining the tasks in the ready queue of each CPU and their execution time, as well as the total number of tasks and their total execution time for each CPU. This allows for calculation of the average load and determination of whether load balancing is necessary. If adjustment is required, it typically involves migrating the lightest tasks from the most loaded core to the least loaded core, followed by continuous system monitoring and adjustments to achieve load balancing. However, this adjustment method is relatively fixed and lacks dynamic responsiveness. Furthermore, the adjustment amount does not consider historical data and trends in CPU utilization; relying solely on the first and second determination values ​​for adjustment cannot guarantee stable CPU utilization.

[0027] To address the aforementioned technical problems, embodiments of this application provide a method, apparatus, device, medium, and product for scheduling the utilization of multi-core processors. By acquiring the task utilization rate of each task across multiple processors at multiple historical time points, and obtaining the task utilization rate of each task on the target processor at the current time (the target processor being any processor among the multiple processors), the total task utilization rate of each processor across multiple historical time points and the total task utilization rate of the target processor at the current time are determined based on the task utilization rate of each task. The target processor utilization rate is then determined based on the total task utilization rate of multiple processors across multiple historical time points. Based on the target processor utilization rate and the total task utilization rate of the target processor at multiple historical time points and at the current time, the processor utilization deviation of the target processor at the current time and the total processor utilization deviation across multiple historical time points are calculated. The rate of change of the processor utilization deviation of the target processor at the current time relative to the processor utilization deviation of the previous time point is calculated. Based on the processor utilization deviation of the target processor at the current time, the total processor utilization deviation across multiple historical time points, and the rate of change, the target compensation amount for the target processor is determined. Tasks on the target processor are scheduled according to the target compensation amount. By introducing multi-dimensional compensation amounts and cross-core time-sharing operation, precise adjustment can be achieved to achieve load balancing. The system stability is improved by optimizing adjustment parameters in real time through an online self-learning mechanism. The multi-core processor utilization scheduling method provided in the embodiments of this application will be introduced below.

[0028] Figure 1 This is a flowchart illustrating a multi-core processor utilization scheduling method provided in an embodiment of this application. Figure 1 As shown, the steps of the multi-core processor utilization scheduling method specifically include: S101~S107.

[0029] S101. Obtain the task utilization rate of each task in multiple processors at multiple historical time points, and obtain the task utilization rate of each task in the target processor at the current time. The target processor is any processor among the multiple processors.

[0030] The multiple historical moments mentioned here can be understood as consecutive time slices within a historical time period. Each processor contains multiple tasks, and processor utilization can be understood as the total utilization of all tasks within the processor. Task utilization refers to the CPU utilization of each task within the processor.

[0031] Furthermore, during multi-core processor operation, to achieve load balancing, it is necessary to detect the utilization rate of each processor and determine whether tasks within the processor need to be scheduled based on the processor's utilization rate, thereby achieving load balancing. For high scheduling accuracy, firstly, within a selected historical time range, the time slice rotation length of the processor is set to one historical moment across multiple historical moments. Then, for each historical moment within the selected time range, the task utilization rate of each task within the multiple processors is obtained, as well as the task utilization rate of each task in the specified target processor at the current moment. This provides reference data for determining the utilization rate of each processor in the next step.

[0032] S102. Based on the task utilization rate corresponding to each task, determine the total task utilization rate of each processor at multiple historical moments, and the total task utilization rate of the target processor at the current moment.

[0033] Furthermore, after determining the task utilization rate for each task at different times, the total task utilization rate for multiple historical times is obtained by summing the task utilization rates of tasks across multiple historical times. Similarly, the total task utilization rate for the current time is obtained by summing the task utilization rates of the target processor at the current time, providing a reference for the next step of determining whether processor utilization requires scheduling. For example, within 10 seconds, a certain processor CPU runs three tasks: task1, task2, and task3, with each task taking 1 second, 2 seconds, and 5 seconds to run. Then, the CPU utilization rate for task1 is 10%, for task2 it is 20%, and for task3 it is 50%. The total CPU utilization rate is 80%.

[0034] S103. Determine the target processor utilization rate based on the total task utilization rate of multiple processors at multiple historical moments.

[0035] The target processor utilization rate can be understood as a reference value for processor utilization. The closer the total task utilization rate of the processor is to the target processor utilization rate, the more balanced the processor load is.

[0036] Furthermore, for multi-core processors, the processor utilization rate is obtained by using the total task utilization rate of each processor. The average utilization rate of the multi-core processors is then calculated, and the average value is taken as the target utilization rate of the processor. Processors with a utilization rate exceeding the target utilization rate are identified as processors that need to be removed from tasks, and processors with a utilization rate below the target utilization rate are identified as processors that need to be moved into tasks.

[0037] S104. Based on the target processor utilization rate and the total task utilization rate of the target processor at multiple historical moments and at the current moment, calculate the processor utilization rate deviation of the target processor at the current moment and the total processor utilization rate deviation at multiple historical moments.

[0038] After obtaining the target processor utilization rate, a reference standard for determining whether a processor needs scheduling, the difference between the target processor utilization rate and the total task utilization rate of the target processor at each historical moment is calculated. Then, the differences in total task utilization rates across multiple historical moments are summed to obtain the total processor utilization deviation across multiple historical moments. This total processor utilization deviation represents the long-term deviation of the processor. The difference between the target processor utilization rate and the total task utilization rate of the target processor at the current moment is used as the processor utilization deviation at the current moment. This deviation represents the rapid response capability to instantaneous load imbalances, providing a basis for the next step of determining whether to schedule the target processor.

[0039] S105. Calculate the rate of change of the processor utilization deviation of the target processor at the current moment relative to the processor utilization deviation of the previous moment.

[0040] Based on the processor utilization deviation at the current moment and the processor utilization deviation at the previous moment, the rate of change of the processor utilization deviation of the target processor at the current moment relative to the processor utilization deviation at the previous moment is used to reflect the load change trend of the processor.

[0041] S106. Determine the target compensation amount for the target processor based on the processor utilization deviation of the target processor at the current moment, the total processor utilization deviation at multiple historical moments, and the rate of change.

[0042] The target compensation amount for the processor is determined by using three parameters with historical data. The target compensation amount is obtained by calculating the processor utilization deviation at the current moment, the total processor utilization deviation at multiple historical moments, and the rate of change. The magnitude of the target compensation amount is used to determine whether the target processor needs to be scheduled for tasks.

[0043] S107. Schedule the tasks in the target processor according to the target compensation amount.

[0044] The target processor utilization is determined by the magnitude of the target compensation amount. When the target compensation amount exceeds a set threshold, the target processor's task utilization is considered too high, requiring scheduling to achieve load balancing. When the target compensation amount is below the set threshold, the target processor's task utilization is considered too low, requiring migration scheduling to achieve load balancing. When the target compensation amount equals the set threshold, the target processor's task utilization is considered to be in a load-balanced state, and no task scheduling is required. This allows for further limiting the target processor's task scheduling by referencing the magnitude of the target compensation amount, which represents changes in historical data, thereby improving scheduling accuracy and achieving rapid load balancing.

[0045] This application provides a multi-core processor utilization scheduling method. It involves obtaining the task utilization rate of each task across multiple processors at multiple historical time points, and obtaining the task utilization rate of each task on a target processor at the current time. The target processor is any one of the multiple processors. Based on the task utilization rate of each task, it determines the total task utilization rate of each processor across multiple historical time points, and the total task utilization rate of the target processor at the current time. Based on the total task utilization rate of multiple processors across multiple historical time points, it determines the target processor utilization rate. Finally, it determines the target processor utilization rate based on the target processor utilization rate and the total task utilization rate of the target processor at multiple historical time points and at the current time. The system calculates the processor utilization deviation of the target processor at the current moment and the total processor utilization deviation over multiple historical moments; it calculates the rate of change of the processor utilization deviation of the target processor at the current moment relative to the processor utilization deviation of the previous moment; based on the processor utilization deviation of the target processor at the current moment, the total processor utilization deviation over multiple historical moments, and the rate of change, it determines the target compensation amount for the target processor; it schedules tasks in the target processor according to the target compensation amount; it can achieve precise adjustment and load balancing by introducing multi-dimensional compensation amounts and cross-core time-sharing operation; and it improves system stability by optimizing adjustment parameters in real time through an online self-learning mechanism.

[0046] Figure 2 This is a schematic diagram of a process for determining the target utilization rate of a processor, provided in an embodiment of this application. Figure 2 This refers to the process of determining the target processor utilization rate in step S103. Figure 2 This description is based on the previous embodiment. Figure 2 The provided diagram shows that the steps for determining the target processor utilization rate specifically include: S201~S202.

[0047] S201. Sum the total task utilization of multiple processors at the current moment to obtain the total task utilization of multiple processors.

[0048] S202. The ratio of the total task utilization of multiple processors to the total number of processors is taken as the target processor utilization.

[0049] The processor utilization data at a selected time point is obtained by acquiring the total task utilization of each processor at the selected time point, and then averaging the utilization of the multi-core processors. The resulting average utilization is used as the target processor utilization.

[0050] In one possible example scenario, sum the utilization rates of all CPUs, divide by the total number of CPUs on the hardware development board (CPU_NUM), and calculate the average to obtain the target CPU utilization rate u0. The target CPU utilization rate u0 can be obtained according to Equation 1: Equation 1 in, This represents the total task utilization of each processor in a multi-core processor.

[0051] For example, suppose multiple processors are configured as CPU1, CPU2, CPU3, CPU4, and CPU5. The corresponding task utilization rates (tasks) for each processor are as follows: CPU1 (task1-20%, task2-30%), CPU2 (task1-10%, task2-30%, task3-30%), CPU3 (task1-30%, task2-40%), CPU4 (task1-25%, task2-25%), and CPU5 (task1-20%, task2-30%, task2-30%). This yields the total task utilization rates for each processor: CPU1 (50%), CPU2 (70%), CPU3 (70%), CPU4 (50%), and CPU5 (80%). The average processor utilization is calculated to obtain the target processor utilization rate u0. Therefore, the target processor utilization rate u0 = (50% + 70% + 70% + 50% + 80%) / 5 = 64%.

[0052] The process for determining the target processor utilization rate provided in this application involves selecting the total task utilization rate of the processor at a given time, then calculating the average utilization rate of the included processors, and using this average as the basis for determining whether the target processor is in a load-balanced state. This provides a basis for quickly determining the processor utilization rate.

[0053] Figure 3This is a flowchart illustrating a process for determining processor utilization deviation, total processor utilization deviation, and rate of change, provided in an embodiment of this application. Figure 3 This refers to the process of determining the processor utilization deviation and the total amount and rate of change of the processor utilization deviation in step S104. Figure 3 The description is based on the first embodiment. Figure 3 The provided diagram shows that the steps for determining the processor utilization deviation and the total amount and rate of change of the processor utilization deviation specifically include: S301~S303.

[0054] S301. The difference between the target processor's current utilization rate and the target processor utilization rate at the current moment is taken as the processor utilization rate deviation of the target processor at the current moment.

[0055] To leverage historical processing data to illustrate the impact on processor task scheduling, firstly, calculate the total task utilization u of the target processor at the current time t. t The difference between the target processor utilization rate and the corresponding target processor utilization rate u0 is used to characterize the change in the target processor's task utilization rate, thereby obtaining the target processor's processor utilization rate deviation u at the current time t. t - u0, in one possible example scenario, in the difference u t - If u0 is greater than 0, it means the current target processor utilization is greater than the target processor utilization, indicating that the processor on this core is overloaded and tasks need to be moved out; when u t - If the difference in u0 is less than 0, it means that the current target processor utilization is less than the target processor utilization, indicating that the core processor task is idle and needs to be migrated in.

[0056] S302. Based on the difference between the total task utilization rate of the target processor at multiple historical moments and the target processor utilization rate, the processor utilization rate deviation of the target processor at multiple historical moments is obtained.

[0057] S303. Sum the processor utilization deviations of the target processor at multiple historical moments to obtain the total processor utilization deviation of the target processor at multiple historical moments.

[0058] Considering the impact of historical data on processor task scheduling, the sum of the changes in total processor task utilization relative to the target processor utilization over a given period of time is selected as the total processor utilization deviation across multiple historical moments. The sum of deviations across multiple historical moments is calculated. For example, the sum of processor utilization deviations over a given period of time is calculated to reflect the cumulative effect of the deviation, denoted as […]. .

[0059] The embodiments of this application provide the determination of the total task utilization rate at the current moment and the total deviation of processor utilization rate at multiple historical moments within a historical period as a factor for determining whether the processor needs task scheduling, thereby making task scheduling of the processor more accurate.

[0060] S304. The difference between the current processor utilization deviation of the target processor and the processor utilization deviation of the previous moment is taken as the rate of change.

[0061] Given the processor utilization deviation u at the current moment. t Based on u0, determine the processor utilization deviation u from the previous time step at the current time step. t-1 - u0, thus obtaining the change in the difference between the current time and the previous time, as a factor reflecting the rate of change of the difference (u t - u0)-(u t-1 - u0). The difference in processor utilization is used as the rate of change to determine the trend of load change.

[0062] This application embodiment limits the processor task scheduling direction by defining the processor utilization deviation, the total processor utilization deviation, and the difference in processor utilization deviation as the rate of change and using historical data, thereby further optimizing the accuracy of processor task scheduling.

[0063] Figure 4 This is a schematic diagram of a process for determining the target compensation amount provided in an embodiment of this application. Figure 4 This refers to the process of determining the target compensation amount in step S106. Figure 4 The description is based on the first embodiment. Figure 4 The provided diagram shows that the steps for determining the target compensation amount specifically include: S401~S404.

[0064] S401. Calculate the load standard deviation of the target processor at multiple historical moments, and use it as the dynamic adjustment compensation coefficient of the target processor.

[0065] Considering the impact of load fluctuations, the load standard deviation over a historical period is calculated as a dynamic weighting factor. The load volatility adaptive mechanism enhances the processor's responsiveness to load fluctuations by dynamically adjusting the compensation coefficient volatility. For example, the load standard deviation of the target processor at multiple historical moments is represented by Equation 2: Equation 2 Where n represents the number of historical moments within the historical time period, t represents each historical moment within the historical time period, and the value of volatility obtained by calculating the load standard deviation is used as the dynamic adjustment compensation coefficient.

[0066] S402. Based on the preset target scheduling time, the online self-learning mechanism of parameters is used to determine the adjustment coefficient set of the target processor. The adjustment coefficient set includes a first adjustment coefficient for adjusting the processor utilization deviation at the current moment, a second adjustment coefficient for adjusting the total processor utilization deviation, a third adjustment coefficient for adjusting the rate of change, and a fourth adjustment coefficient for adjusting the dynamic adjustment compensation coefficient.

[0067] S403. Calculate the product of the dynamic adjustment compensation coefficient and the fourth adjustment coefficient, and sum the product with the first adjustment coefficient.

[0068] S404. The summation process is performed by multiplying the summed value by the product of the processor utilization deviation, the total processor utilization deviation by the product of the second adjustment coefficient, and the rate of change by the product of the third adjustment coefficient, to obtain the target compensation amount of the target processor.

[0069] In order to utilize the obtained processor utilization deviation, total processor utilization deviation, rate of change, and dynamic adjustment compensation coefficient to influence the processor's task scheduling, a set of adjustment coefficients is set, including the first adjustment coefficient k1, the second adjustment coefficient k2, the third adjustment coefficient k3, and the fourth adjustment coefficient k4.

[0070] The product of the compensation coefficient and the fourth adjustment coefficient is dynamically adjusted to obtain k4*volatility. Then, the product is summed with the first adjustment coefficient to obtain k1+k4*volatility. The product of the processed value and the processor utilization deviation is used as the first target compensation amount, resulting in (k1+k4*volatility)*(u t - u0), representing the current target processor's task utilization deviation. The product of the total processor utilization deviation and the second adjustment coefficient is used as the second target compensation amount, resulting in k2*. As a cumulative historical data term, it corrects for long-term biases. The product of the rate of change and the third adjustment coefficient is represented as k3*((u t - u0)-(u t-1 - u0) is used as the third target compensation quantity, representing the trend of change and predicting the direction of load change. The target compensation quantity comp is constructed by summing the first, second, and third target compensation quantities.

[0071] The target compensation amount comp is determined by Equation 3: Equation 3 Where comp represents the target compensation amount, k1 represents the first adjustment coefficient, k2 represents the second adjustment coefficient, k3 represents the third adjustment coefficient, k4 represents the fourth adjustment coefficient, and volatility represents the dynamic adjustment compensation coefficient. This represents the total processor task utilization at the current moment. Indicates the target processor utilization. This represents the total task utilization of the processor at a given historical moment. This represents the total processor task utilization from the previous time step to the current time step, where n represents the number of historical time steps and t represents time. This indicates the processor utilization deviation at the current moment. This indicates the total deviation in processor utilization. This represents the rate of change. The first adjustment coefficient k1, the second adjustment coefficient k2, the third adjustment coefficient k3, and the fourth adjustment coefficient k4 are obtained through online parameter self-learning mechanism training over a pre-set adjustment time.

[0072] This application embodiment sets adjustment coefficients and combines multiple adjustment coefficients with processor utilization deviation, total processor utilization deviation, rate of change, and dynamic adjustment compensation coefficients that affect the task scheduling of the target processor to obtain the target compensation amount. This highlights the impact of historical data on processor task scheduling and further obtains the judgment and control of whether the target processor needs task scheduling, thereby simplifying and optimizing the judgment process.

[0073] Figure 5 This is a schematic diagram of a process for determining a set of adjustment coefficients provided in an embodiment of this application. Figure 5 This refers to the process of determining the set of adjustment coefficients in step S402. Figure 5 This description is based on the previous embodiment. Figure 5 The provided diagram shows that the steps for determining the set of adjustment coefficients specifically include: S501~S504.

[0074] S501. Based on the target processor's adjustment time, the first adjustment coefficient, the second adjustment coefficient, the third adjustment coefficient, and the fourth adjustment coefficient in the adjustment coefficient set, an online self-learning training model is constructed.

[0075] S502. Using the pre-acquired training data, perform model training and validation on the online self-learning training model of parameters to obtain the trained online self-learning model of parameters.

[0076] First, using a pre-set adjustment time t0, calculate the first adjustment coefficient k1, the second adjustment coefficient k2, the third adjustment coefficient k3, and the fourth adjustment coefficient k4. Assuming the task scheduling process for the target processor needs to be completed within the set adjustment time t0, establish the mapping relationship between the adjustment time and the set of adjustment coefficients, and construct an online self-learning training model for the parameters. The resulting influence relationship is expressed by Equation 4: Equation 4 Based on the established mapping relationship between time and the set of adjustment coefficients, to further determine the specific relationship between time and the set of adjustment coefficients, a training data interval is selected. Multiple sets (e.g., 500 sets) of different data are arbitrarily selected within the interval (-10, 10). The aforementioned adjustment strategy is applied and tested multiple times (e.g., 500 times). The time t taken to reach the adjusted processor utilization target u0 is recorded each time. This results in a dataset of 500 sets: (k1(i), k2(i), k3(i), k4(i), t(i)), where i ranges from 0 to 499. A model is trained using scikit-learn, inputting the data from the previous step for training and validation, to obtain the mapping relationship of the model. .

[0077] S503. The square of the difference between the predicted value output by the online self-learning model and the target scheduling time is used as the objective optimization function.

[0078] S504. Based on the initial values ​​of the online self-learning model of parameters and the pre-set learning coefficients, perform gradient and iterative update processing on the objective optimization function to obtain the first adjustment coefficient, the second adjustment coefficient, the third adjustment coefficient and the fourth adjustment coefficient in the optimized adjustment coefficient set.

[0079] Based on the obtained online self-learning model with parameters, an objective function is defined to find k1, k2, k3, and k4 such that the model's predicted t value is close to the settling time t0. The objective function is defined as the square of the difference between the predicted value and the settling time t0. The objective function E is expressed in the form of Equation 5: Equation 5 After setting the objective function, calculate the gradient of the objective function. The gradient is a vector of the partial derivatives of the objective function with respect to k1, k2, k3, and k4. The gradient of the objective function is obtained through Equation 6: Equation 6 in, This represents the vector of partial derivatives of the objective function corresponding to the first adjustment coefficient k1. This represents the vector of partial derivatives of the objective function corresponding to the second adjustment coefficient k2. This represents the vector of partial derivatives of the objective function corresponding to the third adjustment coefficient k3. This represents the vector of partial derivatives of the objective function corresponding to the fourth adjustment coefficient k4.

[0080] Select initialization parameters The learning rate was set to 0.01, and the parameters were iteratively updated to find the optimal parameter values. This yields optimization equation 7: Equation 7 Where i = 1, 2, 3, 4. After multiple iterations (e.g., 1000 iterations), the final output is obtained. , which serves as the set of adjustment coefficients for the optimal value.

[0081] Substituting the optimized set of adjustment coefficients into the target compensation equation yields the target compensation value, providing a reference for the next step of determining whether the target processor needs to perform task migration out or task migration in.

[0082] The process of determining the adjustment coefficient set provided in this application embodiment involves introducing an online self-learning training model for model training and verification to obtain the mapping relationship between adjustment time and adjustment coefficient set. Then, by setting an objective function as the optimization function and using the gradient of the objective function for multiple iterations, an optimized adjustment coefficient set is obtained, thereby determining the target compensation amount of the target processor. This further supports the use of historical data as a basis for judging whether the target processor's tasks need to be scheduled, and improves the impact of historical data on processor task scheduling.

[0083] Figure 6 This is a flowchart illustrating another multi-core processor utilization scheduling method provided in an embodiment of this application. According to... Figure 6 The provided diagram illustrates the steps of the multi-core processor utilization scheduling method, specifically including: S601~S603.

[0084] S601. Determine whether the target compensation amount corresponding to the target processor is equal to zero within each preset time interval.

[0085] S602. When the target compensation amount is equal to zero, the task of controlling the target processor remains unchanged.

[0086] S603. If the target compensation amount is not equal to zero, determine the step of scheduling the tasks in the target processor according to the target compensation amount.

[0087] By calculating the target compensation amount for the target processor and analyzing historical data changes, it's determined whether task scheduling is needed. When the target compensation amount (comp) is zero, the target processor's task utilization rate changes little compared to historical rates, not reaching a point where task scheduling is required; therefore, no task migration out or migration in processing is necessary. When the target compensation amount (comp) is not zero, it indicates that the target processor's task utilization rate has changed within a certain range compared to historical rates, impacting its overall utilization, necessitating task migration out or migration in processing.

[0088] The multi-core processor utilization scheduling method provided in this application selects historical change data as the basis for determining whether the target processor needs task scheduling, and then calculates the target compensation amount of the target processor. The method uses the determination of whether the target compensation amount is zero as the basis for determining whether the target processor needs task scheduling. The conditions are simple and the judgment is fast, which can achieve the purpose of rapid analysis and judgment and improve the processing efficiency of processor task scheduling.

[0089] Figure 7 This is a flowchart illustrating another multi-core processor utilization scheduling method provided in the embodiments of this application. Figure 7 The description is based on the above embodiments. Figure 7 The provided diagram illustrates the steps of the multi-core processor utilization scheduling method, specifically including: S701~S705.

[0090] S701. When the target compensation amount is greater than zero, determine the scheduling type of the target processor as the migrated core type.

[0091] S702. Determine the migration amount based on the processor utilization deviation of the target processor, and use the maximum migration amount among the processors of the migration core type as the maximum migration compensation amount.

[0092] S703. When the target compensation amount is less than zero, determine the scheduling type of the target processor as the migration core type.

[0093] S704. Determine the migration amount corresponding to the processor of the migration core type based on the processor utilization deviation of the processor of the migration core type, and take the minimum migration amount of the processor of the migration core type as the minimum migration compensation amount.

[0094] S705: Initiate task scheduling control for each processor of each migrating core type based on the maximum migrating-out compensation amount and the minimum migrating-in compensation amount.

[0095] When the target compensation amount is greater than zero (i.e., the CPU's target compensation amount *comp* is greater than zero), the processor's scheduling type is set to a migrated-out core type, and the maximum migration amount among processors of multiple migrated-out core types is taken as the maximum migrated-out compensation amount *comp_out*. When the target compensation amount is less than zero (i.e., the CPU's target compensation amount *comp* is less than zero), the processor's scheduling type is set to a migrated-in core type, and the minimum migration amount among processors of multiple migrated-in core types is taken as the minimum migrated-in compensation amount *comp_in*. Based on the maximum migrated-out compensation amount *comp_out* and the minimum migrated-in compensation amount *comp_in*, tasks on processors of the desired migrated-out type are migrated out, and the task scheduling process ends when the processor's target utilization rate is reached. This achieves balanced scheduling and adjustment of the processor's load, improving the processor's scheduling efficiency.

[0096] The multi-core processor utilization scheduling method provided in this application uses historical data to obtain the target compensation amount for constraining processor task scheduling. Based on the value of the target compensation amount, it determines processors of either a migration-out or migration-in type. Then, according to the defined maximum migration-out compensation amount `comp_out` and minimum migration-in compensation amount `comp_in`, it performs migration-out operations on tasks on processors of the migration-out type, migrating the tasks to the processors at the target utilization level and ending the task scheduling process. This achieves balanced scheduling and adjustment of the processor load, improving processor scheduling efficiency.

[0097] Figure 8 This is a flowchart illustrating a coarse adjustment migration process provided in an embodiment of this application. Figure 8 This refers to the coarse adjustment and relocation scheduling process in step S705. Figure 8 This description is based on the previous embodiment. Figure 8 The provided diagram shows that the steps of the coarse adjustment and relocation process specifically include: S801~S805.

[0098] S801. Sort the task utilization rates of processors of the migrated core type from smallest to largest to obtain the target task utilization rate sequence.

[0099] S802. The minimum value between the absolute value of the maximum out-migration compensation and the absolute value of the minimum in-migration compensation is used as the coarse adjustment threshold.

[0100] Using the calculated target compensation amount for each processor, processors of the migration type are selected, and then sorted by the total task utilization of each processor from smallest to largest (the order is not specified, only sorting is performed), resulting in a sorted sequence of target task utilization. This provides a reference for the next step of calculating the specific migration task utilization of each migration type processor. Furthermore, using the calculated maximum migration compensation amount `comp_out` and minimum migration in compensation amount `comp_in` as references, the minimum of the absolute values ​​of the maximum migration compensation amount `abs(comp_out)` and the minimum migration in compensation amount `abs(comp_in)` is selected as the coarse adjustment threshold `min(abs(comp_out), abs(comp_in))`, serving as the basis for determining the number of tasks migrated out by a processor.

[0101] S803. If the sum of the first n items in the target task utilization rate sequence is less than the coarse adjustment threshold, and the sum of the first n+1 items in the target task utilization rate sequence is greater than the coarse adjustment threshold, the tasks in the first n items of the target task utilization rate sequence are determined as the target migration task set.

[0102] S804. Perform coarse adjustment and relocation control on tasks in the target relocation task set.

[0103] S805. If the total remaining task utilization of the processor of the migrated core type meets the preset fine-tuning threshold, perform cross-core fine-tuning control on the (n+1)th task in the target task utilization sequence.

[0104] Tasks on the outgoing processor are sorted by their total CPU utilization from smallest to largest, and the sum of their CPU utilization is calculated sequentially. The set of tasks whose sum does not exceed the minimum of the absolute values ​​of comp_out and comp_in is determined as the outgoing task set. .in, This indicates the first task in the processor. Let represent the nth task in the processor. Tasks are migrated to the target core based on a defined set of tasks to be migrated out. That is, the task utilization in the processor satisfies inequalities 1 and 2: Inequality 1 Inequality 2 Here, task[0] to task[n-1] is the set of target migration tasks consisting of the utilization rates of the first n tasks in the target task utilization rate sequence in the processor. In assembly language, task[0] to task[n-1] are represented as... This indicates that coarse-grained migration control is performed on the task utilization rate of the target migration task set. To further determine whether the processor's task utilization rate has reached the processor's target utilization rate, if the total remaining task utilization rate of the processor of the migration core type meets the preset fine-tuning threshold, cross-core fine-tuning control is performed on the (n+1)th task in the target task utilization rate sequence, and further fine-tuning is used to achieve scheduling control of the processor's tasks.

[0105] The multi-core processor utilization scheduling method provided in this application sets a target compensation amount as the basis for determining whether task scheduling is needed, and then uses two adjustment methods of coarse adjustment and fine adjustment to achieve precise scheduling of processor tasks, thereby further improving the accuracy of processor task scheduling.

[0106] Figure 9 This is a flowchart illustrating a cross-core fine-tuning process provided in an embodiment of this application. Figure 9 This refers to the cross-core fine-tuning process in step S805. Figure 9 This description is based on the previous embodiment. Figure 9 The provided diagram shows that the specific steps for cross-core fine-tuning include: S901~S905.

[0107] S901, The difference between the total remaining task utilization of the processor of the migrated core type and the target utilization of the processor is used as the fine-tuning deviation value.

[0108] S902. Determine whether the fine-tuning deviation value is greater than the fine-tuning threshold.

[0109] S903. If the fine-tuning deviation value is greater than the fine-tuning threshold, the (n+1)th item in the target task utilization sequence corresponding to the processor of the migrated core type shall be taken as the cross-core fine-tuning task.

[0110] S904. After the cross-core fine-tuning task is moved out of the corresponding outgoing core type processor, calculate the difference between the total remaining task utilization of the outgoing core type processor and the target utilization of the processor, calculate the difference between the total task utilization of each incoming core type processor and the target utilization of the processor, and determine the ratio of the calculated differences to determine the running time proportion of the cross-core fine-tuning task.

[0111] S905. Run cross-core fine-tuning tasks in segments according to the running time ratio.

[0112] After coarse tuning, a fine-tuning deviation is set between the total remaining task utilization of the outgoing core type processors and the target processor utilization. If the fine-tuning deviation exceeds a fine-tuning threshold, the ratio of the deviation of the (n+1)th task utilization in the sorted target task utilization sequence of the outgoing core type processors to the total deviation of task utilization of other incoming core type processors is calculated. This yields the runtime ratio of the current outgoing core type processor to other incoming core type processors. Cross-core fine-tuning is performed based on the runtime ratio, and the process is divided into time slices for execution according to the calculated time slice rotation method. This achieves task fine-tuning control for the outgoing core type processors.

[0113] In one possible example scenario, Figure 10 This is a flowchart illustrating another cross-core fine-tuning process provided in an embodiment of this application. According to... Figure 10 The provided diagram, using a dual-core CPU as an example, shows that in fine-tuning mode, tasks need to run across cores in a time-sharing manner. The task with the lowest current processor utilization on the outgoing processor is selected as the cross-core running task. The time ratio of the cross-core task running on different incoming processors is calculated. Assuming coarse-tuning is successful (the first n tasks have been migrated to the incoming processor), and the (n+1)th task has been migrated from the outgoing processor but not yet migrated to the incoming processor, it is in a "detached" state. At this time, the total task utilization of the outgoing processor is cpu_out, the total task utilization of the incoming processor is cpu_in, and the target processor utilization is u0. The total increase in task utilization that the outgoing processor should compensate for is u0 - cpu_out, and the total increase in task utilization that the incoming processor should increase is u0 - cpu_in. Precise adjustment is achieved by adjusting the running time ratio of the cross-core running task on different processor types. The running time ratio is determined by Equation 8: Equation 8 The (n+1)th task in the migration-out class processor is time-sharing across multiple processors according to the runtime ratio. Figure 10 The provided diagram shows that the total task utilization of the processor after migration is cpu_out, and the total task utilization of the processor after migration is cpu_in. It can be seen that the total task utilization of the two processors, cpu_out, is lower than the target utilization of the processor, u0. However, the total task utilization of cpu1 is higher than that of cpu2, indicating that the processors after migration have not achieved load balancing. The running time in cpu1 needs to be shorter than that in cpu2 in order to run in time-sharing proportion.

[0114] The multi-core processor utilization scheduling method provided in this application sets a target compensation amount to determine whether the processor needs task scheduling. If task scheduling is needed, it first uses coarse adjustment and then fine adjustment, and performs cross-core time-sharing of tasks of the migrated processor according to the time-sharing running time ratio, thereby improving the accuracy of task scheduling, solving the problem that it can only schedule the entire task utilization and cannot perform time-sharing scheduling, and improving the efficiency of processor task scheduling.

[0115] Figure 11 This is a flowchart illustrating another multi-core processor utilization scheduling method provided in an embodiment of this application. According to... Figure 11 The provided diagram illustrates the steps of the multi-core processor utilization scheduling method, specifically including: S1101~S1102.

[0116] S1101. Determine whether the processor of the migrated core type has latency-sensitive requirements.

[0117] S1102. When the processor of the migrated core type has a latency-sensitive requirement, the running time ratio of the processor of the migrated core type is increased and corrected by using a pre-set latency-sensitive factor.

[0118] Considering latency sensitivity during task scheduling, if task scheduling is set to latency-sensitive, dynamic adjustments are made, with the runtime ratio adjusted according to `base_ratio * (1 + latency_factor)`. Here, `latency_factor` is the latency sensitivity factor for task scheduling; increasing `base_ratio` can improve the runtime ratio on migrated processors. The latency sensitivity factor `latency_factor` can be set within the range [0, 1], configured by the task attributes. In one possible scenario, real-time tasks have `latency_factor = 1`, and non-real-time tasks have `latency_factor = 0`. Based on the runtime ratio of tasks on different cores, the processor affinity of cross-core tasks is dynamically modified to allow them to run in a time-sharing manner on multi-core processors, achieving the expected runtime ratio. The aforementioned steps of determining the target compensation amount are repeated, adjusting periodically at fixed time intervals to dynamically migrate tasks and ensure dynamic stability of the processor load.

[0119] The multi-core processor utilization scheduling method proposed in this application includes a task-characteristic-aware time-slice segmentation algorithm that dynamically adjusts the cross-core running time ratio based on the latency sensitivity of tasks, reducing the migration of critical tasks and minimizing performance loss caused by cache misses.

[0120] Figure 12 This is a schematic diagram of a multi-core processor utilization scheduling device provided in an embodiment of this application. Figure 12 The provided diagram illustrates that the multi-core processor utilization scheduling device specifically includes: The acquisition module 1201 is used to acquire the task utilization rate of each task in multiple processors at multiple historical time points, and to acquire the task utilization rate of each task in the target processor at the current time. The target processor is any processor among multiple processors. The determination module 1202 is used to determine the total task utilization of each processor at multiple historical moments and the total task utilization of the target processor at the current moment, based on the task utilization corresponding to each task. The determination module 1202 is also used to determine the target utilization rate of the processor based on the total task utilization rate of multiple processors at multiple historical moments; The parameter calculation module 1203 is used to calculate the processor utilization deviation of the target processor at the current moment and the total processor utilization deviation at multiple historical moments based on the target processor utilization rate and the total task utilization rate of the target processor at multiple historical moments and at the current moment. The parameter calculation module 1203 is also used to calculate the rate of change of the processor utilization deviation of the target processor at the current moment relative to the processor utilization deviation of the previous moment. The compensation module 1204 is used to determine the target compensation amount for the target processor based on the processor utilization deviation of the target processor at the current moment, the total processor utilization deviation at multiple historical moments, and the rate of change. The scheduling module 1205 is used to schedule tasks in the target processor according to the target compensation amount.

[0121] The multi-core processor utilization scheduling device provided in this embodiment can be as follows: Figure 12 The multi-core processor utilization scheduling device 100 shown can achieve Figures 1-11 For a detailed description of the technical effects of the multi-core processor utilization scheduling method shown, please refer to [link / reference]. Figures 1-11 The corresponding explanation is concise and will not be elaborated upon here.

[0122] Figure 13 This is a schematic diagram of a multi-core processor utilization scheduling device provided in an embodiment of this application. The multi-core processor utilization scheduling device includes a processor 1301 and a memory 1302 storing computer program instructions.

[0123] Specifically, the processor 1301 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0124] Memory 1302 may include mass storage for data or instructions. For example, and not limitingly, memory 1302 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 1302 may include removable or non-removable (or fixed) media. Where appropriate, memory 1302 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 1302 is non-volatile solid-state memory.

[0125] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to the first aspect of this application.

[0126] The processor 1301 implements any of the multi-core processor utilization scheduling methods in the above embodiments by reading and executing computer program instructions stored in the memory 1302.

[0127] In one example, the multi-core processor utilization scheduling device also includes a communication interface 1303 and a bus 1310. Among them, such as... Figure 13 As shown, the processor 1301, memory 1302, and communication interface 1303 are connected through bus 1310 and complete communication with each other.

[0128] The communication interface 1303 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0129] Bus 1310 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 1310 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0130] Furthermore, in conjunction with the multi-core processor utilization scheduling method in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by the processor, they implement any of the multi-core processor utilization scheduling methods in the above embodiments.

[0131] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the multi-core processor utilization scheduling methods described in the above embodiments.

[0132] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0133] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0134] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0135] The aspects of this application have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0136] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A multi-core processor utilization scheduling method, characterized in that, The method comprises the following steps: obtaining the task usage of each task in each processor at a plurality of historical moments, and obtaining the task usage of each task in a target processor at a current moment, wherein the target processor is any processor in the plurality of processors; determining the total task usage of each processor at a plurality of historical moments and the total task usage of the target processor at the current moment according to the task usage of each task; determining the target processor usage according to the total task usage of the plurality of processors at the plurality of historical moments; calculating the processor usage deviation of the target processor at the current moment and the total processor usage deviation of the target processor at the plurality of historical moments according to the target processor usage and the total task usage of the target processor at the plurality of historical moments and at the current moment; calculating the change rate of the processor usage deviation of the target processor at the current moment relative to the processor usage deviation of the target processor at a previous moment of the current moment; determining the target compensation amount of the target processor based on the processor usage deviation of the target processor at the current moment, the total processor usage deviation of the target processor at the plurality of historical moments, and the change rate; scheduling the tasks in the target processor according to the target compensation amount.

2. The method of claim 1, wherein, The method further comprises the following steps: summing the total task usage of the plurality of processors at the current moment to obtain the total task usage of the plurality of processors; taking the ratio of the total task usage of the plurality of processors to the total number of processors as the target processor usage.

3. The method of claim 1, wherein, The method further comprises the following steps: taking the difference between the total task usage of the target processor at the current moment and the target processor usage as the processor usage deviation of the target processor at the current moment; obtaining the processor usage deviation of the target processor at the plurality of historical moments based on the difference between the total task usage of the target processor at the plurality of historical moments and the target processor usage; summing the processor usage deviation of the target processor at the plurality of historical moments to obtain the total processor usage deviation of the target processor at the plurality of historical moments.

4. The method of claim 1, wherein, The method further comprises the following steps: taking the difference between the processor usage deviation of the target processor at the current moment and the processor usage deviation of the target processor at the previous moment of the current moment as the change rate. taking the difference between the processor usage deviation of the target processor at the current moment and the processor usage deviation of the target processor at the previous moment of the current moment as the change rate.

5. The method of claim 1, wherein, The target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the current time, the total amount of processor usage rate biases at multiple historical times, and the change rate, and the target compensation amount of the target processor is determined based on the processor usage rate bias of the target processor at the ​ ​ ​ ​ 6. The method of claim 5, wherein, ​ ​ ​ ​ ​ 7. The method of claim 5, wherein, ​ wherein, comp represents a target compensation amount, k1 represents a first adjustment coefficient, k2 represents a second adjustment coefficient, k3 represents a third adjustment coefficient, k4 represents a fourth adjustment coefficient, volatility represents the dynamic adjustment compensation coefficient, represents a total amount of task usage rate of a processor at a current time point, represents a target usage rate of a processor, represents a total amount of task usage rate of a processor corresponding to a historical time point, represents a total amount of task usage rate of a processor at a previous time point of a current time point, n represents a number of historical time points within a historical time period, and t represents each historical time point within the historical time period, represents a processor usage rate deviation at a current time point, represents a total amount of the processor usage rate deviation, represents the change rate.

8. The method of claim 1, wherein, ​ ​ ​ ​ 9. The method of claim 8, wherein, ​ ​ determining a migration-out amount according to a processor usage rate bias of the target processor, and taking a maximum value of the migration-out amounts of the processors of the migration-out core type as a maximum migration-out compensation amount; in a case where the target compensation amount is less than zero, determining a scheduling type of the target processor as a migration-in core type; determining a migration-in amount corresponding to the processor of the migration-in core type according to a processor usage rate bias of the processor of the migration-in core type, and taking a minimum value of the migration-in amounts of the processors of the migration-in core type as a minimum migration-in compensation amount; controlling task start scheduling of each of the processors of the migration-out core type according to the maximum migration-out compensation amount and the minimum migration-in compensation amount.

10. The method of claim 9, wherein, The controlling task start scheduling of each of the processors of the migration-out core type according to the maximum migration-out compensation amount and the minimum migration-in compensation amount comprises: sorting task usage rates of the processors of the migration-out core type from small to large to obtain a target task usage rate sequence; taking a minimum value of an absolute value of the maximum migration-out compensation amount and an absolute value of the minimum migration-in compensation amount as a coarse adjustment threshold value; in a case where a first n items in the target task usage rate sequence are less than the coarse adjustment threshold value and a first n+1 item in the target task usage rate sequence is greater than the coarse adjustment threshold value, determining tasks of the first n items in the target task usage rate sequence as a target migration-out task set; performing coarse adjustment migration-out control on the tasks in the target migration-out task set; in a case where a total amount of remaining task usage rates of the processors of the migration-out core type meets a pre-set fine adjustment threshold value, performing cross-core fine adjustment control on a task of the n+1 item in the target task usage rate sequence.

11. The method of claim 10, wherein, The performing cross-core fine adjustment control on the task of the n+1 item in the target task usage rate sequence in a case where the total amount of the remaining task usage rates of the processors of the migration-out core type meets the pre-set fine adjustment threshold value comprises: taking a difference value between the total amount of the remaining task usage rates of the processors of the migration-out core type and the processor target usage rate as a fine adjustment bias value; judging whether the fine adjustment bias value is greater than the fine adjustment threshold value; in a case where the fine adjustment bias value is greater than the fine adjustment threshold value, taking the task of the n+1 item in the target task usage rate sequence corresponding to the processor of the migration-out core type as a cross-core fine adjustment task; after the cross-core fine adjustment task is migrated out from the corresponding processor of the migration-out core type, calculating a difference value between a total amount of task usage rates of each of the processors of the migration-in core type and the processor target usage rate, performing ratio judgment on the calculated difference values, and determining a running time ratio of the cross-core fine adjustment task; performing sliced running of the cross-core fine adjustment task according to the running time ratio.

12. The method of claim 11, wherein, After the performing sliced running of the cross-core fine adjustment task according to the running time ratio, the method further comprises: determining whether the processor of the migration-out core type is set with a delay-sensitive requirement; In the case that the processor of the migration-out core type sets a delay-sensitive requirement, the running time ratio corresponding to the processor of the migration-out core type is increased by using a preset delay-sensitive factor.

13. A multi-core processor usage scheduling apparatus, comprising: The device comprises: An acquisition module is configured to acquire a task usage ratio corresponding to each task in a plurality of processors at a plurality of historical moments, and acquire a task usage ratio corresponding to each task in a target processor at a current moment, the target processor being any processor in the plurality of processors; A determination module is configured to determine a total amount of task usage ratios of each of the processors at the plurality of historical moments and a total amount of task usage ratios of the target processor at the current moment according to the task usage ratio corresponding to each task; The determination module is further configured to determine a target usage ratio of the processors according to the total amount of task usage ratios of the plurality of processors at the plurality of historical moments; A parameter calculation module is configured to calculate a processor usage ratio deviation of the target processor at the current moment and a total amount of processor usage ratio deviations of the target processor at the plurality of historical moments according to the target usage ratio of the processors and the total amount of task usage ratios corresponding to the target processor at the plurality of historical moments and at the current moment, respectively; The parameter calculation module is further configured to calculate a change rate of the processor usage ratio deviation of the target processor at the current moment relative to a processor usage ratio deviation at a moment prior to the current moment; A determination compensation module is configured to determine a target compensation amount of the target processor based on the processor usage ratio deviation of the target processor at the current moment, the total amount of processor usage ratio deviations of the target processor at the plurality of historical moments, and the change rate; A scheduling module is configured to schedule tasks in the target processor according to the target compensation amount.

14. A multi-core processor usage scheduling device, comprising: The device comprises a processor and a memory storing computer program instructions; The processor executes the computer program instructions to implement the multi-core processor usage ratio scheduling method according to any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The computer program instructions are stored on the computer readable storage medium, and the computer program instructions are executed by the processor to implement the multi-core processor usage ratio scheduling method according to any one of claims 1-12.

16. A computer program product, characterised in that, The instructions in the computer program product are executed by the processor of the electronic device, so that the electronic device performs the multi-core processor usage ratio scheduling method according to any one of claims 1-12.

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