ISAR (inverse synthetic aperture radar) imaging multichannel data high-bandwidth dual-mode transmission system and method based on FPGA (field programmable gate array)

Abstract

The invention relates to the technical field of data transmission mechanisms, in particular to an ISAR (inverse synthetic aperture radar) imaging multi-channel data high-bandwidth dual-mode transmission system based on an FPGA (field programmable gate array). The ISAR imaging multi-channel data high-bandwidth dual-mode transmission system is oriented to a plurality of independently configured data transmission channels, and each data transmission channel works cooperatively with a DDR (double data rate) data processing module A and a DDR data processing module B through a data channel selection module. A multi-channel data transmission function is realized on an FPGA platform, and the requirements of high-real-time signal processing applications such as ISAR imaging and the like on continuous high-bandwidth data transmission are met; two groups of independent DDR data processing modules A and B are adopted, the DDR data processing modules A and B correspond to independent data paths and control logics, one of the DDR data processing modules A and B executes data writing or original sequence reading operation, and the other one of the DDR data processing modules A and B executes transposition reading or other read-write operation in a clock period, so that the data processing efficiency is improved. Therefore, double-channel concurrent access is achieved, and read-write conflicts and pipeline blocking in a traditional single-channel architecture are eliminated.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of data transmission mechanisms, and particularly relates to an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system and method. BACKGROUND

[0002] Inverse Synthetic Aperture Radar (ISAR) imaging technology is widely used in the field of high-resolution target imaging and identification. With the continuous improvement of the real-time processing capability requirement of a radar system, a traditional implementation based on a general-purpose processor or a digital signal processor (DSP) has been difficult to meet the high-performance imaging requirement in terms of computing delay and data throughput. Field programmable gate array (FPGA) becomes an ideal platform for implementing ISAR imaging algorithm acceleration due to its highly parallel hardware architecture and reconfigurable characteristics.

[0003] In the ISAR signal processing flow, key algorithm modules such as envelope alignment, Keystone transformation and azimuth self-focusing usually involve multi-dimensional data rearrangement and cross-dimension access, resulting in frequent data transpose requirements in the data stream transmission process. Since the ISAR imaging data volume is large, the intermediate processing results usually need to be cached in an external DDR (Double Data Rate) memory. In the traditional implementation scheme, the data transpose operation depends on the non-continuous address jump access to the DDR storage space, causing a significant decrease in the storage bandwidth utilization, which seriously restricts the overall data throughput capacity of the system. SUMMARY

[0004] The application aims to provide an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system and method to solve the problems in the background technology.

[0005] To achieve the above object, one aspect of the present application provides a FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system, comprising a data channel selection module, a DDR data processing module A and a DDR data processing module B, the DDR data processing module A and the DDR data processing module B are the same in structure, the data channel selection module selects a specific data transmission channel according to requirements, the data channel selection module sends the data of the selected data transmission channel to one of the DDR data processing module A and the DDR data processing module B for writing, and sends the data transmission mode of the data transmission channel to one of the DDR data processing module A and the DDR data processing module B to control the reading mode thereof; the other one of the DDR data processing module A and the DDR data processing module B receives and caches the data processed by one of the DDR data processing module A and the DDR data processing module B, reads and sends to the data channel selection module in the original sequence transmission mode, and the data channel selection module distributes the received data to the selected data transmission channel, completes the scheduling and external output of data.

[0006] Preferably, the data transmission mode information comprises: Original sequence transmission mode: control the reading unit to read data from the DDR memory in row priority order; Transposed transmission mode: control the reading unit to read data from the DDR memory in column priority order to realize matrix transposition output.

[0007] Preferably, the DDR data processing module A and the DDR data processing module B each comprise: A write unit, the write port width of the write unit is 64bit, and the output port width is 512bit; A reading unit, the write port width of the reading unit is 512bit, and the output port width is 64bit; An AXI4 dual-mode control unit for generating a write command or a read command conforming to the AXI4 protocol; A MIG controller for executing the write command or the read command; A DDR memory for storing data.

[0008] Another aspect of the present application provides a FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method, comprising the following steps: S1, scheduling at least one data transmission channel through a data channel selection module, and assigning the data writing task to one of a DDR data processing module A and a DDR data processing module B for execution; S2, dispatch at least one data transmission channel through the data channel selection module, and assign its data reading task to one of the DDR data processing module A and the DDR data processing module B for execution, wherein the data reading task performs original sequence transmission mode reading or transposition transmission mode reading based on transmission mode information; S3, the other of the DDR data processing module A and the DDR data processing module B receives and caches data processed by one of the DDR data processing module A and the DDR data processing module B, and sends to the data channel selection module for output; Wherein, the data transmission channel dispatched in step S1 and step S2 is the same or different.

[0009] Preferably, step S1 specifically comprises: S11, the data channel selection module selects a specific data transmission channel m according to the demand, wherein 1≤m≤M, M is the total number of data transmission channels, and the data channel selection module receives and forwards the data of the channel to one of the DDR data processing module A and the DDR data processing module B; S12, the write unit of one of the DDR data processing module A and the DDR data processing module B completes data bit width conversion, and writes data with a bit width of 512 bits to the AXI4 dual mode control module; a first counter of 512 bit data is set to locate the current transmission data; S13, based on the address mapping formula, the write unit calculates and outputs the corresponding write burst transmission address according to the current value of the first counter, and sends it to the AXI4 dual mode control module; S14, the AXI4 dual mode control module receives 512 bit data and write burst transmission address, generates write command conforming to AXI4 protocol, and outputs data and write burst transmission address to MIG controller to complete data write operation.

[0010] Preferably, step S2 specifically comprises: S21, the data channel selection module sends the data transmission mode information of the data transmission channel m to one of the DDR data processing module A and the DDR data processing module B, wherein 1 represents original sequence transmission mode and 0 represents transposition transmission mode, and initiates reading instruction at the same time to trigger data reading operation; S22, the read unit in one of the DDR data processing module A and the DDR data processing module B completes data bit width conversion, and the write port of the read unit receives output data from the AXI4 dual mode control module; a second counter of 512 bit data is set to locate the current transmission data; S23, when set to the original sequence transmission mode, the reading unit generates the corresponding read burst transmission address in row priority access mode according to the current value of the second counter based on the address mapping formula, and outputs to the AXI4 dual-mode control module; When set to the transpose transmission mode, the reading unit generates the corresponding read burst transmission address in column priority access mode according to the current value of the second counter based on the address mapping formula, and transmits to the AXI4 dual-mode control module; S24, the AXI4 dual-mode control module receives the read burst transmission address required for reading data, generates a read command conforming to the AXI4 protocol, and accesses the DDR memory through the MIG controller to read the corresponding data; then the read data is returned to the data FIFO group of the reading unit; S25, when set to the original sequence transmission mode, the data read by the AXI4 dual-mode control module is sent to the original sequence read data FIFO group, at this time each FIFO is used to buffer the data of the same row, and the number of FIFOs in the FIFO group is the same as the number of rows of the sub-matrix to which the data belongs; When set to the transpose transmission mode, the data read by the AXI4 dual-mode control module is sent to the transpose read data FIFO group, at this time each FIFO is used to buffer the data of the same column, and the number of FIFOs in the FIFO group is the same as the number of columns of the sub-matrix to which the data belongs; S26, the reading unit reads the data of each FIFO in the data FIFO group in turn, and monitors the number of currently read data by setting the third counter; In the original sequence transmission mode, when the number of output data of a certain FIFO reaches the number of columns of the sub-matrix, the third counter triggers the switching signal, and the reading unit immediately accesses the next FIFO in a predetermined order to continue reading; In the transpose transmission mode, when the number of output data of a certain FIFO reaches the number of rows of the sub-matrix, the third counter triggers the switching signal, and the reading unit immediately accesses the next FIFO in a predetermined order to continue reading.

[0011] Preferably, step S3 specifically comprises: S31, one of the DDR data processing module A and the DDR data processing module B outputs the processed data, and transmits to the other of the DDR data processing module A and the DDR data processing module B, to realize backup caching of the data; S32, the other of the DDR data processing module A and the DDR data processing module B receives and caches the data, and sets to read the data in the original sequence transmission mode, and sends the data to the data channel selection module; S33, the data channel selection module receives data, and distributes the data to the output interface of the data transmission channel n, wherein 1<=n<=M, the scheduling and external output of the data are completed.

[0012] Preferably, the address mapping formula is: (1); In formula (1), represents the mapping result, that is, the write burst transmission address or the read burst transmission address; and respectively represent the row coordinate and the column coordinate of the current data belonging to the sub-matrix, wherein , , represents the total number of rows of the sub-matrix, represents the total number of columns of the sub-matrix; and respectively represent the row coordinate and the column coordinate of the current data in the sub-matrix, wherein , , and respectively represent the number of rows and the number of columns of the data in the sub-matrix.

[0013] Compared with the prior art, the beneficial effects of the present application are: 1. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by the present application faces multiple independently configured data transmission channels, each data transmission channel cooperates with the DDR data processing module A and the DDR data processing module B through a data channel selection module, realizes the multi-channel data transmission function on the FPGA platform, and meets the needs of high real-time signal processing applications such as ISAR imaging for continuous high-bandwidth data transmission; 2. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by the present application adopts two independent DDR data processing modules A and B, the DDR data processing module A and the DDR data processing module B correspond to independent data paths and control logic, support one to perform data writing or original sequence reading operation while the other performs transpose reading or other read-write operation in one clock cycle, thereby realizing double-channel concurrent access and eliminating read-write conflict and pipeline blocking in the traditional single-channel architecture; 3. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiment of the present application can independently configure each data transmission channel as the original sequence transmission mode or the transpose transmission mode, and dynamically switch through the control signal. In the original sequence transmission mode, the data is continuously read and written in the row priority order; in the transpose transmission mode, the block storage strategy is adopted, and the transpose output of the matrix is realized in combination with the address remapping mechanism. The transmission mode of each data transmission channel can be set independently and does not affect each other, thereby supporting the processing and flexible scheduling of multi-channel heterogeneous data streams. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The structural block diagram of the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by the embodiment of the present application is shown. Figure 2 The structural block diagram of the DDR data processing module A and the DDR data processing module B in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by the embodiment of the present application is shown. Figure 3 The flowchart of the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiment of the present application is shown. Figure 4 The schematic diagram of the original sequence transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiment of the present application is shown. Figure 5 The schematic diagram of the transpose transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiment of the present application is shown. Figure 6 The data block structure diagram in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0016] Figure 1 The structural block diagram of the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by the embodiment of the present application is shown. As shown in the figure, Figure 1As shown, the embodiment of the application provides a FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system, which comprises a data channel selection module, a DDR data processing module A and a DDR data processing module B, the structure of the DDR data processing module A and the DDR data processing module B is the same, the data channel selection module selects a specific data transmission channel according to the requirement, the data channel selection module sends the data of the selected data transmission channel to one of the DDR data processing module A and the DDR data processing module B for writing, and sends the data transmission mode of the data transmission channel to one of the DDR data processing module A and the DDR data processing module B to control the reading mode thereof; the other one of the DDR data processing module A and the DDR data processing module B receives and caches the data processed by one of the DDR data processing module A and the DDR data processing module B, reads and sends to the data channel selection module in the original sequence transmission mode, and the data channel selection module distributes the received data to the selected data transmission channel, and completes the scheduling and external output of the data.

[0017] The data channel selection module is provided with M data transmission channels, each channel can independently perform data writing and reading operation; the structure and function of the DDR data processing module A and the DDR data processing module B are the same, and each is used for writing data into a DDR memory and realizing original sequence transmission mode reading or transposition transmission mode reading according to the reading requirement.

[0018] The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by the application faces a plurality of independently configured data transmission channels, each data transmission channel cooperates with the DDR data processing module A and the DDR data processing module B through the data channel selection module, realizes the multi-channel data transmission function on the FPGA platform, and meets the requirement of continuous high-bandwidth data transmission of high real-time signal processing applications such as ISAR imaging; the application adopts two independent DDR data processing modules A and DDR data processing modules B, the DDR data processing module A and the DDR data processing module B correspond to independent data paths and control logic, support one to execute data writing or original sequence reading operation while the other one executes transposition reading or other reading and writing operation in one clock cycle, so as to realize double-channel concurrent access and eliminate the reading and writing conflict and pipeline blocking in the traditional single-channel architecture.

[0019] In one embodiment of the application, the data transmission mode information comprises: Original sequence transmission mode: control the reading unit to read data from the DDR memory in row priority order; Transposition transmission mode: control the reading unit to read data from the DDR memory in column priority order to realize matrix transposition output.

[0020] To standardize the description of the input timing and storage mapping logic of data streams, this invention unifies the input data into a row-first transmission mode, meaning that data is input sequentially according to the row order of the matrix, with each row's elements arranged consecutively. Under this convention, the original-order transmission mode maintains the row-first reading order; while the transpose transmission mode implements column-first output, equivalent to performing a matrix transpose operation.

[0021] Figure 2 This diagram illustrates the structural block diagrams of DDR data processing module A and DDR data processing module B in an FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system provided by an embodiment of the present invention. In one embodiment of the present invention, as shown... Figure 2 As shown, both DDR data processing module A and DDR data processing module B include: The writing unit has a writing port width of 64 bits and an output port width of 512 bits. The read unit has a write port width of 512 bits and an output port width of 64 bits. The AXI4 dual-mode control unit is used to generate write or read commands that conform to the AXI4 protocol. The MIG controller is used to execute write or read commands. DDR memory, which is used to store data.

[0022] Figure 3 A flowchart of a high-bandwidth dual-mode transmission method for multi-channel ISAR imaging data based on an embodiment of the present invention is shown. Figure 3 As shown, in one embodiment of the present invention, another aspect of the present invention provides a method for high-bandwidth dual-mode transmission of multi-channel data for ISAR imaging based on FPGA, comprising the following steps: S1. Schedule at least one data transmission channel through the data channel selection module and write its data to one of the DDR data processing module A and DDR data processing module B for execution. S2. At least one data transmission channel is scheduled through the data channel selection module, and its data reading task is assigned to one of the DDR data processing module A and DDR data processing module B for execution. The data reading task is performed in the original transmission mode or in the transposed transmission mode based on the transmission mode information. S3. The other of the DDR data processing modules A and B receives and buffers the data processed by one of the DDR data processing modules A and B, and sends it to the data channel selection module for output. The data transmission channels scheduled in step S1 and step S2 may be the same or different.

[0023] The number of data transmission channels described in this invention is not limited to a specific value and can be flexibly adjusted according to the actual needs of the application scenario or the resource capacity of the target hardware platform. In different embodiments, the number of channels can be set to 4, 12, or any other positive integer. Increasing or decreasing the number of channels does not change the core architecture and working principle of this invention and is therefore within the scope of protection of this invention.

[0024] The present invention provides an FPGA-based high-bandwidth dual-mode transmission method for multi-channel ISAR imaging data. Each data transmission channel can be independently configured into either in-order transmission mode or transposed transmission mode, and dynamically switched via control signals. DDR data processing module A and DDR data processing module B work collaboratively, each capable of executing their respective data transmission tasks in parallel. In in-order transmission mode, data is read and written continuously in row-priority order. In transposed transmission mode, a block storage strategy is employed, combined with an address remapping mechanism to achieve matrix transpose output. The transmission mode of each data transmission channel can be set independently without affecting each other, thus supporting the processing and flexible scheduling of multi-channel heterogeneous data streams.

[0025] In one embodiment of the present invention, step S1 specifically includes: S11. The data channel selection module selects a specific data transmission channel m according to the requirements, where 1≤m≤M, and M is the total number of data transmission channels. The data channel selection module receives and forwards the data of the channel to one of the DDR data processing module A and the DDR data processing module B. S12, the write unit of one of the DDR data processing modules A and B completes the data bit width conversion and writes the 512-bit data into the AXI4 dual-mode control module; the first counter of the 512-bit data is set to locate the current data transmission; S13. Based on the address mapping formula, the writing unit calculates and outputs the corresponding write burst transmission address according to the current value of the first counter, and sends it to the AXI4 dual-mode control module. The S14 and AXI4 dual-mode control modules receive 512-bit data and a write burst transfer address, generate a write command conforming to the AXI4 protocol, and output the data and the write burst transfer address to the MIG controller to complete the data write operation.

[0026] Figure 4 A schematic diagram of the original sequence transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by the embodiments of the present invention is shown. Figure 5This diagram illustrates the transposed transmission mode in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by an embodiment of the present invention. In one embodiment of the present invention, step S2 specifically includes: S21. The data channel selection module sends the data transmission mode information of the data transmission channel m to one of the DDR data processing module A and the DDR data processing module B. Here, 1 indicates the original transmission mode and 0 indicates the transposed transmission mode. At the same time, it initiates a read command to trigger the data read operation. S22, the read unit of one of the DDR data processing modules A and B completes the data bit width conversion, and the write port of the read unit receives the output data from the AXI4 dual-mode control module; a second counter of 512 bits is set to locate the currently transmitted data; S23. When set to in-order transmission mode, the read unit generates the corresponding read burst transmission address based on the address mapping formula and the current value of the second counter, using a row-first access method, and outputs it to the AXI4 dual-mode control module, such as... Figure 4 As shown; When set to transpose transfer mode, the read unit generates the corresponding read burst transfer address based on the address mapping formula and the current value of the second counter, using a column-first access method, and transmits it to the AXI4 dual-mode control module, such as... Figure 5 As shown; The S24 and AXI4 dual-mode control modules receive the read burst transmission address required for reading data, generate read commands conforming to the AXI4 protocol, and access the DDR memory through the MIG controller to read the corresponding data; then, the read data is sent back to the data FIFO group of the read unit. S25. When set to original order transmission mode, the data read by the AXI4 dual-mode control module is sent to the original order read data FIFO group. At this time, each FIFO is used to buffer the data of the same row. The number of FIFOs in the FIFO group is the same as the number of rows of the sub-matrix to which the data belongs. When set to transpose transmission mode, the data read by the AXI4 dual-mode control module is sent to the transpose read data FIFO group. At this time, each FIFO is used to cache the data of the same column. The number of FIFOs in this FIFO group is the same as the number of columns of the sub-matrix to which the data belongs. S26. The reading unit sequentially reads the data from each FIFO in the data FIFO group and monitors the current amount of data read by setting a third counter. In the original sequence transmission mode, when the output data of a certain FIFO reaches the number of columns of the sub-matrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading; In transposed transmission mode, when the output data of a certain FIFO reaches the number of rows of the submatrix, the third counter triggers a switching signal, and the reading unit then cyclically accesses the next FIFO in a preset order to continue reading.

[0027] In one embodiment of the present invention, step S3 specifically includes: S31. One of the DDR data processing modules A and B outputs the processed data and transmits it to the other of the DDR data processing modules A and B to achieve data backup and caching. S32, after the other of DDR data processing module A and DDR data processing module B receives and buffers the data, it is fixed to read the data in the original order transmission mode and sends the data to the data channel selection module; S33. After receiving the data, the data channel selection module allocates the data to the output interface of the data transmission channel n, where 1≤n≤M, thus completing the data scheduling and external output.

[0028] This invention proposes a multi-channel, high-bandwidth, dual-mode data transmission method based on FPGA. Utilizing a dual-group DDR memory structure and introducing a data channel selection module, it constructs a data transmission mechanism supporting high bandwidth, multiple channels, simultaneous dual-channel read / write, and flexible dual-mode switching. This effectively solves the bandwidth bottleneck and real-time performance degradation problems caused by single-channel limitations, fixed modes, and read / write conflicts in traditional architectures. It significantly improves the parallel processing capability and overall system throughput of complex ISAR imaging algorithms on the FPGA platform, providing reliable data path support for achieving high-performance, real-time ISAR imaging processing.

[0029] Figure 6 This diagram illustrates the data block structure in the FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method provided by an embodiment of the present invention. In one embodiment of the present invention, the ISAR imaging data is a block containing... OK, The data matrix consists of columns, each with a width of 64 bits. To improve data transfer bandwidth, DDR memory employs a block storage strategy, with a structure as follows: Figure 6 As shown. By Figure 6 It can be seen that the entire data matrix is ​​divided into multiple parts of size 1. OK The columns are submatrices, and the data within each submatrix is ​​stored contiguously in row-major order, with contiguous storage addresses. Furthermore, the storage arrangement between the submatrices also follows a row-major order.

[0030] Furthermore, the address mapping formula is as follows: (1); In equation (1), Indicates based on Figure 6 The mapping result of the DDR memory data block storage structure shown is the writing burst transfer address or reading burst transfer address; and These represent the row and column coordinates of the submatrix to which the current data belongs, respectively. , , This represents the total number of rows in the submatrix. This represents the total number of columns in the submatrix; and These represent the row and column coordinates of the current data within the submatrix, respectively. , , and These represent the number of rows and columns of data within the submatrix, respectively.

[0031] This invention avoids storing the complete data matrix on the FPGA on-chip storage resources through a block storage strategy and address mapping multiplexing mechanism, significantly reducing the consumption of scarce logic resources such as BRAM; at the same time, multi-channel shared control logic and dual DDR architecture improve resource utilization and achieve optimized resource configuration while ensuring high performance.

[0032] In the block storage strategy adopted in this invention, the size of the submatrix is ​​not fixed, but can be dynamically set according to the system's requirements for data transmission bandwidth, latency, and the usage of on-chip storage resources (such as BRAM) on the FPGA. In different embodiments, smaller submatrixes (such as 2×2 or 4×4) can be selected to reduce resource consumption, suitable for resource-constrained scenarios; larger submatrixes (such as 16×16 or 32×32) can be selected to improve burst transmission efficiency and bandwidth utilization. All size configurations are based on the same address mapping mechanism and read / write control logic, which fall within the technical scope of this invention.

[0033] In embodiments of the present invention, for application scenarios that do not require support for simultaneous dual-channel read / write functionality, the system architecture of the present invention can be simplified: only one DDR data processing module (e.g., only DDR data processing module A) is retained, and the data scheduling strategy is adjusted accordingly. Although this simplified version sacrifices some concurrency capabilities, it still supports multi-channel, dual-mode data transmission functions and is suitable for scenarios with strict limitations on cost, power consumption, or logic resources. This single-DDR architecture, as an alternative implementation of the present invention, does not depart from its basic technical concept and should be included within the scope of protection of the present invention.

[0034] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system, characterized in that, The data channel selection module, the DDR data processing module A and the DDR data processing module B, the structure of the DDR data processing module A and the DDR data processing module B is same, the data channel selection module selects a specific data transmission channel according to the requirement, the data channel selection module sends the data of the selected data transmission channel to one of the DDR data processing module A and the DDR data processing module B for writing, and sends the data transmission mode of the data transmission channel to one of the DDR data processing module A and the DDR data processing module B to control the reading mode thereof; the other one of the DDR data processing module A and the DDR data processing module B receives and caches the data processed by one of the DDR data processing module A and the DDR data processing module B, reads and sends to the data channel selection module in the original sequence transmission mode, and the data channel selection module distributes the received data to the selected data transmission channel, completes the scheduling and external output of the data.

2. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system according to claim 1, characterized in that, The data transmission mode information includes: Original sequence transmission mode: control the reading unit to read data from the DDR memory in row priority order; Transposition transmission mode: control the reading unit to read data from the DDR memory in column priority order to realize matrix transposition output.

3. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission system according to claim 2, characterized in that, The DDR data processing module A and the DDR data processing module B both include: The write-in unit, the write-in port width of the write-in unit is 64bit, and the output port width is 512bit; The reading unit, the write-in port width of the reading unit is 512bit, and the output port width is 64bit; The AXI4 dual-mode control unit is used for generating a write-in command or a reading command conforming to the AXI4 protocol; The MIG controller is used for executing the write-in command or the reading command; The DDR memory is used for storing data.

4. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method, characterized in that, The method includes the following steps: S1, at least one data transmission channel is scheduled by the data channel selection module, and the data writing task thereof is distributed to one of the DDR data processing module A and the DDR data processing module B for execution; S2, at least one data transmission channel is scheduled by the data channel selection module, and the data reading task thereof is distributed to one of the DDR data processing module A and the DDR data processing module B for execution, wherein the data reading task performs original sequence transmission mode reading or transposition transmission mode reading based on the transmission mode information; S3, the other one of the DDR data processing module A and the DDR data processing module B receives and caches the data processed by one of the DDR data processing module A and the DDR data processing module B, and sends to the data channel selection module for output; Wherein, the data transmission channels scheduled in steps S1 and S2 are same or different.

5. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method according to claim 4, characterized in that, Step S1 specifically includes: S11, the data channel selection module selects a specific data transmission channel m according to the requirement, wherein 1≤m≤M, M is the total number of data transmission channels, the data channel selection module receives and forwards the data of the channel to one of the DDR data processing module A and the DDR data processing module B; S12, the write unit of one of the DDR data processing module A and the DDR data processing module B completes data bit width conversion, and writes data with a bit width of 512 bits into the AXI4 dual-mode control module; a first counter of 512 bit data is set to locate the current transmission data; S13, based on the address mapping formula, the write unit calculates and outputs the corresponding write burst transmission address according to the current value of the first counter, and sends it to the AXI4 dual-mode control module; S14, the AXI4 dual-mode control module receives 512 bit data and the write burst transmission address, generates a write command conforming to the AXI4 protocol, and outputs the data and the write burst transmission address to the MIG controller to complete the data write operation.

6. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method according to claim 5, characterized in that, Step S2 specifically includes: S21, the data channel selection module sends the data transmission mode information of the data transmission channel m to one of the DDR data processing module A and the DDR data processing module B, wherein 1 represents the original sequence transmission mode, and 0 represents the transposed transmission mode, and simultaneously initiates a read instruction to trigger a data reading operation; S22, the read unit in one of the DDR data processing module A and the DDR data processing module B completes data bit width conversion, and the write port of the read unit receives the output data from the AXI4 dual-mode control module; a second counter of 512 bit data is set to locate the current transmission data; S23, when set as the original sequence transmission mode, the read unit generates the corresponding read burst transmission address according to the current value of the second counter in a row priority access mode based on the address mapping formula, and outputs it to the AXI4 dual-mode control module; When set as the transposed transmission mode, the read unit generates the corresponding read burst transmission address according to the current value of the second counter in a column priority access mode based on the address mapping formula, and transmits it to the AXI4 dual-mode control module; S24, the AXI4 dual-mode control module receives the read burst transmission address required for reading data, generates a read command conforming to the AXI4 protocol, and accesses the DDR memory through the MIG controller to read the corresponding data; then the read data is returned to the data FIFO group of the read unit; S25, when set as the original sequence transmission mode, the data read by the AXI4 dual-mode control module is sent into the original sequence read data FIFO group, at this time each FIFO is used to buffer the data of the same row, and the number of FIFOs in the FIFO group is the same as the number of rows of the sub-matrix to which the data belongs; When set as the transposed transmission mode, the data read by the AXI4 dual-mode control module is sent into the transposed read data FIFO group, at this time each FIFO is used to buffer the data of the same column, and the number of FIFOs in the FIFO group is the same as the number of columns of the sub-matrix to which the data belongs; S26, the reading unit reads the data of each FIFO in the data FIFO group in turn, and monitors the number of currently read data by setting a third counter; In the original sequence transmission mode, when the number of output data of a certain FIFO reaches the column number of the sub-matrix, the third counter triggers a switching signal, and the reading unit immediately accesses the next FIFO in a preset order to continue reading; In the transpose transmission mode, when the number of output data of a certain FIFO reaches the row number of the sub-matrix, the third counter triggers a switching signal, and the reading unit immediately accesses the next FIFO in a preset order to continue reading.

7. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method according to claim 6, characterized in that, Step S3 specifically comprises: S31, one of the DDR data processing modules A and B outputs the processed data, and transmits the data to the other of the DDR data processing modules A and B, so as to realize backup caching of the data; S32, the other of the DDR data processing modules A and B receives and caches the data, sets to read the data in the original sequence transmission mode, and sends the data to the data channel selection module; S33, the data channel selection module receives the data, allocates the data to the output interface of the data transmission channel n, where 1≤n≤M, and completes scheduling and external output of the data.

8. The FPGA-based ISAR imaging multi-channel data high-bandwidth dual-mode transmission method according to claim 7, characterized in that, The address mapping formula is: （1）； In formula (1), represents the mapping result, i.e. the write burst transfer address or the read burst transfer address; and respectively represent the row coordinate and the column coordinate of the sub-matrix to which the current data belongs, wherein , , represents the total number of rows of the sub-matrix, represents the total number of columns of the sub-matrix; and respectively represent the row coordinate and the column coordinate of the current data inside the sub-matrix, wherein , , and respectively represent the number of rows and the number of columns of the data inside the sub-matrix.

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