Method for optimizing welding spot shearing and stretching stress of chip component

Abstract

The invention discloses a method for optimizing shear and tensile stress of a welding spot of a chip component, which comprises the following steps of: establishing a finite element analysis model of the welding spot of the chip component based on ANSYA software, and obtaining a shear stress distribution rule and a tensile stress distribution rule of the welding spot of the chip component; the method comprises the following steps: determining factors (welding spot volume, gap height and bonding pad length) and level values influencing the welding spot stress of the chip component, designing 16 groups of different parameter level combinations by utilizing an orthogonal test method, and carrying out shear stress and tensile stress dual-objective optimization design on the welding spot of the chip component by combining a grey correlation analysis method. The optimal level combination with the maximum shear stress and tensile stress is obtained, simulation verification is carried out, the optimization method is simple, the effect is obvious, and certain reference significance is also achieved for structural parameter optimization of other types of welding spots.

Description

Technical Field

[0001] This invention relates to a method for optimizing the shear and tensile stress of solder joints in chip components, belonging to the field of electronic packaging reliability technology. Background Technology

[0002] Surface mount components (SMTs), or miniature components with no leads or only short leads, are designed for printed circuit boards without through-holes and are core components of surface mount technology (SMT). Renowned for their small size, light weight, excellent reliability, and superior high-frequency performance, they are widely used in various fields such as automotive, aerospace, and communications. In practical applications, the solder joints of SMTs play crucial roles in mechanical support, electrical connection, and heat conduction. However, these solder joints are often subjected to harsh environments during service, such as temperature fluctuations, vibration, and shock. These factors can cause stress concentration at the solder joints, affecting their reliability and potentially leading to electronic device failures. Therefore, excellent tensile and shear strength of the solder joints are key mechanical properties to ensure the long-term stable operation of electronic components.

[0003] In terms of optimization, orthogonal experimental design can only analyze and optimize single objectives, but cannot analyze and optimize dual objectives. Therefore, combining it with grey relational analysis solves the problem of dual objective optimization and provides a methodological guide for dual objective optimization of other types of solder joints. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of orthogonal experimental design optimization techniques by providing an optimization method based on grey relational analysis to solve the optimal combination of weld joint structural parameters, thereby minimizing both tensile and shear stresses in the weld joint and solving the problem of dual-objective optimization of weld joints.

[0005] The technical solution to achieve the objective of this invention is:

[0006] A method for optimizing the shear and tensile stress of solder joints in chip components specifically includes the following steps:

[0007] Step 1: Use ANSYS software to establish a finite element analysis model of the solder joints of the chip components;

[0008] Step 2: Obtain the shear stress and tensile stress values ​​of the weld joint;

[0009] Step 3: Determine the factors affecting the shear stress and tensile stress of the weld joint;

[0010] Step 4: Determine the parameter levels for each influencing factor;

[0011] Step 5: Use orthogonal experimental design to create 16 sets of parameter level combinations for factors affecting weld joints;

[0012] Step 6: Use ANSYS software to establish a finite element analysis model of the solder joints of the chip components with various parameter levels;

[0013] Step 7: Obtain the shear stress and tensile stress values ​​of each group of weld points;

[0014] Step 8: Normalize the shear stress and tensile stress values ​​of each group of weld joints;

[0015] Step 9: Obtain the grey relational coefficients and grey relational degrees of the shear stress and tensile stress of the weld joint;

[0016] Step 10: Obtain the average correlation between shear stress and tensile stress at each level of the weld joint for each parameter, and obtain the optimal combination of structural parameters at the weld joint level.

[0017] In step 1, the finite element simulation analysis model of the chip component solder joint is established. The dimensions of each part are as follows: chip component (L1×W1×H1) 0.60mm×0.30mm×0.25mm, pad length (L) 0.35mm, pad width (W) 0.30mm, pad thickness (D) 0.02mm, solder end coverage depth (D1) 0.1mm, pad diameter 0.41mm, pad spacing (L1) 0.30mm, PCB board size is 10×8×0.8mm, and the solder joint material in the model is lead-free solder SAC305.

[0018] In step 3, the influencing factors are solder joint volume, gap height, and pad length.

[0019] In step 4, the number of parameter levels for each influencing factor is 4.

[0020] In step 8, the dimensionless normalization formula for the stress value is:

[0021]

[0022] In the formula, X represents the original data; x represents the data after range transformation; max(x) and min(x) are the minimum and maximum values ​​in the original data sequence, respectively.

[0023] In step 9, the weighting coefficients for each solder joint of the chip component are all set to 0.5.

[0024] This invention provides a method for optimizing the shear and tensile stress of solder joints in chip components. This method is based on orthogonal experimental design and grey relational analysis to solve for the optimal combination of solder joint structural parameters, thereby minimizing both shear and tensile stress. This method combines grey relational analysis with the original orthogonal experimental design, which overcomes the limitation of orthogonal experimental design optimization methods that can only optimize a single objective, thus solving the problem of dual-objective optimization of solder joint stress. Attached Figure Description

[0025] Figure 1 This is a finite element analysis model diagram of the solder joints of chip components;

[0026] Figure 2 A cloud map showing the shear stress distribution at the solder joints of a chip component.

[0027] Figure 3 A cloud map showing the tensile stress distribution at solder joints of a chip component.

[0028] Figure 4 The optimized cloud map shows the shear stress distribution at the solder joints of the chip components.

[0029] Figure 5 This is a cloud map showing the tensile stress distribution at the solder joints of the optimized chip component. Detailed Implementation

[0030] The invention will now be described in further detail with reference to the accompanying drawings:

[0031] A method for optimizing the shear and tensile stress of solder joints in chip components specifically includes the following steps:

[0032] Step 1: Use ANSYS software to establish a finite element analysis model of the solder joints of the chip components;

[0033] Step 2: Obtain the shear stress and tensile stress values ​​of the weld joint;

[0034] Step 3: Determine the factors affecting the shear stress and tensile stress of the weld joint;

[0035] Step 4: Determine the parameter levels for each influencing factor;

[0036] Step 5: Use orthogonal experimental design to create 16 sets of parameter level combinations for factors affecting weld joints;

[0037] Step 6: Use ANSYS software to establish a finite element analysis model of the solder joints of the chip components with various parameter levels;

[0038] Step 7: Obtain the shear stress and tensile stress values ​​of each group of weld points;

[0039] Step 8: Normalize the shear stress and tensile stress values ​​of each group of weld joints;

[0040] Step 9: Obtain the grey relational coefficients and grey relational degrees of the shear stress and tensile stress of the weld joint;

[0041] Step 10: Obtain the average correlation between shear stress and tensile stress at each level of the weld joint for each parameter, and obtain the optimal combination of structural parameters at the weld joint level.

[0042] In step 1, the finite element simulation analysis model of the chip component solder joint is established. The dimensions of each part are as follows: chip component (L1×W1×H1) 0.60mm×0.30mm×0.25mm, pad length (L) 0.35mm, pad width (W) 0.30mm, pad thickness (D) 0.02mm, solder end coverage depth (D1) 0.1mm, pad diameter 0.41mm, pad spacing (L1) 0.30mm, PCB board size is 10×8×0.8mm, and the solder joint material in the model is lead-free solder SAC305.

[0043] In step 3, the influencing factors are solder joint volume, gap height, and pad length.

[0044] In step 4, the number of parameter levels for each influencing factor is 4.

[0045] In step 8, the dimensionless normalization formula for the stress value is:

[0046]

[0047] In the formula, X represents the original data; x represents the data after range transformation; max(x) and min(x) are the minimum and maximum values ​​in the original data sequence, respectively.

[0048] In step 9, the weighting coefficient λ for each solder joint of the chip component is set to 0.5.

[0049] Example:

[0050] A method for optimizing the shear and tensile stress of solder joints in chip components specifically includes the following steps:

[0051] Step 1: Use ANSYS software to create a finite element analysis model of the solder joints of the chip components. The solder joint model of the chip components is as follows: Figure 1 As shown, the material parameters are shown in Table 1;

[0052] Step 2: Obtain the shear stress and tensile stress values ​​of the weld joint. The shear stress contour plot is shown below. Figure 2 As shown, the tensile stress contour diagram is as follows: Figure 3 As shown;

[0053] Step 3: The factors affecting the shear stress and tensile stress of the solder joint are determined to be the solder joint volume, gap height and pad length. The parameter level of each influencing factor is 4, and the factor level table is shown in Table 2.

[0054] Step 4: The orthogonal experimental design was used to design 16 sets of parameter level combinations of the influencing factors of the weld joint. The finite element analysis model of the weld joint for each parameter level combination was established using ANSYS software. The maximum stress value of the weld joint under shear and tensile loading in each test group was obtained. The test combination and simulation results are shown in Table 3.

[0055] Step 5: Normalize the maximum shear and tensile stress values ​​of each group of weld points in Table 3. The dimensionless normalization formula is:

[0056]

[0057] In the formula, X represents the original data; x represents the data after range transformation; max(x) and min(x) are the minimum and maximum values ​​in the original data sequence, respectively.

[0058] Step 6: Using the grey relational analysis method, with each weight coefficient λ set to 0.5, obtain the grey relational coefficients and grey relational degrees of the maximum shear and tensile stresses of the weld joint in Table 3, as shown in Table 4.

[0059] Step 7: Obtain the average correlation between the shear stress and tensile stress of each level of the solder joint for each parameter, and obtain the optimal combination of structural parameters for the solder joint, as shown in Table 5. The optimal structural parameter levels corresponding to each factor are: solder joint volume 0.0147 mm3, gap height 0.05 mm, and pad length 0.35 mm.

[0060] Step 8: Based on the above optimal combination of structural parameters, establish the corresponding finite element analysis model of the chip device solder joints. The simulated maximum shear stress result is 57.87 MPa. Figure 4 As shown, the maximum tensile stress result is 49.50 MPa. Figure 5 As shown, the optimized parameter level combination takes into account both the increase of shear stress and tensile stress at the solder joint, achieving the dual objective optimization of the maximum shear stress and maximum tensile stress at the solder joint of the chip component, and verifying the effectiveness of the optimization method combining orthogonal experimental design and grey relational analysis.

[0061] Table 1 Material Parameters

[0062]

[0063] Table 2 Factor Levels

[0064]

[0065] Table 3 Orthogonal Experimental Design Table

[0066]

[0067]

[0068] Table 4. Grey Relation Coefficient and Relation Degree of the Two-Objective System

[0069]

[0070] Table 5. Average correlation between design variables and objective function

[0071]

[0072]

Claims

1. A method of optimizing shear and tensile stresses of a chip component solder joint, characterized in that Specifically comprising the following steps: Step 1: establishing a chip component solder joint finite element analysis model by using ANSYS software; Step 2: obtaining the shear stress and tensile stress values of the solder joint; Step 3: determining the factors affecting the shear stress and tensile stress of the solder joint; Step 4: determining the parameter level values of each influencing factor; Step 5: adopting orthogonal test to design 16 groups of parameter level combination test groups of the solder joint influencing factors; Step 6: establishing a chip component solder joint finite element analysis model of each parameter level combination by using ANSYS software; Step 7: obtaining the shear stress and tensile stress values of each group of solder joints; Step 8: performing normalization processing on the shear stress and tensile stress values of each group of solder joints; Step 9: obtaining the shear stress and tensile stress grey correlation coefficients and grey correlation degrees of the solder joint; Step 10: obtaining the average correlation degrees of the shear stress and tensile stress of each parameter level solder joint, and obtaining the optimal structure parameter level combination of the solder joint.

2. The method of claim 1, wherein the method further comprises: In the step 1, the established chip component solder joint finite element simulation analysis model has the following dimensions: chip component (L1 x W1 x H1) 0.60 mm x 0.30 mm x 0.25 mm, solder pad length (L) 0.35 mm, solder pad width (W) 0.30 mm, solder pad thickness (D) 0.02 mm, solder end coverage depth (D1) 0.1 mm, solder pad diameter 0.41 mm, solder pad pitch (L1) 0.30 mm, and the size of the PCB board is 10 x 8 x 0.8 mm. In the model, the solder joint material is lead-free solder SAC305.

3. The method of claim 1, wherein the method is for optimizing the shear and tensile stresses of a chip component solder joint. The influencing factors in the step 3 are the solder joint volume, gap height and solder pad length.

4. The method of claim 1, wherein the method is for optimizing the shear and tensile stresses of a chip component solder joint. The parameter level number of each influencing factor in the step 4 is 4.

5. The method of claim 1, wherein the method is for optimizing the shear and tensile stresses of a chip component solder joint. In the step 8, the stress value dimensionless normalization formula is: In the formula, X is the original data; x is the data after range transformation processing; max(x) and min(x) are the minimum and maximum values in the original data sequence, respectively.

6. The method of claim 1, wherein the method is for optimizing the shear and tensile stresses of a chip component solder joint. In the step 9, the weight coefficients λ of the chip component solder joint are all set to 0.5.

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