Data processing method and device

Abstract

The invention discloses a data processing method. The method comprises the following steps: acquiring first data; the first data is a two-dimensional feature in a three-dimensional feature map; obtaining a calculation result according to the first matrix and the plurality of second matrixes; wherein the first matrix is obtained according to the first data, each second matrix is a matrix constructed according to a part of elements in a convolution kernel, and the calculation result is a convolution operation result of the first data. According to the method and the device, the convolution kernel with relatively small data volume is split, so that zero insertion data expansion of the input feature map in H and W dimensions is avoided, and time consumed by data handling and calculation is saved exponentially; especially for a scene with a small input feature size, the calculation memory access ratio of the converted matrix multiplication calculation is greatly improved, the overall performance of the convolution calculation is further improved, and the operator performance in the convolution calculation is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence, and in particular to a data processing method and device thereof. BACKGROUND

[0002] Artificial intelligence (AI) is the use of digital computers or digital computer-controlled machines to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that aims to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is the design principle and implementation method of various intelligent machines, enabling machines to have perception, reasoning and decision-making functions.

[0003] Large model training and inference accelerate the advancement of neural networks in academia and industry. Large model inference can extract valuable information from complex models and solve a variety of problems such as image recognition, speech recognition, natural language processing, etc. However, the inference of large models usually requires a large amount of computing resources, which to some extent limits the universality and real-time performance of its application. Therefore, how to accelerate the inference of large models and improve their efficiency in practical applications is a problem that needs to be solved. SUMMARY

[0004] In a first aspect, the present application provides a data processing method, comprising: obtaining first data; the first data is a two-dimensional feature in a three-dimensional feature map; obtaining a calculation result according to a first matrix and a plurality of second matrices; wherein the first matrix is obtained according to the first data, each second matrix is a matrix constructed according to part of elements in a convolution kernel, and the calculation result is a convolution operation result of the first data.

[0005] Compared with the zero insertion and expansion of the feature map with a large amount of data in the prior art, in the present application, the convolution kernel with a small amount of data is split, and the matrix obtained by the split sub-convolution kernel and the matrix obtained by the input data (first data) are operated to obtain the convolution operation result, which avoids the zero insertion and expansion of the input feature map in the H and W dimensions, greatly saves the data transfer and calculation time, especially for the scene with small input feature size, the calculation memory ratio of the converted matrix multiplication calculation is greatly improved, which further improves the overall performance of the convolution calculation, and the operator performance in the convolution calculation is improved.

[0006] Each matrix row in the first matrix can be composed of partial elements in the first data, and each matrix row includes elements corresponding to one convolution operation, that is, if the first data is to be convolved, the elements in the first data corresponding to each sliding of the convolution kernel can constitute a matrix row in the first matrix.

[0007] The second matrix can be a column matrix composed of elements contained in one sub-convolution kernel in the convolution kernel.

[0008] The column matrix can be understood as: formally a column of a matrix, and each element of the column is multi-dimensional, for example, two-dimensional, and therefore, it is called a column matrix.

[0009] In a possible implementation, the method further includes: obtaining the convolution kernel; splitting the convolution kernel to obtain a plurality of sub-convolution kernels; obtaining the first matrix according to the first data; and obtaining the second matrix according to each of the sub-convolution kernels.

[0010] The first data includes a width dimension and a height dimension.

[0011] In a possible implementation, the three-dimensional feature map is an input feature map in a back propagation process of training the machine learning model.

[0012] In a possible implementation, a convolution step of a convolution operation corresponding to the convolution kernel in a forward propagation process of training the machine learning model is greater than 1. Since the convolution step is greater than 1 in the forward propagation, the size of the feature obtained by the convolution operation becomes smaller, and in the back propagation, the feature with a large size needs to be obtained based on the feature with a small size.

[0013] In a possible implementation, different elements contained in each of the sub-convolution kernels correspond to the same first remainder, and different elements contained in each of the sub-convolution kernels correspond to the same second remainder. The first remainder is a remainder obtained by dividing a position serial number of an element in the height dimension by a corresponding step, and the second remainder is a remainder obtained by dividing a position serial number of an element in the width dimension by a corresponding step.

[0014] Specifically, by performing congruence splitting and rearrangement on the convolution kernel with small data volume, redundant data transfer and calculation are effectively avoided, and the operator performance in convolution calculation is doubled. For the congruence splitting part of the convolution kernel, based on the observation and analysis of the sequence number relationship between the input and output associated data, it is proposed to split the convolution kernel and the reverse output feature map into corresponding blocks according to the congruence classification method, and each block is orthogonal to each other. For the rearrangement part of the convolution kernel, further, in the process of converting the convolution operation into matrix multiplication, the blocks of the split convolution kernel are rearranged in the N dimension of matrix multiplication, thereby converting multiple matrix multiplication operations into zero, and greatly improving the calculation memory ratio of the converted matrix multiplication, so as to further improve the operator performance.

[0015] In a possible implementation, the method further includes: splicing each of the plurality of second matrices as a column matrix to obtain a third matrix; and obtaining the calculation result according to the first matrix and the plurality of second matrices includes: obtaining the calculation result by performing operation on the first matrix and the third matrix.

[0016] In a possible implementation, obtaining the calculation result according to the first matrix and the plurality of second matrices includes: obtaining the calculation result by performing operation on the first matrix and each of the second matrices respectively.

[0017] In a possible implementation, obtaining the calculation result according to the first matrix and the plurality of second matrices includes: performing matrix multiplication operation on the first matrix and the plurality of second matrices, and rearranging elements in the matrix multiplication operation result to obtain the calculation result.

[0018] In a possible implementation, the three-dimensional feature map includes a plurality of two-dimensional features arranged in the depth dimension, the second data and the third data are different two-dimensional features in the plurality of two-dimensional features, and the method further includes: performing operation on the second data and a corresponding convolution kernel by the first processing core to obtain a first result; writing the first result into a storage space corresponding to a first address in a general memory (GM); performing operation on the third data and a corresponding convolution kernel by the first processing core to obtain a second result; triggering the general memory to perform accumulation of the first result and the second result, and replacing the first result stored in the storage space corresponding to the first address with the accumulated result.

[0019] In a possible implementation, the first processing core is configured to process an output feature map, and the first processing core is configured to process a plurality of two-dimensional features arranged in the depth dimension of the three-dimensional feature map, the plurality of two-dimensional feature maps being divided from the three-dimensional feature map based on the output feature map, and the first processing core processes the plurality of two-dimensional features based on the outer loop of the depth dimension of the input feature map.

[0020] In one possible implementation, the method further includes: the first processing core reads the second data from the dedicated memory, and the read second data is not repeated.

[0021] Therefore, the accumulation in dimension D can be performed on GM, so that the input feature map no longer needs additional inflation in dimension D, which can save time in transport by a factor of two.

[0022] Secondly, this application provides a data processing apparatus, the apparatus comprising:

[0023] The acquisition module is used to acquire first data; the first data is a two-dimensional feature in a three-dimensional feature map;

[0024] The processing module is used to obtain a calculation result based on a first matrix and multiple second matrices; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

[0025] In one possible implementation, the first data includes a width dimension and a height dimension.

[0026] In one possible implementation, the three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

[0027] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1.

[0028] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0029] In one possible implementation, the processing module is further configured to: obtain a third matrix by concatenating each of the plurality of second matrices as column matrices;

[0030] The processing module is specifically used for:

[0031] The calculation result is obtained by performing operations on the first matrix and the third matrix.

[0032] In one possible implementation, the processing module is specifically used for:

[0033] The calculation results are obtained by performing operations on the first matrix and each of the second matrices respectively.

[0034] In one possible implementation, the processing module is specifically used for:

[0035] Perform matrix multiplication on the first matrix and multiple second matrices, and rearrange the elements in the matrix multiplication result to obtain the calculation result.

[0036] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data, and the second and third data are different two-dimensional features among the multiple two-dimensional features. The processing module is further configured to:

[0037] The first processing kernel performs operations on the second data and the corresponding convolution kernel to obtain the first result.

[0038] Write the first result into the storage space corresponding to the first address in the dedicated memory (GM);

[0039] The first processing kernel performs operations on the third data and the corresponding convolution kernel to obtain the second result.

[0040] The dedicated memory is triggered to accumulate the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

[0041] In one possible implementation, the processing module is further configured to:

[0042] The first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

[0043] Thirdly, embodiments of this application provide a data processing apparatus, which may include a memory, a processor, and a bus system, wherein the memory is used to store a program, and the processor is used to execute the program in the memory to perform the methods described in the first aspect above and any of its optional methods.

[0044] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0045] Fifthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the first aspect and any of its optional methods described above.

[0046] Sixthly, this application provides a chip system including a processor for supporting an execution data processing device in implementing the functions involved in the foregoing aspects, such as transmitting or processing data involved in the foregoing methods; or, information. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the execution device or training device. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0047] FIG. 1A A structural diagram illustrating the main framework of artificial intelligence;

[0048] FIG. 1B Hezhi FIG. 1C This is a schematic diagram of the application system framework of the present invention;

[0049] FIG. 1D This is a schematic diagram of an optional hardware structure for a terminal.

[0050] FIG. 2 This is a schematic diagram of the structure of a server;

[0051] FIG. 3 This is a schematic diagram of a system architecture according to this application;

[0052] FIG. 4 This is a schematic diagram of a system architecture according to this application;

[0053] FIG. 5 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0054] FIG. 6A , FIG. 6B and FIG. 6C This is a schematic diagram of the system architecture;

[0055] FIG. 7 This is an illustration of a data processing method provided in an embodiment of this application;

[0056] FIG. 8 This is an illustration of a data processing method provided in an embodiment of this application;

[0057] FIG. 9 A schematic diagram of a framework provided for an embodiment of this application;

[0058] FIG. 10 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application;

[0059] FIG. 11 A schematic diagram of the structure of the execution device provided in the embodiments of this application;

[0060] FIG. 12A schematic diagram of the structure of the training device provided in the embodiments of this application;

[0061] FIG. 13 This is a schematic diagram of a chip structure provided in an embodiment of this application. Detailed Implementation

[0062] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0063] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0064] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0065] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” in describing embodiments of the invention refers to “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration.

[0066] First, the overall workflow of the artificial intelligence system is described; please refer to [link / reference]. FIG. 1A , FIG. 1AThe diagram illustrates a structural framework for artificial intelligence (AI). The framework is further elaborated below along two dimensions: the "Intelligent Information Chain" (horizontal axis) and the "IT Value Chain" (vertical axis). The "Intelligent Information Chain" reflects a series of processes from data acquisition to processing. For example, it could be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, and intelligent execution and output. In this process, data undergoes a condensation process of "data—information—knowledge—wisdom." The "IT Value Chain" reflects the value that AI brings to the information technology industry, from the underlying infrastructure of human intelligence and information (provided and processed through technological means) to the industrial ecosystem of the system.

[0067] (1) Infrastructure

[0068] Infrastructure provides computing power to support artificial intelligence systems, enabling communication with the external world and providing support through a basic platform. This communication occurs through sensors; computing power is provided by intelligent chips (hardware acceleration chips such as CPUs, NPUs, GPUs, ASICs, and FPGAs); and the basic platform includes distributed computing frameworks and related platform guarantees and support, which may include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to acquire data, and this data is provided to intelligent chips in the distributed computing system provided by the basic platform for computation.

[0069] (2) Data

[0070] The data at the next layer of infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data from traditional devices, including business data from existing systems and sensor data such as force, displacement, liquid level, temperature, and humidity.

[0071] (3) Data processing

[0072] Data processing typically includes methods such as data training, machine learning, deep learning, search, reasoning, and decision-making.

[0073] Among them, machine learning and deep learning can perform intelligent information modeling, extraction, preprocessing, and training on data, including symbolization and formalization.

[0074] Reasoning refers to the process in which, in a computer or intelligent system, the machine thinks and solves problems by simulating human intelligent reasoning, based on reasoning control strategies and using formalized information. Typical functions include search and matching.

[0075] Decision-making refers to the process of making decisions based on intelligent information after reasoning, and it typically provides functions such as classification, sorting, and prediction.

[0076] (4) General ability

[0077] After the data processing mentioned above, the results of the data processing can be used to form some general capabilities, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0078] (5) Smart Products and Industry Applications

[0079] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields. They are the encapsulation of overall artificial intelligence solutions, productizing intelligent information decision-making and realizing practical applications. Their application areas mainly include: intelligent terminals, intelligent transportation, intelligent healthcare, autonomous driving, smart cities, etc.

[0080] This application can be applied to the field of natural language processing in the field of artificial intelligence. The following will introduce several application scenarios that have been implemented in products, taking natural language processing as an example.

[0081] First, we will introduce the application scenarios of this application. This application can be used, but is not limited to, applications with generative artificial intelligence (AIGC) functionality (hereinafter referred to as synthetic applications) or cloud services provided by cloud-side servers, etc., which will be introduced separately below:

[0082] I. Synthesis Applications

[0083] The product form of this application embodiment can be a synthetic application. Synthetic applications can run on terminal devices or cloud-based servers.

[0084] In one possible implementation, a synthesis application can perform data generation tasks based on input data (e.g., images, text, audio, video, etc.), wherein the synthesis application can perform data generation tasks in response to the input data (e.g., images, text, audio, video, etc.) to obtain generated data.

[0085] For example, the task of generating the above data can be, but is not limited to:

[0086] Text generation task: It can generate various types of text content, including news reports, blog posts, product descriptions, social media posts, etc. It can generate logical and coherent text based on given themes and requirements.

[0087] Image generation task: This task can generate images, including illustrations, artworks, design drafts, etc. It can generate image content related to given descriptions or keywords.

[0088] Audio generation task: This task can generate speech content, including text readings and responses from voice assistants. It can simulate human speech characteristics and intonation, making the generated speech sound more natural.

[0089] Content summarization and conclusion tasks: It can read large amounts of text content and generate summaries or conclusions. It can extract key information from the text and present it to the user in a concise manner.

[0090] Language translation task: This function performs language translation, converting text from one language to another. It can handle multiple language pairs and provide accurate translation results.

[0091] Automated replies and customer service: This can be used to automatically answer user questions and provide customer service. It can understand the user's intent and provide accurate answers or suggestions.

[0092] In one possible implementation, a user can open a synthesis application installed on a terminal device and input data (such as images, text, audio, video, etc.). The synthesis application can generate data from the input data using the method provided in the embodiments of this application and present the generated data to the user (the presentation method may include, but is not limited to, displaying, saving, uploading to the cloud, etc.).

[0093] In one possible implementation, a user can open a synthesis application installed on a terminal device and input data. The synthesis application can then send the input data to a cloud-based server. The cloud-based server uses the method provided in this application to generate data from the input data and sends the generated data back to the terminal device. The terminal device can then present the generated data to the user (the presentation method may include, but is not limited to, displaying, saving, or uploading to the cloud).

[0094] The following sections will describe the synthetic application in this application from the perspectives of functional architecture and product architecture that implements the functions.

[0095] Reference FIG. 1B , FIG. 1B This is a schematic diagram of the functional architecture of the synthetic application in the embodiments of this application:

[0096] In one possible implementation, such as FIG. 1B As shown, the synthetic application 102 can receive input parameters 101 (e.g., containing input data) and generate generated data 103. The synthetic application 102 can execute on at least one computer system (for example) and includes computer code that, when executed by one or more computers, causes the computers to execute a natural language model trained by the methods provided in the embodiments of this application.

[0097] Reference FIG. 1C , FIG. 1C This is a schematic diagram of the entity architecture for running a synthetic application in the embodiments of this application:

[0098] See FIG. 1C , FIG. 1C A schematic diagram of a system architecture is shown. The system may include a terminal 100 and a server 200. The server 200 may include one or more servers (…). FIG. 1C (The example includes a server), and server 200 can provide synthesis function services for one or more terminals.

[0099] The terminal 100 may have a synthesis application installed or a webpage related to the synthesis function open. The application and webpage can provide an interface. The terminal 100 can receive relevant parameters input by the user on the synthesis function interface and send the parameters to the server 200. The server 200 can obtain the processing result based on the received parameters and return the processing result to the terminal 100.

[0100] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters on its own, without the need for the server to cooperate. This application embodiment is not limited to this.

[0101] The following description FIG. 1C The product form of the mid-terminal 100;

[0102] The terminal 100 in this application embodiment can be a mobile phone, tablet computer, wearable device, vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc., and this application embodiment does not impose any restrictions on it.

[0103] FIG. 1D A schematic diagram of an optional hardware structure for terminal 100 is shown.

[0104] refer to FIG. 1DAs shown, the terminal 100 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, a power supply 190, and other components. Those skilled in the art will understand that... FIG. 1D These are merely examples of terminals or multi-functional devices and do not constitute a limitation on terminals or multi-functional devices. They may include more or fewer components than shown in the illustration, or combine certain components, or use different components.

[0105] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 may include a touchscreen 131 (optional) and / or other input devices 132. The touchscreen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using fingers, knuckles, styluses, or any suitable object on or near the touchscreen), and drive the corresponding connection devices according to a pre-set program. The touchscreen can detect the user's touch actions, convert the touch actions into touch signals and send them to the processor 170, and can receive and execute commands sent by the processor 170; the touch signal includes at least touch point coordinate information. The touchscreen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, various types of touchscreens, such as resistive, capacitive, infrared, and surface acoustic wave, can be used to implement the touchscreen. Besides the touchscreen 131, the input unit 130 may also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons 132, power buttons 133, etc.), trackball, mouse, joystick, etc.

[0106] Among them, the input device 132 can receive input data, etc.

[0107] The display unit 140 can be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In this embodiment, the display unit 140 can be used to display the interface of a synthesis application, generated data, etc.

[0108] The memory 120 can be used to store instructions and data. The memory 120 may primarily include an instruction storage area and a data storage area. The data storage area can store various types of data, such as multimedia files and text. The instruction storage area can store software units such as operating systems, applications, and instructions required for at least one function, or subsets or extended sets thereof. It may also include non-volatile random access memory. It provides the processor 170 with hardware, software, and data resources for managing the computing device, supporting control software and applications. It is also used for storing multimedia files, as well as storing running programs and applications.

[0109] The processor 170 is the control center of the terminal 100. It connects various parts of the terminal 100 via various interfaces and lines. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it performs various functions and processes data of the terminal 100, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 170. In some embodiments, the processor and memory can be implemented on a single chip; in some embodiments, they can also be implemented separately on independent chips. The processor 170 can also be used to generate corresponding operation control signals, send them to the corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that the various functional modules therein perform corresponding functions, thereby controlling the corresponding components to act according to the instructions.

[0110] The memory 120 can be used to store software code related to the data processing method, and the processor 170 can execute the steps of the chip's data processing method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to achieve the corresponding functions.

[0111] The radio frequency unit 110 (optional) can be used for receiving and transmitting signals during information transmission or calls. For example, it can receive downlink information from the base station and process it for the processor 170; additionally, it can transmit uplink data to the base station. Typically, the RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, the radio frequency unit 110 can also communicate wirelessly with network devices and other devices. This wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0112] In this embodiment of the application, the radio frequency unit 110 can send input data to the server 200 and receive generated data sent by the server 200.

[0113] It should be understood that the radio frequency unit 110 is optional and can be replaced with other communication interfaces, such as a network port.

[0114] The terminal 100 also includes a power supply 190 (such as a battery) that supplies power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0115] Terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, which can be used to connect terminal 100 to other devices for communication or to connect a charger to charge terminal 100.

[0116] Although not shown, terminal 100 may also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with various functions, etc., which will not be described in detail here. Some or all of the methods described below can be applied to, for example... FIG. 1D In the terminal 100 shown.

[0117] The following description FIG. 1C The product form of the mid-range server 200;

[0118] FIG. 2 A structural diagram of a server 200 is provided, as follows: FIG. 2 As shown, server 200 includes bus 201, processor 202, communication interface 203, and memory 204. Processor 202, memory 204, and communication interface 203 communicate with each other via bus 201.

[0119] Bus 201 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, FIG. 2 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0120] The processor 202 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0121] Memory 204 may include volatile memory, such as random access memory (RAM). Memory 204 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0122] The memory 204 can be used to store software code related to the data processing method, and the processor 202 can execute the steps of the chip's data processing method, and can also schedule other units to achieve corresponding functions.

[0123] It should be understood that the aforementioned terminal 100 and server 200 can be centralized or distributed devices. The processors (e.g., processor 170 and processor 202) in the aforementioned terminal 100 and server 200 can be hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the processor can be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0124] It should be understood that the steps related to the model inference process in the embodiments of this application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and server is not limited to the processor-memory architecture described above. The following section will further explain... FIG. 5 The system architecture provided in the embodiments of this application will be described in detail.

[0125] FIG. 5 This is a schematic diagram of the system architecture provided for an embodiment of this application. FIG. 5 As shown, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0126] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0127] The execution device 510 can be a terminal device or a server that runs the aforementioned synthetic application.

[0128] The data acquisition device 560 is used to collect training samples. Training samples can be program files (including program code and program input data), etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0129] The training device 520 can maintain training samples in the database 530 to obtain the target model / rule 501 from the neural network to be trained.

[0130] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0131] The target model / rule 501 trained using training device 520 can be applied to different systems or devices, such as... FIG. 5 The execution device 510 shown can be a terminal, such as a mobile phone terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0132] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0133] exist FIG. 5 In the execution device 510, an input / output (I / O) interface 512 is configured for data interaction with external devices. Users can input data to the I / O interface 512 through the client device 540 (e.g., input data in the embodiment of this application).

[0134] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0135] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0136] Finally, the I / O interface 512 provides the processing results (such as generated data) to the client device 540, thereby providing them to the user.

[0137] exist FIG. 5In the illustrated scenario, the user can manually provide input data, which can be done through the interface provided by I / O interface 512. Alternatively, the client device 540 can automatically send input data to I / O interface 512. If user authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permissions in the client device 540. The user can view the output results of the execution device 510 on the client device 540, which can be presented in various ways such as display, sound, or animation. The client device 540 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530. Alternatively, data can be collected directly from the I / O interface 512 without going through the client device 540, using the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530.

[0138] It is worth noting that, FIG. 5 This is merely a schematic diagram of a system architecture provided in an embodiment of this application. The positional relationships between the devices, components, modules, etc., shown in the diagram do not constitute any limitation. For example, in FIG. 5 In this context, the data storage system 550 is an external storage device relative to the execution device 510. However, in other cases, the data storage system 550 may also be placed within the execution device 510. It should be understood that the aforementioned execution device 510 may be deployed within the client device 540.

[0139] From the inference side of the model:

[0140] In this embodiment, the computing module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the steps related to the model reasoning process in this embodiment.

[0141] In this embodiment of the application, the computing module 511 of the execution device 510 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0142] Specifically, the computing module 511 of the execution device 510 can be a hardware system with the function of executing instructions. The steps related to the model inference process provided in this application embodiment can be software code stored in the memory. The computing module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the steps related to the model inference process provided in this application embodiment.

[0143] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the model reasoning process provided in the embodiments of this application can also be implemented by the hardware system in the computing module 511 of the execution device 510 without the function of executing instructions, which is not limited here.

[0144] From the training side of the model:

[0145] In this embodiment of the application, the training device 520 can access the memory ( FIG. 6A (Not shown in the diagram, but can be integrated into the training device 520 or deployed separately from the training device 520) The code stored in the diagram can be used to implement the steps related to model training in the embodiments of this application.

[0146] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0147] It should be understood that the training device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the training of the neutralization model provided in the embodiments of this application can also be implemented by the hardware system in the training device 520 without the function of executing instructions, which is not limited here.

[0148] II. Cloud services providing synthesis functionality provided by the server:

[0149] In one possible implementation, the server can provide composition services to the client side through an application programming interface (API).

[0150] In this process, the terminal device can send relevant parameters (such as input data) to the server through the API provided by the cloud. The server can obtain the processing result (such as generated data) based on the received parameters and return the processing result to the terminal.

[0151] The description of the terminal and server can be found in the above embodiments, and will not be repeated here.

[0152] like FIG. 3 to FIG. 4 The process of using a synthetic functional cloud service provided by a cloud platform is illustrated.

[0153] 1. Activate and purchase content moderation services.

[0154] 2. Users can download the software development kit (SDK) corresponding to the content moderation service. Cloud platforms usually provide multiple development versions of the SDK for users to choose from according to their development environment needs, such as JAVA version SDK, Python version SDK, PHP version SDK, Android version SDK, etc.

[0155] 3. After downloading the corresponding version of the SDK to their local machine according to their needs, users can import the SDK project into their local development environment, configure and debug it in the local development environment, and develop other functions in the local development environment, thus forming an application that integrates the capabilities of composite functional classes.

[0156] 4. When a composition application is used, it can trigger an API call for the composition function when the composition function is required. When the application triggers the composition function, it sends an API request to the running instance of the composition function service in the cloud environment. The API request carries the input data, which is processed by the running instance in the cloud environment to obtain the processing result (such as generated data).

[0157] 5. The cloud environment returns the processing result to the application, thus completing a synthesis function service call.

[0158] In addition to applications and cloud services, the implementation of this application can also be in a large model inference acceleration library or a large model application SDK.

[0159] To better understand the solutions of the embodiments of this application, text generation will be used as an example below, combined with... FIG. 3 A brief introduction to the possible application scenarios of the embodiments of this application is provided.

[0160] FIG. 3 A natural language processing (NLP) system is illustrated, comprising user devices and data processing devices. The user devices include smart terminals such as mobile phones, personal computers, or information processing centers. The user devices are the initiators of natural language data processing, acting as the initiators of requests such as language question answering or queries; typically, users initiate requests through their user devices.

[0161] The aforementioned data processing equipment can be cloud servers, network servers, application servers, management servers, or other devices or servers with data processing capabilities. The data processing equipment receives queries / voice / text from smart terminals via an interactive interface, then performs language data processing through a storage device and a data processing processor, employing methods such as machine learning, deep learning, search, reasoning, and decision-making. The processing results are then fed back to the user device. The storage device in the data processing equipment can be a general term, including local storage and a database storing historical data. The database can be located on the data processing equipment or on other network servers.

[0162] exist FIG. 3 In the natural language processing system shown, the user device can receive instructions from the user. For example, the user device can receive a piece of text input by the user and then send a request to the data processing device, so that the data processing device can perform natural language processing applications (such as natural language generation, text classification, text reasoning, named entity recognition, translation, etc.) on the piece of text obtained by the user device, thereby obtaining the processing results of the corresponding natural language processing applications on the piece of text (such as word prediction results, classification results, reasoning results, named entity recognition results, translation results, etc.).

[0163] In this embodiment of the application, the user equipment can receive instructions from the user. For example, the user equipment can receive a piece of text input by the user (e.g., input data) and then send a request to the data processing device, so that the data processing device performs a natural language processing application (e.g., text synthesis) on the piece of text obtained by the user equipment, thereby obtaining the processing result (e.g., generated data) of the corresponding natural language processing application on the piece of text.

[0164] The text is in FIG. 4 In this application, the data processing device can process the above-mentioned text data using the method provided in the embodiments of this application.

[0165] FIG. 4 This demonstrates another natural language processing system, in FIG. 3 In this context, the user equipment (UE) directly functions as a data processing device. This UE can directly receive input from the user and process it directly through its own hardware. The specific process is similar to... FIG. 4 Similar to the description above, it will not be repeated here.

[0166] FIG. 3 This is a schematic diagram of the natural language processing related device provided in the embodiments of this application.

[0167] FIG. 4 and FIG. XThe processor in the application can perform data training / machine learning / deep learning using neural network models or other models, and use the model finally trained or learned from the data (such as the natural language model in the embodiments of this application) to perform natural language processing applications (such as program synthesis, etc.) on text data (such as the input data text described in the embodiments of this application) to obtain the corresponding processing results.

[0168] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts such as neural networks involved in the embodiments of this application will be introduced below.

[0169] (1) Neural Network

[0170] A neural network can be composed of neural units, which can be defined as a computational unit that takes xs (i.e., input data) and an intercept of 1 as input. The output of this computational unit can be:

[0171]

[0172] Where s = 1, 2, ..., n, where n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be the sigmoid function. A neural network is a network formed by connecting multiple of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0173] (2) Transformer layer

[0174] The neural network includes an embedding layer and at least one transformer layer. The at least one transformer layer can be N transformer layers (N being an integer greater than 0). Each transformer layer includes sequentially adjacent attention layers, add and normalize layers, feed-forward layers, and add and normalize layers. In the embedding layer, the current input is embedded to obtain multiple embedding vectors. In the attention layer, P input vectors are obtained from the layer above the first transformer layer. Using any first input vector among the P input vectors as the center, intermediate vectors corresponding to the first input vector are obtained based on the correlation between each input vector within a preset attention window and the first input vector. This process determines P intermediate vectors corresponding to the P input vectors. In the pooling layer, the P intermediate vectors are merged into Q output vectors, where the multiple output vectors obtained from the last transformer layer are used as feature representations of the current input.

[0175] (3) Attention mechanism

[0176] Attention mechanisms mimic the internal processes of biological observation—aligning internal experience with external senses to increase the precision of observation in specific areas. They enable the rapid sifting of high-value information from a large volume of data using limited attentional resources. Attention mechanisms can quickly extract important features from sparse data and are therefore widely used in natural language processing tasks, particularly machine translation. Self-attention mechanisms, an improvement on attention mechanisms, reduce reliance on external information and are better at capturing the internal correlations of data or features. The core idea of ​​attention mechanisms can be rewritten as follows:

[0177] In this formula, Lx = ||Source|| represents the length of the Source. The meaning is that the elements in the Source are imagined as a series of data pairs. Given a Query element in the Target, the similarity or relevance between the Query and each Key is calculated to obtain the weight coefficient of the Value corresponding to each Key. Then, the Values ​​are weighted and summed to obtain the final Attention value. Therefore, the Attention mechanism essentially performs a weighted sum of the Values ​​of the elements in the Source, while the Query and Key are used to calculate the weight coefficients of their corresponding Values. Conceptually, Attention can be understood as selectively filtering a small amount of important information from a large amount of information and focusing on this important information, ignoring most of the unimportant information. The focusing process is reflected in the calculation of the weight coefficients; the larger the weight, the more focused it is on its corresponding Value. That is, the weight represents the importance of the information, and the Value is the corresponding information. Self-attention can be understood as intra attention. The attention mechanism occurs between the elements of the Target (Query) and all elements of the Source. Self-attention refers to the attention mechanism that occurs between elements within the Source or between elements within the Target. It can also be understood as the attention calculation mechanism in the special case where Target = Source. The specific calculation process is the same, only the calculation object changes.

[0178] (4) Natural Language Processing (NLP)

[0179] Natural language is human language, and Natural Language Processing (NLP) is the processing of human language. NLP is a systematic process of analyzing, understanding, and extracting information from text data in an intelligent and efficient manner. By using NLP and its components, we can manage very large amounts of text data, perform numerous automated tasks, and solve a wide variety of problems, such as automatic summarization, machine translation (MT), named entity recognition (NER), relation extraction (RE), information extraction (IE), sentiment analysis, speech recognition, question answering systems, and topic segmentation, among others.

[0180] (5) Pre-trained language model

[0181] A pre-trained language model is a natural language sequence encoder that encodes each word in a natural language sequence into a vector representation for prediction tasks. Its training consists of two phases. In the pre-training phase, the model is trained on a large-scale unsupervised text environment to learn word representations. In the fine-tuning phase, the model is initialized using the parameters learned in the pre-training phase and then trained on downstream tasks such as text classification and sequence labeling with fewer steps, successfully transferring the semantic information obtained in pre-training to downstream tasks.

[0182] (6) Reasoning / Deployment: The forward computation process of a neural network.

[0183] (7) Large Language Model (LLM): A large language model is a natural language processing model trained on large-scale data, typically with billions or tens of billions of parameters. These models learn to capture the general features of language by learning from a large amount of text data during the pre-training stage, and can then be fine-tuned on downstream tasks to adapt to the needs of specific tasks.

[0184] (8) Matrix processing unit (cube unit): The unit in the NPU used to calculate matrix multiplication. It can only calculate matrix multiplication of data of the same type, such as integer matrix multiplication by integer matrix, or floating-point matrix multiplication by floating-point matrix. In general NPU chips, the cube unit has strong computing power.

[0185] (9) Vector processing unit: The unit used by the NPU to perform vector operations. It can perform a variety of vector operations, but its computing power is weaker than that of the Cube unit.

[0186] (10) Global memory (GM): Memory used to store data. It has a large space. The data involved in the calculation of Cube and Vector units need to be read from GM, but the bandwidth (reading speed) of reading data from GM is small.

[0187] (11) L2: L2 cache (secondary cache) is used to store data. It has a smaller space than GM and a higher read and write speed than GM. At the beginning of the calculation process, the data is located in GM and needs to enter L2 first and then enter Cube / UB; while the data coming out of Cube / UB can directly enter L2.

[0188] (12) L1: Level 1 cache, i.e., the cache in the Cube unit. The space is relatively smaller than L2, and the read and write speed is relatively higher than L2.

[0189] (13) L0A / L0B / L0C: Level 0 cache, which is a cache in the Cube cell specifically used to store computational data. It has the smallest space and the highest read and write speed. Among them, L0A / B / C are specifically used to store the left matrix / right matrix and the computation result matrix.

[0190] (14)Img2col: A hardware instruction that converts two-dimensional convolution operations into matrix multiplication. In the NPU, it is completed along the path during the data transfer process (MTE1 path).

[0191] (15) Conv2d / 3d: i.e., 2D / 3D convolution forward computation, with features as input. FIG. X The convolution kernel W is used to output the feature map Y.

[0192] (16) Conv2d / 3ddx: That is, the reverse DX calculation of 2D / 3D convolution. The input is the feature map gradient DY = dE / dY and the convolution kernel W, and the output is the feature map gradient DX = dE / dX, where E is the loss function.

[0193] (17) Conv2d / 3ddw: That is, the reverse DW calculation of 2D / 3D convolution, the input is the feature map gradient DY=dE / dY and the feature map gradient DY=dE / dY and the feature map gradient DY=dE / dY. FIG. threeThe output is the convolution kernel gradient DW = dE / dW.

[0194] Large-scale model training and inference have accelerated the technological advancement of neural networks in both academia and industry. Large-scale model inference can extract valuable information from complex models to solve a wide variety of problems, such as image recognition, speech recognition, and natural language processing. However, large-scale model inference typically requires substantial computational resources, which to some extent limits its widespread application and real-time performance. Therefore, how to accelerate large-scale model inference and improve its efficiency in practical applications is an urgent problem to be solved.

[0195] With the emergence of large multimodal models such as Sora, GPT-4o, and Gemini, the industry's demand for efficient computing power for training and inference of large multimodal models has surged dramatically. Convolutional operators, as core operators in multimodal processing, require performance optimization to improve the overall network performance for training and inference. Especially in scenarios where the stride of conv2d / 3ddx (i.e., 2D or 3D convolutional inverse DX operators) is greater than 1, existing implementations have low effective MAC utilization, with overall performance less than 25% of the theoretical hardware limit.

[0196] Since most AI acceleration hardware currently only supports the Img2col instruction for unfolding 2D feature maps, a common practice for 3D convolution operations is to unfold the 3D feature maps... FIG. 6B The outermost dimension D in the (D, H, W) dimension is expanded in an outer loop manner. Specifically, the implementation is kernel-loop coupling; that is, both the kernel and the outer loop along the D axis are divided according to the D dimension of the output feature map (D_out for the positive direction, D_in for the negative direction), and the accumulation of all reduction axes is performed in registers as inner products. FIG. 6B In the example of 3D convolution inverse DX calculation, such as... FIG. 6B As shown, both the kernel division and the outer loop are partitioned according to the D_in dimension of the output feature map DX. FIG. 6C The diagram illustrates the data transformation of the input feature map DY along the D dimension: from D_out to (D_in, D_k). In other words, existing kernel-loop coupling schemes require a forward magnification of the input feature map along the D dimension, similar to Img2col, with a magnification factor of D_k / D_s (where D_k is the size of the convolution kernel in the D dimension, and D_s is the stride size in the D dimension).

[0197] After expanding the D dimension through the outer loop, the expansion of the two internal dimensions (H, W) of the 3D feature map is performed using the hardware instruction Img2col. However, for scenarios with a stride greater than 1 in the convolutional backward DX computation, since the input feature map DY is smaller than the output feature map DX in the (H, W) dimension, the hardware instruction Img2col cannot directly convert this type of convolution computation into matrix multiplication. Existing technical solutions (such as the convolution operator in the CANN package on Ascend NPU) first perform zero-placing inflation on the input feature map DY according to the stride size, so that DY is expanded to the same size as the output feature map DX in the (H, W) dimension, and then perform convolution operation with the convolution matrix W(-H,-W) after the convolution kernel W is flipped by 180°, thereby obtaining the output feature map DX (e.g., ...). FIG. 7 (As shown).

[0198] The drawbacks of existing technologies can be summarized as the need to perform forward dilation on the input feature map data, which leads to excessive redundant handling and computation, resulting in poor operator performance.

[0199] Specifically, at the D-dimensional loop level, the kernel-loop coupling scheme inevitably requires forward scaling of the input feature map in the D dimension, resulting in significant data transport redundancy. Similarly, in scenarios where the stride in the inner dimension (H,W) is greater than 1, zero-placing inflation of the input feature map DY will also multiply the input data volume, introducing redundant transport and computation. For example, in conv3ddx, with a kernel W of size Dk=3 in the D dimension and a stride of 2 in the (H,W) dimension, existing techniques would forward scale the input feature map DY by 12 times and introduce 3 times the redundant computation.

[0200] In addition, the core-loop coupling scheme generally adopts complete sequential accumulation (or segmented accumulation on small granularities and sequential accumulation on large granularities), and the accumulation accuracy is generally lower than that of segmented accumulation on large granularities.

[0201] To address the aforementioned problems, embodiments of this application provide a data processing method. The data processing method of this application embodiment will be described in detail below with reference to the accompanying drawings.

[0202] Reference FIG. 7 , FIG. 7 This is a flowchart illustrating a data processing method provided in an embodiment of this application, such as... FIG. 8 As shown in the embodiment of this application, a data processing method may include steps 701 to 702, which are described in detail below.

[0203] 701. Obtain the first data; the first data is a two-dimensional feature in a three-dimensional feature map;

[0204] The three-dimensional feature map can include depth, height and width dimensions. The first data can be features on the same depth dimension, which can include width and height dimensions.

[0205] In one possible implementation, the three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

[0206] Of course, it can also be forward propagation.

[0207] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1.

[0208] In one possible implementation, the elements contained in the convolutional kernel can be split to obtain multiple sub-convolutional kernels;

[0209] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0210] For the inner loop of the backward computation of conv3ddx in 3D convolution, when the stride is greater than 1, the original scheme also has another case of data forward dilation, namely, zero-placing dilation of the input feature map DY. Compared with the existing scheme that performs zero-placing dilation on the large feature map DY, the embodiment of this application only performs congruential splitting and rearrangement on the convolution kernel W with a smaller data volume. A schematic diagram of the specific operation process is as follows:

[0211] Convolutional kernel congruential partitioning: First, the convolutional kernel is partitioned along the H and W dimensions according to... The differences and similarities are divided into H s ·W s In this block, "%" stands for modulo operation. A 4x4 convolution kernel W is used in H... s =W s Taking the case of 2 as an example,

[0212]

[0213] It can be decomposed into 4 ΔW matrices

[0214]

[0215] In summary, the two dimensions H and W of the convolution kernel are divided into four dimensions, namely...

[0216]

[0217] in, and These are the element indices H(W) of the convolution kernel. k Relative step size H(W) s The divisor and remainder.

[0218] Convolutional kernel rearrangement: Next, the segmented convolutional kernels are merged and rearranged. This merging and rearrangement can be divided into the following steps: a. Each convolutional kernel block ΔW is flipped 180 degrees, i.e. b. Perform `img2col` on each inverted convolutional kernel block to transform it into a column matrix; c. Concatenate each column matrix along its column dimension to form a new matrix. The four ΔW matrices in the example above become the following after these operations:

[0219]

[0220] In addition, if the size of each dimension of the convolution kernel is not an integer multiple of the stride of the corresponding dimension, a certain amount of zero-padding will be involved in the rearrangement process.

[0221] Compared to existing solutions that use zero-insertion to inflate feature maps with large amounts of data, this application avoids zero-insertion in the H and W dimensions of the input feature map by splitting the convolution kernel with smaller data size, thus saving data transfer and computation time by a factor of two. Especially for scenarios with small Cin, the computation-to-memory ratio of the transformed matrix multiplication is greatly improved, further enhancing the overall performance of convolution computation and improving the performance of operators in convolution computation.

[0222] Specifically, by performing congruential splitting and rearranging on convolution kernels with smaller data volumes, redundant data handling and computation are effectively avoided, resulting in a significant improvement in operator performance during convolution computation. For the congruential splitting of the convolution kernel, based on observation and analysis of the ordinal relationships between input and output related data, a method is proposed to split the convolution kernel and the inverse output feature map into several corresponding blocks, with each block being orthogonal to the others. Furthermore, for the rearrangement of the convolution kernel, during the transformation of convolution operations into matrix multiplication, the split convolution kernel blocks are rearranged along the N-dimensional matrix multiplication, thereby consolidating multiple matrix multiplication operations and significantly improving the computation-to-memory ratio of the transformed matrix multiplication, further enhancing operator performance.

[0223] 702. Based on the first matrix and multiple second matrices, a calculation result is obtained; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

[0224] In this first matrix, each matrix row can be composed of some elements from the first data. The elements included in each matrix row correspond to a convolution operation. That is, if convolution is to be performed on the first data, the elements in the first data corresponding to each slide of the convolution kernel can form a matrix row in the first matrix.

[0225] The second matrix can be a column matrix constructed from the elements contained in a sub-convolution kernel of the convolution kernel.

[0226] A column matrix can be understood as a column of a matrix in form, where each element of the column is multidimensional, for example, two-dimensional. Therefore, it is called a column matrix.

[0227] In one possible implementation, the method further includes: concatenating each of the plurality of second matrices as column matrices to obtain a third matrix; and then obtaining a calculation result by performing operations (e.g., matrix multiplication) on the first matrix and the third matrix.

[0228] In one possible implementation, the calculation result can be obtained by performing operations on the first matrix and each of the second matrices respectively.

[0229] In one possible implementation, matrix multiplication can be performed on the first matrix and multiple second matrices, and the elements in the matrix multiplication result can be rearranged to obtain the calculation result.

[0230] For example, the convolution operation can be transformed into matrix multiplication: the input feature map DY is transformed into the left matrix in matrix multiplication using img2col, and then multiplied by the right matrix W. ′ Multiply to obtain a matrix Due to the results obtained in the previous step It is according to (N*) (*(C in The output feature map DX is arranged in (NCHW) format and needs to be rearranged to obtain the output feature map DX in (NCHW) format.

[0231] The above steps can be performed by FIG. 9 As shown.

[0232] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data. The second data and the third data are different two-dimensional features among the multiple two-dimensional features. The second data and the corresponding convolution kernel are processed by a first processing kernel to obtain a first result. The first result is written to the storage space corresponding to a first address in the dedicated memory (GM). The third data and the corresponding convolution kernel are processed by the first processing kernel to obtain a second result. The dedicated memory is triggered to perform the accumulation of the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

[0233] In one possible implementation, the first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

[0234] To address the pain point of requiring forward amplification of input data in the outermost dimension loop-kernel coupling scheme for 3D convolution computation, this application proposes a loop-kernel decoupling scheme. Taking the reverse computation of conv3ddx as an example, to avoid deterministic problems that may arise from the accumulation of different kernels on the same memory, the kernels are still divided according to the D dimension (i.e., D_in) of the output feature map (supplemented by meticulous write order management within a single kernel); however, the outermost loop of the computation within a single kernel takes the D dimension (i.e., D_out) of the input feature map, and the Dk dimension is accumulated using an outer product method on GM to maximize the reuse of data from the reverse input feature map.

[0235] Currently, because the `img2col` hardware instruction on NPU and other chips does not support direct manipulation of 3D feature maps and convolutional kernels, existing technologies for forward and backward computation of conv3d involve looping out the D dimension, with both the outer loop and kernels divided according to the D dimension of the output matrix, resulting in loop-kernel coupling. Taking the backward computation of conv3d as an example (the forward computation is similar), excluding the batch dimension, the outermost loop and kernel dimensions are both D_in (abbreviated as Di). Inevitably, during the data transfer from the GM to the L1 cache, the data storage format of the backward input feature map DY needs to be transformed from (N, Co, Do, Ho, Wo) to (N, Di, Dk, Co1, Ho, Wo, Co0). When the D-dimensional stride Ds equals 1, the data volume is magnified by approximately Dk times, causing significant data transfer redundancy.

[0236] This application addresses this problem in existing technologies by proposing a loop-kernel decoupling solution. Taking the reverse computation of conv3d as an example, the outermost Di loop is transformed into a D_out (Do) loop. Then, in the innermost Dk (the kernel's index in dimension D) loop, the value of Di is derived by reverse calculation based on the relationship Do*Ds = Di + Dk - D_pad. Since the same Do corresponds to different Di values ​​as Dk changes, the accumulation in the Dk dimension can be performed on GM using atomic_add (i.e., the accumulation write instruction), while the accumulation in the (Co, Hk, Wk) dimension is still implemented in the register. This eliminates the need for additional inflation of the input feature map DY in the D dimension, significantly reducing processing time. Simultaneously, to avoid the deterministic problems that may arise from multi-kernel accumulation and writing on GM, the outer loop-kernel decoupling is necessary. The kernels still follow the Di dimension of the output feature map DX, with refined write logic management. For specific kernel decoupling strategies, please refer to [reference needed]. FIG. 10 (Note that the Do values ​​assigned to different cores may overlap) and the corresponding pseudocode.

[0237]

[0238]

[0239] By employing the above method, the forward data expansion of the input feature map is avoided, saving data transportation and computation time by a factor of two. Specifically, the forward data expansion of the input feature map in the D dimension is avoided, saving data transportation time by a factor of two. Furthermore, the segmented accumulation in this technique has higher accumulation accuracy than the sequential accumulation in the original technique.

[0240] Reference FIG. 10 , FIG. 10 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application, such as... FIG. 11 As shown in the embodiment of this application, a data processing apparatus 1000 is provided, the apparatus comprising:

[0241] Acquisition module 1001 is used to acquire first data; the first data is a two-dimensional feature in a three-dimensional feature map;

[0242] The processing module 1002 is used to obtain a calculation result based on a first matrix and a plurality of second matrices; wherein the first matrix is ​​obtained based on the first data, each second matrix is ​​a matrix constructed based on a portion of the elements in the convolution kernel, and the calculation result is the convolution operation result of the first data.

[0243] In one possible implementation, the first data includes a width dimension and a height dimension.

[0244] In one possible implementation, the three-dimensional feature map is the input feature map during the backpropagation process of training the machine learning model.

[0245] In one possible implementation, the convolution stride of the convolution operation corresponding to the convolution kernel during the feedforward process of training the machine learning model is greater than 1.

[0246] In one possible implementation, the first remainders corresponding to different elements contained in each sub-convolutional kernel are the same, and the second remainders corresponding to different elements contained in each sub-convolutional kernel are the same. The first remainder is the remainder obtained by dividing the position index of the element in the height dimension by the corresponding stride, and the second remainder is the remainder obtained by dividing the position index of the element in the width dimension by the corresponding stride.

[0247] In one possible implementation, the processing module 1002 is further configured to: obtain a third matrix by concatenating each of the plurality of second matrices as column matrices;

[0248] The processing module 1002 is specifically used for:

[0249] The calculation result is obtained by performing operations on the first matrix and the third matrix.

[0250] In one possible implementation, the processing module 1002 is specifically used for:

[0251] The calculation results are obtained by performing operations on the first matrix and each of the second matrices respectively.

[0252] In one possible implementation, the processing module 1002 is specifically used for:

[0253] Perform matrix multiplication on the first matrix and multiple second matrices, and rearrange the elements in the matrix multiplication result to obtain the calculation result.

[0254] In one possible implementation, the three-dimensional feature map includes multiple two-dimensional features arranged in the depth dimension, including the first data, and the second and third data are different two-dimensional features among the multiple two-dimensional features. The processing module 1002 is further configured to:

[0255] The first processing kernel performs operations on the second data and the corresponding convolution kernel to obtain the first result.

[0256] Write the first result into the storage space corresponding to the first address in the dedicated memory (GM);

[0257] The first processing kernel performs operations on the third data and the corresponding convolution kernel to obtain the second result.

[0258] The dedicated memory is triggered to accumulate the first result and the second result, and the accumulated result replaces the first result stored in the storage space corresponding to the first address.

[0259] In one possible implementation, the processing module 1002 is further configured to:

[0260] The first processing core reads the second data from the dedicated memory, and the second data read is not repeated.

[0261] The following describes a terminal device provided in an embodiment of this application. Please refer to [link to relevant documentation]. FIG. 11 , FIG. 11 This is a schematic diagram of a terminal device provided in an embodiment of this application. The terminal device 1100 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a laptop computer, a smart wearable device, etc., and is not limited thereto. Specifically, the terminal device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (wherein the number of processors 1103 in the terminal device 1100 can be one or more). FIG. 12 (Taking a processor as an example), processor 1103 may include application processor 11031 and communication processor 11032. In some embodiments of this application, receiver 1101, transmitter 1102, processor 1103 and memory 1104 may be connected via bus or other means.

[0262] Memory 1104 may include read-only memory and random access memory, and provides instructions and data to processor 1103. A portion of memory 1104 may also include non-volatile random access memory (NVRAM). Memory 1104 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0263] Processor 1103 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0264] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1103. The processor 1103 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 1103 or by instructions in software form. The processor 1103 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 1103 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1104. Processor 1103 reads the information in memory 1104 and, in conjunction with its hardware, completes the steps involved in the model training or model inference process described above.

[0265] Receiver 1101 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 1102 can be used to output digital or character information through the first interface; transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 1102 may also include a display device such as a display screen.

[0266] This application also provides a server; please refer to [link / reference]. FIG. 12 , FIG. 13This is a schematic diagram of a server structure provided in an embodiment of this application. The server 1200 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1212 (e.g., one or more processors) and memory 1232, and one or more storage media 1230 (e.g., one or more mass storage devices) for storing application programs 1242 or data 1244. The memory 1232 and storage media 1230 may be temporary or persistent storage. The program stored in the storage media 1230 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the server. Furthermore, the CPU 1212 may be configured to communicate with the storage media 1230 and execute the series of instruction operations in the storage media 1230 on the server 1200.

[0267] Server 1200 may also include one or more power supplies 1226, one or more wired or wireless network interfaces 1250, one or more input / output interfaces 1258; or, one or more operating systems 1241, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0268] In this embodiment, the central processing unit 1212 is used to perform actions related to model training or model inference in the above embodiments.

[0269] This application also provides a computer program product that, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0270] This application also provides a computer-readable storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0271] The execution device, training device, or terminal device provided in this application embodiment can specifically be a chip. The chip includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip within the execution device to execute the data processing method described in the above embodiments, or to cause the chip within the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0272] For details, please refer to FIG. 13 , ​ This is a schematic diagram of a chip provided in an embodiment of this application. The chip can be represented as a neural network processor (NPU) 1300. The NPU 1300 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 1303, which is controlled by the controller 1304 to extract matrix data from the memory and perform multiplication operations.

[0273] In some implementations, the arithmetic circuit 1303 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 1303 is a two-dimensional pulsating array. The arithmetic circuit 1303 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1303 is a general-purpose matrix processor.

[0274] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1302 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1301 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1308.

[0275] Unified memory 1306 is used to store input and output data. Weight data is directly transferred to weight memory 1302 via Direct Memory Access Controller (DMAC) 1305. Input data is also transferred to unified memory 1306 via DMAC.

[0276] BIU stands for Bus Interface Unit, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 1309.

[0277] The Bus Interface Unit (BIU) 1310 is used by the instruction fetch memory 1309 to fetch instructions from external memory, and also by the memory access controller 1305 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0278] The DMAC is mainly used to move input data from external memory DDR to unified memory 1306, or to weight data to weight memory 1302, or to input data to input memory 1301.

[0279] The vector computation unit 1307 includes multiple processing units that further process the output of the computation circuit 1303 when needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as Batch Normalization, pixel-level summation, and upsampling of feature planes.

[0280] In some implementations, the vector computation unit 1307 can store the processed output vector in the unified memory 1306. For example, the vector computation unit 1307 can apply a linear function, or a nonlinear function, to the output of the computation circuit 1303, such as performing linear interpolation on the feature planes extracted by the convolutional layer, or, for example, accumulating a vector of values ​​to generate activation values. In some implementations, the vector computation unit 1307 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as an activation input to the computation circuit 1303, for example, for use in subsequent layers of the neural network.

[0281] The instruction fetch buffer 1309 connected to the controller 1304 is used to store the instructions used by the controller 1304;

[0282] Unified memory 1306, input memory 1301, weighted memory 1302, and instruction fetch memory 1309 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0283] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0284] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0285] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0286] In the above embodiments, the implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.

[0287] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A data processing method, characterized by, The method comprises: obtaining first data; the first data is a two-dimensional feature in a three-dimensional feature map; obtaining a calculation result according to a first matrix and a plurality of second matrices; wherein the first matrix is obtained according to the first data, each second matrix is a matrix constructed according to part of elements in a convolution kernel, and the calculation result is a convolution operation result of the first data.

2. The method of claim 1, wherein, The method further comprises: obtaining a convolution kernel; splitting the convolution kernel to obtain a plurality of sub-convolution kernels; obtaining the first matrix according to the first data; obtaining a second matrix according to each sub-convolution kernel.

3. The method according to claim 1 or 2, characterized in that, Each second matrix is a matrix constructed according to a sub-convolution kernel in the convolution kernel, and the sub-convolution kernel is composed of part of elements of the convolution kernel.

4. The method according to any one of claims 1 to 3, characterized in that, Each matrix row includes part of elements in the first data, which are covered by a convolution sliding window operation on the first data by the convolution kernel.

5. The method according to any one of claims 1 to 4, characterized in that, The first data includes a width dimension and a height dimension.

6. The method according to any one of claims 1 to 5, characterized in that, The three-dimensional feature map is an input feature map in a back propagation process of training a machine learning model.

7. The method of claim 6, wherein, The convolution step of a convolution operation corresponding to the convolution kernel in a feedforward process of training the machine learning model is greater than 1.

8. The method according to any one of claims 1 to 7, characterized in that, Different elements contained in each sub-convolution kernel correspond to the same first remainder, and different elements contained in each sub-convolution kernel correspond to the same second remainder, the first remainder is a remainder obtained by dividing a position serial number of an element in the height dimension by a corresponding step, and the second remainder is a remainder obtained by dividing a position serial number of an element in the width dimension by a corresponding step.

9. The method according to any one of claims 1 to 8, characterized in that, The method further comprises: splicing each of the plurality of second matrices as a column matrix to obtain a third matrix; The calculation result is obtained according to the first matrix and the plurality of second matrices, comprising: obtaining the calculation result by operating the first matrix and the third matrix.

10. The method according to any one of claims 1 to 9, characterized in that, The calculation result is obtained according to the first matrix and the plurality of second matrices, comprising: obtaining the calculation result by operating the first matrix and each second matrix respectively.

11. The method according to any one of claims 1 to 10, characterized in that, The calculation result is obtained according to the first matrix and the plurality of second matrices, comprising: performing matrix multiplication operation on the first matrix and the plurality of second matrices, and rearranging elements in the matrix multiplication operation result to obtain the calculation result.

12. The method according to any one of claims 1 to 11, characterized in that, The three-dimensional feature map includes a plurality of two-dimensional features arranged in a depth dimension, the second data and the third data are different two-dimensional features in the plurality of two-dimensional features, and the method further comprises: performing operation on the second data and a corresponding convolution kernel by a first processing core to obtain a first result; writing the first result into a storage space corresponding to a first address in a general memory (GM); performing operation on the third data and a corresponding convolution kernel by the first processing core to obtain a second result; triggering the general memory to perform accumulation of the first result and the second result, and replacing the first result stored in the storage space corresponding to the first address with the accumulated result.

13. The method of claim 12, wherein, The first processing core is configured to process a plurality of two-dimensional features arranged in a depth dimension of the three-dimensional feature map to obtain an output feature map, the plurality of two-dimensional feature maps being determined from the three-dimensional feature map based on data contained in the output feature map, and the first processing core processes the plurality of two-dimensional features in an outer loop based on the order of the depth dimension of the plurality of two-dimensional features.

14. The method according to claim 12 or 13, characterized in that, The method further comprises: The first processing core reads the second data from the dedicated memory, and the read second data is not repeated.

15. A data processing apparatus, characterized by: The device comprises: An acquisition module is configured to acquire first data; the first data is a two-dimensional feature in a three-dimensional feature map; A processing module is configured to obtain a calculation result according to a first matrix and a plurality of second matrices; the first matrix is obtained according to the first data, each second matrix is a matrix constructed according to part of elements in a convolution kernel, and the calculation result is a convolution operation result of the first data.

16. The apparatus of claim 15, wherein, Different elements contained in each sub-convolution kernel correspond to the same first remainder, and different elements contained in each sub-convolution kernel correspond to the same second remainder; the first remainder is a remainder obtained by dividing a position serial number of an element in a height dimension by a corresponding step size, and the second remainder is a remainder obtained by dividing a position serial number of an element in a width dimension by a corresponding step size.

17. The apparatus of claim 15 or 16, wherein, The processing module is further configured to obtain a third matrix by splicing each of the plurality of second matrices as a column matrix. The processing module is specifically configured to: Obtain a calculation result by performing operations on the first matrix and the third matrix.

18. The apparatus of any one of claims 15 to 17, wherein, The processing module is specifically configured to: Obtain a calculation result by performing operations on the first matrix and each of the second matrices.

19. The apparatus of any one of claims 15 to 18, wherein, The processing module is specifically configured to: Perform matrix multiplication operations on the first matrix and the plurality of second matrices, and rearrange elements in a matrix multiplication operation result to obtain the calculation result.

20. The apparatus of any one of claims 15 to 19, wherein, The three-dimensional feature map comprises a plurality of two-dimensional features arranged in a depth dimension, including the first data, the second data and the third data are different two-dimensional features in the plurality of two-dimensional features, and the processing module is further configured to: Perform operations on the second data and a corresponding convolution kernel by a first processing core to obtain a first result; Write the first result into a storage space corresponding to a first address in a dedicated memory (GM); Perform operations on the third data and a corresponding convolution kernel by the first processing core to obtain a second result; Trigger the dedicated memory to perform accumulation of the first result and the second result, and replace the first result stored in the storage space corresponding to the first address with the accumulated result.

21. The apparatus of claim 20, wherein, The processing module is further configured to: The first processing core reads the second data from the dedicated memory, and the read second data is not repeated.

22. A computer storage medium, comprising, The computer storage medium stores one or more instructions, which, when executed by one or more computers, cause the one or more computers to perform the operations of the method in any one of claims 1 to 14.

23. A computer program product, characterised in that, Computer readable instructions, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 14.

24. A system comprising at least one processor, at least one memory; the processor, the memory being connected through a communication bus and completing communication between each other; the at least one memory is configured to store code; the at least one processor is configured to execute the code to perform the method of any one of claims 1 to 14.

25. A chip comprising a processor, wherein: the processor is configured to support a data processing apparatus to implement the method of any one of claims 1 to 14.

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