Data processing method and device

Abstract

The invention discloses a data processing method, and the method comprises the steps: carrying out a first processing process through a first instance, and enabling the first processing process to be a full-amount reasoning process through a machine learning model; performing a second processing process through a second instance, wherein the second processing process is an incremental reasoning process performed through the machine learning model; wherein the first instance and the second instance are different instances running on the same computing unit, and the first processing process and the second processing process are performed in parallel. In the embodiment of the invention, the total reasoning process and the incremental reasoning process of the machine learning model are respectively performed through different instances running on the same computing unit, so that the data communication overhead and the storage overhead between equipment are reduced, the overall end-to-end time delay is shortened, and the TPS (request per second) is correspondingly improved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence, and more particularly to a data processing method and apparatus thereof. Background Technology

[0002] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a branch of computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0003] Currently, large language models primarily employ the Transformer network structure. Characterized by self-attention, the Transformer network effectively captures key information and relationships between preceding and following words in a dialogue, resulting in better output. The Transformer network consists of multiple layers, each including Attention and FFN structures. The Attention structure uses the Q-variable of the current token and the key-value pairs (KV) of the preceding tokens to calculate the relationship between them. To accelerate the computation process, a KV cache is typically used to store the KV of the preceding tokens, reducing redundant calculations of their KV values. The processing of the first token is called the full computation phase (prefill phase), while the processing of subsequent tokens is called the incremental computation phase (decoding phase).

[0004] In existing technologies, processing in two stages using the same instance results in poor end-to-end latency and other performance issues. Alternatively, using different processing units (physically) to perform the full calculation process and the incremental calculation process separately leads to additional communication and storage overhead between hardware components. Summary of the Invention

[0005] In a first aspect, this application provides a data processing method, the method comprising: performing a first processing procedure through a first instance, the first processing procedure being a full inference process performed through a machine learning model; performing a second processing procedure through a second instance, the second processing procedure being an incremental inference process performed through the machine learning model; wherein the first instance and the second instance are different instances running on the same computing unit, and the first processing procedure and the second processing procedure are performed in parallel.

[0006] In this embodiment, the full inference process and incremental inference process of the machine learning model are performed separately by different instances running on the same computing unit. Therefore, the data communication overhead and storage overhead between devices are reduced, the overall end-to-end latency is shortened, and the number of requests per second is increased accordingly.

[0007] In one possible implementation, the method further includes: determining an allocation strategy for allocating computing resources to the first instance based on the operating performance of the computing unit; or, adjusting the allocation strategy for allocating computing resources to the second instance based on the operating performance of the computing unit.

[0008] The configuration of the aforementioned computing resources can be done at each step or even at a finer granular level, thereby increasing TPS.

[0009] In one possible implementation, the operational performance includes computing load;

[0010] The step of determining the allocation strategy for allocating computing resources to the first instance based on the operating performance of the computing unit includes:

[0011] When the computing load is below a first threshold, increase the computing resources allocated to the first instance; or,

[0012] The step of adjusting the allocation strategy for computing resources to the second instance based on the operating performance of the computing unit includes:

[0013] When the computing load exceeds the second threshold, the computing resources allocated to the second instance are reduced.

[0014] Typically, the Prefill phase is a computationally intensive task, while the Decoding phase is a memory-intensive task. Therefore, when the performance indicator on the computing unit indicates that there are more computing resources (i.e., the computing load is lower than the first threshold), the computing resources can be allocated to the first instance first. When the performance indicator on the computing unit indicates that there are fewer memory access resources (i.e., the computing load is higher than the second threshold), the computing resources allocated to the second instance can be reduced.

[0015] In one possible implementation, the operational performance includes memory access load;

[0016] The step of determining the allocation strategy for allocating computing resources to the first instance based on the operating performance of the computing unit includes:

[0017] When the memory access load exceeds a third threshold, reduce the memory access bandwidth resources allocated to the first instance; or,

[0018] The step of adjusting the allocation strategy for computing resources to the second instance based on the operating performance of the computing unit includes:

[0019] When the memory access load is below the third threshold, increase the memory access bandwidth resources allocated to the second instance.

[0020] Typically, the Prefill phase is a computationally intensive task, while the Decoding phase is a memory-intensive task. Therefore, when the performance indicator on the computing unit indicates that there are more memory resources available (e.g., the memory load is below the third threshold), computing resources can be preferentially allocated to the first instance. When the performance indicator on the computing unit indicates that there are fewer memory resources available (e.g., the memory load is above the third threshold), memory resources can be preferentially allocated to the second instance.

[0021] In one possible implementation, the runtime performance includes execution latency;

[0022] The step of determining the allocation strategy for allocating computing resources to the first instance based on the operating performance of the computing unit includes:

[0023] When the execution latency exceeds a fourth threshold, increase the computing resources allocated to the first instance; or,

[0024] The step of adjusting the allocation strategy for computing resources to the second instance based on the operating performance of the computing unit includes:

[0025] When the execution latency exceeds the fourth threshold, the memory access bandwidth resources allocated to the first instance are increased.

[0026] In one possible implementation, the method further includes:

[0027] Based on the processing load of the first instance during the first processing step, determine the allocation strategy for allocating computing resources to the first instance; or,

[0028] Based on the processing load of the second instance during the second processing procedure, adjust the allocation strategy for computing resources to the second instance.

[0029] In one possible implementation, determining the allocation strategy for allocating computing resources to the first instance based on the processing load during the first processing step includes:

[0030] When the processing load exceeds the fifth threshold, increase the computing resources allocated to the first instance; or,

[0031] The method of adjusting the allocation strategy for computing resources to the second instance based on the processing load during the second processing step includes:

[0032] When the processing load exceeds the fifth threshold, increase the memory access bandwidth resources allocated to the second instance.

[0033] In one possible implementation, the method further includes:

[0034] When the memory access bandwidth for the second processing through the second instance is less than the preset minimum bandwidth, or the execution latency is greater than the preset maximum latency, the computing resources allocated to the second instance will not be reduced.

[0035] In one possible implementation, the method further includes:

[0036] When encountering a bottleneck in memory access resources or an execution latency exceeding the preset maximum latency during the first processing through the first instance, the memory access bandwidth resources allocated to the first instance will not be reduced.

[0037] Memory access bandwidth during the Decoding phase is the most sensitive factor affecting Decoding latency, and the number of computation cores during the Prefill phase is the most sensitive factor affecting Prefill latency. When the increase in Decoding latency exceeds the maximum Decoding latency, the number of Decoding computation cores will no longer be reduced. When the Decoding bandwidth is less than the minimum Decoding bandwidth, the number of Decoding computation cores will no longer be reduced. When the increase in Prefill latency exceeds the maximum Prefill latency, the Prefill bandwidth will no longer be reduced. When Prefill is converted from a computation bond task to a memory access bond task, the Prefill bandwidth will no longer be reduced.

[0038] In one possible implementation, the method further includes:

[0039] Received processing request;

[0040] Add the full inference task in the processing request to the first queue;

[0041] Add the incremental processing task in the processing request to the second queue;

[0042] The first processing procedure includes: executing the tasks to be processed in the first queue;

[0043] The second processing procedure includes: executing the tasks to be processed in the second queue.

[0044] In one possible implementation, the machine learning model is a language model. The first processing step includes loading the parameters of the language model, obtaining a processing request, executing the processing request using the parameters of the language model, and obtaining key-value data and a newly generated first token. The second processing step includes loading the parameters of the language model, obtaining key-value data from the key-value cache, and obtaining the key-value data of the first token and a newly generated second token using the parameters of the language model.

[0045] Secondly, this application provides a data processing apparatus, the apparatus comprising:

[0046] The full inference module is used to perform a first processing procedure through a first instance, wherein the first processing procedure is a full inference procedure performed through a machine learning model.

[0047] An incremental inference module is used to perform a second processing procedure through a second instance, the second processing procedure being an incremental inference procedure performed through the machine learning model; wherein the first instance and the second instance are different instances running on the same computing unit, and the first processing procedure and the second processing procedure are performed in parallel.

[0048] In one possible implementation, the device further includes:

[0049] The control module is configured to determine an allocation strategy for allocating computing resources to the first instance based on the operating performance of the computing unit; or,

[0050] Based on the operating performance of the computing unit, the allocation strategy for allocating computing resources to the second instance is adjusted.

[0051] In one possible implementation, the operational performance includes computing load;

[0052] The control module is specifically used for:

[0053] When the computing load is below a first threshold, increase the computing resources allocated to the first instance; or,

[0054] When the computing load exceeds the second threshold, the computing resources allocated to the second instance are reduced.

[0055] In one possible implementation, the operational performance includes memory access load;

[0056] The control module is specifically used for:

[0057] When the memory access load exceeds a third threshold, reduce the memory access bandwidth resources allocated to the first instance; or,

[0058] When the memory access load is below the third threshold, increase the memory access bandwidth resources allocated to the second instance.

[0059] In one possible implementation, the runtime performance includes execution latency;

[0060] The control module is specifically used for:

[0061] When the execution latency exceeds a fourth threshold, increase the computing resources allocated to the first instance; or,

[0062] When the execution latency exceeds the fourth threshold, the memory access bandwidth resources allocated to the first instance are increased.

[0063] In one possible implementation, the device further includes:

[0064] The control module is configured to determine an allocation strategy for computing resources to be allocated to the first instance based on the processing load during the first processing step; or,

[0065] Based on the processing load of the second instance during the second processing procedure, adjust the allocation strategy for computing resources to the second instance.

[0066] In one possible implementation, the control module is specifically used for:

[0067] When the processing load exceeds the fifth threshold, increase the computing resources allocated to the first instance; or,

[0068] When the processing load exceeds the fifth threshold, increase the memory access bandwidth resources allocated to the second instance.

[0069] In one possible implementation, the device further includes:

[0070] The control module is configured to not reduce the computing resources allocated to the second instance when the memory access bandwidth for the second processing through the second instance is less than the preset minimum bandwidth or the execution latency is greater than the preset maximum latency.

[0071] In one possible implementation, the device further includes:

[0072] The control module is configured to not reduce the memory access bandwidth resources allocated to the first instance when encountering a bottleneck in memory access resources or an execution latency greater than the preset maximum latency during the first processing through the first instance.

[0073] In one possible implementation, the device further includes:

[0074] The control module is used to receive processing requests;

[0075] Add the full inference task in the processing request to the first queue;

[0076] Add the incremental processing task in the processing request to the second queue;

[0077] The first processing procedure includes: executing the tasks to be processed in the first queue;

[0078] The second processing procedure includes: executing the tasks to be processed in the second queue.

[0079] In one possible implementation,

[0080] The machine learning model is a language model. The first processing step includes loading the parameters of the language model, obtaining a processing request, executing the processing request through the parameters of the language model, and obtaining key-value data and a newly generated first token. The second processing step includes loading the parameters of the language model, obtaining key-value data in the key-value cache, and obtaining the key-value data of the first token and a newly generated second token through the parameters of the language model.

[0081] Thirdly, embodiments of this application provide a data processing apparatus, which may include a memory, a processor, and a bus system, wherein the memory is used to store a program, and the processor is used to execute the program in the memory to perform the methods described in the first aspect above and any of its optional methods.

[0082] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0083] Fifthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the first aspect and any of its optional methods described above.

[0084] Sixthly, this application provides a chip system including a processor for supporting an execution data processing device in implementing the functions involved in the foregoing aspects, such as transmitting or processing data involved in the foregoing methods; or, information. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the execution device or training device. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0085] Figure 1 A structural diagram illustrating the main framework of artificial intelligence;

[0086] Figures 2 to 4 This is a schematic diagram of the application system framework of the present invention;

[0087] Figure 5 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0088] Figures 6A to 7C This application provides an example of its application.

[0089] Figure 8 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application;

[0090] Figure 9 A schematic diagram of the structure of the execution device provided in the embodiments of this application;

[0091] Figure 10 A schematic diagram of the structure of the training device provided in the embodiments of this application;

[0092] Figure 11 This is a schematic diagram of a chip structure provided in an embodiment of this application. Detailed Implementation

[0093] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0094] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0095] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0096] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” in describing embodiments of the invention refers to “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration.

[0097] First, the overall workflow of the artificial intelligence system is described; please refer to [link / reference]. Figure 1 , Figure 1 The diagram illustrates a structural framework for artificial intelligence (AI). The framework is further elaborated below along two dimensions: the "Intelligent Information Chain" (horizontal axis) and the "IT Value Chain" (vertical axis). The "Intelligent Information Chain" reflects a series of processes from data acquisition to processing. For example, it could be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, and intelligent execution and output. In this process, data undergoes a condensation process of "data—information—knowledge—wisdom." The "IT Value Chain" reflects the value that AI brings to the information technology industry, from the underlying infrastructure of human intelligence and information (provided and processed through technological means) to the industrial ecosystem of the system.

[0098] (1) Infrastructure

[0099] Infrastructure provides computing power to support artificial intelligence systems, enabling communication with the external world and providing support through a basic platform. This communication occurs through sensors; computing power is provided by intelligent chips (hardware acceleration chips such as CPUs, NPUs, GPUs, ASICs, and FPGAs); and the basic platform includes distributed computing frameworks and related platform guarantees and support, which may include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to acquire data, and this data is provided to intelligent chips in the distributed computing system provided by the basic platform for computation.

[0100] (2) Data

[0101] The data at the next layer of infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data from traditional devices, including business data from existing systems and sensor data such as force, displacement, liquid level, temperature, and humidity.

[0102] (3) Data processing

[0103] Data processing typically includes methods such as data training, machine learning, deep learning, search, reasoning, and decision-making.

[0104] Among them, machine learning and deep learning can perform intelligent information modeling, extraction, preprocessing, and training on data, including symbolization and formalization.

[0105] Reasoning refers to the process in which, in a computer or intelligent system, the machine thinks and solves problems by simulating human intelligent reasoning, based on reasoning control strategies and using formalized information. Typical functions include search and matching.

[0106] Decision-making refers to the process of making decisions based on intelligent information after reasoning, and it typically provides functions such as classification, sorting, and prediction.

[0107] (4) General ability

[0108] After the data processing mentioned above, the results of the data processing can be used to form some general capabilities, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0109] (5) Smart Products and Industry Applications

[0110] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields. They are the encapsulation of overall artificial intelligence solutions, productizing intelligent information decision-making and realizing practical applications. Their application areas mainly include: intelligent terminals, intelligent transportation, intelligent healthcare, autonomous driving, smart cities, etc.

[0111] The following is combined Figure 2 The system architecture provided in the embodiments of this application will be described in detail.

[0112] Figure 2 This is a schematic diagram of the system architecture provided for an embodiment of this application. Figure 2 As shown, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0113] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0114] The data acquisition device 560 is used to collect training samples. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0115] The training device 520 can maintain training samples in the database 530 to obtain the target model / rule 501 from the neural network to be trained (e.g., the machine learning model in the embodiments of this application).

[0116] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0117] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0118] The target model / rule 501 trained using training device 520 can be applied to different systems or devices, such as... Figure 2 The execution device 510 shown can be a terminal, such as a mobile phone terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0119] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0120] exist Figure 2 In the execution device 510, an input / output (I / O) interface 512 is configured for data interaction with external devices. Users can input data to the I / O interface 512 through the client device 540.

[0121] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0122] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0123] Finally, the I / O interface 512 provides the processing result to the client device 540, thereby providing it to the user.

[0124] exist Figure 2 In the illustrated scenario, the user can manually provide input data, which can be done through the interface provided by I / O interface 512. Alternatively, the client device 540 can automatically send input data to I / O interface 512. If user authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permissions in the client device 540. The user can view the output results of the execution device 510 on the client device 540, which can be presented in various forms such as display, sound, or animation. The client device 540 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530. Alternatively, data can be collected directly from the I / O interface 512 without going through the client device 540, using the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530.

[0125] It is worth noting that, Figure 2 This is merely a schematic diagram of a system architecture provided in an embodiment of this application. The positional relationships between the devices, components, modules, etc., shown in the diagram do not constitute any limitation. For example, in Figure 2 In this context, the data storage system 550 is an external storage device relative to the execution device 510. However, in other cases, the data storage system 550 may also be placed within the execution device 510. It should be understood that the aforementioned execution device 510 may be deployed within the client device 540.

[0126] From the inference side of the model:

[0127] In this embodiment, the computing module 511 of the execution device 520 can obtain the code stored in the data storage system 550 to implement the steps related to the model reasoning process in this embodiment.

[0128] In this embodiment of the application, the computing module 511 of the execution device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0129] Specifically, the computing module 511 of the execution device 520 can be a hardware system with the function of executing instructions. The steps related to the model inference process provided in this application embodiment can be software code stored in the memory. The computing module 511 of the execution device 520 can obtain the software code from the memory and execute the obtained software code to implement the steps related to the model inference process provided in this application embodiment.

[0130] It should be understood that the computing module 511 of the execution device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the model reasoning process provided in the embodiments of this application can also be implemented by the hardware system in the computing module 511 of the execution device 520 without the function of executing instructions, which is not limited here.

[0131] From the training side of the model:

[0132] In this embodiment of the application, the training device 520 can access the memory ( Figure 2 (Not shown in the diagram, but can be integrated into the training device 520 or deployed separately from the training device 520) The code stored in the diagram can be used to implement the steps related to model training in the embodiments of this application.

[0133] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0134] It should be understood that the training device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the training of the neutralization model provided in the embodiments of this application can also be implemented by the hardware system in the training device 520 without the function of executing instructions, which is not limited here.

[0135] In this embodiment, the forward propagation process of the model is involved, which can be executed by the execution device 510 or the training device 520 described in the above embodiments.

[0136] Furthermore, the execution device 510 or training device 520 can process the input data using a machine learning model. This machine learning model may include an attention layer that performs attention calculations on the input tokens. During these attention calculations, the attention layer can obtain intermediate results that can be reused in subsequent attention calculations on the same tokens. For example, these intermediate results could be key-value (KV) data. In this process, when processing a new token, reusable intermediate results can be stored in memory. These intermediate results can then be retrieved from memory and used as the basis for attention calculations on other tokens. However, the amount of reusable intermediate results that need to be stored grows rapidly as inference progresses, leading to a large storage requirement. Furthermore, excessively large intermediate results can severely slow down the inference process; therefore, compressing reusable intermediate results is crucial.

[0137] In one implementation, the compression process can be performed by a compression module, which can be centrally deployed with the execution device 510 or training device 520, for example, belonging to the same chip or other granular computing units, or it can be deployed separately, for example, belonging to different chips. For example, the execution device 510 or training device 520 can be an AI chip, and the compression module can belong to the CPU.

[0138] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts such as neural networks involved in the embodiments of this application will be introduced below.

[0139] (1) Neural Network

[0140] A neural network can be composed of neural units, which can be defined as a computational unit that takes xs (i.e., input data) and an intercept of 1 as input. The output of this computational unit can be:

[0141]

[0142] Where s = 1, 2, ..., n, where n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be the sigmoid function. A neural network is a network formed by connecting multiple of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0143] (2) A convolutional neural network (CNN) is a deep neural network with a convolutional structure. A CNN contains a feature extractor consisting of convolutional layers and subsampling layers, which can be viewed as a filter. A convolutional layer refers to the layer of neurons in a CNN that performs convolutional processing on the input signal. In a convolutional layer of a CNN, a neuron can be connected to only some of the neurons in its neighboring layers. A convolutional layer typically contains several feature planes, each composed of rectangularly arranged neural units. Neural units on the same feature plane share weights, which are the convolutional kernel. Shared weights can be understood as the way features are extracted being independent of their location. The convolutional kernel can be formalized as a matrix of random size, and during the training process of the CNN, the kernel can learn reasonable weights. Furthermore, the direct benefit of shared weights is reducing the connections between layers in the CNN, while also reducing the risk of overfitting.

[0144] CNN is a very common type of neural network, and the following section focuses on a detailed introduction to its structure. As mentioned in the basic concept introduction above, a convolutional neural network is a deep neural network with a convolutional structure. It is a deep learning architecture, which refers to learning at multiple levels of different abstraction levels through machine learning algorithms. As a deep learning architecture, CNN is a feed-forward artificial neural network, in which each neuron can respond to the input image.

[0145] (3) Deep Neural Networks

[0146] Deep Neural Networks (DNNs), also known as multilayer neural networks, can be understood as neural networks with many hidden layers, though there's no specific metric for "many." DNNs can be categorized into three layers based on their position: input layers, hidden layers, and output layers. Generally, the first layer is the input layer, the last layer is the output layer, and the layers in between are hidden layers. All layers are fully connected, meaning that any neuron in the i-th layer is connected to any neuron in the (i+1)-th layer. Although DNNs appear complex, the operation of each layer is actually quite simple, resembling a linear relationship as follows: in, It is the input vector. It is the output vector. α is the offset vector, W is the weight matrix (also called coefficients), and α() is the activation function. Each layer is simply an adjustment of the input vector. The output vector is obtained through such a simple operation. Because DNNs have many layers, the coefficients W and the offset vector... The number of these parameters is therefore quite large. The definitions of these parameters in a DNN are as follows: Taking the coefficient W as an example: Assuming a three-layer DNN, the linear coefficient from the 4th neuron in the second layer to the 2nd neuron in the third layer is defined as... The superscript 3 represents the layer number where coefficient W resides, while the subscript corresponds to the output third layer index 2 and the input second layer index 4. In summary, the coefficients from the k-th neuron in layer L-1 to the j-th neuron in layer L are defined as follows: It's important to note that the input layer does not have a W parameter. In deep neural networks, more hidden layers allow the network to better represent complex real-world situations. Theoretically, the more parameters a model has, the higher its complexity and "capacity," meaning it can perform more complex learning tasks. Training a deep neural network is essentially the process of learning the weight matrix, with the ultimate goal of obtaining the weight matrix of all layers in the trained deep neural network (a weight matrix formed by the vectors W from many layers).

[0147] (4) Loss Function

[0148] In training a deep neural network, to ensure the output closely approximates the desired predicted value, we compare the network's prediction with the target value. Based on the difference, we update the weight vector of each layer (usually pre-configuring parameters before the initial update). For example, if the prediction is too high, the weight vector is adjusted to predict a lower value. This adjustment continues until the deep neural network predicts the target value or a value very close to it. Therefore, we need to predefine "how to compare the difference between the predicted and target values," which is the loss function or objective function. These are important equations used to measure the difference between the predicted and target values. Taking the loss function as an example, a higher output value (loss) indicates a greater difference, and training the deep neural network becomes a process of minimizing this loss.

[0149] (5) Backpropagation algorithm

[0150] Backpropagation (BP) can be used during training to correct the parameters in the initial model, thereby reducing the model's error loss. Specifically, forward propagation of the input signal to the output generates error loss; this error loss information is then propagated back to update the parameters in the initial model, leading to convergence of the error loss. The backpropagation algorithm is an error-loss-driven backpropagation process aimed at obtaining optimal model parameters, such as the weight matrix.

[0151] (6) Large Language Model: A large language model is a natural language processing model trained on large-scale data, typically with billions or tens of billions of parameters. These models learn the general features of language by studying a large amount of text data during the pre-training stage, and can then be fine-tuned on downstream tasks to adapt to the needs of specific tasks.

[0152] (7) Transformer: The transformer is a deep learning model architecture originally used for sequence-to-sequence tasks, such as machine translation. It uses a self-attention mechanism to process input sequences and has achieved great success in the field of natural language processing. Most large language models, such as BERT, GPT, and T5, are based on the Transformer architecture.

[0153] (8) Key-Value Cache: A key-value cache is a cache structure that stores key-value pairs. In large language models, key-value caches are often used to store intermediate results or other useful information that the model is processing text in order to improve efficiency. By using a key-value cache, the model can avoid redundant calculations when processing text.

[0154] (9) Key-Value Cache Quantization: Key-value cache quantization refers to quantizing the values ​​in the key-value cache to reduce storage space and computational overhead. In some large language models, to adapt the model to limited resources, the values ​​in the key-value cache can be quantized to reduce the model's storage and computational costs.

[0155] (10) PPL (Perplexity): PPL is a metric used to evaluate the performance of a language model, representing the model's ability to predict a given text sequence. PPL is a positive real number, which can be understood as the average difficulty the model has in predicting the observed data sequence. The lower the PPL, the better the model performance.

[0156] (11) Non-uniform quantization: Non-uniform quantization is a quantization method in which the range of values ​​is divided into intervals of different sizes to better adapt to the distribution of data. Unlike uniform quantization, non-uniform quantization can assign different numbers of values ​​to each interval according to the distribution of data.

[0157] (12) Token: In natural language processing, a "token" is the basic unit for segmenting a text string. This can be a word, a character, or a fragment of a word. Large language models typically need to segment the input text into tokens and then convert these tokens into numerical representations (such as word vectors) that the model can understand.

[0158] (13) Sequence: In the context of a large language model, "sequence" refers to a sequence of elements with a certain order relationship. Multiple tokens make up a sequence.

[0159] (14) Incremental Inference: Incremental inference allows the model to process only newly added parts of the input, rather than reprocessing the entire sequence each time. This is achieved by maintaining contextual information in the model's internal state, allowing the model to respond quickly when it receives new input. Incremental inference is particularly useful in interactive applications, such as chatbots or real-time translation, as it can significantly reduce latency and computational resource usage.

[0160] (15) Step: One reasoning stage, used to generate one or more tokens.

[0161] (16) Prefill: Prefill KV Cache stage, i.e. the process of outputting the first token.

[0162] (17)Decoding: The decoding process, i.e. the process of outputting non-first tokens.

[0163] (18) Bond: The bottleneck is a certain resource. For example, memory bond is the bottleneck of memory access, and compute bond is the bottleneck of computation.

[0164] Currently, large language models primarily employ the Transformer network structure. Characterized by self-attention, the Transformer network effectively captures key information and relationships between preceding and following words in a dialogue, resulting in better output. The Transformer network consists of multiple layers, each including Attention and FFN structures. The Attention structure uses the Q-variable of the current token and the key-value pairs (KV) of the preceding tokens to calculate the relationship between them. To accelerate the computation process, a KV cache is typically used to store the KV of the preceding tokens, reducing redundant calculations of their KV values. The processing of the first token is called the full computation phase (prefill phase), while the processing of subsequent tokens is called the incremental computation phase (decoding phase).

[0165] In existing technologies, processing in two stages using the same instance results in poor end-to-end latency and other performance issues. Alternatively, using different processing units (physically) to perform the full calculation process and the incremental calculation process separately leads to additional communication and storage overhead between hardware components.

[0166] by Figure 3 Let's take an example to illustrate the input-to-output process. The user inputs "The future of AI is," and the expected model completes the output by writing the text. The user input is called the prompt. Depending on the encoding method, a word can be encoded as multiple tokens, or multiple words can be encoded as a single token. For simplicity, let's assume one word is one token. After the user inputs, the model begins the calculation process, outputting the next token at a time. In this example, it first outputs "exciting," then "and," and then "uncertain." Each calculation is called a step. Based on whether the output is the first token, it's divided into first token and non-first token. For the first token, the KV cache of the preceding 5 tokens needs to be calculated, which is the light gray area in the diagram. For non-first tokens, such as "and," only the KV cache of "exciting" needs to be calculated, and the KV cache of the previously stored light gray 5 tokens can be directly retrieved. The step for the first token is called the full calculation phase (prefill phase), and the steps for non-first tokens are called the incremental calculation phase (decoding phase).

[0167] The computation of Transformer networks has the following characteristics:

[0168] 1. The Prefill stage takes much longer than the Decoding stage.

[0169] 2. The load models for the Prefill and Decoding phases are different. The Prefill phase is a computationally intensive task, while the Decoding phase is a memory-intensive task.

[0170] Model inference services typically use batch processing to improve throughput. Batch processing means performing multiple calculations on multiple user inputs in one step. Generally, since prefill is a computationally intensive task, batch processing cannot improve business throughput. However, the decoding stage can improve throughput by batch processing because it can solve the decoding memory access bottleneck by performing multiple calculations on a single memory access.

[0171] The inference service of a large language model can simultaneously accept different requests from multiple clients and return model output results to multiple clients. Requests and outputs can take various forms, such as text continuation and question answering. Common metrics for measuring the performance of the inference service include the following:

[0172] 1. End-to-end latency: The time from the input of each request to the completion of all outputs.

[0173] 2. TPS or RPS: This refers to requests per second, used to measure service throughput.

[0174] 3. First Token Latency: The latency of the first token requested in each request.

[0175] 4. Non-first token latency: Latency for each request for a non-first token.

[0176] Generally, lower end-to-end latency, first-to-toe latency, and non-first-toe latency result in better performance, while higher TPS or RPS also contribute to better performance. AI services aim to achieve higher TPS with the same latency, meaning they can serve more users. Existing technologies for improving TPS include Continuous Batching, SplitFuse, and PD separation, which will be discussed in more detail later.

[0177] Continuous batching improves performance by computing a prefill and multiple decoding batches. Batch processing essentially reduces memory overhead by performing multiple computations within a single memory access. For example... Figure 4As shown, the light gray area represents prefill, and the dark gray area represents decoding. R1 and R2 represent the two incoming requests. The horizontal axis represents time. After two requests arrive, the inference service batches the prefill from R2 and the decoding from R1 into a single step for computation. Compared to executing prefill alone, this prefill can include more decoding steps. Although the prefill takes slightly longer (the gray area represents the extended time), it increases overall throughput.

[0178] Existing technologies can effectively improve overall service throughput by using batch processing, but for R1, their end-to-end latency is increased. This is because the decoding in the batch processing is slowed down by prefilling, turning decoding latency into prefill latency.

[0179] To address the aforementioned problems, embodiments of this application provide a data processing method. The data processing method of this application embodiment will be described in detail below with reference to the accompanying drawings.

[0180] Reference Figure 5 , Figure 5 This is a flowchart illustrating a data processing method provided in an embodiment of this application, such as... Figure 5 As shown in the embodiment of this application, a data processing method may include steps 501 to 502, which are described in detail below.

[0181] 501. A first processing procedure is performed through a first instance, wherein the first processing procedure is a full inference process performed through a machine learning model;

[0182] 502. A second processing procedure is performed through a second instance, wherein the second processing procedure is an incremental inference process performed through the machine learning model; wherein the first instance and the second instance are different instances running on the same computing unit, and the first processing procedure and the second processing procedure are performed in parallel.

[0183] An instance is a software module that can run applications or system programs. Furthermore, a software module can only be considered an instance when it is run by the operating system; otherwise, it is just a piece of code. Instances can take many forms; for example, processes and threads can both be understood as types of instances.

[0184] The computing unit can be a computing card, such as an AI processing chip like an NPU, TPU, or GPU.

[0185] In one possible implementation, the machine learning model is a language model. The first processing step includes loading the parameters of the language model, obtaining a processing request, executing the processing request using the parameters of the language model, and obtaining key-value data and a newly generated first token. The second processing step includes loading the parameters of the language model, obtaining key-value data from the key-value cache, and obtaining the key-value data of the first token and a newly generated second token using the parameters of the language model.

[0186] In one possible implementation, a processing request can be received; the full inference task in the processing request can be added to a first queue, and the incremental processing task in the processing request can be added to a second queue; then, the pending tasks in the first queue can be executed, and the pending tasks in the second queue can be executed.

[0187] In this embodiment, the full inference process and incremental inference process of the machine learning model are performed separately by different instances running on the same computing unit. Therefore, the data communication overhead between devices is reduced, the overall end-to-end latency is shortened, and the number of requests per second (TPS) is increased accordingly.

[0188] In one possible implementation, the allocation strategy for allocating computing resources to the first instance can be determined based on the operating performance of the computing unit; and the allocation strategy for allocating computing resources to the second instance can be adjusted based on the operating performance of the computing unit.

[0189] The configuration of the aforementioned computing resources can be done at each step or even at a finer granular level, thereby increasing TPS.

[0190] Computing resources can be configured by setting the block dim parameter, for example, when launching a kernel, the corresponding block dim parameter can be set to allocate computing resources. Computing resources can also be controlled by controlling the grid dim or thread dim parameters.

[0191] The memory access bandwidth can be configured through the MPAM bandwidth control interface. Memory access resources can be allocated by setting the corresponding partid when launching the kernel.

[0192] In one possible implementation, the operational performance includes computing load; when the computing load is below a first threshold, the computing resources allocated to the first instance may be increased; or, when the computing load is above a second threshold, the computing resources allocated to the second instance may be decreased.

[0193] Typically, the Prefill phase is a computationally intensive task, while the Decoding phase is a memory-intensive task. Therefore, when the performance indicator on the computing unit indicates that there are more computing resources (i.e., the computing load is lower than the first threshold), the computing resources can be allocated to the first instance first. When the performance indicator on the computing unit indicates that there are fewer memory access resources (i.e., the computing load is higher than the second threshold), the computing resources allocated to the second instance can be reduced.

[0194] In one possible implementation, the operational performance includes memory access load; the memory access bandwidth resources allocated to the first instance may be reduced when the memory access load is higher than a third threshold; or the memory access bandwidth resources allocated to the second instance may be increased when the memory access load is lower than the third threshold.

[0195] Typically, the Prefill phase is a computationally intensive task, while the Decoding phase is a memory-intensive task. Therefore, when the performance indicator on the computing unit indicates that there are more memory resources available (e.g., the memory load is below the third threshold), computing resources can be preferentially allocated to the first instance. When the performance indicator on the computing unit indicates that there are fewer memory resources available (e.g., the memory load is above the third threshold), memory resources can be preferentially allocated to the second instance.

[0196] In one possible implementation, the operational performance includes execution latency; when the execution latency is higher than a fourth threshold, the computing resources allocated to the first instance may be increased; or, when the execution latency is higher than the fourth threshold, the memory access bandwidth resources allocated to the first instance may be increased.

[0197] In one possible implementation, the allocation strategy for allocating computing resources to the first instance can be determined based on the processing load of the first instance during the first processing step; or, the allocation strategy for allocating computing resources to the second instance can be adjusted based on the processing load of the second instance during the second processing step.

[0198] This means that the current Prefill and Decoding load can be obtained in real time, and the resource strategy can be dynamically adjusted based on the current load.

[0199] In one possible implementation, when the processing load exceeds a fifth threshold, the computing resources allocated to the first instance may be increased; or, when the processing load exceeds a fifth threshold, the memory access bandwidth resources allocated to the second instance may be increased.

[0200] In one possible implementation, when the memory access bandwidth for the second processing through the second instance is less than the preset minimum bandwidth, or the execution latency is greater than the preset maximum latency, the computing resources allocated to the second instance are not reduced.

[0201] In one possible implementation, when a bottleneck in memory access resources is encountered during the first processing through the first instance, or when the execution latency exceeds the preset maximum latency, the memory access bandwidth resources allocated to the first instance are not reduced.

[0202] Memory access bandwidth during the Decoding phase is the most sensitive factor affecting Decoding latency, and the number of computation cores during the Prefill phase is the most sensitive factor affecting Prefill latency. When the increase in Decoding latency exceeds the maximum Decoding latency, the number of Decoding computation cores will no longer be reduced. When the Decoding bandwidth is less than the minimum Decoding bandwidth, the number of Decoding computation cores will no longer be reduced. When the increase in Prefill latency exceeds the maximum Prefill latency, the Prefill bandwidth will no longer be reduced. When Prefill is converted from a computation bond task to a memory access bond task, the Prefill bandwidth will no longer be reduced.

[0203] Reference Figure 6A , Figure 6A This is a system architecture diagram of an embodiment of this application: It includes software modules: AI Client, Load Balancing module, LLM service, wherein the optimization module: LLM service, and a newly added load awareness module. It includes hardware modules: GPU / NPU, wherein the optimization module: a resource scheduling and control unit.

[0204] This section explains the hardware fundamentals from two dimensions: computing power and memory access bandwidth. GPUs / NPUs provide the ability to accelerate the execution of large language models. GPUs provide multiple SMs (NPUs provide multiple acceleration cores) to execute matrix operations in parallel, improving the execution efficiency of large language models. When users issue operators using the GPU / NPU runtime interface, they can specify how many SMs or cores to use for parallel execution. For example, the GPU interface cuLaunchKernel provides parameters such as BlockDim for user configuration.

[0205] The above describes the hardware implementation of the computational load; the following describes the hardware control capabilities for memory bandwidth:

[0206] For memory bandwidth control, ARM hardware provides MPAM capabilities, while x86 provides RDT capabilities. That is, when a compute core initiates a memory access, it can include a partid to identify the request. Users can use MPAM to control the bandwidth and cache size of a request for a specific partid.

[0207] The software structure related to this invention, and the functions of each module are as follows:

[0208] The LLM service module supports parallel prefilling and decoding, and also supports parallel scheduling of prefilling and decoding.

[0209] The load-aware devices and resource policies in the LLM service module support dynamic resource adjustment based on northbound and southbound loads;

[0210] Modify the resource scheduling and control module of GPU / NPU to provide a hardware interface for configuring computing power and memory access resources;

[0211] Reference Figure 6B , Figure 6B Here is a system architecture diagram of an embodiment of this application:

[0212] It includes the following software modules: LLMEngine, PD separation scheduling module, Distributed Workers, KV Cache management module, PD Model parallel execution module (providing resource configuration interface), load awareness device and resource policy module. The newly added (or optimized) modules are shown in red in the figure: LLMEngine, PD separation scheduling module, PD Model parallel execution module (providing resource configuration interface), load awareness device and resource policy module.

[0213] It includes hardware modules: GPU / NPU, with additional (or optimized) modules: the hardware provides resource configuration interfaces and profiler capabilities, whose functions are as follows:

[0214] LLMEngine supports parallel Prefill and Decoding (CPU): this can be achieved by launching Prefill and Decoding threads.

[0215] Independent scheduling capability for Prefill and Decoding load: Supports Prefill threads to independently obtain Prefill scheduling results and Decoding threads to independently obtain Decoding scheduling results;

[0216] The Model execution module supports parallel Prefill and Decoding (GPU / NPU): this can be achieved by creating PrefillStream and Decoding Stream.

[0217] The load-aware device dynamically adjusts resources: it obtains the current Prefill and Decoding load status from the scheduling module in real time, collects the load (computing power / memory access bandwidth / execution latency, etc.) from the GPU / NPU in real time, and dynamically adjusts the resource strategy based on the current business load and hardware resource status.

[0218] Resource strategy configuration: The Model parallel execution module configures the computing power resources according to the resource strategy during Prefill or Decoding execution. It configures the computing power execution block dim method of Prefill and Decoding, and configures the memory access bandwidth through the MPAM bandwidth control interface provided by GPU / NPU.

[0219] The logical (operational / connection) relationship between the hardware and software is as follows:

[0220] The PD Model parallel module uses GPUs or NPUs to execute models and can configure resource usage for the current run via a resource configuration interface before execution. The load-aware module can collect GPU or NPU profiler performance data online or offline and adjust resource strategies accordingly. Ultimately, this achieves... Figure 7A The effect.

[0221] Reference Figure 7B , Figure 7B This is a schematic diagram of an application flow according to an embodiment of this application, including:

[0222] Step 1: LLMEngine accepts new requests and inserts them into the prefill queue of the Scheduler module;

[0223] Step 2: LLMEngine creates two threads, a prefill thread and a decoding thread, which execute the inference step in parallel.

[0224] Step 3: The prefill thread and the decoding thread call the scheduling algorithm of the Scheduler module to obtain the corresponding request. The interface passes the current thread identity, for example, prefill passes prefill and decoding passes decoding.

[0225] Step 4: The scheduler module queries the prefill queue or decoding queue based on the thread identity. For a prefill thread, it returns one prefill request, and for a decoding thread, it returns multiple decoding requests.

[0226] Step 5: The prefill thread and decoding thread allocate their respective device resources, including computing resources and memory resources, according to the resource strategy. Computing resources are allocated by setting the corresponding blockdim parameter when launching the kernel, and memory resources are allocated by setting the corresponding partid when launching the kernel.

[0227] Step Six: LLMEngine begins prefill inference and decoding inference;

[0228] Step 7: Distributed Workers perform TP splitting;

[0229] Step 8: The Model execution module uses the GPU / NPU to complete the inference and return the results;

[0230] Step 9: Check if the current request has been processed. If it has, end the process. If it has not been processed, re-insert the request into the corresponding scheduler queue. For example, requests that have finished prefilling are inserted into the scheduler's decoding queue, and requests that have finished decoding are still inserted into the scheduler's decoding queue. Repeat steps 3 to 8 until the request is processed.

[0231] In addition, the load-aware device adjusts resource strategies in real time based on the length of the prefill and decoding queues in the scheduler and the profiler data on the GPU / NPU side, so as to achieve the effect of optimal resource allocation according to PD load. When PD load changes, the load-aware device can flexibly adjust PD resources to achieve optimal performance.

[0232] Reference Figure 7C , Figure 7C The flowchart for the load awareness module includes: scheduling load status and device-side performance profiling data. It is known that: memory access bandwidth during the Decoding phase is the most sensitive factor affecting Decoding latency, and the number of computation cores during the Prefill phase is the most sensitive factor affecting Prefill latency.

[0233] Device-side PD latency and bandwidth are used as negative feedback to adjust resource strategies, including:

[0234] 1. When the increase in Decoding latency exceeds the maximum Decoding latency, the number of Decoding computation cores will no longer be reduced;

[0235] 2. If the Decoding bandwidth is less than the minimum Decoding bandwidth, then the number of Decoding computation cores will not be reduced further;

[0236] 3. When the increase in prefill latency exceeds the maximum prefill latency, the prefill bandwidth will no longer be reduced;

[0237] 4. When Prefill is changed from a computation bond task to a memory access bond task, the Prefill bandwidth will no longer be reduced;

[0238] It should be understood that device-side profiling data can also be obtained from offline data analysis.

[0239] Reference Figure 8 , Figure 8 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application, such as... Figure 8 As shown in the embodiment of this application, a data processing apparatus 800 is provided, the apparatus comprising:

[0240] The full inference module 801 is used to perform a first processing procedure through a first instance, wherein the first processing procedure is a full inference procedure performed through a machine learning model.

[0241] The incremental inference module 802 is used to perform a second processing procedure through a second instance, the second processing procedure being an incremental inference procedure performed through the machine learning model; wherein the first instance and the second instance are different instances running on the same computing unit, and the first processing procedure and the second processing procedure are performed in parallel.

[0242] In one possible implementation, the device further includes:

[0243] The control module is configured to determine an allocation strategy for allocating computing resources to the first instance based on the operating performance of the computing unit; or,

[0244] Based on the operating performance of the computing unit, the allocation strategy for allocating computing resources to the second instance is adjusted.

[0245] In one possible implementation, the operational performance includes computing load;

[0246] The control module is specifically used for:

[0247] When the computing load is below a first threshold, increase the computing resources allocated to the first instance; or,

[0248] When the computing load exceeds the second threshold, the computing resources allocated to the second instance are reduced.

[0249] In one possible implementation, the operational performance includes memory access load;

[0250] The control module is specifically used for:

[0251] When the memory access load exceeds a third threshold, reduce the memory access bandwidth resources allocated to the first instance; or,

[0252] When the memory access load is below the third threshold, increase the memory access bandwidth resources allocated to the second instance.

[0253] In one possible implementation, the runtime performance includes execution latency;

[0254] The control module is specifically used for:

[0255] When the execution latency exceeds a fourth threshold, increase the computing resources allocated to the first instance; or,

[0256] When the execution latency exceeds the fourth threshold, the memory access bandwidth resources allocated to the first instance are increased.

[0257] In one possible implementation, the device further includes:

[0258] The control module is configured to determine an allocation strategy for computing resources to be allocated to the first instance based on the processing load during the first processing step; or,

[0259] Based on the processing load of the second instance during the second processing procedure, adjust the allocation strategy for computing resources to the second instance.

[0260] In one possible implementation, the control module is specifically used for:

[0261] When the processing load exceeds the fifth threshold, increase the computing resources allocated to the first instance; or,

[0262] When the processing load exceeds the fifth threshold, increase the memory access bandwidth resources allocated to the second instance.

[0263] In one possible implementation, the device further includes:

[0264] The control module is configured to not reduce the computing resources allocated to the second instance when the memory access bandwidth for the second processing through the second instance is less than the preset minimum bandwidth or the execution latency is greater than the preset maximum latency.

[0265] In one possible implementation, the device further includes:

[0266] The control module is configured to not reduce the memory access bandwidth resources allocated to the first instance when encountering a bottleneck in memory access resources or an execution latency greater than the preset maximum latency during the first processing through the first instance.

[0267] In one possible implementation, the device further includes:

[0268] The control module is used to receive processing requests;

[0269] Add the full inference task in the processing request to the first queue;

[0270] Add the incremental processing task in the processing request to the second queue;

[0271] The first processing procedure includes: executing the tasks to be processed in the first queue;

[0272] The second processing procedure includes: executing the tasks to be processed in the second queue.

[0273] In one possible implementation,

[0274] The machine learning model is a language model. The first processing step includes loading the parameters of the language model, obtaining a processing request, executing the processing request through the parameters of the language model, and obtaining key-value data and a newly generated first token. The second processing step includes loading the parameters of the language model, obtaining key-value data in the key-value cache, and obtaining the key-value data of the first token and a newly generated second token through the parameters of the language model.

[0275] The following describes a terminal device provided in an embodiment of this application. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of a terminal device provided in an embodiment of this application. The terminal device 900 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a laptop computer, a smart wearable device, etc., and is not limited thereto. Specifically, the terminal device 900 includes: a receiver 901, a transmitter 902, a processor 903, and a memory 904 (wherein the terminal device 900 may have one or more processors 903). Figure 9 (Taking a processor as an example), processor 903 may include application processor 9031 and communication processor 9032. In some embodiments of this application, receiver 901, transmitter 902, processor 903 and memory 904 may be connected via a bus or other means.

[0276] Memory 904 may include read-only memory and random access memory, and provides instructions and data to processor 903. A portion of memory 904 may also include non-volatile random access memory (NVRAM). Memory 904 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0277] Processor 903 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0278] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 903. The processor 903 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 903 or by instructions in software form. The processor 903 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 903 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 904. The processor 903 reads the information from memory 904 and, in conjunction with its hardware, completes the steps involved in the model training or model inference process described above.

[0279] Receiver 901 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 902 can be used to output digital or character information through the first interface; transmitter 902 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 902 may also include a display device such as a display screen.

[0280] This application also provides a server; please refer to [link / reference]. Figure 10 , Figure 10 This is a schematic diagram of a server structure provided in an embodiment of this application. The server 1000 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1010 (e.g., one or more processors) and memory 1032, and one or more storage media 1030 (e.g., one or more mass storage devices) for storing application programs 1042 or data 1044. The memory 1032 and storage media 1030 can be temporary or persistent storage. The program stored in the storage media 1030 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the server. Furthermore, the CPU 1010 may be configured to communicate with the storage media 1030 and execute the series of instruction operations in the storage media 1030 on the server 1000.

[0281] Server 1000 may also include one or more power supplies 1026, one or more wired or wireless network interfaces 1050, one or more input / output interfaces 1058; or, one or more operating systems 1041, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0282] In this embodiment, the central processing unit 1010 is used to perform actions related to model training or model inference in the above embodiments.

[0283] This application also provides a computer program product that, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0284] This application also provides a computer-readable storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0285] The execution device, training device, or terminal device provided in this application embodiment can specifically be a chip. The chip includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip within the execution device to execute the data processing method described in the above embodiments, or to cause the chip within the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0286] For details, please refer to Figure 11 , Figure 11 This is a schematic diagram of a chip provided in an embodiment of this application. The chip can be represented as a neural network processor (NPU) 1100. The NPU 1100 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 1103, which is controlled by the controller 1104 to extract matrix data from the memory and perform multiplication operations.

[0287] In some implementations, the arithmetic circuit 1103 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 1103 is a two-dimensional pulsating array. The arithmetic circuit 1103 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1103 is a general-purpose matrix processor.

[0288] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1102 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1101 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1108.

[0289] Unified memory 1106 is used to store input and output data. Weight data is directly transferred to weight memory 1102 via Direct Memory Access Controller (DMAC) 1105. Input data is also transferred to unified memory 1106 via DMAC.

[0290] BIU stands for Bus Interface Unit, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 1109.

[0291] The Bus Interface Unit (BIU) 1110 is used by the instruction fetch memory 1109 to fetch instructions from external memory, and also by the memory access controller 1105 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0292] The DMAC is mainly used to move input data from external memory DDR to unified memory 1106, or to weight data to weight memory 1102, or to input data to input memory 1101.

[0293] The vector computation unit 1107 includes multiple processing units that, when needed, further process the output of the computation circuit 1103, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as batch normalization, pixel-level summation, and upsampling of feature planes.

[0294] In some implementations, vector computation unit 1107 can store the processed output vector in unified memory 1106. For example, vector computation unit 1107 can apply a linear function, or a nonlinear function, to the output of computation circuit 1103, such as linear interpolation of feature planes extracted by convolutional layers, or, for example, a vector of accumulated values, to generate activation values. In some implementations, vector computation unit 1107 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as activation input to computation circuit 1103, for example, for use in subsequent layers of the neural network.

[0295] The instruction fetch buffer 1109 connected to the controller 1104 is used to store the instructions used by the controller 1104;

[0296] Unified memory 1106, input memory 1101, weight memory 1102, and instruction fetch memory 1109 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0297] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0298] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0299] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0300] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0301] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A data processing method, characterized by, The method comprises: performing a first processing process by a first instance, the first processing process being a full inference process by a machine learning model; performing a second processing process by a second instance, the second processing process being an incremental inference process by the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

2. The method of claim 1, wherein, The method further comprises: determining an allocation strategy of allocating computing resources to the first instance according to a running performance of the computing unit; or adjusting the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit.

3. The method according to claim 1 or 2, characterized in that, The running performance comprises a computing power load; The determining of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises: when the computing power load is lower than a first threshold, increasing the computing power resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises: when the computing power load is higher than a second threshold, decreasing the computing power resources allocated to the second instance.

4. The method according to any one of claims 1 to 3, characterized in that, The running performance comprises a memory load; The determining of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises: when the memory load is higher than a third threshold, decreasing the memory bandwidth resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises: when the memory load is lower than a third threshold, increasing the memory bandwidth resources allocated to the second instance.

5. The method according to any one of claims 1 to 4, characterized in that, The running performance comprises an execution latency; The determining of the allocation strategy of allocating computing resources to the first instance according to the running performance of the computing unit comprises: when the execution latency is higher than a fourth threshold, increasing the computing power resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the running performance of the computing unit comprises: when the execution latency is higher than a fourth threshold, increasing the memory bandwidth resources allocated to the first instance.

6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: determining the allocation strategy of allocating computing resources to the first instance according to a processing load when the first instance performs the first processing process; or adjusting the allocation strategy of allocating computing resources to the second instance according to a processing load when the second instance performs the second processing process.

7. The method according to any one of claims 1 to 5, characterized in that, The determining of the allocation strategy of allocating computing resources to the first instance according to the processing load when the first instance performs the first processing process comprises: when the processing load is greater than a fifth threshold, increasing the computing power resources allocated to the first instance; or The adjusting of the allocation strategy of allocating computing resources to the second instance according to the processing load when the second instance performs the second processing process comprises: when the processing load is greater than a fifth threshold, increasing the memory bandwidth resources allocated to the second instance.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises: When a memory access bandwidth of the second processing process performed by the second instance is less than a preset minimum bandwidth, or an execution time delay is greater than a preset maximum time delay, the computing resource allocated to the second instance is not reduced.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: When a bottleneck of memory access resource is encountered in the first processing process performed by the first instance, or an execution time delay is greater than a preset maximum time delay, the memory bandwidth resource allocated to the first instance is not reduced.

10. The method according to any one of claims 1 to 9, characterized in that, The method further includes: receiving a processing request; adding a full reasoning task in the processing request to a first queue; adding an incremental processing task in the processing request to a second queue; the first processing process includes: executing a to-be-processed task in the first queue; the second processing process includes: executing a to-be-processed task in the second queue.

11. The method of any one of claims 1-10, wherein the machine learning model is a language model, the first processing process includes loading parameters of the language model, obtaining a processing request, and executing the processing request by using the parameters of the language model to obtain KV data and newly generated first tokens, and the second processing process includes loading the parameters of the language model, obtaining KV data in a KV cache, and executing the KV data in the first tokens by using the parameters of the language model to obtain newly generated second tokens.

12. A data processing apparatus, characterized by The apparatus includes: a full reasoning module configured to perform a first processing process by a first instance, the first processing process being a full reasoning process performed by a machine learning model; an incremental reasoning module configured to perform a second processing process by a second instance, the second processing process being an incremental reasoning process performed by the machine learning model; wherein the first instance and the second instance are different instances running on a same computing unit, and the first processing process and the second processing process are performed in parallel.

13. The apparatus of claim 12, wherein, The apparatus further includes: a control module configured to determine an allocation strategy of computing resources allocated to the first instance according to a running performance of the computing unit; or adjust an allocation strategy of computing resources allocated to the second instance according to the running performance of the computing unit.

14. The apparatus of claim 12 or 13, wherein, The running performance includes a computing power load; The control module is specifically configured to: when the computing power load is lower than a first threshold, increase the computing resource allocated to the first instance; or when the computing power load is higher than a second threshold, decrease the computing resource allocated to the second instance.

15. The apparatus of any one of claims 12 to 14, wherein, The running performance includes a memory load; The control module is specifically configured to: when the memory load is higher than a third threshold, decrease the memory bandwidth resource allocated to the first instance; or when the memory load is lower than the third threshold, increase the memory bandwidth resource allocated to the second instance.

16. The apparatus of any one of claims 12 to 15, wherein, The running performance includes an execution time delay; The control module is specifically configured to: when the execution time delay is higher than a fourth threshold, increase the computing resource allocated to the first instance; or when the execution time delay is higher than the fourth threshold, increase the memory bandwidth resource allocated to the first instance.

17. The apparatus of any one of claims 12 to 16, wherein, The apparatus further includes: determine an allocation strategy of allocating computing resources to the first instance according to a processing load when the first instance performs the first processing process; or adjust the allocation strategy of allocating computing resources to the second instance according to a processing load when the second instance performs the second processing process.

18. The apparatus of any one of claims 12 to 17, wherein, The control module is specifically configured to: increase the computing resource allocated to the first instance when the processing load is greater than a fifth threshold; or increase the memory bandwidth resource allocated to the second instance when the processing load is greater than a fifth threshold.

19. The apparatus of any of claims 12 to 18, wherein, The device further includes: a control module configured to, when the memory bandwidth for performing the second processing process by the second instance is less than a preset minimum bandwidth or an execution delay is greater than a preset maximum delay, not reduce the computing resource allocated to the second instance.

20. The apparatus of any of claims 12 to 19, wherein, The device further includes: a control module configured to, when a bottleneck of memory resource is encountered or an execution delay is greater than a preset maximum delay when the first instance performs the first processing process, not reduce the memory bandwidth resource allocated to the first instance.

21. The apparatus of any one of claims 12 to 20, wherein, The device further includes: a control module configured to receive a processing request; add all the inference tasks in the processing request to a first queue; add the incremental processing tasks in the processing request to a second queue; The first processing process includes: executing the to-be-processed tasks in the first queue; The second processing process includes: executing the to-be-processed tasks in the second queue.

22. The device of any one of claims 12-21, wherein the machine learning model is a language model, the first processing process includes loading parameters of the language model, obtaining a processing request, executing the processing request by using the parameters of the language model, obtaining KV data and newly generated first tokens, and the second processing process includes loading the parameters of the language model, obtaining the KV data in the KV cache, and obtaining the KV data of the first tokens and newly generated second tokens by using the parameters of the language model.

23. A computer storage medium, comprising, The computer storage medium stores one or more instructions which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11.

24. A computer program product, characterised in that, The computer storage medium stores one or more instructions which, when executed by one or more computers or processors, cause the one or more computers or the processors to perform the method of any one of claims 1-11.

25. A system comprising at least one processor, at least one memory; The at least one processor and the at least one memory are connected through a communication bus; The at least one memory is configured to store code; The at least one processor is configured to execute the code to perform the method of any one of claims 1-11.

26. A chip comprising a processor, wherein: The processor is configured to support a data processing device to implement the method of any one of claims 1-11. The processor is configured to support a data processing device to implement the method of any one of claims 1-11.

Images