Quantum circuit and quantum computer applied to QAOA algorithm

Abstract

The embodiment of the invention discloses a quantum circuit and a quantum computer applied to a QAOA algorithm, and relates to the technical field of quantum computing, and by setting a plurality of controlled NOT gates, any quantum bit can be used as a control bit of the controlled NOT gate and can also be used as a controlled bit of the controlled NOT gate, so that the quantum circuit and the quantum computer can be applied to the QAOA algorithm. The information interaction of any quantum bit in the plurality of quantum bits can be conveniently realized. Due to the arrangement mode, when the QAOA algorithm is used for solving the dense QUBO problem, a logic gate needed in an adopted quantum circuit is only a neighbor double-quantum logic gate, and the overall circuit design is matched with a chained chip structure, so that implementation on the superconductive quantum calculation chip level at the present stage is facilitated, and the method has important significance on application and development of quantum calculation.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum circuit and quantum computer applied to the QAOA algorithm. Background Technology

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Because of its ability to process mathematical problems more efficiently than ordinary computers—for example, reducing the time to crack RSA keys from hundreds of years to hours—quantum computers have become a key technology under research.

[0003] Quantum computing simulation is a simulation program that uses numerical computation and computer science to simulate computations that follow the laws of quantum mechanics. As a simulation program, it uses the high-speed computing power of computers to characterize the spacetime evolution of quantum states based on the fundamental laws of quantum bits in quantum mechanics.

[0004] Currently, quantum algorithms are playing an increasingly important role in solving practical problems. For example, combinatorial optimization problems involve finding the optimal object in a finite set of objects. The proposed QAOA (Quantum Approximate Optimization Algorithm) has effectively solved these problems, and has wide applications and practical significance in classical problems such as the Max Cut problem, the Max Independent Set (MIS) problem, the Satisfaction Problem, and the Traveling Salesman Problem.

[0005] At the same time, QAOA also faces some challenges due to the limitations of current NISQ (Noisy Intermediate-Scale Quantum) quantum computer hardware. For example, during QAOA operations, when solving certain dense QUBO (Quadratic Unconstrained Binary Optimization) problems, the corresponding Hamiltonian simulation circuits may be very complex. This can be understood as making it difficult to perform the interaction between all qubit information, which may require a significant waste of quantum logic gate resources to implement on a quantum computer, or make it difficult to retain quantum advantage on a quantum computer. Summary of the Invention

[0006] This application provides a quantum circuit and a quantum computer applied to the QAOA algorithm, and provides a quantum circuit for solving certain dense QUBO problems. The overall quantum circuit is more compatible with the chain structure, which makes it easier to implement the quantum circuit at the current superconducting quantum computing chip level.

[0007] The first aspect of this application provides a quantum circuit applied to the QAOA algorithm. This quantum circuit is used to perform bit information exchange between any two qubits. The qubits acted upon by the quantum circuit are pre-ordered sequentially. The quantum circuit includes: a first information exchange circuit, which includes multiple controlled NOT gates acting on adjacent qubits. The multiple controlled NOT gates include first-type controlled NOT gates and second-type controlled NOT gates. The control bits of the first-type controlled NOT gates are pre-ordered qubits, while the controlled bits of the first-type controlled NOT gates are post-ordered qubits.

[0008] The control bits of the second type of controlled NOT gate are the last-ordered qubits, while the control bits of the second type of controlled NOT gate are the first-ordered qubits. Except for the two qubits ordered at the beginning and end, each qubit serves as the control bit of the first type of controlled NOT gate at least once, and as the control bit of the second type of controlled NOT gate at least once.

[0009] Optionally, the multiple controlled NOT gates in the first quantum information interaction circuit constitute multiple logic processing layers, and the multiple logic processing layers act on the qubits in sequence; wherein, each logic processing layer includes the first type of controlled NOT gate and the second type of controlled NOT gate.

[0010] The total number of controlled NOT gates varies across different logic processing layers.

[0011] Optionally, in each logic processing layer, the qubits from the end of the sorting to the target position are sequentially used as the controlled bits of a first-type controlled NOT gate; and,

[0012] The qubits from the end of the sorting to the target position are used sequentially as the control bits of the second type of controlled NOT gate.

[0013] Optionally, along the timing direction, the corresponding target bits in each logic processing layer increase or decrease sequentially.

[0014] Optionally, along the temporal direction, if the target position corresponding to the first logical processing layer is the second positive number in the sorting sequence, the target position corresponding to each logical processing layer along the temporal direction increases sequentially; if the target position corresponding to the first logical processing layer is the last number in the sorting sequence, the target position corresponding to each logical processing layer along the temporal direction decreases sequentially.

[0015] Optionally, along the temporal direction, the three temporal stages corresponding to the first or last logical processing layer are the first temporal processing stage, the second temporal processing stage, and the third temporal processing stage, respectively; wherein, in the first and third temporal processing stages, the qubits from the end to the beginning of the sorting are all operated by a first type of controlled NOT gate; and in the second temporal processing stage, the qubits from the end to the beginning of the sorting are all operated by a second type of controlled NOT gate.

[0016] Optionally, the first information interaction circuit mentioned above further includes multiple single-qubit rotation gates; for each qubit, after being acted upon by two consecutive controlled NOT gates, it is acted upon by a single-qubit rotation gate.

[0017] Optionally, the quantum circuit further includes a second quantum information interaction circuit, wherein the operation timing of the first quantum information interaction circuit precedes that of the second quantum information interaction circuit, and each of the second quantum information interaction circuits also includes multiple controlled NOT gates operating on adjacent qubits; wherein the first quantum information interaction circuit is used to flip the input first quantum state into a second quantum state, and the second quantum information interaction circuit is used to flip the input second quantum state into the first quantum state.

[0018] Optionally, the logic gate configuration in the first quantum information interaction circuit corresponds to the logic gate configuration in the second quantum information interaction circuit described above; wherein, the correspondence includes:

[0019] In the first quantum information interaction circuit, the logic gate that operates on the i-th qubit is set to operate on the mi-th qubit in the second quantum information interaction circuit; 0≤i≤m, m+1 equals the total number of qubits operated by the above quantum circuit.

[0020] The second aspect of this application provides a quantum computer, which includes a quantum chip and a quantum measurement and control integrated machine. The quantum chip and the quantum measurement and control integrated machine are combined to realize the quantum circuit shown in the first aspect.

[0021] The quantum circuit and quantum computer applied to the QAOA algorithm provided in this application, by setting up multiple controlled NOT gates, allow any qubit to act as both the control bit of a controlled NOT gate and a controlled bit of that gate. This facilitates information exchange between any qubits from multiple qubits. Furthermore, due to this configuration, when using the QAOA algorithm to solve the dense QUBO problem, the logic gates required in the quantum circuit are only nearest-neighbor dual-qubit logic gates. The overall circuit design is more consistent with a chain structure, making it easier to implement at the current superconducting quantum computing chip level, which is of great significance to the application and development of quantum computing. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 An example system block diagram of a quantum circuit implementing the QAOA algorithm according to an embodiment of this application is shown;

[0024] Figure 2 A schematic diagram of a quantum circuit in the related art provided in one embodiment of this application is shown;

[0025] Figure 3 This illustration shows a partial equivalent circuit diagram of a possible quantum circuit according to one embodiment of this application;

[0026] Figure 4 A schematic diagram of a possible first information interaction circuit provided in one embodiment of this application is shown;

[0027] Figure 5 A schematic diagram of a possible first information interaction circuit provided in one embodiment of this application is shown;

[0028] Figure 6 A schematic diagram of a possible second information interaction circuit provided in one embodiment of this application is shown;

[0029] Figure 7 A schematic diagram of a possible first information interaction circuit provided in one embodiment of this application is shown;

[0030] Figure 8 This illustration shows a possible combination of a first information interaction circuit and a second information interaction circuit according to an embodiment of this application;

[0031] Figure 9 This illustration shows a schematic diagram of another possible combination of the first information interaction circuit and the second information interaction circuit according to an embodiment of this application;

[0032] Figure 10 A schematic diagram of a possible quantum circuit provided in one embodiment of this application is shown. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0034] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0035] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can simultaneously represent both "0" and "1" states, and quantum computers can use quantum entanglement to link the information of all qubits. For example, if there are n bits of data, then 2^n qubits can be used to represent the data of all qubits. n A number of quantum states can be represented simultaneously. Optionally, the qubits in the superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether it's 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0036] Please refer to Figure 1 This illustrates an example system block diagram of a quantum circuit implementing the QAOA algorithm according to an embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0037] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0038] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0039] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0040] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Optionally, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0041] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0042] It should be understood that quantum circuits, as a manifestation of quantum programming, also known as quantum logic circuits, are the most commonly used general-purpose quantum computing model. They represent the circuits that operate on qubits under an abstract concept. Their components include qubits, circuits (timelines), and various quantum logic gates. Finally, the results are often read out through quantum measurement operations.

[0043] Unlike traditional circuits that use metal wires to connect and transmit voltage or current signals, in quantum circuits, the lines can be seen as connected by time. That is, the state of a quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated on.

[0044] A quantum program corresponds to a total quantum circuit, and the quantum program refers to this total quantum circuit, where the total number of qubits in the total quantum circuit is the same as the total number of qubits in the quantum program. It can be understood that a quantum program can consist of a quantum circuit, measurement operations on the qubits in the quantum circuit, registers to store the measurement results, and control flow nodes (jump instructions). A quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution process of a quantum program is the process of executing all the quantum logic gates in a certain timing order. It should be noted that the timing order refers to the chronological order in which individual quantum logic gates are executed.

[0045] To better understand the ideas behind this disclosure, the principle of the QAOA algorithm will be briefly explained again below.

[0046] The QAOA algorithm operates based on the quantum adiabatic theorem, which can be roughly understood as follows: given a physical system, its Hamiltonian evolves from the initial H(0) to the final state H(t). If the system is initially in the nth eigenstate, then when it evolves to the final state H(t), it is also in the nth eigenstate of H(t).

[0047] This theorem allows us to define a time-dependent Hamiltonian:

[0048]

[0049] Let's assume, according to conventional methods (Related papers already exist that use other Hamiltonians as initial systems), H C Given the target Hamiltonian and the system at the initial time, it is in state H. B ground state According to the adiabatic theorem, the final state is H. C The ground state, which is the target state we are looking for. According to the Schrödinger equation, the quantum state of the system at time t is:

[0050]

[0051] Applying Trotter decomposition to the above equation, we can approximate it as:

[0052]

[0053] The process of simulating using quantum circuits involves changing the time parameter to a trainable parameter, resulting in:

[0054]

[0055] Here, α and β are both trainable parameters, thus transforming the problem into a learning problem.

[0056] Therefore, it is necessary to complete the parameter input in the circuit, and at the same time, it is also necessary to complete the circuit construction of this multiplication method. Multiplication is naturally valid in the circuit, so it is necessary to consider exp(-iβ) k H B ) and exp(-iγ k H C () route construction.

[0057] exp(-iβ k H B The corresponding line only requires a series of parallel RX(2β) lines with the same parameters. k The gate can complete the task, while exp(-iγ) k H C Then, Hamiltonian simulation is required. In this disclosure, we can consider the problem of Pauli_Weight=2, which is the dense QUBO problem (QUBO can also be understood as an NP-hard problem).

[0058] exp(-iγ k H C In ) At this point, the line simulated by its Hamiltonian can be as follows: Figure 2 ( Figure 2 As shown in the diagram (which can be understood as a quantum equivalent circuit diagram in related technologies), these two horizontal lines can represent any two qubits respectively. When H CIn denser environments, it may be very costly to exchange bit information between qubits.

[0059] That is, in related technologies, when H C In dense quantum environments, there is usually no simple quantum circuit that can achieve bit information exchange between any two qubits.

[0060] The quantum circuit and quantum computer disclosed herein, which are applied to the QAOA algorithm, enable information exchange between arbitrary qubits. The overall quantum circuit is relatively simple, making it easy to implement on a quantum chip.

[0061] Please see Figure 3 , Figure 3 This disclosure can be understood as a schematic diagram of a quantum circuit applied to the QAOA algorithm. Figure 3 This example uses seven qubits acted upon by the quantum circuit. In specific implementations, the number of qubits acted upon by the quantum circuit can be limited according to the actual situation. Figure 3 The document primarily presents the logic gate connection method of the first information interaction circuit. Specifically:

[0062] In this disclosure, a quantum circuit is used to exchange bit information between any two qubits, and the qubits acted upon by the quantum circuit can be pre-ordered sequentially.

[0063] The quantum circuit may include: a first information interaction circuit, which may include multiple controlled NOT gates acting on adjacent qubits, and the multiple controlled NOT gates may include first-type controlled NOT gates and second-type controlled NOT gates.

[0064] Here, the control bits of the first type of controlled NOT gate are the pre-ordered qubits, while the control bits of the first type of controlled NOT gate are the post-ordered qubits.

[0065] The control bits of the second type of controlled NOT gate are back-ordered qubits, while the control bits of the second type of controlled NOT gate are front-ordered qubits.

[0066] Except for the first and last qubits in the sequence, each qubit serves as the control bit of the first type of controlled NOT gate at least once, and as the control bit of the second type of controlled NOT gate at least once.

[0067] As can be seen, any qubit other than the first and last qubits in the sequence can control the two adjacent qubits. This method facilitates the establishment of entanglement between qubits, thereby enabling the exchange of bit information between them.

[0068] The first type of controlled NOT gate can be understood as follows: in two adjacent qubits, the qubit that is later in the order is controlled by the qubit that is earlier in the order. The second type of controlled NOT gate can be understood as follows: in two adjacent qubits, the qubit that is later in the order controls the qubit that is earlier in the order. This achieves mutual control between adjacent qubits, thus enabling better entanglement.

[0069] In the QAOA algorithm, when H C In dense quantum computing, enabling information exchange between arbitrary qubits is quite difficult. This disclosure addresses this by setting up multiple controlled NOT gates, allowing any qubit to act as both the control bit and a controlled bit of a controlled NOT gate. This facilitates convenient information exchange between any qubits within a large group. Furthermore, due to this setup, when using the QAOA algorithm to solve the dense QUBO problem, the required logic gates in the quantum circuit are only nearest-neighbor dual-qubit logic gates. The overall circuit design better fits a chain structure, making it easier to implement at the current level of superconducting quantum computing chips. This has significant implications for the application and development of quantum computing.

[0070] In some implementations, multiple controlled NOT gates in the first quantum information interaction circuit constitute multiple logic processing layers, which then act sequentially on the qubits.

[0071] Here, the total number of controlled NOT gates included in different logic processing layers is different. Specifically, along the timing direction, the total number of controlled NOT gates included in the preceding logic processing layer is greater than the total number of controlled NOT gates included in the following logic processing layer, or the total number of controlled NOT gates included in the preceding logic processing layer is less than the total number of controlled NOT gates included in the following logic processing layer.

[0072] That is, the total number of controlled NOT gates included in each logic processing layer along the timing direction can increase or decrease sequentially.

[0073] As an example, a logic processing layer can be understood as performing a round of bit information exchange for each quantum bit. However, during the bit information exchange process, it is not necessary to exchange all the bit information in each round. Therefore, the total number of controlled NOT gates included in different logic processing layers can be set differently, which helps to reduce the total number of controlled NOT gates required in quantum circuits and is more conducive to implementation at the chip level.

[0074] As an example, each logic processing layer can include a first-type controlled NOT gate and a second-type controlled NOT gate, and the number of first-type controlled NOT gates and second-type controlled NOT gates can be the same; and the first-type controlled NOT gates correspond to the second-type controlled NOT gates. The correspondence between the first-type controlled NOT gates and the second-type controlled NOT gates can be understood as follows: if a certain first-type controlled NOT gate acts on a group of qubits, then that group of qubits will also be acted on by a certain second-type controlled NOT gate.

[0075] In other words, in a logical processing layer, when a certain qubit is used as a controlled bit, it will also be used as a control bit, thus enabling better interaction of bit information.

[0076] To facilitate understanding of each logical processing layer, it is possible to combine... Figure 4 To explain, in Figure 4 In the diagram, each dashed box can be understood as a logical processing layer. These logical processing layers may have some overlap in their processing timing. Figure 4 As can be seen, the number of controlled NOT gates can be different for each logic processing layer. Figure 4 In this context, each dashed box represents a logical processing layer.

[0077] In some embodiments, in each logic processing layer, the qubits from the end of the sorting to the target position are sequentially used as the controlled bits of the first type of controlled NOT gate;

[0078] Furthermore, the qubits from the end of the sorting to the target position are sequentially used as the control bits of the second type of controlled NOT gate.

[0079] That is, in each logic layer, when a certain qubit is used as the controlled bit of a first-type controlled NOT gate, then the qubit is also used as the control bit of a second-type controlled NOT gate; and in this way, it is convenient to exchange bit information.

[0080] In some embodiments, along the timing direction, the three timing stages corresponding to the first or last logic processing layer are the first timing processing stage, the second timing processing stage, and the third timing processing stage, respectively.

[0081] In the first and third processing stages, the qubits from the end of the sorting to the beginning of the sorting are all acted by the first type of controlled NOT gate.

[0082] In the second time-series processing stage, all qubits from the end of the sorting to the beginning of the sorting are acted upon by a second type of controlled NOT gate.

[0083] As an example, the first or last logic processing layer corresponds to the largest number of controlled NOT gates. For ease of understanding, the controlled NOT gates corresponding to the first or last logic processing layer can be divided into three timing stages. The processing timing of these three stages may have some overlap. To facilitate understanding as three timing stages, we can combine... Figure 5 To explain, in Figure 5 In the diagram, the controlled NOT gate selected by dashed line 501 can be understood as the controlled NOT gate corresponding to the first timing stage, the controlled NOT gate selected by dashed line 502 can be understood as the controlled NOT gate corresponding to the second timing stage, and the controlled NOT gate selected by dashed line 503 can be understood as the controlled NOT gate corresponding to the third timing stage.

[0084] It should be understood that, since real chips are typically chain-like topologies, in this disclosure, dense exp(-iγ) will be used. k H C Improvements will be made, including

[0085] First, the problem can be transformed; its essence can be understood as loading all phases λ. xy This can also be understood as requiring that |q| appear in the quantum circuit for any x,y∈{1,2,...,n}. x +q y That's all.

[0086] For example, consider the initial input states of the qubits: |q1>|q2>|q3>|q4>|q5>...|q n >

[0087] The first step could be |q n-1 >Control|q n > Function of CX gate, |q n-2 >Control|q n-1 >The effect of the CX gate continues until |q1> controls |q2> the effect of the CX gate.

[0088] Therefore, the quantum state becomes: |q1>|q1+q2>|q2+q3>|q3+q4>|q4+q5>...|q n-2 q n-1 >|q n-1 q n >

[0089] The second step could be that the last qubit controls the second-to-last qubit to act as the CX gate, the second-to-last qubit controls the third-to-last qubit to act as the CX gate, and so on, until the second qubit controls the first CX gate. Thus, the quantum state becomes: |q n >|q1+q n >|q2+q n >|q3+qn >|q4+q n >...|q n-3 q n >|q n-2 q n >|q n-1 q n >

[0090] The third step could be that the penultimate qubit controls the last CX gate, the third-to-last qubit controls the penultimate CX gate, and so on, until the first qubit controls the second CX gate. Thus, the quantum state becomes: |q n >|q1>|q1+q2>|q2+q3>|q3+q4>...|q n-4 q n-3 >|q n-3 q n-2 >|q n-2 q n-1 >

[0091] The third step reveals that removing the first qubit from the current state yields the state of the next n-1 qubits after the first step, and at this point, all the states are equal to |q. n The combined quantum target states have all completed their functions. At this point, induction can be completed by repeating the second and third steps.

[0092] The first step mentioned above can correspond to Figure 5 The first step in the process corresponds to the second step, and the third step corresponds to the third step.

[0093] In other words, in quantum circuits, only one logic processing layer needs to perform the above three steps, while other logic processing layers only need to repeat the control logic of the second and third steps.

[0094] This can also be understood as follows: along the timing direction, each logic processing layer other than the first logic processing layer corresponds to two timing stages, namely the fourth timing processing stage and the fifth timing processing stage. In the fourth timing processing stage, the controlled NOT gate is a first-type controlled NOT gate; in the fifth timing processing stage, the controlled NOT gate is a second-type controlled NOT gate.

[0095] In some embodiments of this disclosure, along the timing direction, the corresponding target positions in each logic processing layer can be increased or decreased sequentially.

[0096] In some embodiments, if the target position corresponding to the first logic processing layer is the second positive number in the sorting order, then the target positions in each logic processing layer along the timing direction increase sequentially.

[0097] If the target position corresponding to the first logic processing layer is the last one in the sorting, then the target positions in each logic processing layer along the timing direction decrease sequentially.

[0098] In other words, since the first or last logic layer swaps all qubits, it is not necessary to swap bit information in each logic layer.

[0099] As an example, the controlled NOT gates of this disclosure are reduced or increased sequentially in each logic processing layer along the time sequence, thereby enabling information exchange for qubits to be performed sequentially, which helps to make the overall quantum circuit more concise.

[0100] In some embodiments, the first information interaction circuit may further include multiple single-qubit rotating gates;

[0101] Each qubit, after being acted upon by two consecutive controlled NOT gates, can be acted upon by a single-qubit rotation gate.

[0102] As an example, after two consecutive controlled NOT gates, the state of a qubit can be adjusted through a single-qubit rotation gate, which helps to exchange bit information more accurately.

[0103] As an example, a single-qubit rotation gate can be an RX gate or an RZ gate.

[0104] In some embodiments, the quantum circuit may further include a second quantum information interaction circuit, wherein the first quantum information interaction circuit operates before the second quantum information interaction circuit, and the second quantum information interaction circuit also includes multiple controlled NOT gates that operate on adjacent qubits.

[0105] The first quantum information interaction circuit is used to flip the input first quantum state into a second quantum state, and the second quantum information interaction circuit is used to flip the input second quantum state into the aforementioned first quantum state.

[0106] As an example, since the quantum state of the first quantum information interaction circuit is flipped after the quantum bit information interaction, the circuit can be inverted to complete the entire construction and realize the interaction of all quantum bit information.

[0107] In some embodiments, the logic gate configuration in the first quantum information interaction circuit corresponds to the logic gate configuration in the second quantum information interaction circuit.

[0108] The corresponding methods include:

[0109] In the first quantum information interaction circuit, the logic gate that operates on the i-th qubit is set to operate on the mi-th qubit in the second quantum information interaction circuit.

[0110] 0≤i≤m, m+1 equals the total number of qubits acted upon by the quantum circuit.

[0111] This can be understood as the second quantum information interaction circuit being the inverse of the first quantum information interaction circuit. By merging the first and second quantum information interaction circuits, the entire quantum circuit can be constructed. This completed quantum circuit can then be applied to the QAOA algorithm. Furthermore, when using the QAOA algorithm to solve dense problems, the overall circuit structure is relatively simple, making it easier to implement at the chip level. Therefore, this has significant implications for the application and development of quantum science.

[0112] Can be combined Figure 3 and Figure 6 This invention describes the quantum circuit disclosed herein. Figure 3 This can be understood as a possible schematic diagram of the first information interaction circuit, and Figure 6 This can be understood as a schematic diagram of the second information interaction circuit, combined with... Figure 3 and Figure 6 It can be seen that when the initial input states of the qubits are |q1>|q2>|q3>|q4>|q5>...q n After passing through the first information interaction circuit, the resulting quantum state is |q n >|q n-1 >…|q2>|q1>, at this point, it is still necessary to reduce it to the quantum state |q1>|q2>|q3>|q4>|q5>...q n If this is not the case, then a second information interaction circuit can be used for restoration. The theoretical derivation process is as follows:

[0113] Assume the restored SWAP network matrix is ​​M; let exp{iH′ C}=Mexp{iH″ C}M then exp{iH″ C The line of} is exp{iH′ C The up-and-down flipping circuit of} can be understood as the first information interaction circuit and the second information interaction circuit actually being up-and-down flipping circuits.

[0114] Therefore, for the original formula, only exp{iH′ can be loaded. C} and exp{iH″ C}, at the same time H B It is exchanged with M. Therefore, the original objective function can be rewritten as follows:

[0115]

[0116] In other words, this expression can also be understood as the expression corresponding to quantum circuits.

[0117] To make it easier to understand, we can continue to combine... Figure 7 This invention describes the interaction process of quantum bit information in the quantum circuit disclosed herein. Figure 7 This can be understood as a schematic diagram of a possible first information interaction circuit of this disclosure. When the input quantum state is |q0>|q1>|q2>|q3>|q4>|q5>|q6>, after... Figure 7 The first information interaction circuit shown can be used to perform the quantum state transformation process as follows:

[0118] |q0>|q1>|q2>|q3>|q4>|q5>|q6>

[0119] |q0>|q1>|q2>|q3>|q4>|q6>|q5+q6>

[0120] |q0>|q1>|q2>|q3>|q4>|q4+q6>|q4+q5>

[0121] |q0>|q1>|q2>|q3>|q6>|q5+q6>|q4+q5>

[0122] |q0>|q1>|q2>|q3>|q3+q6>|q3+q5>|q3+q4>

[0123] |q0>|q1>|q2>|q6>|q5+q6>|q4+q5>|q3+q4>

[0124] |q0>|q1>|q2>|q2+q6>|q2+q5>|q2+q4>|q2+q3>

[0125] |q0>|q1>|q6>|q5+q6>|q4+q5>|q3+q4>|q2+q3>

[0126] |q0>|q1>|q1+q6>|q1+q5>|q1+q4>|q1+q3>|q1+q2>

[0127] |q0>|q6>|q5+q6>|q4+q5>|q3+q4>|q2+q3>|q1+q2>

[0128] |q0>|q0+q6>|q0+q5>|q0+q4>|q0+q3>|q0+q2>|q0+q1>

[0129] |q6>|q5+q6>|q4+q5>|q3+q4>|q2+q3>|q1+q2>|q0+q1>

[0130] |q6>|q5>|q4>|q3>|q2>|q1>|q0>

[0131] At this point, after passing through a second information interaction circuit that is an up-and-down flip circuit to the first information interaction circuit, the |q6>|q5>|q4>|q3>|q2>|q1>|q0> can be transformed into |q0>|q1>|q2>|q3>|q4>|q5>|q6> in the manner described above, so that the initial state and the final state remain consistent after passing through the quantum circuit.

[0132] To make it easier to understand, we can continue to combine... Figure 8 and Figure 9 To explain, Figure 8 and Figure 9 This can be understood as a schematic diagram of combining the first information interaction circuit and the second information interaction circuit to form a quantum circuit.

[0133] It should be understood that when the first information interaction circuit and the second information interaction circuit are combined, some logic gates may be merged, so that the total number of logic gates in the final quantum circuit is less than the sum of the total number of logic gates in the first information interaction circuit and the second information interaction circuit.

[0134] It can also be understood that although the quantum circuit is formed by combining the first information interaction circuit and the second information interaction circuit, the first information interaction circuit and the second information interaction circuit can share some logic gates during the combination process. In this way, the total number of logic gates in the quantum circuit can be further reduced, which is more conducive to realizing the quantum circuit designed in this disclosure at the chip level.

[0135] It should be understood that in the quantum circuit disclosed herein, every two layers require a depth of approximately 3n, which means that a depth of approximately 1.5pn is required at a depth of p layers. Therefore, the overall depth is relatively shallow, the complexity is low, and this is more conducive to implementation at the chip level.

[0136] You can continue to refer to Figure 10 Understand the overall diagram of the quantum circuit provided in this disclosure. Figure 10 This can be understood as a schematic diagram of the quantum circuit when the number of active bits is 4 qubits, derived from... Figure 10 As can be seen, the entire quantum circuit structure is relatively simple. Based on this quantum circuit, the initial input state and the final output state can be the same.

[0137] In some embodiments, this disclosure also provides a quantum computer whose quantum chip includes the quantum circuit described above, thereby enabling the quantum computer to run the quantum circuit described above, thereby realizing the computation of dense problems using the QAOA algorithm.

[0138] In some embodiments, the quantum processing system including the quantum computer may specifically perform the following steps:

[0139] Get the dataset to be selected and the filtering criteria;

[0140] Each candidate data in the candidate data set is encoded onto multiple qubits, and a quantum circuit is generated according to the selection criteria;

[0141] By using the generated quantum circuit to act on the above-mentioned multiple qubits, data in the above-mentioned candidate data set that meet the above-mentioned screening criteria are determined;

[0142] The quantum circuit mentioned above includes: a first information interaction circuit, which includes multiple controlled NOT gates acting on adjacent qubits, and the multiple controlled NOT gates include a first type of controlled NOT gate and a second type of controlled NOT gate.

[0143] Among them, the control bits of the first type of controlled NOT gate are pre-ordered qubits, while the controlled bits of the first type of controlled NOT gate are post-ordered qubits.

[0144] The control bits of the second type of controlled NOT gate mentioned above are post-ordered qubits, while the control bits of the second type of controlled NOT gate mentioned above are pre-ordered qubits;

[0145] Except for the first and last qubits in the sequence, each qubit serves as the control bit of the first type of controlled NOT gate at least once, and as the control bit of the second type of controlled NOT gate at least once.

[0146] It should be noted that a quantum processing system can be understood as a combination of a classical computer and a quantum system. In the process described above, the quantum system can perform tasks related to quantum circuits, while other tasks can be performed by the classical computer, and the quantum processing system can refer to... Figure 1 To understand.

[0147] As an example, the candidate data set and filtering conditions can be different in different application scenarios. For example, in the path selection scenario, the candidate data set can be location path data, and the filtering condition can be the shortest path between location A and location B. Or, when the scenario is the maximum cut problem scenario, the candidate data set can be the image vertex information set, and the filtering condition can be how to divide the vertices in the graph into two parts so that the number of edges connecting the two parts is maximized.

[0148] Of course, there are other application scenarios in the specific implementation. In the corresponding application scenarios, it is only necessary to select the appropriate candidate dataset and filtering conditions according to the actual situation.

[0149] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0150] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0151] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0152] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0153] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0154] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0155] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0156] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0158] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0159] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0160] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0161] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum circuit applied to a QAOA algorithm, characterized in that, The quantum circuit is used for bit information interaction of any two quantum bits, and quantum bits acted on by the quantum circuit are sequentially sorted in advance; The quantum circuit comprises a first information interaction circuit, the first information interaction circuit comprises a plurality of controlled NOT gates acting on adjacent quantum bits, and the plurality of controlled NOT gates comprise first-type controlled NOT gates and second-type controlled NOT gates; The control bit of the first-type controlled NOT gate is a quantum bit sorted in front, and the controlled bit of the first-type controlled NOT gate is a quantum bit sorted in back; The control bit of the second-type controlled NOT gate is a quantum bit sorted in back, and the controlled bit of the second-type controlled NOT gate is a quantum bit sorted in front; Except for two quantum bits sorted at the head and the tail, any quantum bit is at least once used as the control bit of the first-type controlled NOT gate and at least once used as the control bit of the second-type controlled NOT gate.

2. The quantum circuit of claim 1, wherein, The plurality of controlled NOT gates in the first quantum information interaction circuit respectively form a plurality of logical processing layers, and the plurality of logical processing layers sequentially act on quantum bits; Each logical processing layer comprises the first-type controlled NOT gate and the second-type controlled NOT gate; The total number of controlled NOT gates included in different logical processing layers is different.

3. The quantum circuit of claim 2, wherein, In each logical processing layer, quantum bits from the end of the sorting to a target bit position are sequentially used as the controlled bits of the first-type controlled NOT gates; And, Quantum bits from the end of the sorting to the target bit position are sequentially used as the control bits of the second-type controlled NOT gates.

4. The quantum circuit of claim 3, wherein, In the time sequence direction, the target bit positions corresponding to the logical processing layers are sequentially increased or sequentially decreased.

5. The quantum circuit of claim 4, wherein, In the time sequence direction, if the target bit position corresponding to the first logical processing layer is the second bit in the sorting, the target bit positions corresponding to the logical processing layers in the time sequence direction are sequentially increased; If the target bit position corresponding to the first logical processing layer is the last bit in the sorting, the target bit positions corresponding to the logical processing layers in the time sequence direction are sequentially decreased.

6. The quantum circuit of claim 5, wherein, In the time sequence direction, three time sequence stages corresponding to the first logical processing layer or the last logical processing layer are a first time sequence processing stage, a second time sequence processing stage and a third time sequence processing stage; In the first time sequence processing stage and the third time sequence processing stage, quantum bits from the end of the sorting to the first bit in the sorting are acted on by the first-type controlled NOT gates; In the second time sequence processing stage, quantum bits from the end of the sorting to the first bit in the sorting are acted on by the second-type controlled NOT gates.

7. The quantum circuit of claim 1, wherein, The first information interaction circuit further comprises a plurality of single quantum bit rotation gates; For each quantum bit, after being acted on by two continuous controlled NOT gates, the quantum bit is acted on by a single quantum bit rotation gate.

8. The quantum circuit of claim 1, wherein, The quantum circuit further comprises a second quantum information interaction circuit, The action time sequence of the first quantum information interaction circuit is before that of the second quantum information interaction circuit, and the second quantum information interaction circuit also comprises a plurality of controlled NOT gates acting on adjacent quantum bits; The first quantum information interaction circuit is used for flipping an input first quantum state into a second quantum state, and the second quantum information interaction circuit is used for flipping the input second quantum state into the first quantum state.

9. The quantum circuit of claim 1, wherein, The logic gate setting mode in the first quantum information interaction circuit corresponds to the logic gate setting mode in the second quantum information interaction circuit; The corresponding mode includes: In the first quantum information interaction circuit, the logic gate acting on the i-th quantum bit is set to act on the m-i-th quantum bit in the second quantum information interaction circuit; 0≤i≤m, m+1 is equal to the total number of quantum bits acted on by the quantum circuit.

10. A quantum computer, comprising: The quantum computer comprises a quantum chip and a quantum measurement and control all-in-one machine, and the quantum chip and the quantum measurement and control all-in-one machine are combined to realize the quantum circuit in any one of claims 1-9.

Images