Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof. In an ith-level gate driving unit of the display device, a gate of a first transistor is electrically connected to a second node, a source and a drain are electrically connected to a first clock signal line and a gate driving signal output end respectively, a gate of a second transistor is electrically connected to a first frequency division signal input end, and a source and a drain are electrically connected to a second node and a first node respectively. The grid electrode and the source electrode of the third transistor are electrically connected to a second frequency division signal input end, the grid electrode of the fourth transistor is electrically connected to the drain electrode of the third transistor, the source electrode and the drain electrode are electrically connected to a first power line and a second node respectively, and the grid electrode of the fifth transistor is electrically connected to a first frequency division signal input end. The source and the drain are electrically connected to the first power supply line and the drain of the third transistor, respectively. By controlling the level states of the first frequency division signal input end and the second frequency division signal input end, different areas of the display panel are refreshed at different refresh frequencies, and the power consumption of the display device is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and a driving method thereof. BACKGROUND

[0002] In practical applications, different regions of the display panel of the display device often need to present different display contents. For example, in some application scenarios, part of the regions of the display panel need to display dynamic changing contents, while other regions only need to display static contents or contents changing slowly.

[0003] In the traditional display device, the gate driving circuit of the display panel usually adopts a uniform refresh frequency to drive the entire display region. Specifically, the gate driving circuit includes multiple cascaded gate driving units, which output gate driving signals in turn according to a fixed timing to drive the pixel units in the display panel to display. In this driving mode, whether the contents displayed by each region of the display panel need to be frequently updated or not, all regions are refreshed at the same refresh frequency.

[0004] When some regions of the display panel display static contents or contents changing slowly, if these regions are still refreshed at a high refresh frequency, it will lead to unnecessary increase of power consumption. This is because in each refresh period, the gate driving unit needs to output a gate driving signal to turn on the transistor in the pixel unit, so as to charge the pixel unit. For the regions displaying static contents, frequent refresh operations will not change the display contents, but will continuously consume electric energy. Especially in large size display panel or high resolution display panel, since the number of pixel units is large, uniformly adopting high refresh frequency to drive the entire display region will lead to high overall power consumption of the display device.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. SUMMARY

[0006] The purpose of the present application is to provide a display device and a driving method thereof, aiming to reduce the power consumption of the display device.

[0007] The application provides a display device, which comprises a display panel, the display panel comprising at least one gate drive circuit and a plurality of pixel units, the gate drive circuit comprising N-stage cascaded gate drive units, N being a positive integer, the i-th stage gate drive unit in the N-stage gate drive units comprising: a first transistor, the gate of which is electrically connected to a second node, one of the source and the drain of which is electrically connected to a first clock signal line, and the other of the source and the drain of which is electrically connected to a gate drive signal output end; a second transistor, the gate of which is electrically connected to a first frequency division signal input end, one of the source and the drain of which is electrically connected to the second node, and the other of the source and the drain of which is electrically connected to a first node; a third transistor, the gate and one of the source and the drain of which are electrically connected to a second frequency division signal input end; a fourth transistor, the gate of which is electrically connected to the other of the source and the drain of the third transistor, one of the source and the drain of which is electrically connected to a first power supply line, and the other of the source and the drain of which is electrically connected to the second node; and a fifth transistor, the gate of which is electrically connected to the first frequency division signal input end, one of the source and the drain of which is electrically connected to the first power supply line, and the other of the source and the drain of which is electrically connected to the other of the source and the drain of the third transistor.

[0008] In the display device, the display area of the display panel comprises a first region and a second region arranged along the column direction of the plurality of pixel units, the plurality of rows of pixel units in the first region are electrically connected to the 1st-stage gate drive unit to the j-1st-stage gate drive unit, the plurality of rows of pixel units in the second region are electrically connected to the jth-stage gate drive unit to the kth-stage gate drive unit, j and k are positive integers, and 1

[0009] In the display device, k < N, the display area further comprises a third area arranged along the column direction with the first area and the second area, and a plurality of pixel units in the third area are electrically connected with the (k+1)th-stage gate driving unit to the Nth-stage gate driving unit; the first area and the third area have the same refresh frequency; the driving period of the P+1th frame picture further comprises a third time period, during which the first level signal is input to the second frequency division signal input end, the second level signal is input to the first frequency division signal input end, and the (k+1)th-stage gate driving unit to the Nth-stage gate driving unit outputs the second level gate driving signal.

[0010] In the display device, when the first level signal is input to the first frequency division signal input end and the second level signal is input to the second frequency division signal input end, the second transistor and the fifth transistor are turned on, the third transistor and the fourth transistor are turned off, and the potential of the first node is transmitted to the second node.

[0011] In the display device, when the second level signal is input to the first frequency division signal input end and the first level signal is input to the second frequency division signal input end, the second transistor and the fifth transistor are turned off, the third transistor and the fourth transistor are turned on, and the potential of the second node is pulled down to the potential of the first power supply line.

[0012] In the display device, the signals input to the first frequency division signal input end and the second frequency division signal input end are inverted.

[0013] In the display device, the gate driving unit of the i-th stage further comprises a sixth transistor, a gate of which is electrically connected to the start signal input terminal, one of a source and a drain of which is electrically connected to the first node, and the other of the source and the drain is electrically connected to the first node; a seventh transistor, a gate of which is electrically connected to the first node, one of a source and a drain of which is electrically connected to the first clock signal line, and the other of the source and the drain is electrically connected to the stage transmission signal output terminal; an eighth transistor, a gate of which is electrically connected to the reset signal input terminal, one of a source and a drain of which is electrically connected to the first node, and the other of the source and the drain is electrically connected to the first power supply line; a ninth transistor, a gate of which is electrically connected to the start signal input terminal, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the third node; a tenth transistor, a gate of which is electrically connected to the first control signal input terminal, one of a source and a drain of which is electrically connected to the third node, and the other of the source and the drain is electrically connected to the third node; an eleventh transistor, a gate of which is electrically connected to the first node, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the third node; a twelfth transistor, a gate of which is electrically connected to the third node, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the first node; a thirteenth transistor, a gate of which is electrically connected to the third node, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the stage transmission signal output terminal; a fourteenth transistor, a gate of which is electrically connected to the third node, one of a source and a drain of which is electrically connected to the second power supply line, and the other of the source and the drain is electrically connected to the gate driving signal output terminal; a fifteenth transistor, a gate of which is electrically connected to the start signal input terminal, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the fourth node; a sixteenth transistor, a gate of which is electrically connected to the second control signal input terminal, one of a source and a drain of which is electrically connected to the fourth node, and the other of the source and the drain is electrically connected to the fourth node; a seventeenth transistor, a gate of which is electrically connected to the first node, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the fourth node; an eighteenth transistor, a gate of which is electrically connected to the fourth node, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the first node; a nineteenth transistor, a gate of which is electrically connected to the fourth node, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain is electrically connected to the stage transmission signal output terminal; and a twentieth transistor, a gate of which is electrically connected to the fourth node, one of a source and a drain of which is electrically connected to the second power supply line, and the other of the source and the drain is electrically connected to the gate driving signal output terminal.A twenty-first transistor, a gate of which is electrically connected to a first pull-down control signal terminal, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain of which is electrically connected to the first node; a twenty-second transistor, a gate of which is electrically connected to a second pull-down control signal terminal, one of a source and a drain of which is electrically connected to the first power supply line, and the other of the source and the drain of which is electrically connected to the gate drive signal output terminal; a first capacitor, two poles of which are electrically connected to the first node and the stage transmission signal output terminal, respectively; and a second capacitor, two poles of which are electrically connected to the second node and the gate drive signal output terminal, respectively.

[0014] The application further provides a driving method of a display device, the display device comprising a display panel, the display panel comprising a plurality of pixel units and N-stage cascaded gate drive units, a display area of the display panel comprising a first area and a second area arranged along a column direction of the plurality of pixel units, a plurality of rows of the pixel units in the first area being electrically connected to a first-stage gate drive unit to a j-1-stage gate drive unit, a plurality of rows of the pixel units in the second area being electrically connected to a j-stage gate drive unit to a k-stage gate drive unit, j and k being positive integers, and 1 < j < k ≤ N, a refresh frequency of the second area being higher than that of the first area, the driving method comprising: in a driving period of a Pth frame of picture, inputting a second-level signal to a second frequency division signal input terminal of the gate drive unit and inputting a first-level signal to a first frequency division signal input terminal of the gate drive unit, so that the first-stage gate drive unit to the N-stage gate drive unit output first-level gate drive signals in turn, P being a positive integer; in a first time period in a driving period of a (P+1)th frame of picture, inputting the first-level signal to the second frequency division signal input terminal of the gate drive unit and inputting the second-level signal to the first frequency division signal input terminal of the gate drive unit, so that the first-stage gate drive unit to the j-1-stage gate drive unit output second-level gate drive signals; in a second time period in the driving period of the (P+1)th frame of picture, inputting the second-level signal to the second frequency division signal input terminal of the gate drive unit and inputting the first-level signal to the first frequency division signal input terminal of the gate drive unit, so that the j-stage gate drive unit to the k-stage gate drive unit output first-level gate drive signals in turn.

[0015] In the driving method, k < N, the display area of the display panel further comprises a third area arranged along the column direction with the first area and the second area, and a plurality of pixel units in the third area are electrically connected with the (k+1)th-stage gate driving unit to the Nth-stage gate driving unit; the refresh frequency of the first area and the third area is the same; the driving period of the (P+1)th frame picture further comprises a third time period, and the driving method further comprises: in the third time period, a first level signal is input to the second frequency division signal input end of the gate driving unit, and a second level signal is input to the first frequency division signal input end of the gate driving unit, so that the (k+1)th-stage gate driving unit to the Nth-stage gate driving unit outputs a gate driving signal of the second level.

[0016] In the driving method, when the first level signal is input to the first frequency division signal input end and the second level signal is input to the second frequency division signal input end, the second transistor and the fifth transistor in the gate driving unit are turned on, the third transistor in the gate driving unit is turned off, and the potential of the first node of the gate driving unit is transmitted to the second node of the gate driving unit.

[0017] In the driving method, when the second level signal is input to the first frequency division signal input end and the first level signal is input to the second frequency division signal input end, the second transistor and the fifth transistor in the gate driving unit are turned off, the third transistor and the fourth transistor in the gate driving unit are turned on, and the potential of the second node of the gate driving unit is pulled down to the potential of the first power supply line.

[0018] In the driving method, the signals input to the first frequency division signal input end and the second frequency division signal input end are inverted.

[0019] The display device provided by the embodiment of the present application realizes output control of the gate driving signal output end by arranging the second transistor, the third transistor, the fourth transistor and the fifth transistor in the gate driving unit and introducing the first frequency division signal input end and the second frequency division signal input end. When the first frequency division signal input end inputs the first level signal and the second frequency division signal input end inputs the second level signal, the second transistor and the fifth transistor are turned on, the third transistor and the fourth transistor are turned off, the potential of the first node is transmitted to the second node through the turned-on second transistor, the second node controls the on-off state of the first transistor, so that the gate driving signal output end outputs the gate driving signal. When the first frequency division signal input end inputs the second level signal and the second frequency division signal input end inputs the first level signal, the second transistor and the fifth transistor are turned off, the third transistor and the fourth transistor are turned on, the turned-on fourth transistor pulls down the potential of the second node to the potential of the first power supply line, the second node is in a low potential state, the first transistor is turned off, and the gate driving signal output end does not output the gate driving signal of the first level. By controlling the level state of the first frequency division signal input end and the second frequency division signal input end, the output control of the gate driving signal output end of a specific gate driving unit is realized without affecting the cascade transmission between the gate driving units, so that different regions of the display panel use different refresh frequencies for refresh. For the region with a lower refresh frequency, the output frequency of the gate driving signal is reduced, the charging frequency of the pixel unit is reduced, and thus the power consumption of the display device is reduced.

[0020] In the display device provided by the embodiment of the present application, the display area of the display panel includes a first region and a second region, and the refresh frequency of the second region is higher than that of the first region. In the driving period of the Pth frame of picture, the second frequency division signal input end inputs the second level signal, the first frequency division signal input end inputs the first level signal, the 1st gate driving unit to the Nth gate driving unit sequentially output the gate driving signal of the first level, and the first region and the second region are refreshed. In the first time period in the driving period of the P+1th frame of picture, the second frequency division signal input end inputs the first level signal, the first frequency division signal input end inputs the second level signal, the 1st gate driving unit to the j-1th gate driving unit corresponding to the first region output the gate driving signal of the second level, and the first region is not refreshed. In the second time period in the driving period of the P+1th frame of picture, the second frequency division signal input end inputs the second level signal, the first frequency division signal input end inputs the first level signal, the jth gate driving unit to the kth gate driving unit corresponding to the second region sequentially output the gate driving signal of the first level, and the second region is refreshed. Through this driving mode, the first region is not refreshed in the driving period of the P+1th frame of picture, and the refresh frequency of the first region is lower than that of the second region, so that the overall power consumption of the display device is reduced.

[0021] In the display device provided by the embodiment of the present application, the display area further comprises a third area, the refresh frequency of the first area and the third area is the same, and the refresh frequency of the second area is higher than the refresh frequency of the first area and the third area. In the third time period of the driving period of the (P+1)th frame picture, the first level signal is input to the second frequency division signal input end, the second level signal is input to the first frequency division signal input end, the second level gate driving signal is output by the k+1th gate driving unit to the Nth gate driving unit corresponding to the third area, and the third area is not refreshed. Through the driving mode, the multiple areas of the display panel are refreshed at different refresh frequencies, the refresh frequency of the first area and the third area is reduced, and the power consumption of the display device is further reduced.

[0022] In the driving method of the display device provided by the embodiment of the present application, the level state of the first frequency division signal input end and the second frequency division signal input end of the gate driving unit is controlled, the output control of the gate driving unit of different areas is realized, different areas of the display panel are refreshed at different refresh frequencies, and the power consumption of the display device is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present application.

[0024] Figure 2 FIG. 2 is a schematic diagram of the partition of the display area of the display device provided by the embodiment of the present application.

[0025] Figure 3 FIG. 3 is a circuit diagram of the gate driving unit of the display device provided by the embodiment of the present application.

[0026] Figure 4 FIG. 4 is a waveform diagram of the driving signal of the Pth frame picture of the display device provided by the embodiment of the present application.

[0027] Figure 5 FIG. 5 is a waveform diagram of the driving signal of the (P+1)th frame picture of the display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0028] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0029] The terms “first”, “second”, and similar words do not represent any order, number, or importance, but are only used to distinguish different technical features. The term “multiple” and similar words represent two or more, unless otherwise explicitly limited.

[0030] The technical solutions of different embodiments of the present application can be combined with each other.

[0031] As Figure 1 shown, the embodiment of the present application provides a display device, which comprises a display panel, a timing controller and a source driving chip. The display panel comprises at least one gate driving circuit and a plurality of pixel units PX, the plurality of pixel units PX are arranged in an array, the gate driving circuit comprises N-stage cascaded gate driving units, and N is a positive integer. The gate driving circuit is integrated on at least one side of the display area of the display panel, and the gate driving circuit is used to provide a gate driving signal to the plurality of pixel units PX to control the opening and closing of the pixel units PX. The timing controller is used to provide a control signal to the gate driving circuit and the source driving chip, and the source driving chip is used to provide a data signal to the plurality of pixel units PX.

[0032] In the embodiment of the present application, the display panel is a liquid crystal display panel, an organic light emitting diode display panel, a mini light emitting diode display panel or a micro light emitting diode display panel. Taking the display panel as a liquid crystal display panel as an example, the display panel comprises a plurality of gate lines SCAN, a plurality of data lines DATA and a plurality of pixel units PX, the plurality of gate lines SCAN extend along a first direction, the plurality of data lines DATA extend along a second direction, the first direction intersects the second direction, and the plurality of pixel units PX are respectively located at the intersection positions of the gate lines SCAN and the data lines DATA.

[0033] As Figure 3 shown, the i-th gate driving unit in the N-stage gate driving unit comprises a first transistor T21, a second transistor T81, a third transistor T83, a fourth transistor T84, a fifth transistor T82, a sixth transistor T11, a seventh transistor T22, an eighth transistor TrQ, a ninth transistor T54, a tenth transistor T51, an eleventh transistor T52, a twelfth transistor T42, a thirteenth transistor T72, a fourteenth transistor T32, a fifteenth transistor T64, a sixteenth transistor T61, a seventeenth transistor T62, an eighteenth transistor T43, a nineteenth transistor T73, a twentieth transistor T33, a twenty-first transistor T41, a twenty-second transistor T31, a first capacitor Ca and a second capacitor Cb, i is a positive integer, and i is less than or equal to N.

[0034] In the embodiments of the present application, the first transistor T21, the second transistor T81, the third transistor T83, the fourth transistor T84, the fifth transistor T82, the sixth transistor T11, the seventh transistor T22, the eighth transistor TrQ, the ninth transistor T54, the tenth transistor T51, the eleventh transistor T52, the twelfth transistor T42, the thirteenth transistor T72, the fourteenth transistor T32, the fifteenth transistor T64, the sixteenth transistor T61, the seventeenth transistor T62, the eighteenth transistor T43, the nineteenth transistor T73, the twentieth transistor T33, the twenty-first transistor T41, and the twenty-second transistor T31 are N-type transistors. The N-type transistor is turned on when a first level signal is input at the gate, and is turned off when a second level signal is input at the gate. The first transistor T21 to the twenty-second transistor T31 can also be P-type transistors, or some transistors are N-type transistors and some transistors are P-type transistors, and the level state of each signal can be adjusted accordingly. The first level is one of a high level and a low level, and the second level is the other of the high level and the low level.

[0035] The gate of the first transistor T21 is electrically connected to the second node Qr(i), one of the source and the drain of the first transistor T21 is electrically connected to the first clock signal line CK(l), and the other of the source and the drain of the first transistor T21 is electrically connected to the gate drive signal output end G(i). The first clock signal line CK(l) is used to provide a clock signal to the first transistor T21, and l is a positive integer. The first transistor T21 is used to be turned on when the second node Qr(i) is at a high potential, to transmit the clock signal of the first clock signal line CK(l) to the gate drive signal output end G(i), so that the gate drive signal output end G(i) outputs a gate drive signal.

[0036] The gate of the second transistor T81 is electrically connected to the first frequency division signal input end Mask1, one of the source and the drain of the second transistor T81 is electrically connected to the second node Qr(i), and the other of the source and the drain of the second transistor T81 is electrically connected to the first node Q(i). The first frequency division signal input end Mask1 is used to receive a first frequency division signal, and the first frequency division signal is a first level signal or a second level signal. The second transistor T81 is used to be turned on when the first frequency division signal input end Mask1 inputs the first level signal, to transmit the potential of the first node Q(i) to the second node Qr(i).

[0037] The gate of the third transistor T83 is electrically connected to the second frequency division signal input terminal Mask2 and one of the source and the drain of the third transistor T83. The second frequency division signal input terminal Mask2 is used to receive a second frequency division signal, which is a first level signal or a second level signal. The third transistor T83 is in diode connection, and is used to be turned on when the first level signal is input to the second frequency division signal input terminal Mask2.

[0038] The gate of the fourth transistor T84 is electrically connected to the other of the source and the drain of the third transistor T83, one of the source and the drain of the fourth transistor T84 is electrically connected to the first power supply line VSSQ, and the other of the source and the drain of the fourth transistor T84 is electrically connected to the second node Qr(i). The first power supply line VSSQ is used to provide a second level signal. The fourth transistor T84 is used to be turned on when the other of the source and the drain of the third transistor T83 is at a high potential, and to pull down the potential of the second node Qr(i) to the potential of the first power supply line VSSQ.

[0039] The gate of the fifth transistor T82 is electrically connected to the first frequency division signal input terminal Mask1, one of the source and the drain of the fifth transistor T82 is electrically connected to the first power supply line VSSQ, and the other of the source and the drain of the fifth transistor T82 is electrically connected to the other of the source and the drain of the third transistor T83 / the gate of the fourth transistor T84. The fifth transistor T82 is used to be turned on when the first level signal is input to the first frequency division signal input terminal Mask1, to pull down the potential of the other of the source and the drain of the third transistor T83 / the gate of the fourth transistor T84 to the potential of the first power supply line VSSQ, so as to make the fourth transistor T84 cut off.

[0040] The gate of the sixth transistor T11 is electrically connected to the start signal input terminal STV / ST(i-4) and one of the source and the drain of the sixth transistor T11, and the other of the source and the drain of the sixth transistor T11 is electrically connected to the first node Q(i). The start signal input terminal STV / ST(i-4) is used to receive a start signal, which is a stage transmission signal output by a stage gate drive unit of a previous stage, or an externally input start signal STV. The sixth transistor T11 is in diode connection, and is used to be turned on when the first level signal is input to the start signal input terminal STV / ST(i-4), to transmit the start signal to the first node Q(i), so as to raise the potential of the first node Q(i).

[0041] The gate of the seventh transistor T22 is electrically connected to the first node Q(i), one of the source and drain of the seventh transistor T22 is electrically connected to the first clock signal line CK(l), and the other of the source and drain of the seventh transistor T22 is electrically connected to the stage transmission signal output terminal ST(i). The stage transmission signal output terminal ST(i) is used to provide a stage transmission signal to the lower-level gate drive unit. The seventh transistor T22 is turned on when the first node Q(i) is at a high potential, transmitting the clock signal of the first clock signal line CK(l) to the stage transmission signal output terminal ST(i), thereby causing the stage transmission signal output terminal ST(i) to output the stage transmission signal.

[0042] The gate of the eighth transistor TrQ is electrically connected to the reset signal input terminal Reset. One of the source and drain of the eighth transistor TrQ is electrically connected to the first node Q(i), and the other of the source and drain of the eighth transistor TrQ is electrically connected to the first power supply line VSSQ. The reset signal input terminal Reset is used to receive a reset signal. The eighth transistor TrQ is used to turn on when a first-level signal is input to the reset signal input terminal Reset, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ, thereby resetting the first node Q(i).

[0043] The gate of the ninth transistor T54 is electrically connected to the start signal input terminal STV / ST(i-4), one of the source and drain of the ninth transistor T54 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the ninth transistor T54 is electrically connected to the third node K(i). The ninth transistor T54 is used to turn on when a first level signal is input to the start signal input terminal STV / ST(i-4), pulling the potential of the third node K(i) down to the potential of the first power supply line VSSQ.

[0044] The gate of the tenth transistor T51, along with one of its source and drain, is electrically connected to the first control signal input terminal LC1. The other of its source and drain is electrically connected to the third node K(i). The first control signal input terminal LC1 receives the first control signal. The tenth transistor T51 is connected in a diode configuration. When a first-level signal is input to the first control signal input terminal LC1, the tenth transistor T51 is turned on, transmitting the first control signal to the third node K(i), thereby raising the potential of the third node K(i).

[0045] The gate of the eleventh transistor T52 is electrically connected to the first node Q(i), one of the source and drain of the eleventh transistor T52 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the eleventh transistor T52 is electrically connected to the third node K(i). The eleventh transistor T52 is used to turn on when the first node Q(i) is at a high potential, pulling the potential of the third node K(i) down to the potential of the first power supply line VSSQ.

[0046] The gate of the twelfth transistor T42 is electrically connected to the third node K(i), one of the source and drain of the twelfth transistor T42 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the twelfth transistor T42 is electrically connected to the first node Q(i). The twelfth transistor T42 is used to turn on when the third node K(i) is at a high potential, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ.

[0047] The gate of the thirteenth transistor T72 is electrically connected to the third node K(i). One of the sources and drains of the thirteenth transistor T72 is electrically connected to the first power supply line VSSQ, and the other of the sources and drains of the thirteenth transistor T72 is electrically connected to the stage transmission signal output terminal ST(i). The thirteenth transistor T72 is used to turn on when the third node K(i) is at a high potential, pulling the potential of the stage transmission signal output terminal ST(i) down to the potential of the first power supply line VSSQ.

[0048] The gate of the fourteenth transistor T32 is electrically connected to the third node K(i). One of the source and drain of the fourteenth transistor T32 is electrically connected to the second power supply line VSSG, and the other of the source and drain of the fourteenth transistor T32 is electrically connected to the gate drive signal output terminal G(i). The second power supply line VSSG is used to provide a second level signal. The fourteenth transistor T32 is used to turn on when the third node K(i) is at a high potential, pulling the potential of the gate drive signal output terminal G(i) down to the potential of the second power supply line VSSG.

[0049] The gate of the fifteenth transistor T64 is electrically connected to the start signal input terminal STV / ST(i-4). One of the source and drain of the fifteenth transistor T64 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the fifteenth transistor T64 is electrically connected to the fourth node P(i). The fifteenth transistor T64 is used to turn on when a first level signal is input to the start signal input terminal STV / ST(i-4), pulling the potential of the fourth node P(i) down to the potential of the first power supply line VSSQ.

[0050] The gate of the sixteenth transistor T61, along with one of its source and drain, is electrically connected to the second control signal input terminal LC2. The other of its source and drain is electrically connected to the fourth node P(i). The second control signal input terminal LC2 is used to receive the second control signal. The sixteenth transistor T61 is connected in a diode configuration. When a first-level signal is input to the second control signal input terminal LC2, the sixteenth transistor T61 is turned on, transmitting the second control signal to the fourth node P(i), thereby raising the potential of the fourth node P(i).

[0051] The gate of the seventeenth transistor T62 is electrically connected to the first node Q(i), one of the source and drain of the seventeenth transistor T62 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the seventeenth transistor T62 is electrically connected to the fourth node P(i). The seventeenth transistor T62 is used to turn on when the first node Q(i) is at a high potential, pulling the potential of the fourth node P(i) down to the potential of the first power supply line VSSQ.

[0052] The gate of the eighteenth transistor T43 is electrically connected to the fourth node P(i), one of the source and drain of the eighteenth transistor T43 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the eighteenth transistor T43 is electrically connected to the first node Q(i). The eighteenth transistor T43 is used to turn on when the fourth node P(i) is at a high potential, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ.

[0053] The gate of the nineteenth transistor T73 is electrically connected to the fourth node P(i), one of the source and drain of the nineteenth transistor T73 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the nineteenth transistor T73 is electrically connected to the stage transmission signal output terminal ST(i). The nineteenth transistor T73 is used to turn on when the fourth node P(i) is at a high potential, pulling the potential of the stage transmission signal output terminal ST(i) down to the potential of the first power supply line VSSQ.

[0054] The gate of the twentieth transistor T33 is electrically connected to the fourth node P(i). One of the sources and drains of the twentieth transistor T33 is electrically connected to the second power supply line VSSG, and the other of the sources and drains of the twentieth transistor T33 is electrically connected to the gate drive signal output terminal G(i). The twentieth transistor T33 is used to turn on when the fourth node P(i) is at a high potential, pulling the potential of the gate drive signal output terminal G(i) down to the potential of the second power supply line VSSG.

[0055] The gate of the 21st transistor T41 is electrically connected to the first pull-down control signal terminal ST(i+5) / Reset. One of the source and drain of the 21st transistor T41 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the 21st transistor T41 is electrically connected to the first node Q(i). The first pull-down control signal terminal ST(i+5) / Reset is used to receive the first pull-down control signal, which is either the stage transmission signal output terminal of the subsequent gate drive unit or the reset signal Reset. The 21st transistor T41 is turned on when the first level signal is input to the first pull-down control signal terminal ST(i+5) / Reset, pulling the potential of the first node Q(i) down to the potential of the first power supply line VSSQ.

[0056] The gate of the 22nd transistor T31 is electrically connected to the second pull-down control signal terminal G(i+4) / Reset. One of the source and drain of the 22nd transistor T31 is electrically connected to the first power supply line VSSQ, and the other of the source and drain of the 22nd transistor T31 is electrically connected to the gate drive signal output terminal G(i). The second pull-down control signal terminal G(i+4) / Reset is used to receive the second pull-down control signal, which is either the gate drive signal output terminal of the subsequent gate drive unit or the reset signal Reset. The 22nd transistor T31 is turned on when the second pull-down control signal terminal G(i+4) / Reset receives a first-level signal, pulling the potential of the gate drive signal output terminal G(i) down to the potential of the first power supply line VSSQ.

[0057] The two plates of the first capacitor Ca are electrically connected to the first node Q(i) and the cascade signal output terminal ST(i), respectively. The first capacitor Ca is used to stabilize the potential of the first node Q(i) and further increase the potential of the first node Q(i) through bootstrapping.

[0058] The two plates of the second capacitor Cb are electrically connected to the second node Qr(i) and the gate drive signal output terminal G(i), respectively. The second capacitor Cb is used to stabilize the potential of the second node Qr(i) and further increase the potential of the second node Qr(i) through bootstrapping.

[0059] In the embodiments of this application, the signals input to the first frequency divider signal input terminal Mask1 and the second frequency divider signal input terminal Mask2 are out of phase. When the first frequency divider signal input terminal Mask1 receives a first-level signal, the second frequency divider signal input terminal Mask2 receives a second-level signal. When the first frequency divider signal input terminal Mask1 receives a second-level signal, the second frequency divider signal input terminal Mask2 receives a first-level signal.

[0060] When the first frequency divider signal input terminal Mask1 receives a first-level signal and the second frequency divider signal input terminal Mask2 receives a second-level signal, the second transistor T81 and the fifth transistor T82 are turned on, while the third transistor T83 and the fourth transistor T84 are turned off. The turned-on second transistor T81 transfers the potential of the first node Q(i) to the second node Qr(i), and the turned-on fifth transistor T82 pulls the potential of the other of the source and drain of the third transistor T83 down to the potential of the first power line VSSQ, thereby causing the gate of the fourth transistor T84 to be at a low potential and the fourth transistor T84 to be turned off. In this case, the potential of the second node Qr(i) follows the potential change of the first node Q(i). When the first node Q(i) is at a high potential, the second node Qr(i) is also at a high potential, the first transistor T21 is turned on, and the gate drive signal output terminal G(i) outputs the gate drive signal.

[0061] When the first frequency divider signal input terminal Mask1 receives a second-level signal and the second frequency divider signal input terminal Mask2 receives a first-level signal, the second transistor T81 and the fifth transistor T82 are turned off, while the third transistor T83 and the fourth transistor T84 are turned on. The turned-on third transistor T83 transmits the first-level signal from the second frequency divider signal input terminal Mask2 to the gate of the fourth transistor T84, thereby turning on the fourth transistor T84. The turned-on fourth transistor T84 pulls the potential of the second node Qr(i) down to the potential of the first power line VSSQ. In this case, the second node Qr(i) is at a low potential, the first transistor T21 is turned off, the gate drive signal output terminal G(i) does not output a first-level gate drive signal, and the gate drive signal output terminal G(i) outputs a second-level gate drive signal.

[0062] Through the cooperation of the second transistor T81, the third transistor T83, the fourth transistor T84 and the fifth transistor T82, the control of the potential of the second node Qr(i) is achieved, thereby realizing the output control of the gate drive signal output terminal G(i). When it is necessary for the gate drive signal output terminal G(i) to output a gate drive signal, by controlling the first frequency division signal input terminal Mask1 to input a first level signal and the second frequency division signal input terminal Mask2 to input a second level signal, the potential of the second node Qr(i) follows the change of the potential of the first node Q(i), so that the gate drive signal output terminal G(i) outputs a gate drive signal. When it is necessary for the gate drive signal output terminal G(i) not to output a gate drive signal of the first level, by controlling the first frequency division signal input terminal Mask1 to input a second level signal and the second frequency division signal input terminal Mask2 to input a first level signal, the potential of the second node Qr(i) is pulled down to the potential of the first power supply line VSSQ, so that the gate drive signal output terminal G(i) does not output a gate drive signal of the first level. In this way, the output control of the gate drive signal output terminal G(i) of a specific gate drive unit is achieved without affecting the cascaded transmission between the gate drive units.

[0063] As Figure 2 shown, the display area of the display panel includes a first area AA1, a second area AA2 and a third area AA3 arranged along the column direction of multiple pixel units PX. Multiple rows of pixel units PX in the first area AA1 are electrically connected to the first-stage gate drive unit to the (j - 1)-th stage gate drive unit, multiple rows of pixel units PX in the second area AA2 are electrically connected to the j-th stage gate drive unit to the k-th stage gate drive unit, and multiple rows of pixel units PX in the third area AA3 are electrically connected to the (k + 1)-th stage gate drive unit to the N-th stage gate drive unit, where j and k are positive integers, and 1 < j < k < N. The refresh frequency of the second area AA2 is higher than that of the first area AA1, and the refresh frequencies of the first area AA1 and the third area AA3 are the same.

[0064] In an embodiment of the present application, the refresh frequencies of the first area AA1 and the third area AA3 are 60 Hz, and the refresh frequency of the second area AA2 is 120 Hz. The first area AA1 and the third area AA3 are used to display static content or content with slow changes, and the second area AA2 is used to display dynamically changing content. By adopting a lower refresh frequency for the first area AA1 and the third area AA3 and a higher refresh frequency for the second area AA2, the overall power consumption of the display device is reduced.

[0065] As Figure 4 and Figure 5 shown, the driving period for the display device to display a frame of picture includes a first time period, a second time period and a third time period.

[0066] During the first time period S1(P) of the driving cycle of the P-th frame, the second frequency divider signal input terminal Mask2 inputs a second level signal, and the first frequency divider signal input terminal Mask1 inputs a first level signal. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off. The first-level gate driving unit to the (j-1)-level gate driving unit sequentially outputs the first-level gate driving signals G1 to Gj-1, and the first region AA1 is refreshed.

[0067] During the second time period S2(P) of the driving cycle of the P-th frame, the second frequency divider signal input terminal Mask2 inputs a second level signal, and the first frequency divider signal input terminal Mask1 inputs a first level signal. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off. The j-th level gate driving unit to the k-th level gate driving unit sequentially output the first level gate driving signals Gj to Gk, and the second region AA2 is refreshed.

[0068] During the third time period S3(P) of the driving cycle of the P-th frame, the second frequency divider signal input terminal Mask2 inputs a second level signal, and the first frequency divider signal input terminal Mask1 inputs a first level signal. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off. The gate driving unit from the (k+1)th level to the Nth level outputs the first level gate driving signals Gk+1 to GN in sequence, and the third region AA3 is refreshed.

[0069] During the first time period S1(P+1) of the driving cycle of the P+1 frame, the first level signal is input to the second frequency divider signal input terminal Mask2, and the second level signal is input to the first frequency divider signal input terminal Mask1. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned off, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned on. The first-level gate driving unit to the (j-1)-level gate driving unit all output the second-level gate driving signals G1 to Gj-1. The first region AA1 is not refreshed.

[0070] During the second time period S2(P+1) of the driving cycle of the P+1 frame, the second frequency divider signal input terminal Mask2 inputs a second level signal, and the first frequency divider signal input terminal Mask1 inputs a first level signal. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned off. The j-th level gate driving unit to the k-th level gate driving unit sequentially output the first level gate driving signals Gj to Gk, and the second region AA2 is refreshed.

[0071] During the third time period S3(P+1) of the driving cycle of the P+1 frame, the first level signal is input to the second frequency divider signal input terminal Mask2, and the second level signal is input to the first frequency divider signal input terminal Mask1. The second transistor T81 and the fifth transistor T82 in the gate driving unit are turned off, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned on. The gate driving units from the (k+1)th level to the Nth level all output the second level gate driving signals Gk+1 to GN. The third region AA3 is not refreshed.

[0072] With the above driving method, the first area AA1 and the third area AA3 are refreshed during the driving cycle of frame P, but not during the driving cycle of frame P+1. The refresh rate of the first area AA1 and the third area AA3 is 60Hz. The second area AA2 is refreshed during both the driving cycles of frame P and frame P+1, and its refresh rate is 120Hz. This driving method enables different areas of the display panel to be refreshed at different refresh rates, reducing the power consumption of the display device.

[0073] In the embodiments of this application, the gate driving unit adopts an 8-clock signal driving method, that is, the gate driving circuit uses 8 clock signal lines to provide clock signals to the gate driving unit. The first clock signal line CK(l) is one of the 8 clock signal lines, and the 8 clock signal lines are CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8, respectively. The 8 clock signal lines sequentially provide clock signals to different gate driving units.

[0074] In embodiments of this application, both the first power line VSSQ and the second power line VSSG are used to provide a second level signal. In some embodiments, the first power line VSSQ and the second power line VSSG are the same power line. In other embodiments, the first power line VSSQ and the second power line VSSG are different power lines, and the potential of the second level signal provided by the first power line VSSQ is the same as or different from the potential of the second level signal provided by the second power line VSSG.

[0075] An embodiment of the present application further provides a driving method for a display device, and this driving method is applied to the above display device. The display device includes a display panel, the display panel includes a plurality of pixel units PX and N-stage cascaded gate driving units, the display area of the display panel includes a first area AA1 and a second area AA2 arranged along the column direction of the plurality of pixel units PX, multiple rows of pixel units PX in the first area AA1 are electrically connected to the first-stage to the (j - 1)-stage gate driving units, multiple rows of pixel units PX in the second area AA2 are electrically connected to the j-stage to the k-stage gate driving units, j and k are positive integers, and 1 < j < k ≤ N, and the refresh frequency of the second area AA2 is higher than that of the first area AA1.

[0076] This driving method includes: in the driving period of the P-th frame of the picture, a second-level signal is input to the second frequency division signal input end Mask2 of the gate driving unit, and a first-level signal is input to the first frequency division signal input end Mask1 of the gate driving unit, so that the first-stage to the N-stage gate driving units sequentially output gate driving signals of the first level, where P is a positive integer. In the first time period S1(P + 1) in the driving period of the (P + 1)-th frame of the picture, a first-level signal is input to the second frequency division signal input end Mask2 of the gate driving unit, and a second-level signal is input to the first frequency division signal input end Mask1 of the gate driving unit, so that the first-stage to the (j - 1)-stage gate driving units output gate driving signals of the second level. In the second time period S2(P + 1) in the driving period of the (P + 1)-th frame of the picture, a second-level signal is input to the second frequency division signal input end Mask2 of the gate driving unit, and a first-level signal is input to the first frequency division signal input end Mask1 of the gate driving unit, so that the j-stage to the k-stage gate driving units sequentially output gate driving signals of the first level.

[0077] In some embodiments, k < N, the display area of the display panel further includes a third area AA3, the third area AA3 is arranged along the column direction with the first area AA1 and the second area AA2, multiple rows of pixel units PX in the third area AA3 are electrically connected to the (k + 1)-stage to the N-stage gate driving units, the refresh frequencies of the first area AA1 and the third area AA3 are the same, and the driving period of the (P + 1)-th frame of the picture further includes a third time period S3(P + 1). This driving method further includes: in the third time period S3(P + 1), a first-level signal is input to the second frequency division signal input end Mask2 of the gate driving unit, and a second-level signal is input to the first frequency division signal input end Mask1 of the gate driving unit, so that the (k + 1)-stage to the N-stage gate driving units output gate driving signals of the second level.

[0078] In the embodiments of this application, when a first level signal is input at the first frequency divider signal input terminal Mask1 and a second level signal is input at the second frequency divider signal input terminal Mask2, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned on, the third transistor T83 in the gate driving unit is turned off, and the potential of the first node Q(i) of the gate driving unit is transferred to the second node Qr(i) of the gate driving unit.

[0079] In the embodiments of this application, when the second level signal is input at the first frequency divider signal input terminal Mask1 and the first level signal is input at the second frequency divider signal input terminal Mask2, the second transistor T81 and the fifth transistor T82 in the gate driving unit are turned off, and the third transistor T83 and the fourth transistor T84 in the gate driving unit are turned on, and the potential of the second node Qr(i) of the gate driving unit is pulled down to the potential of the first power line VSSQ.

[0080] In the embodiments of this application, the signals input to the first frequency divider signal input terminal Mask1 and the second frequency divider signal input terminal Mask2 are out of phase.

[0081] The above driving method enables different areas of the display panel to be refreshed at different refresh rates, thereby reducing the power consumption of the display device.

[0082] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized by comprising: The display device comprises a display panel, the display panel comprising at least one gate drive circuit and a plurality of pixel units, the gate drive circuit comprising N-stage cascaded gate drive units, N being a positive integer, the i-th stage gate drive unit in the N-stage gate drive units comprising: a first transistor, the gate of which is electrically connected to a second node, one of the source and the drain thereof being electrically connected to a first clock signal line, the other of the source and the drain thereof being electrically connected to a gate drive signal output end; a second transistor, the gate of which is electrically connected to a first frequency division signal input end, one of the source and the drain thereof being electrically connected to the second node, the other of the source and the drain thereof being electrically connected to a first node; a third transistor, the gate and one of the source and the drain thereof being electrically connected to a second frequency division signal input end; a fourth transistor, the gate of which is electrically connected to the other of the source and the drain of the third transistor, one of the source and the drain thereof being electrically connected to a first power supply line, the other of the source and the drain thereof being electrically connected to the second node; and a fifth transistor, the gate of which is electrically connected to the first frequency division signal input end, one of the source and the drain thereof being electrically connected to the first power supply line, the other of the source and the drain thereof being electrically connected to the other of the source and the drain of the third transistor.

2. The display device according to claim 1, wherein The display area of the display panel comprises a first region and a second region arranged along a column direction of the plurality of pixel units, a plurality of rows of the pixel units in the first region are electrically connected to the first-stage gate drive unit to the j-1-stage gate drive unit, a plurality of rows of the pixel units in the second region are electrically connected to the j-stage gate drive unit to the k-stage gate drive unit, j and k being positive integers, and 1 < j < k ≤ N; The refresh frequency of the second region is higher than that of the first region; In a driving period of a P-th frame of picture, the second frequency division signal input end inputs a second level signal, the first frequency division signal input end inputs a first level signal, and the first-stage gate drive unit to the N-stage gate drive unit sequentially outputs a gate drive signal of the first level, P being a positive integer; In a first time period in a driving period of a P+1-th frame of picture, the second frequency division signal input end inputs the first level signal, the first frequency division signal input end inputs the second level signal, and the first-stage gate drive unit to the j-1-stage gate drive unit outputs a gate drive signal of the second level; In a second time period in the driving period of the P+1-th frame of picture, the second frequency division signal input end inputs the second level signal, the first frequency division signal input end inputs the first level signal, and the j-stage gate drive unit to the k-stage gate drive unit sequentially outputs a gate drive signal of the first level.

3. The display device according to claim 2, wherein k < N, the display area further comprises a third region, the third region being arranged along the column direction with the first region and the second region, a plurality of rows of the pixel units in the third region being electrically connected to the k+1-stage gate drive unit to the N-stage gate drive unit; The refresh frequencies of the first region and the third region are the same; The driving period of the (P+1)th frame picture further comprises a third time period, during which the second frequency division signal input end inputs a first level signal, the first frequency division signal input end inputs a second level signal, and the (k+1)th to Nth gate driving units output gate driving signals of the second level.

4. The display device according to claim 1, wherein When the first frequency division signal input end inputs the first level signal and the second frequency division signal input end inputs the second level signal, the second transistor and the fifth transistor are turned on, the third transistor and the fourth transistor are turned off, and the potential of the first node is transmitted to the second node.

5. The display device according to claim 1, wherein When the first frequency division signal input end inputs the second level signal and the second frequency division signal input end inputs the first level signal, the second transistor and the fifth transistor are turned off, the third transistor and the fourth transistor are turned on, and the potential of the second node is pulled down to the potential of the first power supply line.

6. The display device according to claim 1, wherein The signals input by the first frequency division signal input end and the second frequency division signal input end are inverted.

7. The display device according to claim 1, wherein The (i)th gate driving unit further comprises: a sixth transistor, one of a gate and a source and a drain thereof being electrically connected to a start signal input end, and the other being electrically connected to the first node; a seventh transistor, a gate thereof being electrically connected to the first node, one of a source and a drain thereof being electrically connected to the first clock signal line, and the other being electrically connected to a stage transmission signal output end; an eighth transistor, a gate thereof being electrically connected to a reset signal input end, one of a source and a drain thereof being electrically connected to the first node, and the other being electrically connected to the first power supply line; a ninth transistor, a gate thereof being electrically connected to the start signal input end, one of a source and a drain thereof being electrically connected to the first power supply line, and the other being electrically connected to a third node; a tenth transistor, one of a gate and a source and a drain thereof being electrically connected to a first control signal input end, and the other being electrically connected to the third node; an eleventh transistor, a gate thereof being electrically connected to the first node, one of a source and a drain thereof being electrically connected to the first power supply line, and the other being electrically connected to the third node; a twelfth transistor, a gate thereof being electrically connected to the third node, one of a source and a drain thereof being electrically connected to the first power supply line, and the other being electrically connected to the first node; a thirteenth transistor, a gate thereof being electrically connected to the third node, one of a source and a drain thereof being electrically connected to the first power supply line, and the other being electrically connected to the stage transmission signal output end; a fourteenth transistor, a gate thereof being electrically connected to the third node, one of a source and a drain thereof being electrically connected to a second power supply line, and the other being electrically connected to a gate driving signal output end; a fifteenth transistor, a gate thereof being electrically connected to the start signal input end, one of a source and a drain thereof being electrically connected to the first power supply line, and the other being electrically connected to a fourth node; The sixteenth transistor has one of a gate and a source and a drain electrically connected to the second control signal input terminal, and the other of the source and the drain electrically connected to the fourth node; The seventeenth transistor has a gate electrically connected to the first node, one of a source and a drain electrically connected to the first power supply line, and the other of the source and the drain electrically connected to the fourth node; The eighteenth transistor has a gate electrically connected to the fourth node, one of a source and a drain electrically connected to the first power supply line, and the other of the source and the drain electrically connected to the first node; The nineteenth transistor has a gate electrically connected to the fourth node, one of a source and a drain electrically connected to the first power supply line, and the other of the source and the drain electrically connected to the stage transmission signal output terminal; The twentieth transistor has a gate electrically connected to the fourth node, one of a source and a drain electrically connected to the second power supply line, and the other of the source and the drain electrically connected to the gate drive signal output terminal; The twenty-first transistor has a gate electrically connected to the first pull-down control signal terminal, one of a source and a drain electrically connected to the first power supply line, and the other of the source and the drain electrically connected to the first node; The twenty-second transistor has a gate electrically connected to the second pull-down control signal terminal, one of a source and a drain electrically connected to the first power supply line, and the other of the source and the drain electrically connected to the gate drive signal output terminal; The first capacitor has two poles respectively electrically connected to the first node and the stage transmission signal output terminal; and The second capacitor has two poles respectively electrically connected to the second node and the gate drive signal output terminal.

8. A driving method of a display device, comprising the steps of: The display device includes a display panel including a plurality of pixel units and N-stage cascaded gate drive units, a display area of the display panel includes a first area and a second area arranged along a column direction of the plurality of pixel units, a plurality of rows of the pixel units in the first area are electrically connected to the 1st gate drive unit to the j-1st gate drive unit, a plurality of rows of the pixel units in the second area are electrically connected to the jth gate drive unit to the kth gate drive unit, j and k are positive integers, and 1 In the driving period of the Pth frame of picture, the second frequency division signal input terminal of the gate drive unit inputs the second level signal, and the first frequency division signal input terminal of the gate drive unit inputs the first level signal, so that the 1st gate drive unit to the Nth gate drive unit output the first level of gate drive signal in turn, P is a positive integer; In the first time period in the driving period of the P+1th frame of picture, the second frequency division signal input terminal of the gate drive unit inputs the first level signal, and the first frequency division signal input terminal of the gate drive unit inputs the second level signal, so that the 1st gate drive unit to the j-1st gate drive unit output the second level of gate drive signal; In a second time period in the driving period of the P+1th frame picture, a second level signal is input to the second frequency division signal input end of the gate driving unit, and a first level signal is input to the first frequency division signal input end of the gate driving unit, so that the jth gate driving unit to the kth gate driving unit output the gate driving signal of the first level in turn.

9. The driving method according to claim 8, wherein k<N, the display area of the display panel further comprises a third area, the third area and the first area and the second area are arranged along the column direction, and a plurality of rows of the pixel units in the third area are electrically connected with the k+1th gate driving unit to the Nth gate driving unit; The refresh frequencies of the first area and the third area are the same; The driving period of the P+1th frame picture further comprises a third time period, and the driving method further comprises: In the third time period, a first level signal is input to the second frequency division signal input end of the gate driving unit, and a second level signal is input to the first frequency division signal input end of the gate driving unit, so that the k+1th gate driving unit to the Nth gate driving unit output the gate driving signal of the second level.

10. The driving method according to claim 8, wherein When the first level signal is input to the first frequency division signal input end and the second level signal is input to the second frequency division signal input end, the second transistor and the fifth transistor in the gate driving unit are turned on, the third transistor in the gate driving unit is turned off, and the potential of the first node of the gate driving unit is transmitted to the second node of the gate driving unit.

11. The driving method according to claim 8, wherein When the second level signal is input to the first frequency division signal input end and the first level signal is input to the second frequency division signal input end, the second transistor and the fifth transistor in the gate driving unit are turned off, the third transistor and the fourth transistor in the gate driving unit are turned on, and the potential of the second node of the gate driving unit is pulled down to the potential of the first power supply line.

12. The driving method according to claim 8, wherein The signals input to the first frequency division signal input end and the second frequency division signal input end are inverted.

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