Signal distortion suppression circuit and method, display device and system

Abstract

The invention discloses a signal distortion suppression circuit, a signal distortion suppression method, display equipment and a signal distortion suppression system. The signal distortion suppression circuit comprises a signal input port, a data extraction unit, a feature code control module, a polarity reversal output module and a signal output port, wherein the feature code control module is used for solidifying a unique feature code of the display equipment; the polarity reversal output module is connected between the signal input port and the signal output port and is used for performing polarity reversal on a signal from the signal input port and then outputting the signal from the signal output port; the data extraction unit is connected with the feature code control module and the display equipment, is also connected to the signal input port, and is used for selectively performing polarity reversal processing on a signal from the signal input port according to the parity of a feature code in the feature code control module, and outputting the signal to the display equipment; and extracting effective data corresponding to the feature code.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic communication and display technology, in particular to a signal distortion suppression circuit, method, display device and system. BACKGROUND

[0002] In LED display screen, industrial control bus and other applications, a plurality of display devices are often connected in a serial cascade mode. A Schmitt trigger is usually included in each display device for signal shaping. However, due to the influence of semiconductor process deviation, PCB wiring and the parasitic parameters of resistance, capacitance and inductance in the circuit, the rising edge and falling edge of the digital signal will produce asymmetric time delay distortion (for example, the rising edge becomes slower to a greater extent than the falling edge) when passing through the Schmitt trigger of each device. In the traditional "receiving-shaping-forwarding" cascade mode, this asymmetric distortion will be linearly accumulated along the link, resulting in a serious deviation of the signal pulse width from the original value, and ultimately making the device at the end of the link unable to correctly identify the data, and the system reliability decreases sharply.

[0003] The prior art mainly alleviates the signal distortion problem by reducing the transmission rate, optimizing the layout of the circuit or adding an anti-interference magnetic ring, but it is difficult to fundamentally solve the signal distortion problem caused by the characteristics of the Schmitt trigger in the serial cascade system. SUMMARY

[0004] The present application provides a signal distortion suppression circuit, method, display device and system to solve the technical problem that the existing signal distortion alleviation scheme is difficult to fundamentally solve the signal distortion problem caused by the characteristics of the Schmitt trigger in the serial cascade system.

[0005] In a first aspect, the present application provides a signal distortion suppression circuit applied to a display device with a Schmitt trigger, comprising a signal input port, a data extraction unit, a feature code control module, a polarity inversion output module and a signal output port; wherein, The feature code control module is used to solidify the unique feature code of the display device. The polarity inversion output module is connected between the signal input port and the signal output port, and is used to output the signal from the signal input port after polarity inversion from the signal output port. The data extraction unit is connected to the feature code control module and the display device, and is also connected to the signal input port, and is used to selectively perform polarity inversion processing on the signal from the signal input port according to the parity of the feature code in the feature code control module, and extract the valid data corresponding to the feature code.

[0006] In a second aspect, the present application provides a display device, comprising a Schmitt trigger, a display module and the signal distortion suppression circuit as described above, wherein the input end of the Schmitt trigger receives an external signal, the signal input port of the signal distortion suppression circuit is connected to the output end of the Schmitt trigger, and the output end of the data extraction module is connected to the display module for driving display.

[0007] In a third aspect, the present application provides a display system, comprising a controller and a plurality of display devices as described above, the plurality of display devices are connected in series in sequence, and the output end of the controller is connected to the signal input port of the first display device.

[0008] In a fourth aspect, the present application provides a signal distortion suppression method applied to the display system as described above, the signal distortion suppression method comprises: sending a feature code configuration signal to each display device connected in series through the transmission link of the display system; according to the connection sequence, each display device solidifies its own feature code in sequence through the feature code control module according to the received feature code configuration signal; each display device reverses the polarity of the input signal received by the polarity inversion output module and outputs it to the next display device connected in series; each display device selectively performs the NOT operation on the input signal according to the parity of the feature code through the data extraction unit, and parses the valid data corresponding to its own feature code from the NOT or non-NOT signal and outputs it to the display module for display.

[0009] Compared with the prior art, the polar inversion output module is arranged, the input signal can be output after polar inversion, the data extraction unit is further arranged inside, the signal from the signal input port is selectively subjected to polar inversion processing according to the parity of the display device characteristic code by the data extraction unit, and the valid data corresponding to the characteristic code is extracted, when the display device is applied to cascaded connection, each device can output the input signal after inversion, the polarity of the signal on the link alternately changes, the edges processed by adjacent devices are opposite (the rising edge of the previous display device becomes the falling edge of the next display device), thus the large delay of a certain edge by the previous device is transferred to the small delay of the opposite edge by the next device, distortion is converted from linear accumulation to oscillation compensation, the cascaded distortion accumulation effect is avoided, the signal distortion problem is fundamentally solved, the system performance is not affected, the cascaded depth and signal transmission distance are greatly improved, and inside the device, whether the signal is inverted before data extraction is determined according to the parity of the characteristic code, so that the signal polarity is consistent with the original transmitted signal during internal processing, and the data can be correctly extracted, it can be seen that, the strategy of combining polar inversion output and internal parity selective inversion is adopted, the problem of accumulation of signal asymmetric distortion in the cascaded link is effectively solved without increasing additional signal lines and without significantly increasing the cost. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0011] Figure 1 It is a circuit schematic diagram of the signal distortion suppression circuit provided by an embodiment of the present application.

[0012] Figure 2 It is Figure 1 The waveform diagram of the signal distortion suppression circuit shown in FIG. 8 is applied to the output of each display device in a display system.

[0013] Figure 3 It is Figure 1 Another waveform diagram of the signal distortion suppression circuit shown in FIG. 8 is applied to the output of each display device in a display system.

[0014] Figure 4 It is a structural block diagram of the display system provided by an embodiment of the present application.

[0015] Figure 5 It is Figure 4 The structural block diagram of the display device in the display system shown in FIG. 10.

[0016] Figure 6 is a flowchart of a signal distortion suppression method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.

[0018] It should be understood that the terms "comprise" and "include" as used in the specification and the appended claims indicate the presence of the described features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or groups thereof.

[0019] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and the appended claims of the present application, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should be further understood that the term "and / or" as used in the specification and the appended claims of the present application means any combination of one or more of the associated listed terms and all possible combinations, and includes these combinations.

[0020] Reference Figure 1 , Figure 1It is a circuit structure schematic diagram of a specific embodiment of the signal distortion suppression circuit of the present application. The signal distortion suppression circuit of the present application can be applied to a display device with a Schmitt trigger. In the embodiment shown in the drawing, the signal distortion suppression circuit comprises a signal input port A, a data extraction unit 30, a feature code control module 10, a polarity inversion output module 20 and a signal output port B. The feature code control module 10 is used to solidify the unique feature code of the display device. The polarity inversion output module 20 is connected between the signal input port A and the signal output port B and is used to output the signal from the signal input port A after polarity inversion from the signal output port B. The data extraction unit 30 is connected with the feature code control module 10 and the display device and is also connected to the signal input port A. It is used to selectively perform polarity inversion processing on the signal from the signal input port A according to the parity of the feature code in the feature code control module 10 and extract the valid data corresponding to the feature code. In the present application, the feature code is a unique identifier solidified in each display device and can be an integer (such as 0, 1, 2, …). It can be understood that the feature code of each display device is unique on the same associated link. The feature code can be used not only for device identification but also for data extraction addressing, that is, the corresponding valid data is extracted according to the feature code. In the present application, the parity is used as a control signal to determine whether the received signal is subjected to a polarity inversion operation inside the device, thereby forming a compensation mechanism for suppressing signal distortion accumulation in combination with fixed output inversion.

[0021] Based on the above design, when the signal distortion suppression circuit of the present application is applied to each display device in a cascade connection, the different response characteristics of adjacent display devices to opposite edges are utilized to offset the distortion in positive and negative conversion, eliminating the cascade distortion accumulation effect. That is, the signal distortion suppression circuit in each display device can output the input signal after inversion. The polarity of the signal alternates on the link, so that the edges processed by adjacent devices are opposite (the rising edge of the previous display device becomes the falling edge of the next display device), thereby transferring the large delay of a certain edge of the previous device to the small delay of the opposite edge of the next device, converting the linear accumulation of distortion into oscillatory compensation, fundamentally solving the signal distortion problem without affecting the system performance, greatly improving the cascade depth and signal transmission distance. Moreover, inside the device, it is determined whether to invert the signal before extracting the data according to the parity of the feature code, so that the signal polarity is consistent with the original transmitted signal during internal processing, ensuring that the data can be correctly extracted.

[0022] In some embodiments, the data extraction unit 30 comprises an inverting selection circuit and a decoding module 32. The input end of the inverting selection circuit is connected to the signal input port A, the control end thereof is connected to the feature code control module 10, and the inverting selection circuit is configured to: when the feature code is odd, output the signal from the signal input port A inversely; and when the feature code is even, output the signal from the signal input port A directly. The decoding module 32 is connected to the output end of the inverting selection circuit, and is used to extract the valid data corresponding to the feature code from the signal output by the inverting selection circuit. Preferably, in the present embodiment, the decoding module 32 can be implemented by a data decoder.

[0023] Specifically, as shown in Figure 1 The inverting selection circuit comprises a first multiplexer S1 and a first inverter NOT1. The first input end of the first multiplexer S1 is connected to the signal input port A, the second input end thereof is connected to the signal input port A through the first inverter NOT1, and the selection control end of the first multiplexer S1 is connected to the feature code control module 10, so as to select the signal from the first input end or the second input end to be transmitted to the decoding module 32 according to the parity information of the feature code from the feature code control module 10. Based on the above design, when the feature code is even, the first input end of the first multiplexer S1 and the output end thereof are gated, so as to output the signal from the signal input port A directly to the decoding module 32 for decoding and extraction; and when the feature code is odd, the second input end of the first multiplexer S1 and the output end thereof are gated, so as to output the signal after inversion by the first inverter NOT1 to the decoding module 32 for decoding and extraction.

[0024] In some embodiments, the feature code control module 10 comprises a feature code storage unit 11 and a configuration management unit 12, wherein the feature code storage unit 11 is configured to store the unique feature code of the display device; the configuration management unit 12 is connected between the signal input port A and the feature code storage unit 11, and is configured to write the feature code into the feature code storage unit 11 according to the input signal containing the feature code configuration information in the feature code configuration mode; and the configuration management unit 12 is further connected to the selection control end of the first multiplexer S1 and the signal output port B, and is configured to send the selection control signal representing the parity information of the feature code to the first multiplexer S1 according to the parity of the feature code, and generate the feature code configuration signal containing the updated feature code information based on the feature code stored in the feature code storage unit 11, and output the feature code configuration signal through the signal output port B. In this embodiment, the configuration management unit 12 can be implemented based on a microcontroller or the like; when the feature code is odd, the selection control signal can be high; when the feature code is even, the selection control signal can be low; and the generation of the feature code configuration signal containing the updated feature code information specifically refers to performing a plus one operation on the stored feature code value to generate the feature code configuration information for the next associated display device, i.e., the updated feature code information. It can be understood that in some other embodiments, the selection control signal can also be adjusted according to the model of the first multiplexer S1 and its connection with the signal input port A and the first inverter NOT1. Based on the above design, in the present application, the signal input by the signal input port A can be a feature code configuration signal or a display signal, and initially the display device can also be subjected to a feature code solidification operation, and after solidification, the display signal is transmitted.

[0025] Preferably, in some embodiments, the output end of the decoding module 32 in the data extraction unit 30 is further connected to the configuration management unit 12 in the feature code control module 10, and the decoding module 32 in the data extraction unit 30 can be further configured to: perform frame type identification on the signal input from the signal input port A, when identifying as a feature code configuration frame, route it to the configuration management unit 12 for feature code solidification; when identifying as a display data frame, extract the valid display data corresponding to the feature code, and route it to the display module of the display device for display. It can be understood that during initialization, the first input end of the first multiplexer S1 can be pre-set to be in communication with the output end thereof, so that the input feature code configuration signal can be directly input to the decoding module 32 for decoding identification, and transmitted to the configuration management unit 12 for feature code solidification.

[0026] Further, in the embodiment, the polarity inversion output module 20 comprises a second inverter NOT2 and a second multiplexer S2; wherein an input terminal of the second inverter NOT2 is connected to the signal input port A for receiving the display signal; a first input terminal and a second input terminal of the second multiplexer S2 are connected to the second inverter NOT2 and the output terminal of the configuration management unit 12 respectively for receiving the inverted display signal and the feature code configuration signal containing the updated feature code information, and an output terminal of the second multiplexer S2 is connected to the signal output port B; and a selection control terminal of the second multiplexer S2 is connected to the output terminal of the decoding module 32 for receiving the routing control signal from the decoding module 32, and the second multiplexer S2 selects to transmit the feature code configuration signal to the signal output port B in response to the routing control signal indicating the feature code configuration mode, and selects to transmit the inverted display signal to the signal output port B in response to the routing control signal indicating the display mode. In the embodiment, the routing control signal indicating the feature code configuration mode can be high level, and the routing control signal indicating the display mode can be low level. It can be understood that in some other embodiments, the routing control signal indicating the feature code configuration mode can also be low level, and the routing control signal indicating the display mode can be high level. Based on the above design, the decoding module 32 outputs the routing control signal indicating the feature code configuration mode / display mode to the selection control terminal of the second multiplexer S2 according to the result of frame type identification, so as to select the second input terminal / first input terminal of the second multiplexer S2 and the output terminal thereof, and output the feature code configuration signal containing the updated feature code configuration information in the feature code configuration mode, and output the inverted display signal in the display mode.

[0027] It can be understood that when the signal distortion suppression circuit of the present application is applied to a display device connected in cascade, initialization can be performed first to fix the feature code. After the signal input port A receives the feature code configuration signal, the input signal enters the decoding module 32 from the first input end of the first multiplexer S1 for decoding. The decoding module 32 performs frame type identification on the signal. When the identification result is a feature code configuration frame, the feature code configuration signal is sent to the configuration management unit 12 of the feature code control module 10. The configuration management unit 12 writes the feature code into the feature code storage unit 11 according to the feature code configuration signal, and at the same time, the feature code of the configuration management unit 12 is incremented by 1 to generate a feature code configuration signal containing the updated feature code information. The decoding module 32 also sends a routing control signal indicating the feature code configuration mode to the second multiplexer S2 to output the feature code configuration signal containing the updated feature code information to the next display device connected in cascade, so that each display device connected in cascade in turn fixes the feature code according to the feature code configuration signal containing the updated feature code information output by the previous display device, and allocates a unique feature code to each display device. In this embodiment, after the feature code is fixed, if the feature code configuration signal is received again, the feature code fixing operation is not performed, and the feature code configuration signal with the feature code incremented by 1 is directly output. After the feature codes of all display devices are fixed, when the display signal (display frame) is received, the signal path is multiplexed as a display signal transmission path, that is, the first input end of the second multiplexer S2 is selected and the output end is selected. The signal output port B directly outputs the display signal taken by the second inverter NOT2 to the next display device connected in cascade. In the device, the configuration management unit 12 also sends a selection control signal representing the parity of the feature code to the first multiplexer S1 according to the input feature code configuration signal. If the feature code is odd, the second input end of the first multiplexer S1 is selected and the output end is selected. The display signal is transmitted to the decoding module 32 after being inverted by the first inverter NOT1. The decoding module 32 takes out the feature code display frame corresponding to the feature code of the display signal and sends it to the display module of the display device for display. If the feature code is even, the first input end of the first multiplexer S1 is selected and the output end is selected. The display signal is directly transmitted to the decoding module 32. The decoding module 32 takes out the feature code display frame corresponding to the feature code of the display signal and sends it to the display module of the display device for display.

[0028] As can be seen, the signal distortion suppression circuit of the present application can be applied to each display device connected in cascade. When used, the polarity alternation inversion mechanism is used to suppress the distortion (widening / narrowing) of the pulse width in the positive and negative alternation conversion, as shown in Figure 2 and Figure 3 , Figure 2 and Figure 3 , respectively, which respectively show the suppression effect in the case of slow falling edge and slow rising edge, as shown in Figure 2As shown, the falling edge of the second display device is outputted slowly, and if the third display device is directly outputted, the waveform pulse will be widened. After the inverting output, the original rising edge is turned to the falling edge output, the falling waveform will be slow, and the original falling edge is turned to the rising edge output, which changes less, and is suppressed back in the fourth device and then inverted output, and so on. Similarly, the rising edge is slower than the falling edge (for example Figure 3 ), and if the three devices are directly outputted, the waveform will be narrowed. After the inverting output, the original falling edge is turned to the rising edge, the rising waveform will be slow, and the original rising edge is turned to the falling edge output, which changes less, and is suppressed back in the fourth device and then inverted output, and so on. The distortion can be prevented from accumulating in a single direction (such as the same edge continuously slowing down), and the distortion can be converted from linear accumulation to oscillation compensation. The distortion suppression can be realized by a hardware circuit, which has fast response, high reliability, clear circuit structure, and is easy to integrate into the existing cascade device architecture using the Schmidt trigger. Without increasing additional signal lines and reducing the transmission rate, the cascade depth and signal transmission stability of the system are significantly improved. In the device, whether the signal is inverted before data extraction is determined according to the parity of the characteristic code, so that the signal polarity is consistent with the original transmitted signal during internal processing, and the data can be correctly extracted.

[0029] Referring to Figures 4 to 5 , Figures 4 to 5 A specific embodiment of the display system is shown. In the embodiment shown in the drawings, the display system includes a controller 200 and N display devices 100, the N display devices 100 are connected in series in turn, and the output end of the controller 200 is connected to the signal input port of the first display device 100. As shown in the drawings, Figure 5As shown, in the embodiment, the display device 100 comprises a Schmitt trigger 40, a display module 50, and the signal distortion suppression circuit described in the above embodiment, wherein the input end of the Schmitt trigger 40 receives an external signal, the signal input port A of the signal distortion suppression circuit is connected to the output end of the Schmitt trigger 40, and the output end of the data extraction module 30 is connected to the display module 50 for driving display. Based on the above design, after the initialization feature code is solidified, in operation, the controller 200 sends a display signal to the signal input port of the display device 1, and the signal distortion suppression circuit in the display device 1 processes the display signal in two ways. One way is internal processing, which determines whether to invert and send the display signal to the decoding module 32 by judging the feature code of the display device 100. When the feature code is even, the signal distortion suppression circuit sends the display frame corresponding to the feature code of the display device 100 in the display signal to the display module 50 for subsequent system display. When the feature code is odd, the signal distortion suppression circuit inverts the display signal, and then sends the display frame corresponding to the feature code of the display device 100 in the inverted display signal to the display module 50 for subsequent system display. The other way is output processing, which inverts and outputs the input display signal to the next display device 100.

[0030] As can be seen, in the embodiment, the plurality of cascaded display devices 100 output the display signal alternately by inverting the polarity, and the different response characteristics of adjacent display devices 100 to opposite edges are used to suppress the distortion caused by the inconsistent (asymmetric) responses of the Schmitt trigger 40 of each device to rising and falling edges. The signal distortion suppression circuit in each display device 100 processes the display signal internally according to the parity of the feature code of the device, and the polarity of the display signal processed by the internal decoding module 32 of each node is consistent with the original transmitted signal, ensuring that the data can be correctly extracted.

[0031] Referring to Figure 6 , Figure 6 A flowchart of the signal distortion suppression method provided by an embodiment of the application is shown. The signal distortion suppression method of the application is implemented based on the signal distortion suppression circuit described in the above embodiment and can be applied to the display system described above, and comprises the following steps. S1. A feature code configuration signal is sent to each cascaded display device through the transmission link of the display system.

[0032] In this step, the feature code configuration signal of the first display device is sent by the controller, and the feature code configuration signal of the subsequent display device is sent by the previous display device.

[0033] S2, according to the cascade order, the plurality of display devices solidify their respective feature codes in turn according to the received feature code configuration signals through the respective feature code control modules.

[0034] In this step, after the first display device solidifies the feature code, the first display device performs a plus 1 operation on the feature code to generate an updated feature code, and outputs a feature code configuration signal containing the updated feature code to the next display device. The next display device performs feature code solidification according to the updated feature code, and also performs a plus 1 operation on the feature code and outputs the result to the next display device. In this way, the feature code solidification of all the cascade display devices is completed according to the cascade order.

[0035] S3, each display device performs polarity inversion on the received input signal through the polarity inversion output module, and outputs the result to the next cascade-connected display device.

[0036] In this step, after all the feature codes are solidified, the first display device transmits the received display signal to the second display device after performing an inversion operation on the received display signal. The second display device transmits the received inverted display signal to the third display device after performing an inversion operation on the received inverted display signal. Each display device outputs the received display signal after performing an inversion operation on the received display signal.

[0037] S4, each display device selectively performs an inversion operation on the input signal according to the parity of the feature code through the data extraction unit, and parses the valid data corresponding to the feature code from the inverted or non-inverted signal and outputs the result to the display module for display.

[0038] In this step, each display device internally performs display processing on the display signal according to the parity of the feature code. Specifically, if the feature code is odd, the input signal is inverted, and the inverted input signal is parsed to obtain the valid data corresponding to the feature code. If the feature code is even, the input signal is directly parsed to obtain the valid data corresponding to the feature code.

[0039] It can be seen that the signal distortion suppression method of the embodiment can realize automatic sequential addressing of the devices through the feature code configuration process, simplifying system installation and maintenance. Through the hardware circuit, the influence of signal distortion on the entire transmission display system in the serial cascade system can be suppressed without complex algorithms, greatly improving the reliability of the transmission display system. It should be noted that the specific limitations of the display device, the display system and the signal distortion suppression method can also be referred to the description of the signal distortion suppression circuit embodiment in the foregoing, and will not be repeated here.

[0040] In summary, the application can realize automatic sequential addressing of cascaded display devices by the hardware circuit for multiplexing signal polarity inversion and feature code burning, combined with the feature code configuration process, simplifies system installation and maintenance, and can realize polarity alternation of signals on the cascaded link, so that the edges processed by adjacent devices are opposite (the rising edge of the previous display device becomes the falling edge of the next display device), thereby transferring the large delay of the previous device on a certain edge to the small delay of the next device on the opposite edge, converting the linear accumulation of distortion into oscillation compensation, to avoid the cascaded distortion accumulation effect, fundamentally solve the signal distortion problem, and do not affect the system performance, greatly improve the cascaded depth and signal transmission distance, and, in the device, whether to take the signal after the inversion and then extract the data can be determined according to the parity of the feature code, so that the signal polarity is consistent with the original transmitted signal during internal processing, ensuring that the data can be correctly extracted, that is, by combining the strategy of polarity inversion output and internal parity selective inversion, the problem of accumulation of signal asymmetric distortion in the cascaded link is effectively solved without increasing additional signal lines and significantly increasing the cost.

[0041] The above is only a specific embodiment of the application, but the protection scope of the application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the application, and these modifications or replacements should be covered within the protection scope of the application.

Claims

1. A signal distortion suppression circuit applied to a display device, characterized by, The signal distortion suppression circuit comprises a signal input port, a data extraction unit, a feature code control module, a polarity inversion output module and a signal output port. The feature code control module is configured to solidify a unique feature code of a display device. The polarity inversion output module is connected between the signal input port and the signal output port, and is configured to output a signal from the signal input port after polarity inversion from the signal output port. The data extraction unit is connected to the feature code control module and the display device, and is further connected to the signal input port, and is configured to selectively perform polarity inversion processing on the signal from the signal input port according to the parity of the feature code in the feature code control module, and extract valid data corresponding to the feature code.

2. The signal distortion suppression circuit of claim 1, wherein, The data extraction unit comprises: The inversion selection circuit is connected to the signal input port at the input end and connected to the feature code control module at the control end, and is configured to output the signal from the signal input port inversely when the feature code is odd, and output the signal from the signal input port directly when the feature code is even. The decoding module is connected to the output end of the inversion selection circuit, and is configured to extract valid data corresponding to the feature code from the signal output by the inversion selection circuit.

3. The signal distortion suppression circuit of claim 2, wherein, The inversion selection circuit comprises a first multiplexer and a first inverter, wherein the first input end of the first multiplexer is connected to the signal input port, the second input end of the first multiplexer is connected to the signal input port through the first inverter, and the selection control end of the first multiplexer is connected to the feature code control module, so as to select the signal from the first input end or the second input end to be transmitted to the decoding module according to the parity information of the feature code from the feature code control module.

4. The signal distortion suppression circuit according to any one of claims 1 to 3, wherein The feature code control module comprises: The feature code storage unit is configured to store the unique feature code of the display device. The configuration management unit is connected between the signal input port and the feature code storage unit, and is configured to write the feature code into the feature code storage unit according to the input signal containing the feature code configuration information in the feature code configuration mode; and the configuration management unit is further connected to the data extraction unit and the signal output port, and is configured to send a selection control signal representing the parity information of the feature code to the data extraction unit, and generate a feature code configuration signal containing updated feature code information based on the feature code stored in the feature code storage unit, and output the feature code configuration signal through the signal output port.

5. The signal distortion suppression circuit of claim 4, wherein, The output end of the data extraction unit is further connected to the feature code control module, and the data extraction unit is further configured to perform frame type identification on the signal input from the signal input port, route the feature code configuration frame to the feature code control module for feature code solidification when the feature code configuration frame is identified, and extract valid display data corresponding to the feature code and route the valid display data to the display module of the display device for display when the display data frame is identified.

6. The signal distortion suppression circuit of claim 5, wherein, The polarity inversion output module comprises a second inverter and a second multiplexer, wherein An input terminal of the second inverter is connected to the signal input port for receiving a display signal; First and second input terminals of the second multiplexer are connected to the second inverter and an output terminal of the configuration management unit respectively for receiving the inverted display signal and the feature code configuration signal containing the updated feature code information, and an output terminal of the second multiplexer is connected to the signal output port; The data extraction unit is further configured to output a routing control signal to a selection control terminal of the second multiplexer according to the result of the frame type identification; The second multiplexer is configured to select to transmit the feature code configuration signal to the signal output port in response to the routing control signal indicating the feature code configuration mode, and select to transmit the inverted display signal to the signal output port in response to the routing control signal indicating the display mode.

7. A display device, characterized by The signal distortion suppression circuit according to any one of claims 1-6, wherein an input terminal of a Schmitt trigger receives an external signal, a signal input port of the signal distortion suppression circuit is connected to an output terminal of the Schmitt trigger, and an output terminal of the data extraction module is connected to a display module for driving display.

8. A display system characterized by, The display device according to claim 7, wherein a plurality of display devices are serially connected in sequence, and an output terminal of a controller is connected to a signal input port of a first display device.

9. A signal distortion suppression method applied to the display system of claim 8, characterized in that, The signal distortion suppression method comprises: sending a feature code configuration signal to each display device connected in sequence through a transmission link of the display system; According to the sequence of connection, each display device solidifies its own feature code in sequence through its own feature code control module according to the received feature code configuration signal; Each display device performs polarity inversion on the input signal received by the polarity inversion output module and outputs the inverted signal to the next display device connected in sequence; Each display device selectively performs inversion on the input signal through the data extraction unit according to the parity of the feature code, and parses the valid data corresponding to its own feature code from the inverted or non-inverted signal and outputs the valid data to the display module for display.

10. The signal distortion suppression method of claim 9, wherein, The selective inversion of the input signal according to the parity of the feature code, and the parsing of the valid data corresponding to its own feature code from the inverted or non-inverted signal, specifically comprises: If the feature code is odd, the input signal is inverted in polarity, and the inverted input signal is parsed to obtain the valid data corresponding to its own feature code; If the feature code is even, the input signal is directly parsed to obtain the valid data corresponding to its own feature code.

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