Array substrate and display device

Abstract

The array substrate comprises a first corresponding data line which is configured to provide a data signal to a first electrode of a data writing transistor in a first row of pixel driving circuits in the same column and two adjacent rows of pixel driving circuits; and the second corresponding data line is configured to provide the data signal to the first electrode of the data writing transistor in the second row of the pixel driving circuits in the same column and two adjacent rows. The first and second respective data lines extend at least partially in the same column. The first respective data lines are electrically isolated from the first electrodes of the data write transistors located in the same column and the second row. The second respective data lines are electrically isolated from the first electrodes of the data write transistors located in the same column and the first row. In the row direction, the first electrodes of the first transistors in the adjacent first sub-pixels and second sub-pixels are of an integrated structure, the first electrodes are electrically connected with the third reset signal lines, and the second electrodes are electrically connected with the grid electrodes of the driving transistors.

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular to an array substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) displays are one of the hotspots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal displays (TFT-LCD) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes a plurality of pixel units configured with pixel driving circuits arranged in multiple rows and multiple columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When the pixel unit is turned on by the selected row, a switch transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line to the driving transistor via the switch transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of a corresponding brightness. SUMMARY

[0003] In one aspect, the present disclosure provides an array substrate, comprising a plurality of data lines, a plurality of third reset signal lines and a plurality of sub-pixels; the sub-pixels comprise pixel driving circuits; wherein the plurality of data lines comprises a first corresponding data line and a second corresponding data line, the first corresponding data line is configured to provide a data signal to a first electrode of a data write transistor located in a first row of the same column pixel driving circuit and two adjacent rows of pixel driving circuits; and the second corresponding data line is configured to provide a data signal to a first electrode of a data write transistor located in a second row of the same column pixel driving circuit and the two adjacent rows of pixel driving circuits; the first corresponding data line and the second corresponding data line extend at least partially in the same column; the first corresponding data line is electrically isolated from the first electrode of the data write transistor located in the second row of the same column pixel driving circuit and the two adjacent rows of pixel driving circuits; and the second corresponding data line is electrically isolated from the first electrode of the data write transistor located in the first row of the same column pixel driving circuit and the two adjacent rows of pixel driving circuits; the plurality of sub-pixels comprises a first sub-pixel and a second sub-pixel; in the row direction, the first electrode of a first transistor in the adjacent first sub-pixel and the second sub-pixel is a unitary structure; the first electrode of the first transistor is electrically connected to the third reset signal line, and the second electrode of the first transistor is electrically connected to the gate of a driving transistor.

[0004] Optionally, a projection of the same pixel driving circuit on the substrate substrate partially overlaps with a projection of the first corresponding data line on the substrate substrate, and partially overlaps with a projection of the second corresponding data line on the substrate substrate.

[0005] Optionally, a projection of the first corresponding data line on the substrate substrate partially overlaps with a first electrode of the driving transistor on the substrate substrate; and a projection of the second corresponding data line on the substrate substrate partially overlaps with a second electrode of the driving transistor on the substrate substrate.

[0006] Optionally, the array substrate further comprises a plurality of first data signal connection pads and a plurality of second data signal connection pads in the same column of pixel driving circuits; each first data signal connection pad in the plurality of first data signal connection pads connects the first corresponding data line with a first electrode of a data write transistor in a first corresponding pixel driving circuit in the first row of the adjacent two rows of pixel driving circuits; each second data signal connection pad in the plurality of second data signal connection pads connects the second corresponding data line with a first electrode of a data write transistor in a second corresponding pixel driving circuit in the second row of the adjacent two rows of pixel driving circuits.

[0007] Optionally, the array substrate further comprises a plurality of fourth reset signal lines; the sub-pixel further comprises a light emitting element;

[0008] In the row direction, a first electrode of a sixth transistor in the adjacent first sub-pixel and the second sub-pixel is an integral structure; the first electrode of the sixth transistor is electrically connected with the fourth reset signal line, and a second electrode of the sixth transistor is electrically connected with an anode of the light emitting element.

[0009] Optionally, the array substrate further comprises a node connection line, the node connection line connects the second electrode of the first transistor and a gate of the driving transistor;

[0010] A projection of the third reset signal line on the substrate substrate is located between a projection of the node connection line and a projection of the first corresponding data line on the substrate substrate, or a projection of the third reset signal line on the substrate substrate is located between a projection of the node connection line and a projection of the second corresponding data line on the substrate substrate.

[0011] Optionally, in the same column of adjacent two rows of the sub-pixels, a projection of the third reset signal line on the substrate substrate is between a projection of the first corresponding data line in the first row and a projection of the node connection line on the substrate substrate, and is not between a projection of the first corresponding data line in the second row and a projection of the node connection line on the substrate substrate.

[0012] Optionally, the array substrate further comprises a node connection line and a plurality of fourth reset signal lines.

[0013] The node connection line connects the second electrode of the first transistor and the gate of the driving transistor.

[0014] A projection of the fourth reset signal line on the substrate substrate is between the projection of the node connection line and the first corresponding data line on the substrate substrate, or the projection of the fourth reset signal line on the substrate substrate is between the projection of the node connection line and the second corresponding data line on the substrate substrate.

[0015] Optionally, in the same column and adjacent two rows of the sub-pixels, the projection of the fourth reset signal line on the substrate substrate is between the projection of the first corresponding data line of the first row and the node connection line on the substrate substrate, and is not between the projection of the first corresponding data line of the second row and the node connection line on the substrate substrate.

[0016] Optionally, the array substrate comprises a substrate substrate, and a semiconductor material layer, a gate insulating layer, a first conductive layer, an insulating layer, a second conductive layer, an interlayer dielectric layer and a first signal line layer arranged in sequence away from the substrate substrate.

[0017] The node connection line and the third reset signal line are located in the first signal line layer; and / or,

[0018] The node connection line and the fourth reset signal line are located in the first signal line layer.

[0019] Optionally, the array substrate comprises a substrate substrate, and a semiconductor material layer, a gate insulating layer, a first conductive layer, an insulating layer, a second conductive layer, an interlayer dielectric layer, a first signal line layer, a first planarization layer and a second signal line layer arranged in sequence away from the substrate substrate.

[0020] The first corresponding data line and the second corresponding data line are located in the second signal line layer.

[0021] Optionally, the array substrate further comprises a plurality of first voltage supply lines and / or a plurality of second voltage supply lines; the extension direction of the first voltage supply line and / or the second voltage supply line is the same as the extension direction of the first corresponding data line and the second corresponding data line.

[0022] Optionally, the projection of the first voltage supply line and / or the second voltage supply line on the substrate substrate is between the projections of at least two data lines on the substrate substrate.

[0023] Optionally, the array substrate further includes a first reset signal network and a second reset signal network; wherein, the first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; the second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; each of the plurality of first reset signal lines is connected to one or more of the plurality of third reset signal lines; each of the plurality of third reset signal lines is connected to one or more of the plurality of first reset signal lines; each of the plurality of second reset signal lines is connected to one or more of the plurality of fourth reset signal lines; and each of the plurality of fourth reset signal lines is connected to one or more of the plurality of second reset signal lines.

[0024] Optionally, the array substrate further includes pixel driving circuits arranged in K columns and M rows, where K and M are positive integers; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer and 1 ≤ k ≤ (K / 4); the M rows include the (2m-1)th row and the 2mth row, where m is a positive integer and 1 ≤ m ≤ (M / 2); the plurality of third reset signal lines are not present in the (4k-2)th column and the (4k)th column; the plurality of fourth reset signal lines are not present in the (4k-3)th column and the (4k-1)th column; the plurality of first reset signal lines are not present in the (2m)th row; and the plurality of second reset signal lines are not present in the (2m-1)th row.

[0025] Optionally, each of the plurality of first reset signal lines located in the (2m-1)th row is connected to one or more of the plurality of third reset signal lines located in the (4k-3)th or (4k-1)th column; each of the plurality of third reset signal lines located in the (4k-3)th or (4k-1)th column is connected to one or more of the plurality of first reset signal lines located in the (2m-1)th row; each of the plurality of second reset signal lines located in the (2m)th row is connected to one or more of the plurality of fourth reset signal lines located in the (4k-2)th or (4k)th column; and each of the plurality of fourth reset signal lines located in the (4k-2)th or (4k)th column is connected to one or more of the plurality of second reset signal lines located in the (2m)th row.

[0026] In another aspect, this disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0027] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0028] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0029] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0030] FIG. 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] FIG. 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0032] FIG. 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0033] FIG. 3B It is shown FIG. 3A A schematic diagram of the arrangement of multiple pixel driving circuits in a portion of the array substrate shown.

[0034] FIG. 3C It is shown FIG. 3AA schematic diagram of the structure of the semiconductor material layer in a portion of the array substrate shown.

[0035] FIG. 3D It is shown FIG. 3A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate shown.

[0036] FIG. 3E It is shown FIG. 3A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate shown.

[0037] FIG. 3F It is shown FIG. 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate shown.

[0038] FIG. 3G It is shown FIG. 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate shown.

[0039] FIG. 3H It is shown FIG. 3A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate shown.

[0040] FIG. 3I It is shown FIG. 3A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate shown.

[0041] FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram.

[0042] FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram.

[0043] FIG. 4C It is along FIG. 3A A cross-sectional view of line C-C' in the diagram.

[0044] FIG. 4D It is along FIG. 3A A cross-sectional view of the D-D' line in the diagram.

[0045] FIG. 5 It is shown FIG. 3A The diagram shows the connection between certain reset signal lines and their corresponding transistors in the array substrate.

[0046] FIG. 6 It is shown FIG. 3A A schematic diagram of the structure of the semiconductor material layer in a portion of the array substrate shown.

[0047] FIG. 7 It is shownFIG. 3A The diagram shows the connection between the data lines and the corresponding transistors in the array substrate.

[0048] FIG. 8 This is a schematic diagram illustrating the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0049] FIG. 9 This is a schematic diagram illustrating the layout of signal lines in a semiconductor material layer and a second conductive layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0050] FIG. 10 This is a schematic diagram illustrating the structure of an anti-interference block according to some embodiments of the present disclosure. Detailed Implementation

[0051] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0052] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of data lines and a plurality of sub-pixels; each sub-pixel includes pixel driving circuitry. Optionally, the plurality of data lines include a first corresponding data line and a second corresponding data line, the first corresponding data line being configured to provide a data signal to a first electrode of a data writing transistor located in a first row of pixel driving circuitry in the same column and adjacent rows of pixel driving circuitry; and the second corresponding data line being configured to provide a data signal to a first electrode of a data writing transistor located in a second row of pixel driving circuitry in the same column and adjacent rows of pixel driving circuitry. Optionally, the first corresponding data line and the second corresponding data line extend at least partially in the same column. Optionally, the first corresponding data line is electrically isolated from the first electrode of the data writing transistor located in the second row of pixel driving circuitry in the same column and adjacent rows of pixel driving circuitry. Optionally, the second corresponding data line is electrically isolated from the first electrode of the data writing transistor located in the first row of pixel driving circuitry in the same column and adjacent rows of pixel driving circuitry.

[0053] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0054] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, and multiple second voltage supply lines Vdd (e.g., multiple first voltage supply lines and / or multiple second voltage supply lines). The light emission of each subpixel Sp is driven by the corresponding pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding voltage supply line among the multiple voltage supply lines Vdd; a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low-voltage supply line. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0055] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN of the current stage, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, The transistor T4 has a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding light-emitting control signal line, a first electrode connected to the second electrode of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to the reset control signal line rst(N+1) of the next stage, a first electrode connected to the second reset signal line among a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding first voltage supply line and the first electrode of the fourth transistor T4.

[0056] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light-emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0057] FIG. 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is... FIG. 3D This is represented as "G1", where the first transistor T1 is a "dual-gate" transistor. The gate of the third transistor T3 is... FIG. 3D The transistor is designated as "G3", where the third transistor, T3, is a "dual-gate" transistor.

[0058] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0059] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0060] FIG. 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) FIGS. 2A-2CDuring one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first transistor T1 via the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. In the initial sub-stage t0, the corresponding gate lines in the plurality of gate lines GL are provided with cutoff signals, therefore the second transistor T2 and the third transistor T3 are turned off.

[0061] In reset phase t1, a turn-on reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, turning on the first transistor T1; allowing the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and further to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding second voltage supply line in the plurality of second voltage supply lines Vdd2. Due to the increase in the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, the corresponding gate line in the plurality of gate lines GL is provided with a cutoff signal, thus turning off the second transistor T2 and the third transistor T3. The corresponding light-emitting control signal line in the plurality of light-emitting control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0062] During the data write sub-stage t2, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the corresponding reset control signal line in the multiple reset control signal lines rst, thus turning off the first transistor T1. The corresponding gate line GL in the multiple gate lines GL is provided with a conduction signal, therefore the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The second transistor T2 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line in the multiple data lines DL is received by the first electrode of the second transistor T2 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level at node N1 gradually rises to (Vdata + Vth) during the data write sub-stage t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal lines in the plurality of light-emitting control signal lines em are provided with high-voltage signals to cut off the fourth transistor T4 and the fifth transistor T5.

[0063] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 via the corresponding reset control signal line in the next adjacent stage among multiple reset control signal lines rst, to turn on the sixth transistor T6; this allows the initialization voltage signal from the corresponding second reset signal line in multiple second reset signal lines Vint2 to be transmitted from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and sequentially to node N4. The anode of the light-emitting element LE is initialized.

[0064] In the light-emitting phase t3, a cutoff reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, to turn off the first transistor T1. A cutoff signal is provided to the corresponding gate line GL in the plurality of gate lines GL, turning off the second transistor T2 and the third transistor T3. A low voltage signal is provided to the corresponding light-emitting control signal line em in the plurality of light-emitting control signal lines to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting phase t3, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, the fifth transistor T5, and the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0065] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0066] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0067] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0068] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0069] FIG. 3A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. FIG. 3B It is shown FIG. 3A The diagram shows the arrangement of multiple pixel driving circuits in the array substrate. FIG. 3A and FIG. 3B A portion of an array substrate with eight pixel driving circuits (including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7 and PDC8) is shown.

[0070] FIG. 3C It is shown FIG. 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. FIG. 3D It is shown FIG. 3A A schematic diagram of the structure of the first conductive layer in the array substrate shown. FIG. 3E It is shown FIG. 3A A schematic diagram of the structure of the second conductive layer in the array substrate shown. FIG. 3F It is shown FIG. 3A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate. FIG. 3G It is shown FIG. 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. FIG. 3H It is shown FIG. 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown. FIG. 3I It is shown FIG. 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown. FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram. FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram. FIG. 4C It is along FIG. 3A A cross-sectional view of line C-C' in the diagram. FIG. 4D It is along FIG. 3A A cross-sectional view of the D-D' line in the diagram.

[0071] refer to FIGS. 3A-3I and FIGS. 4A-4D In some embodiments, the display panel includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer CT1 on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN on the side of the first conductive layer CT1 away from the gate insulating layer GI, a second conductive layer CT2 on the side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD on the side of the second conductive layer CT2 away from the insulating layer IN, a first signal line layer SL1 on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2, a first planarization layer PLN1 on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD, a second signal line layer SL2 on the side of the first planarization layer PLN1 away from the first signal line layer SL1, and a second planarization layer PLN2 on the side of the second signal line layer SL2 away from the first planarization layer PLN1.

[0072] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3CEach pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number, which indicates the component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes active layer ACT1, first electrode S1, and second electrode D1. Second transistor T2 includes active layer ACT2, first electrode S2, and second electrode D2. Third transistor T3 includes active layer ACT3, first electrode S3, and second electrode D3. Fourth transistor T4 includes active layer ACT4, first electrode S4, and second electrode D4. Fifth transistor T5 includes active layer ACT5, first electrode S5, and second electrode D5. Sixth transistor T6 includes active layer ACT6, first electrode S6, and second electrode D6. Driving transistor Td includes active layer ACTd, first electrode Sd, and second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0073] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. A first electrode refers to a portion of the transistor connected to one side of the active layer, and a second electrode refers to a portion of the transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a portion of the transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the context of a dual-gate transistor, a first electrode refers to a portion of the transistor connected to the side of the first portion away from the third portion, and a second electrode refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0074] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3D In some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst (including the current stage reset control signal line rstN and the next stage reset control signal line rst(N+1)), a plurality of light emission control signal lines em, a plurality of gate lines GL, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of reset control signal lines rst, the plurality of light emission control signal lines em, the plurality of gate lines GL, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0075] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple gate lines GL and a first capacitor electrode Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple gate lines GL and a first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0076] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3E In some embodiments, the second conductive layer includes an anti-interference block IPB, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the anti-interference block IPB, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0077] FIG. 3F The image shows a via extending through the interlayer dielectric layer (ILD).

[0078] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3G In some embodiments, the first signal line layer includes node connection lines Cln, multiple second voltage supply lines Vdd2, an anode connection pad ACP, and a data signal connection pad DCP. In some embodiments, the first signal line layer further includes multiple third reset signal lines Vint3 and multiple fourth reset signal lines Vint4.

[0079] Node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1. Data signal connection pad DCP is configured to connect a corresponding data line among multiple data lines to the first electrode of the second transistor T2. Anode contact pad ACP connects the fourth node N4 in each sub-pixel to the corresponding anode. Anode contact pad ACP is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in each sub-pixel is connected to anode contact pad ACP.

[0080] Multiple second voltage supply lines Vdd2 are connected to multiple first voltage supply lines in the second signal line layer and to the second capacitor electrode Ce2 of the storage capacitor in the second conductive layer. The second capacitor electrodes in the same row are interconnected as part of an integral structure. Multiple integral structures of the second capacitor electrodes in multiple rows, the multiple second voltage supply lines Vdd2, and the multiple first voltage supply lines form an interconnected voltage signal network. A corresponding second voltage supply line among the multiple second voltage supply lines Vdd2 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the multiple second voltage supply lines Vdd2 extend in a direction substantially parallel to the second direction DR2; the multiple first voltage supply lines extend in a direction substantially parallel to the second direction DR2. Optionally, the integral structure including the interconnected second capacitor electrodes in the same row extends in a direction substantially parallel to the first direction DR1. As used herein, the term "substantially parallel" means an angle ranging from 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0081] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises multiple sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection line Cln, multiple second voltage supply lines Vdd2, data signal connection pad DCP, anode connection pad ACP, multiple third reset signal lines Vint3, and multiple fourth reset signal lines Vint4 are located in the same layer.

[0082] FIG. 3H The vias extending through the first planarization layer PLN1 are shown.

[0083] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3IIn some embodiments, the second signal line layer includes a plurality of first voltage supply lines Vdd1 and a plurality of data lines DL, namely, a first corresponding data line RDL1 and a second corresponding data line RDL2. As described above, the plurality of first voltage supply lines Vdd1 are connected to a plurality of second voltage supply lines in the first signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 via a data signal connection pad.

[0084] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple first voltage supply lines Vdd1 and multiple data lines DL are located in the same layer.

[0085] Reference FIG. 3A , FIG. 3B , FIG. 3E and FIG. 3G The array substrate includes two adjacent columns of pixel driving circuits, for example, a first column of pixel driving circuits including PDC1 and a second column of pixel driving circuits including PDC2. In some embodiments, the third reset signal lines of the plurality of third reset signal lines Vint3 are present in the first column of the two adjacent columns of pixel driving circuits, and the plurality of third reset signal lines Vint3 are not present in the second column of the two adjacent columns of pixel driving circuits. In some embodiments, the fourth reset signal lines of the plurality of fourth reset signal lines Vint4 are present in the second column of the two adjacent columns of pixel driving circuits, and the plurality of fourth reset signal lines Vint4 are not present in the first column of the two adjacent columns of pixel driving circuits.

[0086] In some embodiments, such as FIGS. 3A-3I As shown, each of the plurality of third reset signal lines Vint3 is configured to provide a reset signal to two adjacent pixel driving circuits in the same row of adjacent pixel driving circuits and in the first and second columns of adjacent pixel driving circuits. In some embodiments, each of the plurality of fourth reset signal lines Vint4 is configured to provide a reset signal to two adjacent pixel driving circuits in the same row of adjacent pixel driving circuits and in the first and second columns of adjacent pixel driving circuits.

[0087] Reference FIG. 2A , FIG. 2B , FIGS. 3A-3I as well as FIG. 4A In some embodiments, except for the hole region H where the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers and is larger than the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as at least one of a plurality of second voltage supply lines Vdd2, an anode connection pad ACP, a data signal connection pad DCP, a plurality of third reset signal lines Vint3, or a plurality of fourth reset signal lines Vint4.

[0088] Optionally, refer to FIG. 3A , FIG. 3G as well as FIG. 3I The extension direction of the first voltage supply line Vdd1 and / or the second voltage supply line Vdd2 is the same as the extension direction of the data line DL (the first corresponding data line RDL1 and the second corresponding data line RDL2).

[0089] Optionally, refer to FIG. 3A , FIG. 3G as well as FIG. 3I In the row direction, the orthographic projection of the first voltage supply line Vdd1 and / or the second voltage supply line Vdd2 on the substrate is located between the orthographic projections of at least two data lines DL on the substrate.

[0090] In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor and / or the second electrode D1 of the first transistor, such as... FIG. 4A As shown.

[0091] Reference FIG. 2A , FIG. 2B , FIGS. 3A-3I as well as FIG. 4BIn some embodiments, the array substrate further includes a third via v3 and a fourth via v4. The third via v3 extends through the interlayer dielectric layer ILD. The fourth via v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is connected to a first reset signal line among the plurality of first reset signal lines Vint1 through the third via v3. Optionally, a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is connected to the first electrode S1 of the first transistor T1 through the fourth via v4.

[0092] Reference FIG. 2A , FIG. 2B , FIGS. 3A-3I as well as FIG. 4C In some embodiments, the array substrate further includes a fifth via v5 and a sixth via v6. The fifth via v5 extends through the interlayer dielectric layer (ILD). The sixth via v6 extends through the interlayer dielectric layer (ILD), the insulating layer (IN), and the gate insulating layer (GI). Optionally, a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 is connected to a second reset signal line among the plurality of second reset signal lines Vint2 via the fifth via v5. Optionally, a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 is connected to the first electrode S6 of the sixth transistor T6 via the sixth via v6.

[0093] Reference FIG. 2A , FIG. 2B , FIGS. 3A-3I as well as FIG. 4D In some embodiments, the array substrate further includes a seventh via v7 and an eighth via v8. The seventh via v7 extends through the first planarization layer PLN1. The eighth via v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, data lines in the plurality of data lines DL are connected to the data signal connection pad DCP through the seventh via v7. Optionally, data lines in the plurality of data lines DL are connected to the first electrode S2 of the second transistor T2 through the eighth via v8.

[0094] FIG. 5 It is shown FIG. 3A A schematic diagram showing the connection between certain reset signal lines and corresponding transistors in the array substrate shown. (Refer to...) FIG. 3A , FIG. 3C , FIG. 5 and FIG. 6The connection point between the reset signal line and the corresponding transistor is indicated by a dashed circle. In the row direction, the first electrode of the first transistor T1 in adjacent first and second sub-pixels is a single structure; the first electrode of the first transistor T1 is electrically connected to the third reset signal line Vint3, and the second electrode of the first transistor T1 is electrically connected to the gate of the driving transistor Td. In the row direction, the first electrode of the sixth transistor T6 in adjacent first and second sub-pixels is a single structure; the first electrode of the sixth transistor T6 is electrically connected to the fourth reset signal line Vint4, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element LE.

[0095] In some embodiments, a first adjacent third reset signal line Vint3-1 among a plurality of third reset signal lines is configured to provide a reset signal to the first electrode of a first transistor in a first row of two adjacent pixel driving circuits and a first column of two adjacent column pixel driving circuits, respectively; a first adjacent fourth reset signal line Vint4-1 among a plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of a sixth transistor in a first row of two adjacent pixel driving circuits and a first column of two adjacent column pixel driving circuits, respectively. Optionally, the first adjacent third reset signal line Vint3-1 extends at least partially in the first column of two adjacent column pixel driving circuits (e.g., extends through the first column); and the first adjacent fourth reset signal line Vint4-1 extends at least partially in the second column of two adjacent column pixel driving circuits (e.g., extends through the second column).

[0096] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide reset signals to the first electrodes of the first transistors in the first row of the adjacent two-row pixel driving circuits and the third and fourth columns of the adjacent two-column pixel driving circuits, respectively; the second adjacent fourth reset signal line Vint4-2 among the plurality of fourth reset signal lines is configured to provide reset signals to the first electrodes of the sixth transistors in the first row of the adjacent two-row pixel driving circuits and the third and fourth columns of the adjacent two-column pixel driving circuits, respectively. Optionally, the second adjacent third reset signal line Vint3-2 extends at least partially in the third column of the adjacent two-column pixel driving circuits (e.g., extends through the third column); and the second adjacent fourth reset signal line Vint4-2 extends at least partially in the fourth column of the adjacent two-column pixel driving circuits (e.g., extends through the fourth column). Optionally, the first column, second column, third column, and fourth column are arranged sequentially. Optionally, adjacent columns are separated by a first voltage supply line in a plurality of first voltage supply lines Vdd1 or a second voltage supply line in a plurality of second voltage supply lines Vdd2.

[0097] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide reset signals to the first electrodes of the first transistors in the second row of the adjacent two-row pixel driving circuits and the second and third columns of the adjacent two-column pixel driving circuits, respectively; the first adjacent fourth reset signal line Vint4-1 among the plurality of fourth reset signal lines is configured to provide reset signals to the first electrodes of the sixth transistors in the second row of the adjacent two-row pixel driving circuits and the second and third columns of the adjacent two-column pixel driving circuits, respectively. Optionally, the first row and the second row are arranged sequentially.

[0098] In some embodiments, the array substrate includes pixel driving circuits arranged in K columns and M rows, where K and M are positive integers. The array substrate includes K reset signal lines configured to provide reset signals to reset transistors in the array substrate. In some embodiments, the K columns include the (4k-3)th column C(4k-3), the (4k-2)th column C(4k-2), the (4k-1)th column C(4k-1), and the 4kth column C(4k), where k is a positive integer, 1 ≤ k ≤ (K / 4). The M rows include the (2m-1)th row R(2m-1) and the 2mth row R(2m), where m is a positive integer, 1 ≤ m ≤ (M / 2). In some embodiments, the K reset signal lines include a plurality of third reset signal lines located in column (4k-3) C(4k-3) of the K columns or in column (4k-1) C(4k-1) of the K columns; and a plurality of fourth reset signal lines located in column (4k-2) C(4k-2) of the K columns or in column (4k) C(4k) of the K columns. Optionally, adjacent columns are separated by first voltage supply lines in a plurality of first voltage supply lines Vdd1.

[0099] In some embodiments, the K reset signal lines include a first adjacent third reset signal line Vint3-1 in the (4k-3)th column C(4k-3) of the K columns, a second adjacent third reset signal line Vint3-2 in the (4k-1)th column C(4k-1) of the K columns; a first adjacent fourth reset signal line Vint4-1 in the (4k-2)th column C(4k-2) of the K columns, and a second adjacent fourth reset signal line Vint4-2 in the (4k)th column C(4k) of the K columns. The first adjacent third reset signal line Vint3-1, the first adjacent fourth reset signal line Vint4-1, the second adjacent third reset signal line Vint3-2, and the second adjacent fourth reset signal line Vint4-2 are arranged sequentially.

[0100] As used herein, the terms "column (4k-3)," "column (4k-2)," "column (4k-1)," and "column (4k)" are used in the context of K columns. The array substrate may or may not include additional columns preceding the first column of the K columns and / or additional columns following the last column of the K columns. In the context of the array substrate, the terms "column (4k-3)" or "column (4k-1)" do not necessarily indicate an odd-numbered column, and the terms "column (4k-2)" or "column (4k)" do not necessarily indicate an even-numbered column. In one example, column (4k-3) is an odd-numbered column in the context of K columns, but may be an even-numbered column in the context of the array substrate. In another example, column (4k-3) is an odd-numbered column in both the context of K columns and the context of the array substrate. In one example, column (4k-2) is an even-numbered column in the context of K columns, but may be an odd-numbered column in the context of the array substrate. In another example, column (4k-2) is an even column in the context of the K columns and also an even column in the context of the array substrate. In one example, column (4k-1) is an odd column in the context of the K columns, but can be an even column in the context of the array substrate. In another example, column (4k-1) is an odd column in the context of the K columns and also an odd column in the context of the array substrate. In one example, column (4k) is an even column in the context of the K columns, but can be an odd column in the context of the array substrate. In another example, column (4k) is an even column in the context of the K columns and also an even column in the context of the array substrate.

[0101] As used herein, the terms "row (2m-1)" and "row (2m)" are used in the context of M rows. The array substrate may or may not include additional rows preceding the first row of the M rows and / or following the last row of the M rows. In the context of the array substrate, the term "row (2m-1)" does not necessarily refer to an odd-numbered row, and the term "row (2m)" does not necessarily refer to an even-numbered row. In one example, row (2m-1) is an odd-numbered row in the context of M rows, but may be an even-numbered row in the context of the array substrate. In another example, row (2m-1) is an odd-numbered row in both the context of M rows and the context of the array substrate. In one example, row (2m) is an even-numbered row in the context of M rows, but may be an odd-numbered row in the context of the array substrate. In another example, row (2m) is an even-numbered row in both the context of M rows and the context of the array substrate.

[0102] In some embodiments, the first adjacent third reset signal line Vint3-1 among the plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first transistor in two adjacent pixel driving circuits located in the pixel driving circuits in the (2m-1) row R (2m-1) and the (4k-3) column C (4k-3) and the (4k-2) column C (4k-2) respectively; the first adjacent fourth reset signal line Vint4-1 among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the sixth transistor in two adjacent pixel driving circuits located in the pixel driving circuits in the (2m-1) row R (2m-1) and the (4k-3) column C (4k-3) and the (4k-2) column C (4k-2) respectively. Optionally, the first adjacent third reset signal line Vint3-1 extends at least partially in the pixel driving circuit of the (4k-3)th column C(4k-3) (e.g., extending through the column); and the first adjacent fourth reset signal line Vint4-1 extends at least partially in the pixel driving circuit of the (4k-2)th column C(4k-2) (e.g., extending through the column). Optionally, adjacent columns are separated by a first voltage supply line in a plurality of first voltage supply lines Vdd1 or a second voltage supply line in a plurality of second voltage supply lines Vdd2.

[0103] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first transistor in two adjacent pixel driving circuits located in the pixel driving circuits in the (2m-1) row R (2m-1) and the (4k-1) column C (4k-1) and the (4k) column C (4k), respectively; the second adjacent fourth reset signal line Vint4-2 among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the sixth transistor in two adjacent pixel driving circuits located in the pixel driving circuits in the (2m-1) row R (2m-1) and the (4k-1) column C (4k-1) and the (4k) column C (4k), respectively. Optionally, the second adjacent third reset signal line Vint3-2 extends at least partially in the pixel driving circuit of column (4k-1) C(4k-1) (e.g., extending through the column); and the second adjacent fourth reset signal line Vint4-2 extends at least partially in the pixel driving circuit of column (4k) C(4k) (e.g., extending through the column). Optionally, column (4k-3) C(4k-3), column (4k-2) C(4k-2), column (4k-1) C(4k-1), and column (4k) C(4k) are arranged sequentially. Optionally, adjacent columns are separated by a first voltage supply line in a plurality of first voltage supply lines Vdd1 or a second voltage supply line in a plurality of second voltage supply lines Vdd2.

[0104] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide reset signals to the first electrodes of the first transistors in two adjacent pixel driving circuits located in the pixel driving circuits in the (2m) row R (2m) and the (4k-2) column C (4k-2) and the (4k-1) column C (4k-1) respectively; the first adjacent fourth reset signal line Vint4-1 among the plurality of fourth reset signal lines is configured to provide reset signals to the first electrodes of the sixth transistors in two adjacent pixel driving circuits located in the pixel driving circuits in the (2m) row R (2m) and the (4k-2) column C (4k-2) and the (4k-1) column C (4k-1) respectively. Optionally, the (2m-1) row R (2m-1) and the (2m) row R (2m) are arranged sequentially.

[0105] Reference FIG. 3A as well as FIG. 3C In some embodiments, the corresponding layers of pixel driving circuits located in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) of the same row or multiple rows, and the corresponding layers of pixel driving circuits located in the (4k-1)th column C(4k-1) and the (4k)th column C(4k), for example, have a substantially mirror symmetry with respect to a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2.

[0106] As used herein, the term “the corresponding layers of the pixel driving circuits in column (4k-3) C(4k-3) and column (4k-2) C(4k-2) and the corresponding layers of the pixel driving circuits in column (4k-1) C(4k-1) and column (4k) C(4k)” is not intended to include layers that are not part of the pixel driving circuits. For example, “the corresponding layers of the pixel driving circuits in column (4k-3) C(4k-3) and column (4k-2) C(4k-2) and the corresponding layers of the pixel driving circuits in column (4k-1) C(4k-1) and column (4k) C(4k)” does not include an anode layer or a pixel defining layer. In some embodiments, "the corresponding layers of the pixel driving circuits in columns (4k-3) and (4k-2) and (4k-1) and (4k ... In one specific example, the "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. In another specific example, the "corresponding layer" further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In yet another specific example, the "corresponding layer" includes a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, and a second signal line layer. In yet another specific embodiment, the "corresponding layer" further includes a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, and a second planarization layer.

[0107] See FIG. 5 , FIG. 6 and FIG. 7In some embodiments, multiple third voltage supply lines Vint3 are not present in columns (4k-2) C(4k-2) and (4k) C(4k); multiple fourth voltage supply lines Vint4 are not present in columns (4k-3) C(4k-3) and (4k-1) C(4k-1). Optionally, multiple third voltage supply lines Vint3 are present in columns (4k-3) C(4k-3) and (4k-1) C(4k-1); and multiple fourth voltage supply lines Vint4 are present in columns (4k-2) C(4k-2) and (4k) C(4k).

[0108] FIG. 3A It is shown FIG. 3A A schematic diagram of the structure of the semiconductor material layer in a portion of the array substrate shown. (Refer to...) FIG. 3G , FIG. 3I , FIG. 7 and FIG. 3A In some embodiments, the first electrodes of the first transistors in two adjacent pixel driving circuits located in row (2m-1) R(2m-1) and columns (4k-3) C(4k-3) and (4k-2) C(4k-2) are each part of a first overall structure. In some embodiments, the first electrode of the sixth transistor in two adjacent pixel driving circuits located in row (2m-1) R(2m-1) and columns (4k-3) C(4k-3) and (4k-2) C(4k-2) are each part of a first overall structure. Optionally, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of the transistors in two adjacent pixel driving circuits located in row (2m-1) R(2m-1) and columns (4k-3) C(4k-3) and (4k-2) C(4k-2) are each part of a first overall structure. The inventors of this disclosure have discovered that by setting a first integral structure including the first electrodes of the first transistors in two adjacent pixel driving circuits, only one via is needed to connect the reset signal line to the first electrodes of the first transistors in two adjacent pixel driving circuits. This unique structure helps save layout space and reduce crosstalk between adjacent sub-pixels.

[0109] In some embodiments, the first electrodes of the first transistors in two adjacent pixel driving circuits located in row (2m-1) R(2m-1) and column (4k-1) C(4k-1) and column (4k) C(4k) are each part of the second overall structure. In some embodiments, the first electrodes of the sixth transistors in two adjacent pixel driving circuits located in row (2m-1) R(2m-1) and column (4k-1) C(4k-1) and column (4k) C(4k) are each part of the second overall structure. Optionally, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of the transistors in two adjacent pixel driving circuits located in row (2m-1) R(2m-1) and column (4k-1) C(4k-1) and column (4k) C(4k) are each part of the second overall structure. The inventors of this disclosure have discovered that by setting a second integral structure including the first electrode of the sixth transistor in two adjacent pixel driving circuits, only one via is needed to connect the reset signal line to the first electrode of the sixth transistor in two adjacent pixel driving circuits. This unique structure helps save layout space and reduce crosstalk between adjacent sub-pixels.

[0110] In some embodiments, the first electrodes of the first transistors in two adjacent pixel driving circuits located in row (2m) R(2m) and columns (4k-2) C(4k-2) and (4k-1) C(4k-1) are each part of a third overall structure. In some embodiments, the first electrode of the sixth transistor in two adjacent pixel driving circuits located in row (2m) R(2m) and columns (4k-2) C(4k-2) and (4k-1) C(4k-1) are each part of a third overall structure. Optionally, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of the transistors in two adjacent pixel driving circuits located in row (2m) R(2m) and columns (4k-2) C(4k-2) and (4k-1) C(4k-1) are each part of a third overall structure.

[0111] Optionally, the first integral structure, the second integral structure, and the third integral structure are spaced apart from each other.

[0112] Reference FIG. 3G , FIG. 3I , FIG. 7 and FIG. 3A In some embodiments, the corresponding components of the first transistors in two adjacent pixel driving circuits in the same row and two adjacent columns, for example, have substantially mirror symmetry with respect to a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2.

[0113] Optionally, the corresponding components of the first transistors in two adjacent pixel driving circuits located in the same row and in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2), for example, with respect to a first plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2, have substantially mirror symmetry; the corresponding components of the first transistors in two adjacent pixel driving circuits located in the same row and in the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1), for example, with respect to a first plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2, have substantially mirror symmetry. A second plane, perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2, has substantially mirror symmetry; and corresponding components of the first transistors in two adjacent pixel driving circuits in the same row and in the (4k-1)th column C(4k-1) and the (4k)th column C(4k), for example, with respect to a third plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2, have substantially mirror symmetry.

[0114] In some embodiments, the corresponding components of the driving transistor, the second transistor, the third transistor, the fourth transistor, or the fifth transistor located in the same row and two adjacent columns have substantially translational symmetry along the row direction.

[0115] Optionally, the corresponding components of the driving transistor, second transistor, third transistor, fourth transistor, or fifth transistor located in the same row and in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) have substantially translational symmetry along the row direction; the corresponding components of the driving transistor, second transistor, third transistor, fourth transistor, or fifth transistor located in the same row and in the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) have substantially translational symmetry along the row direction; and the corresponding components of the driving transistor, second transistor, third transistor, fourth transistor, or fifth transistor located in the same row and in the (4k-1)th column C(4k-1) and the (4k)th column C(4k) have substantially translational symmetry along the row direction.

[0116] In some embodiments, the corresponding components of the sixth transistor in two adjacent pixel driving circuits in the same row and the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) have substantially mirror symmetry, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2.

[0117] Optionally, the corresponding components of the sixth transistor in two adjacent pixel driving circuits located in the same row and in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) do not have mirror symmetry; and the corresponding components of the sixth transistor in two adjacent pixel driving circuits located in the same row and in the (4k-1)th column C(4k-1) and the (4k)th column C(4k) do not have mirror symmetry.

[0118] FIG. 3C It is shown FIG. 3I This diagram illustrates the connections between data lines and corresponding transistors in the array substrate shown. (Refer to...) FIG. 7 , FIG. 3A , FIG. 3C and FIG. 3I Optionally, the orthographic projection of the third reset signal line Vint3 on the substrate is located between the orthographic projections of the node connection line Cln and the first corresponding data line RDL1 on the substrate, or the orthographic projection of the third reset signal line Vint3 on the substrate is located between the orthographic projections of the node connection line Cln and the second corresponding data line RDL2 on the substrate. For example, in two adjacent rows of sub-pixels in the same column, the orthographic projection of the third reset signal line Vint3 on the substrate is between the orthographic projections of the first corresponding data line and the node connection line Cln on the substrate in the first row, but not between the orthographic projections of the first corresponding data line and the node connection line Cln on the substrate in the second row.

[0119] Reference FIG. 7 , FIG. 8 , FIG. 8 and FIG. 8 Optionally, the orthographic projection of the fourth reset signal line Vint4 on the substrate is located between the orthographic projections of the node connection line Cln and the first corresponding data line RDL1 on the substrate, or the orthographic projection of the fourth reset signal line Vint4 on the substrate is located between the orthographic projections of the node connection line Cln and the second corresponding data line RDL2 on the substrate. For example, in two adjacent rows of sub-pixels in the same column, the orthographic projection of the fourth reset signal line Vint4 on the substrate is between the orthographic projections of the first corresponding data line and the node connection line Cln on the substrate in the first row, but not between the orthographic projections of the first corresponding data line and the node connection line Cln on the substrate in the second row.

[0120] Reference FIG. 9 , FIGS. 3A-3I , FIG. 9 and FIG. 10In some embodiments, the plurality of data lines DL include a first corresponding data line RDL1 configured to provide a data signal to a first electrode of a second transistor located in a first row of pixel driving circuits in the same column and adjacent rows; and a second corresponding data line RDL2 configured to provide a data signal to a first electrode of a second transistor located in a second row of pixel driving circuits in the same column and adjacent rows. The first corresponding data line RDL1 and the second corresponding data line RDL2 extend at least partially within the same column (e.g., extending through the column). The first corresponding data line RDL1 is electrically isolated from the first electrode of the second transistor located in the second row of pixel driving circuits in the same column and adjacent rows; and the second corresponding data line RDL2 is electrically isolated from the first electrode of the second transistor located in the first row of pixel driving circuits in the same column and adjacent rows.

[0121] Reference FIG. 10 , ​ , ​ and ​ In some embodiments, the plurality of data lines DL includes a first corresponding data line RDL1 configured to provide a data signal to a first electrode of a second transistor in a pixel driving circuit located in the same column and row (2m-1) R(2m-1); and a second corresponding data line RDL2 configured to provide a data signal to a first electrode of a second transistor in a pixel driving circuit located in the same column and row (2m) R(2m). The first corresponding data line RDL1 and the second corresponding data line RDL2 extend at least partially in the same column (e.g., extend through the column). The first corresponding data line RDL1 is electrically isolated from the first electrode of the second transistor in the pixel driving circuit located in the same column and row (2m) R(2m); and the second corresponding data line RDL2 is electrically isolated from the first electrode of the second transistor in the pixel driving circuit located in the same column and row (2m-1) R(2m-1).

[0122] In some embodiments, the first corresponding data line RDL1 and the second corresponding data line RDL2 are located between two adjacent first voltage supply lines in a plurality of first voltage supply lines Vdd1.

[0123] In some embodiments, the orthographic projection of the active layer of the driving transistors located in the same column onto the substrate separates the orthographic projection of the first corresponding data line RDL1 onto the substrate from the orthographic projection of the second corresponding data line RDL2 onto the substrate.

[0124] In some embodiments, the orthographic projection of the same pixel driving circuit on the substrate overlaps with the orthographic projection of the first corresponding data line RDL1 on the substrate, and also overlaps with the orthographic projection of the second corresponding data line RDL2 on the substrate.

[0125] In some embodiments, the orthographic projection of the semiconductor layer of the same pixel driving circuit on the substrate overlaps with the orthographic projection of the first corresponding data line RDL1 on the substrate, and also overlaps with the orthographic projection of the second corresponding data line RDL2 on the substrate.

[0126] In some embodiments, the orthographic projection of the first corresponding data line RDL1 on the substrate partially overlaps with the orthographic projection of the first electrode of the driving transistor on the substrate; the orthographic projection of the second corresponding data line RDL2 on the substrate partially overlaps with the orthographic projection of the second electrode of the driving transistor on the substrate.

[0127] In some embodiments, the array substrate includes a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column of pixel driving circuits. Each first data signal connection pad RDCP1 connects a first corresponding data line RDL1 to the first electrode of a second transistor in the first corresponding pixel driving circuit of the first row of two adjacent pixel driving circuits. Each second data signal connection pad RDCP2 connects a second corresponding data line RDL2 to the first electrode of a second transistor in the second corresponding pixel driving circuit of the second row of two adjacent pixel driving circuits. There are no plurality of first data signal connection pads in the first row of two adjacent pixel driving circuits. There are no plurality of second data signal connection pads in the second row of two adjacent pixel driving circuits.

[0128] In some embodiments, the array substrate includes a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column of pixel driving circuits. Each first data signal connection pad RDCP1 connects a first corresponding data line RDL1 to the first electrode of a second transistor in the first corresponding pixel driving circuit in the (2m-1)th row R(2m-1). Each second data signal connection pad RDCP2 connects a second corresponding data line RDL2 to the first electrode of a second transistor in the second corresponding pixel driving circuit in the (2m)th row R(2m). There are no plurality of first data signal connection pads in the (2m)th row R(2m). There are no plurality of second data signal connection pads in the (2m-1)th row R(2m-1).

[0129] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of columns of the pixel driving circuit is in the range of 1.6:1 to 2.4:1, for example, 1.6:1 to 1.7:1, 1.7:1 to 1.8:1, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, 2.1:1 to 2.2:1, 2.2:1 to 2.3:1, or 2.3:1 to 2.4:1. In one embodiment, the ratio of the total number of data lines in the array substrate to the total number of columns of the pixel driving circuit is 2:1.

[0130] In some embodiments, the ratio of the total number of data signal connection pads to the total number of pixel driving circuits in the array substrate is in the range of 0.8:1 to 1.2:1, for example, 0.8:1 to 0.9:1, 0.9:1 to 1.0:1, 1.0:1 to 1.1:1, or 1.1:1 to 1.2:1. In one example, the ratio of the total number of data signal connection pads to the total number of pixel driving circuits in the array substrate is 1:1.

[0131] ​ This is a schematic diagram illustrating the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure. (Refer to...) ​ In some embodiments, the first reset signal network includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3 interconnected with each other. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to a second direction DR2. Optionally, each of the first reset signal lines Vint1 is connected to one or more of the third reset signal lines Vint3. Optionally, each of the third reset signal lines Vint3 is connected to one or more of the first reset signal lines Vint1.

[0132] In one example, multiple first reset signal lines Vint1 are located on the second conductive layer. Optionally, multiple third reset signal lines Vint3 are located on the first signal line layer.

[0133] Reference ​ In some embodiments, the second reset signal network includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4 interconnected with each other. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. Optionally, each second reset signal line in the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines Vint4. Optionally, each fourth reset signal line in the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0134] In one example, multiple second reset signal lines Vint2 are located on the first signal line layer. Optionally, multiple fourth reset signal lines Vint4 are located on the first signal line layer.

[0135] In some embodiments, there are no multiple third reset signal lines Vint3 in columns (4k-2) and (4k) of C(4k); and there are no multiple fourth reset signal lines Vint4 in columns (4k-3) and (4k-1) of C(4k-1). In some embodiments, there are no multiple first reset signal lines Vint1 in row (2m) of R(2m); and there are no multiple second reset signal lines Vint2 in row (2m-1) of R(2m-1).

[0136] In some embodiments, each of the plurality of first reset signal lines Vint1 located in row (2m-1) R(2m-1) is connected to one or more of the plurality of third reset signal lines Vint3 located in column (4k-3) C(4k-3) or column (4k-1) C(4k-1). Optionally, each of the plurality of third reset signal lines Vint3 located in column (4k-3) C(4k-3) or column (4k-1) C(4k-1) is connected to one or more of the plurality of first reset signal lines Vint1 located in row (2m-1) R(2m-1).

[0137] In some embodiments, each of the plurality of second reset signal lines Vint2 located in row (2m) R (2m) is connected to one or more of the plurality of fourth reset signal lines Vint4 located in column (4k-2) C (4k-2) or column (4k) C (4k). Optionally, each of the plurality of fourth reset signal lines Vint4 located in column (4k-2) C (4k-2) or column (4k) C (4k) is connected to one or more of the plurality of second reset signal lines Vint2 located in row (2m) R (2m).

[0138] The inventors of this disclosure have discovered that high-resolution display and high display quality can be achieved by setting up a first reset signal network and a second reset signal network according to this disclosure.

[0139] ​ This is a schematic diagram illustrating the layout of signal lines in a semiconductor material layer and a second conductive layer in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) ​ as well as ​In some embodiments, the array substrate further includes an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB and the second capacitor electrode Ce2 are located in the same layer. Optionally, the anti-interference block IPB is connected to a corresponding second voltage supply line among a plurality of second voltage supply lines Vdd2. Optionally, the anti-interference block IPB is configured to receive a first reference voltage signal. Optionally, the first reference voltage signal is a constant voltage signal, for example, a high reference voltage signal.

[0140] In some embodiments, the orthographic projection of the anti-interference block IPB onto the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer between the two active layer portions (e.g., the two channel portions) of the third transistor T3 onto the substrate. The inventors of this disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0141] ​ This is a schematic diagram illustrating the structure of an anti-interference block according to some embodiments of the present disclosure. (Reference) ​ In some embodiments, the anti-interference block IPB includes a first portion P1 and a second portion P2. In some embodiments, the orthographic projection of the first portion P1 onto the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer between two active layer portions (e.g., two channel portions) of the third transistor T3 in the first adjacent pixel driving circuit onto the substrate. In some embodiments, the orthographic projection of the second portion P2 onto the substrate at least partially overlaps with the orthographic projection of the second electrode D1 of the first transistor and / or the second electrode D3 of the third transistor in the second adjacent pixel driving circuit onto the substrate. Optionally, the first adjacent pixel driving circuit and the second adjacent pixel driving circuit are located in the same row and are adjacent to each other.

[0142] In some embodiments, the anti-interference block IPB further includes a third portion P3 connecting the first portion P1 and the second portion P2. In some embodiments, the orthographic projection of the third portion P3 on the substrate at least partially overlaps with the orthographic projection of the first electrode S2 of the second transistor in the second adjacent pixel driving circuit on the substrate.

[0143] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0144] In another aspect, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of data lines. Optionally, forming the plurality of data lines includes forming a first corresponding data line and forming a second corresponding data line, the first corresponding data line being configured to provide a data signal to a first electrode of a data write transistor located in a first row of pixel driving circuits in the same column and adjacent two rows of pixel driving circuits; and the second corresponding data line being configured to provide a data signal to a first electrode of a data write transistor located in a second row of pixel driving circuits in the same column and adjacent two rows of pixel driving circuits. Optionally, the first corresponding data line and the second corresponding data line extend at least partially in the same column. Optionally, the first corresponding data line is electrically isolated from the first electrode of the data write transistor located in the second row of pixel driving circuits in the same column and adjacent two rows of pixel driving circuits. Optionally, the second corresponding data line is electrically isolated from the first electrode of the data write transistor located in the first row of pixel driving circuits in the same column and adjacent two rows of pixel driving circuits.

[0145] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising a plurality of data lines, a plurality of third reset signal lines, and a plurality of sub-pixels; the sub-pixel comprises a pixel driving circuit; wherein the plurality of data lines comprises a first corresponding data line and a second corresponding data line, the first corresponding data line is configured to provide a data signal to a first electrode of a data write transistor located in a same column pixel driving circuit and a first row of two adjacent rows of pixel driving circuits; and the second corresponding data line is configured to provide a data signal to a first electrode of a data write transistor located in the same column pixel driving circuit and a second row of the two adjacent rows of pixel driving circuits; the first corresponding data line and the second corresponding data line extend at least partially in the same column; the first corresponding data line is electrically isolated from the first electrode of the data write transistor located in the same column pixel driving circuit and the second row of the two adjacent rows of pixel driving circuits; and the second corresponding data line is electrically isolated from the first electrode of the data write transistor located in the same column pixel driving circuit and the first row of the two adjacent rows of pixel driving circuits; the plurality of sub-pixels comprises a first sub-pixel and a second sub-pixel; in a row direction, a first electrode of a first transistor in the adjacent first sub-pixel and the second sub-pixel is a unitary structure; the first electrode of the first transistor is electrically connected with the third reset signal line, and a second electrode of the first transistor is electrically connected with a gate electrode of a driving transistor.

2. The array substrate according to claim 1, wherein, A normal projection of a same pixel driving circuit on a substrate and a normal projection of the first corresponding data line on the substrate partially overlap, and a normal projection of the second corresponding data line on the substrate partially overlaps.

3. The array substrate according to claim 1, wherein, A normal projection of the first corresponding data line on a substrate and a first electrode of a driving transistor on the substrate partially overlap; and a normal projection of the second corresponding data line on the substrate and a second electrode of the driving transistor on the substrate partially overlap. 4.The array substrate according to any one of claims 1 to 3, further comprising a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column pixel driving circuit; each first data signal connection pad in the plurality of first data signal connection pads connects the first corresponding data line with a first electrode of a data write transistor in a first corresponding pixel driving circuit in the first row of the two adjacent rows of pixel driving circuits; each second data signal connection pad in the plurality of second data signal connection pads connects the second corresponding data line with a first electrode of a data write transistor in a second corresponding pixel driving circuit in the second row of the two adjacent rows of pixel driving circuits.

5. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further comprises a plurality of fourth reset signal lines; the sub-pixel further comprises a light emitting element; In the row direction, a first electrode of a sixth transistor in the adjacent first and second sub-pixels is an integral structure; the first electrode of the sixth transistor is electrically connected with the fourth reset signal line, and a second electrode of the sixth transistor is electrically connected with an anode of the light emitting element.

6. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further comprises a node connection line, the node connection line connecting the second electrode of the first transistor and the gate of the driving transistor; A projection of the third reset signal line on the substrate substrate is located between the node connection line and the first corresponding data line on the substrate substrate, or the projection of the third reset signal line on the substrate substrate is located between the node connection line and the second corresponding data line on the substrate substrate.

7. The array substrate according to claim 6, wherein, In the same column and adjacent two rows of the sub-pixels, the projection of the third reset signal line on the substrate substrate is between the first corresponding data line of the first row and the projection of the node connection line on the substrate substrate, and is not between the first corresponding data line of the second row and the projection of the node connection line on the substrate substrate.

8. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further comprises a node connection line and a plurality of fourth reset signal lines; The node connection line connects the second electrode of the first transistor and the gate of the driving transistor; The projection of the fourth reset signal line on the substrate substrate is located between the node connection line and the first corresponding data line on the substrate substrate, or the projection of the fourth reset signal line on the substrate substrate is located between the node connection line and the second corresponding data line on the substrate substrate.

9. The array substrate of claim 8, wherein, In the same column and adjacent two rows of the sub-pixels, the projection of the fourth reset signal line on the substrate substrate is between the first corresponding data line of the first row and the projection of the node connection line on the substrate substrate, and is not between the first corresponding data line of the second row and the projection of the node connection line on the substrate substrate.

10. The array substrate of claim 7, wherein, The array substrate comprises a substrate substrate, and a semiconductor material layer, a gate insulating layer, a first conductive layer, an insulating layer, a second conductive layer, an interlayer dielectric layer and a first signal line layer arranged in sequence away from the substrate substrate; The node connection line and the third reset signal line are located in the first signal line layer; and / or, The node connection line and the fourth reset signal line are located in the first signal line layer.

11. The array substrate according to any one of claims 1 to 3, wherein, The array substrate comprises a substrate substrate, and a semiconductor material layer, a gate insulating layer, a first conductive layer, an insulating layer, a second conductive layer, an interlayer dielectric layer, a first signal line layer, a first planarization layer and a second signal line layer arranged in sequence away from the substrate substrate; The first corresponding data line and the second corresponding data line are located in the second signal line layer.

12. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further comprises a plurality of first voltage supply lines and / or a plurality of second voltage supply lines; the extension direction of the first voltage supply line and / or the second voltage supply line is the same as the extension direction of the first corresponding data line and the second corresponding data line.

13. The array substrate of claim 12, wherein, In the row direction, the orthogonal projection of the first voltage supply line and / or the second voltage supply line on the substrate substrate is located between the orthogonal projections of at least two of the data lines on the substrate substrate.

14. The array substrate of any one of claims 1 to 3, further comprising a first reset signal network and a second reset signal network; wherein the first reset signal network comprises a plurality of first reset signal lines and a plurality of third reset signal lines that are interconnected with each other; the second reset signal network comprises a plurality of second reset signal lines and a plurality of fourth reset signal lines that are interconnected with each other; each first reset signal line of the plurality of first reset signal lines is connected to one or more third reset signal lines of the plurality of third reset signal lines; each third reset signal line of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines; each second reset signal line of the plurality of second reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; and each fourth reset signal line of the plurality of fourth reset signal lines is connected to one or more second reset signal lines of the plurality of second reset signal lines.

15. The array substrate of claim 14, further comprising pixel driving circuits arranged in K columns and M rows, K and M being positive integers; the K columns comprise a (4k-3)th column of the K columns, a (4k-2)th column of the K columns, a (4k-l)th column of the K columns, and a 4kth column of the K columns, k being a positive integer, 1≤k≤(K / 4); the M rows comprise a (2m-l)th row of the M rows and a 2mth row of the M rows, m being a positive integer, 1≤m≤(M / 2); the plurality of third reset signal lines are absent in the (4k-2)th column and the 4kth column; the plurality of fourth reset signal lines are absent in the (4k-3)th column and the (4k-l)th column; the plurality of first reset signal lines are absent in the (2m)th row; and the plurality of second reset signal lines are absent in the (2m-l)th row.

16. The array substrate of claim 15, wherein, each first reset signal line of the plurality of first reset signal lines located in the (2m-l)th row is connected to one or more third reset signal lines of the plurality of third reset signal lines located in the (4k-3)th column or the (4k-l)th column; each third reset signal line of the plurality of third reset signal lines located in the (4k-3)th column or the (4k-l)th column is connected to one or more first reset signal lines of the plurality of first reset signal lines located in the (2m-l)th row; each second reset signal line of the plurality of second reset signal lines located in the (2m)th row is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines located in the (4k-2)th column or the 4kth column; and each fourth reset signal line of the plurality of fourth reset signal lines located in the (4k-2)th column or the 4kth column is connected to one or more second reset signal lines of the plurality of second reset signal lines located in the (2m)th row. Each of the plurality of fourth reset signal lines located in the (4k-2)th column or the (4k)th column is connected to one or more of the plurality of second reset signal lines located in the (2m)th row.

17. A display device comprising the array substrate according to any one of claims 1 to 16 and one or more integrated circuits connected to the array substrate.

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