Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided, the display device including: a display panel including pixels; a gate driver configured to output a gate signal to the pixel; a data driver configured to apply a data voltage to the display panel; and a driving controller configured to control the gate driver and the data driver. A period in which the display panel is driven may include a first period, a second period, and a third period. In a first period, the first gate signal may have an active level, the second gate signal may have an inactive level, the first data voltage may have a first voltage level, and the second data voltage may have a third voltage level. In a second period, the first gate signal may have an inactive level, the second gate signal may have an active level, the first data voltage may become a second voltage level, and the second data voltage may have a third voltage level.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and an electronic device including the display device. More specifically, the display device improves the display quality of the display panel by reducing fluctuations in the electrical voltage applied to the display panel. Background Technology

[0002] The display device may include a display panel and a display panel driver. The display panel may include multiple gate lines, multiple data lines, multiple emitter lines, and multiple pixels. The display panel driver may include a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, an emitter driver that provides emitter signals to the emitter lines, and a drive controller that provides control signals to the gate driver, data driver, and emitter driver.

[0003] While providing data voltage to the data lines, the electrical voltage applied to the display panel may fluctuate due to coupling with voltage changes in the data lines. These fluctuations in the electrical voltage within the display panel can degrade its display quality. Summary of the Invention

[0004] Embodiments of the present invention provide a display device for improving the display quality of a display panel and an electronic device including the display device.

[0005] According to an embodiment, the display device may include: a display panel including a plurality of pixels; a gate driver configured to output gate signals to the plurality of pixels; a data driver configured to apply a data voltage to the display panel; and a drive controller configured to control the gate driver and the data driver. The display panel can display based on the data voltage. The display panel may include a first pixel row, a second pixel row, a third pixel row, and a fourth pixel row. The data voltage may include a first data voltage and a second data voltage. The first data voltage may be applied to the first pixel row and the third pixel row. The second data voltage may be applied to the second pixel row and the fourth pixel row. The gate signals may include a first gate signal and a second gate signal. The first gate signal may be output to the first pixel row and the second pixel row. The second gate signal may be output to the third pixel row and the fourth pixel row. When the gate signal has an active level, the data voltage may be applied to the corresponding pixel row. The time period during which the display panel is driven may include a first time period, a second time period, and a third time period. In the first time period, the first gate signal may have an active level, the second gate signal may have an inactive level, the first data voltage may have a first voltage level, and the second data voltage may have a third voltage level. During the second time period, the first gate signal may have an inactive level, the second gate signal may have an active level, the first data voltage may change to a second voltage level, and the second data voltage may have a third voltage level.

[0006] In an embodiment, during the third time period, the first gate signal may have an inactive level, the second gate signal may have an active level, the first data voltage may have a second voltage level, and the second data voltage may change to a fourth voltage level.

[0007] In this embodiment, when the first data voltage changes from a first voltage level to a second voltage level, the first data voltage can change at a first switching rate. When the second data voltage changes from a third voltage level to a fourth voltage level, the second data voltage can change at a second switching rate different from the first switching rate.

[0008] In an embodiment, the first conversion rate may be greater than the second conversion rate.

[0009] In an embodiment, the period during which the display panel is driven may further include a fourth period. During the fourth period, the first data voltage may change from a second voltage level to a fifth voltage level different from the second voltage level. During the fourth period, the second data voltage may change from a fourth voltage level to a sixth voltage level different from the fourth voltage level. When the first data voltage changes from the second voltage level to the fifth voltage level, the first data voltage may change at a second switching rate. When the second data voltage changes from the fourth voltage level to the sixth voltage level, the second data voltage may change at a first switching rate.

[0010] In one embodiment, the data driver may include a data voltage generation block and a buffer block. The data voltage generation block is configured to generate a data voltage based on a data signal, and the buffer block is configured to output a first data voltage and a second data voltage based on the data voltage and a delay signal. The buffer block can control the output delay of at least one of the first data voltage and the second data voltage.

[0011] In an embodiment, the buffer block can output a second data voltage with an output delay.

[0012] In one embodiment, the buffer block may include multiple first amplifiers and multiple second amplifiers. The first amplifiers may output a first data voltage based on a first bias voltage. The second amplifiers may output a second data voltage based on a second bias voltage. When the output delay of the second data voltage is controlled, the second bias voltage may be lower than the first bias voltage.

[0013] In an embodiment, the display panel may further include a first data line, a second data line, a third data line, and a fourth data line. At least one of the first amplifiers may be connected to the first data line and the third data line, and at least one of the second amplifiers may be connected to the second data line and the fourth data line.

[0014] In one embodiment, the display panel may include a first data line receiving a first data voltage and a second data line receiving a second data voltage. A first pixel row may include a first pixel, a second pixel row may include a second pixel, a third pixel row may include a third pixel, and a fourth pixel row may include a fourth pixel. The first and third pixels may be connected to the first data line. The second and fourth pixels may be connected to the second data line.

[0015] In an embodiment, at least one of the plurality of pixels may include a first transistor, a second transistor, and a light-emitting element. The first transistor is configured to generate a drive current based on the voltage of the first node, the second transistor is configured to apply a data voltage to the first node in response to a gate signal, and the light-emitting element is configured to emit light based on the drive current.

[0016] According to an embodiment, the display device may include: a display panel including a plurality of pixels; a gate driver configured to output gate signals to the plurality of pixels; a data driver configured to apply a data voltage to the display panel; and a drive controller configured to control the gate driver and the data driver. The display panel can display based on the data voltage. The display panel may include a first pixel row, a second pixel row, a third pixel row, and a fourth pixel row. The data voltage may include a first data voltage and a second data voltage. The first data voltage may be applied to the first pixel row and the third pixel row. The second data voltage may be applied to the second pixel row and the fourth pixel row. The data driver may include: a data voltage generation block configured to generate a data voltage based on a data signal; and a buffer block configured to output the first data voltage and the second data voltage based on the data voltage and a delay signal. The buffer block can control the output delay of at least one of the first data voltage and the second data voltage.

[0017] In this embodiment, the gate signal may include a first gate signal and a second gate signal. The first gate signal may be output to a first pixel row and a second pixel row. The second gate signal may be output to a third pixel row and a fourth pixel row. The second gate signal may be output after the first gate signal is output.

[0018] In one embodiment, the buffer block may include multiple first amplifiers and multiple second amplifiers. The first amplifiers may output a first data voltage based on a first bias voltage. The second amplifiers may output a second data voltage based on a second bias voltage. When the output delay of the second data voltage is controlled, the second bias voltage may be lower than the first bias voltage.

[0019] According to an embodiment, the electronic device may include: a processor configured to input image data and input control signals; a display panel including a plurality of pixels; a gate driver configured to output gate signals to the plurality of pixels; a data driver configured to apply a data voltage to the display panel; and a drive controller configured to control the gate driver and the data driver based on the input image data and the input control signals. The display panel can display based on the data voltage. The display panel may include a first pixel row, a second pixel row, a third pixel row, and a fourth pixel row. The data voltage may include a first data voltage and a second data voltage. The first data voltage may be applied to the first pixel row and the third pixel row. The second data voltage may be applied to the second pixel row and the fourth pixel row. The gate signals may include a first gate signal and a second gate signal. The first gate signal may be output to the first pixel row and the second pixel row. The second gate signal may be output to the third pixel row and the fourth pixel row. When the gate signal has an activation level, the data voltage may be applied to the corresponding pixel row. The time period during which the display panel is driven may include a first time period, a second time period, and a third time period. In the first time period, the first gate signal may have an active level, the second gate signal may have an inactive level, the first data voltage may have a first voltage level, and the second data voltage may have a third voltage level. In the second time period, the first gate signal may have an inactive level, the second gate signal may have an active level, the first data voltage may change to a second voltage level, and the second data voltage may have a third voltage level.

[0020] In an embodiment, during the third time period, the first gate signal may have an inactive level, the second gate signal may have an active level, the first data voltage may have a second voltage level, and the second data voltage may change to a fourth voltage level.

[0021] In this embodiment, when the first data voltage changes from a first voltage level to a second voltage level, the first data voltage can change at a first switching rate. When the second data voltage changes from a third voltage level to a fourth voltage level, the second data voltage can change at a second switching rate different from the first switching rate.

[0022] In an embodiment, the first conversion rate may be greater than the second conversion rate.

[0023] In an embodiment, the period during which the display panel is driven may further include a fourth period. During the fourth period, the first data voltage may change from a second voltage level to a fifth voltage level different from the second voltage level. During the fourth period, the second data voltage may change from a fourth voltage level to a sixth voltage level different from the fourth voltage level. When the first data voltage changes from the second voltage level to the fifth voltage level, the first data voltage may change at a second switching rate. When the second data voltage changes from the fourth voltage level to the sixth voltage level, the second data voltage may change at a first switching rate.

[0024] In one embodiment, the data driver may include a data voltage generation block and a buffer block. The data voltage generation block is configured to generate a data voltage based on a data signal, and the buffer block is configured to output a first data voltage and a second data voltage based on the data voltage and a delay signal. The buffer block can control the output delay of at least one of the first data voltage and the second data voltage.

[0025] Even-numbered data voltages can be changed after odd-numbered data voltages. Because the timing of odd-numbered data voltage changes can differ from that of even-numbered data voltage changes, power voltage fluctuations caused by data voltage variations can be reduced within the frame period, and the driving reliability of the light-emitting elements can be improved. Therefore, the display quality of the display panel can be improved. Attached Figure Description

[0026] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0028] Figure 2 It is a diagram showing the pixels included in the display panel.

[0029] Figure 3 This is a block diagram showing the display panel, gate driver, and data driver included in the display device.

[0030] Figure 4 This is a block diagram showing the display panel and data drive included in the display device.

[0031] Figure 5 This is a timing diagram showing the operation of the display panel.

[0032] Figure 6 This is a timing diagram showing the operation of the display panel during the effective time period.

[0033] Figure 7 This is a timing diagram showing the operation of the display panel during the effective time period.

[0034] Figure 8 This is a timing diagram showing the operation of the display panel during the effective time period.

[0035] Figure 9 This is a timing diagram showing the operation of the display panel during the effective time period.

[0036] Figure 10 This is a timing diagram showing the power voltage fluctuations caused by coupling with changes in data voltage.

[0037] Figure 11 This is a block diagram showing a data driver included in a display device.

[0038] Figure 12 This is a block diagram showing the buffer block included in the data drive.

[0039] Figure 13 This is a circuit diagram showing the pixels included in the display panel.

[0040] Figure 14 This is a circuit diagram showing the pixels included in the display panel.

[0041] Figure 15 This is a circuit diagram showing the pixels included in the display panel.

[0042] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment.

[0043] Figure 17 It is shown Figure 16 An example diagram of an electronic device. Detailed Implementation

[0044] In the following sections, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0045] The display device may include: a display panel including a plurality of pixels; a gate driver configured to provide write gate signals to a pair of odd-numbered pixel rows and even-numbered pixel rows among the plurality of pixels; and a data driver configured to provide data voltages to the selected pair of odd-numbered pixel rows and even-numbered pixel rows. The data voltages include a first data voltage and a second data voltage, wherein the first data voltage is applied to the selected odd-numbered pixel rows in a first timing sequence, and the second data voltage is applied to the selected even-numbered pixel rows in a second timing sequence, and the first timing sequence is preceded by a first delay by the second timing sequence.

[0046] Figure 1 This is a block diagram illustrating a display device 1 according to an embodiment of the concept of the present invention.

[0047] Reference Figure 1The display device 1 may include a display panel 100, a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0048] The display panel 100 may have a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0049] The display panel 100 may include multiple gate lines GL, multiple data lines DL, multiple emitter lines EL, and multiple pixels PX electrically connected to the gate lines GL, data lines DL, and emitter lines EL. The gate lines GL may extend in a first direction D1. The data lines DL may extend in a second direction D2 perpendicular to the first direction D1. The emitter lines EL may extend in the first direction D1.

[0050] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, blue image data, and white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0051] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0052] The drive controller 200 can control the operation of the gate driver 300 by generating a first control signal CONT1 based on the input control signal CONT and providing the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0053] The drive controller 200 can control the operation of the data driver 500 by generating a second control signal CONT2 based on the input control signal CONT and providing the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal. The second control signal CONT2 may also include a reference signal. Figure 11 The delayed signal DS is described in detail.

[0054] The drive controller 200 can generate a data signal DATA based on the input image data IMG and provide the data signal DATA to the data driver 500.

[0055] The drive controller 200 can control the operation of the gamma reference voltage generator 400 by generating a third control signal CONT3 based on the input control signal CONT and providing the third control signal CONT3 to the gamma reference voltage generator 400.

[0056] The drive controller 200 can control the operation of the transmitter driver 600 by generating a fourth control signal CONT4 based on the input control signal CONT and providing the fourth control signal CONT4 to the transmitter driver 600.

[0057] The gate driver 300 can receive a first control signal CONT1 from the drive controller 200, and receive a gate high voltage and a gate low voltage from a voltage generator included in the gate driver 300. The gate driver 300 can generate a gate signal for driving the gate line GL based on the first control signal CONT1, the gate high voltage, and the gate low voltage, and provide the gate signal to the gate line GL. The gate signal may include an initialization gate signal, a write gate signal, a compensation gate signal, and a bias gate signal.

[0058] The gate driver 300 can be disposed in a circuit block in the peripheral region. Alternatively, the gate driver 300 can be disposed in a distributed manner in the peripheral region.

[0059] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200, and provides the gamma reference voltage VGREF to the data driver 500. The voltage value of the gamma reference voltage VGREF can correspond to the voltage level of the data signal DATA.

[0060] The gamma reference voltage generator 400 can be integrated into the drive controller 200 or into the data driver 500.

[0061] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage VDATA, and provides the data voltage VDATA to the data line DL. The pixel PX can emit light with a brightness corresponding to the data voltage VDATA.

[0062] The data driver 500 can be disposed in the circuit block of the peripheral area of ​​the display panel 100. Alternatively, the data driver 500 can be disposed in a distributed manner in the peripheral area.

[0063] The transmitter driver 600 can generate a transmitter signal in response to the fourth control signal CONT4 received from the driver controller 200 and provide the transmitter signal to the display panel 100.

[0064] The transmitter driver 600 can be located in a circuit block in the peripheral area. Alternatively, the transmitter driver 600 can be distributed in the peripheral area.

[0065] although Figure 1 The illustrated embodiment shows a gate driver 300 disposed on a first side of the display panel 100 and an emitter driver 600 disposed on a second side of the display panel 100, but the inventive concept is not limited thereto. For example, the gate driver 300 and the emitter driver 600 may be disposed on the first side of the display panel 100. More specifically, the gate driver 300 and the emitter driver 600 may be disposed in the peripheral region of the first side of the display panel 100. The gate driver 300 and the emitter driver 600 may be formed in an integrated manner.

[0066] Figure 2 This is a diagram showing the pixel PX included in the display device 1.

[0067] Reference Figure 1 and Figure 2 A pixel (PX) may include a pixel circuit (PC) and a light-emitting element (EE).

[0068] The pixel circuit PC can generate a drive current ID based on the data voltage VDATA and the first power voltage ELVDD. The pixel circuit PC can apply the drive current ID to the light-emitting element EE, where the light-emitting element EE emits light corresponding to the drive current ID.

[0069] The light-emitting element EE may include a first electrode receiving a drive current ID and a second electrode connected to a second power voltage ELVSS. The light-emitting element EE may emit light based on the drive current ID. The light-emitting element EE may be an organic light-emitting diode (OLED), but is not limited thereto. For example, the light-emitting element EE may be a nano-light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro-light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. The first power voltage ELVDD connected to the pixel PX may provide the drive current ID to the light-emitting element EE. Because the first power voltage ELVDD may fluctuate while the drive current ID is being drawn from the first power voltage ELVDD, the drive current ID may also change in response to the fluctuation of the first power voltage ELVDD. Furthermore, when multiple pixels operate simultaneously by receiving a data voltage VDATA at a given time point, the fluctuation of the first power voltage ELVDD may become even worse. Therefore, fluctuations in the first power voltage ELVDD and the drive current ID may degrade the display quality of the display panel 100. According to embodiments of the present invention, by allocating the operation timing of the pixels, the fluctuation of the first power voltage ELVDD can be reduced, thereby improving the display quality of the display panel 100.

[0070] Figure 3 This is a block diagram showing a display panel 100, a gate driver 300, and a data driver 500 included in a display device 1. Figure 4 This is a block diagram showing the display panel 100 and data driver 500 included in the display device 1.

[0071] Reference Figures 1 to 4 The display panel 100 may include first write gate lines to Nth write gate lines GWL[1], GWL[2], GWL[3], GWL[4] to GWL[N-1] and GWL[N], and first data lines to Kth data lines DL[1], DL[2], DL[3], DL[4] to DL[K-1] and DL[K]. Here, N and K are even natural numbers. The display panel 100 may include a plurality of pixel rows PX-R. Each pixel row PX-R may include pixels PX connected to the write gate lines, and each of the pixels PX may be connected to the corresponding data line. The display panel 100 may include first pixel rows PX-R to Nth pixel rows PX-R.

[0072] According to an embodiment, each of the first write gate line to the Nth write gate line GWL[1] to GWL[N] provides a write gate signal to the write gate transistor of the pixel PX connected to the write gate line. Each of the pixels PX connected to the write gate line can be connected to a corresponding data line among the first data line DL[1] to the Kth data line DL[K]. For example, a first pixel row can be connected to the first write gate line GWL[1] and receive a data voltage through the odd-numbered data lines among the first data lines DL[1] to the Kth data lines DL[K]. A first write gate signal GW[1] can be applied to the first write gate line GWL[1]. A second pixel row can be connected to the second write gate line GWL[2] and receive a data voltage through the even-numbered data lines among the first data lines DL[1] to the Kth data lines DL[K]. A second write gate signal GW[2] can be applied to the second write gate line GWL[2]. A third pixel row can be connected to the third write gate line GWL[3] and receive a data voltage through the odd-numbered data lines among the first data lines DL[1] to the Kth data lines DL[K]. The third write gate signal GW[3] can be applied to the third write gate line GWL[3]. The fourth pixel row can be connected to the fourth write gate line GWL[4] and receive data voltage through the even-numbered data lines from the first data line DL[1] to the Kth data line DL[K]. The fourth write gate signal GW[4] can be applied to the fourth write gate line GWL[4]. The (N-1)th pixel row can be connected to the (N-1)th write gate line GWL[N-1] and receive data voltage through the odd-numbered data lines from the first data line DL[1] to the Kth data line DL[K]. The (N-1)th write gate signal GW[N-1] can be applied to the (N-1)th write gate line GWL[N-1]. The Nth pixel row can be connected to the Nth write gate line GWL[N] and receive data voltage through the even-numbered data lines from the first data line DL[1] to the Kth data line DL[K]. The Nth write gate signal GW[N] can be applied to the Nth write gate line GWL[N].

[0073] Reference Figure 3 Odd-numbered pixel rows can be connected to odd-numbered data lines. For example, the first and third pixel rows can be connected to the odd-numbered data lines from the first data line DL[1] to the Kth data line DL[K]. Similarly, even-numbered pixel rows can be connected to even-numbered data lines. For example, the second and fourth pixel rows can be connected to the even-numbered data lines from the first data line DL[1] to the Kth data line DL[K].

[0074] The data driver 500 may also include a plurality of demultiplexers for selectively providing a data voltage VDATA to one of the odd and even data lines. For example, a first demultiplexer of the plurality of demultiplexers may select one of a first data line DL[1] and a second data line DL[2] and provide the data voltage VDATA to the selected data line of the first data line DL[1] and the second data line DL[2]. (See also...) Figure 4 The display panel 100 may include multiple pixel columns PX-C. The number of pixel columns may correspond to half the number of data lines. Each pixel column may include a pixel connected to one of the odd-numbered and even-numbered data lines. For example, a pixel PX in the first pixel column may be connected to one of the first data line DL[1] and the second data line DL[2]. The first data line DL[1] may be connected to the first pixel of the first pixel column, and the second data line DL[2] may be connected to the second pixel of the first pixel column.

[0075] The first data line DL[1] can be connected to the odd-numbered pixels of the first pixel column, and the odd-numbered pixels of the first pixel column are also connected to the odd-numbered write gate lines from the first write gate line GWL[1] to the Nth write gate line GWL[N]. The second data line DL[2] can be connected to the even-numbered pixels of the first pixel column, and the even-numbered pixels of the first pixel column are also connected to the even-numbered write gate lines from the first write gate line GWL[1] to the Nth write gate line GWL[N]. The first and third pixels of the pixel column PX-C can be connected to the odd-numbered pixel rows of the multiple pixel rows PX-R, and the second and fourth pixels of the pixel column PX-C can be connected to the even-numbered pixel rows of the multiple pixel rows PX-R.

[0076] Additionally, the data driver 500 can apply an odd data voltage OVDATA to an odd data line. The odd data voltage OVDATA can be referred to as the first data voltage. The data driver 500 can apply an even data voltage EVDATA to an even data line. The even data voltage EVDATA can be referred to as the second data voltage. Odd pixel rows can receive the odd data voltage OVDATA, and even pixel rows can receive the even data voltage EVDATA. When the first data line DL[1] to the Kth data line DL[K] are arranged sequentially in the display panel 100, the odd data lines, including the first data line DL[1] and the third data line DL[3], among the first data lines DL[1] to the Kth data line DL[K], can be alternately arranged with the even data lines. The even data lines, including the second data line DL[2] and the fourth data line DL[4], among the first data lines DL[1] to the Kth data line DL[K], can be alternately arranged with the odd data lines. The data voltages from the first data line DL[1] to the Kth data line DL[K] are transmitted to the pixel PX by turning on the write gate transistor of the pixel PX. The write gate transistor of the pixel PX can be turned on when the activation level of the write gate signal is applied to the write gate transistor. The activation level can be a voltage level that turns on the write gate transistor, and the deactivation level can be a voltage level that turns off the write gate transistor.

[0077] When a write gate signal with an active level is received, the pixel circuit PC can enter the active period, and the data voltage VDATA can be transmitted to the pixel circuit PC. When the write gate signal has an inactive level, the pixel circuit PC can remain in the inactive period, and the data voltage VDATA is not transmitted to the pixel circuit PC.

[0078] According to the embodiment, the activation period of the first write gate signal GW[1] and the activation period of the second write gate signal GW[2] can be substantially the same. Therefore, the first write gate signal GW[1] and the second write gate signal GW[2] can be transmitted to the pixel circuit PC simultaneously. Therefore, the timing of the first pixel row receiving the odd data voltage OVDATA and the timing of the second pixel row receiving the even data voltage EVDATA can be close to each other. In the following, the pair of first write gate signals GW[1] and second write gate signals GW[2] can be referred to as the first gate signal.

[0079] Similarly, the activation periods of the third write gate signal GW[3] and the fourth write gate signal GW[4] can be substantially the same. Therefore, the third write gate signal GW[3] and the fourth write gate signal GW[4] can be transmitted to the pixel circuit PC simultaneously. Therefore, the timing of the third pixel row receiving the odd data voltage OVDATA and the timing of the fourth pixel row receiving the even data voltage EVDATA can be close to each other. In the following text, the pair of third write gate signals GW[3] and fourth write gate signals GW[4] can be referred to as the second gate signals.

[0080] The activation periods of the (N-1)th write gate signal GW[N-1] and the Nth write gate signal GW[N] can be substantially the same. Therefore, the (N-1)th write gate signal GW[N-1] and the Nth write gate signal GW[N] can be transmitted to the pixel circuit PC simultaneously. Therefore, the timing of the (N-1)th pixel row receiving odd-numbered data voltage OVDATA and the timing of the Nth pixel row receiving even-numbered data voltage EVDATA can be close to each other.

[0081] Depending on the selection of the pixel row to be activated by the activation level of the write gate signal corresponding to the selected pixel row, the data voltage VDATA can be applied differently to different pixel rows PX-R. For example, the odd data voltage OVDATA when the first write gate signal GW[1] is at the active level can be different from the odd data voltage OVDATA when the third write gate signal GW[3] is at the active level. For example, when the first write gate signal GW[1] is at the active level, the odd data voltage OVDATA can be at a first voltage level, and when the first write gate signal GW[1] changes from the active level to the inactive level, the odd data voltage OVDATA can change from the first voltage level to a second voltage level, and when the third write gate signal GW[3] is at the active level, the odd data voltage OVDATA can be at a second voltage level, and when the third write gate signal GW[3] changes from the active level to the inactive level, the odd data voltage OVDATA can change from the second voltage level to a fifth voltage level. The even data voltage EVDATA when the second write gate signal GW[2] is at the active level can be different from the even data voltage EVDATA when the fourth write gate signal GW[4] is at the active level. For example, when the second write gate signal GW[2] is at the active level, the even data voltage EVDATA can be at the third voltage level, and when the second write gate signal GW[2] changes from the active level to the inactive level, the even data voltage EVDATA can change from the third voltage level to the fourth voltage level, and when the fourth write gate signal GW[4] is at the active level, the even data voltage EVDATA can be at the fourth voltage level, and when the fourth write gate signal GW[4] changes from the active level to the inactive level, the even data voltage EVDATA can change from the fourth voltage level to the sixth voltage level.

[0082] Figure 5 This is a timing diagram showing the operation of the display panel 100. Figure 6 This is a timing diagram showing the operation of the display panel 100 during the effective time period ACT.

[0083] Reference Figures 1 to 6The display panel 100 displays frames of the input image data IMG during the frame period. The frame period may include an active period ACT and a blanking period BLK. During the active period ACT, write gate signals GW[1], GW[2], GW[3], GW[4] to GW[N-1] and GW[N] may be provided to the write gate transistor of the pixel PX. Each of the write gate signals GW[1], GW[2], GW[3], GW[4] to GW[N-1] and GW[N] may turn on the corresponding write gate transistor of the pixel PX to transmit the data voltage VDATA applied to the pixel PX to the pixel circuit PC.

[0084] The effective time period ACT can include the first time period (also known as the first time period) TP1A, the second time period (also known as the second time period) TP2A, and the third time period (also known as the third time period) TP3A.

[0085] During the first time period TP1A, the first write gate signal GW[1] and the second write gate signal GW[2] (also referred to as the first gate signal) can have an active level, and the third write gate signal GW[3] and the fourth write gate signal GW[4] (also referred to as the second gate signal) can have an inactive level. During the first time period TP1A, the odd data voltage OVDATA can have a first voltage level V1A, and the even data voltage EVDATA can have a third voltage level V3A.

[0086] During the first time period TP1A, the odd data voltage OVDATA can be applied to the first pixel row in response to the first write gate signal GW[1], and the even data voltage EVDATA can be applied to the second pixel row in response to the second write gate signal GW[2].

[0087] During the second time period TP2A, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. During the second time period TP2A, the odd data voltage OVDATA can have a second voltage level V2A, and the even data voltage EVDATA can maintain a third voltage level V3A.

[0088] During the second time period TP2A, the odd data voltage OVDATA can be applied to the third pixel row in response to the third write gate signal GW[3], and the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4].

[0089] The data driver 500 can control the output timing of odd data voltage OVDATA and even data voltage EVDATA differently. The second time period TP2A corresponds to the output delay between the output timing of even data voltage EVDATA and the output timing of odd data voltage OVDATA. Therefore, in the second time period TP2A, while the odd data voltage OVDATA transitions to a different voltage level, the even data voltage EVDATA can maintain its previous even data voltage. For example, in the second time period TP2A, while the odd data voltage OVDATA transitions from a first voltage level V1A to a second voltage level V2A, the even data voltage EVDATA can maintain a third voltage level V3A.

[0090] During the third time period TP3A, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. During the third time period TP3A, the odd data voltage OVDATA can maintain the second voltage level V2A, and the even data voltage EVDATA can change from the third voltage level V3A to the fourth voltage level V4A.

[0091] During the third time period TP3A, the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4], and the fourth voltage level V4A can be applied to the fourth pixel row in response to the fourth write gate signal GW[4].

[0092] When the data voltage changes to different levels, the power voltage of pixel PX may fluctuate due to the change in data voltage. By allocating the timing of applying the data voltage to the data lines, the power voltage fluctuations caused by coupling with changes in data voltage can be reduced.

[0093] According to an embodiment, in order to allocate the timing of applying data voltages to the data lines, the even-numbered data voltage EVDATA can be changed after a first delay starting from the time point when the odd-numbered data voltage OVDATA changes. For example, refer to... Figure 6 After a first delay following the transition from the odd-numbered data voltage OVDATA to the second voltage level V2A, the even-numbered data voltage EVDATA can transition from the third voltage level V3A to the fourth voltage level V4A. This first delay can be controlled by the data driver 500 and can be synchronized with... Figure 6 The second time period corresponds to TP2A. Therefore, the first timing of the odd-numbered data voltage OVDATA change and the second timing of the even-numbered data voltage EVDATA change can be different, thus allowing for the allocation of timing for applying data voltage to the data lines.

[0094] Because the first timing of the odd-numbered data voltage OVDATA change can differ from the second timing of the even-numbered data voltage EVDATA change, the data voltage of the even-numbered data lines can change after the data voltage of the odd-numbered data lines changes. By applying data voltages to the odd-numbered and even-numbered data lines at different times, the timing of applying data voltages to the data lines can be allocated, and power voltage fluctuations can be reduced. Because the change in the first power voltage ELVDD can be reduced within the frame period, the driving reliability of the light-emitting element EE can be improved. More specifically, the emission reliability of the light-emitting element EE of the pixel PX can be improved, thereby improving the display quality of the display panel 100.

[0095] Figure 7 This is a timing diagram showing the operation of the display panel 100 during the effective time period ACT.

[0096] Reference Figures 1 to 5 as well as Figure 7 The effective time period ACT may include a first time period TP1B, a second time period TP2B, and a third time period TP3B. According to an embodiment, by adjusting the slewing rate of the data voltage applied to the data line, power voltage fluctuations caused by coupling with changes in the data voltage can be reduced.

[0097] During the first time period TP1B, the first write gate signal GW[1] and the second write gate signal GW[2] may have an active level, and the third write gate signal GW[3] and the fourth write gate signal GW[4] may have an inactive level. During the first time period TP1B, the odd data voltage OVDATA may have a first voltage level V1B, and the even data voltage EVDATA may have a third voltage level V3B.

[0098] During the first time period TP1B, the odd data voltage OVDATA can be applied to the first pixel row in response to the first write gate signal GW[1], and the even data voltage EVDATA can be applied to the second pixel row in response to the second write gate signal GW[2].

[0099] During the second time period TP2B, the first write gate signal GW[1] and the second write gate signal GW[2] may have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] may have active levels. During the second time period TP2B, the odd data voltage OVDATA may change from the first voltage level V1B to the second voltage level V2B at the first slew rate SR1A, and the even data voltage EVDATA may change from the third voltage level V3B to the fourth voltage level V4B at the second slew rate SR2A.

[0100] The first conversion rate SR1A can be greater than the second conversion rate SR2A, and the change of odd data voltage OVDATA can be faster than the change of even data voltage EVDATA.

[0101] During the second time period TP2B, the odd data voltage OVDATA can be applied to the third pixel row in response to the third write gate signal GW[3], and the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4]. The data driver 500 can control the first conversion rate SR1A of the odd data voltage OVDATA and the second conversion rate SR2A of the even data voltage EVDATA differently.

[0102] During the third time period TP3B, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. During the third time period TP3B, the odd data voltage OVDATA can maintain the second voltage level V2B, and the even data voltage EVDATA can have the fourth voltage level V4B.

[0103] In the third time period TP3B, the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4], and the fourth voltage level V4B can be applied to the fourth pixel row in response to the fourth write gate signal GW[4].

[0104] When the data voltage applied to the data line changes to different levels, the power voltage of pixel PX may fluctuate due to the change in data voltage. By adjusting the switching rate of the data voltage applied to the data line differently, the power voltage fluctuation caused by coupling with the change in data voltage can be reduced.

[0105] According to an embodiment, in order to adjust the switching rate of the data voltage applied to the data line differently, the even-numbered data voltage EVDATA transitions to a different level more slowly than the odd-numbered data voltage OVDATA. For example, refer to... Figure 7After the odd-numbered data voltage OVDATA changes from the first voltage level V1B to the second voltage level V2B at a first slew rate SR1A, the even-numbered data voltage EVDATA can change from the third voltage level V3B to the fourth voltage level V4B at a second slew rate SR2A. Because the first slew rate SR1A is greater than the second slew rate SR2A, the timing of applying the data voltage to the data lines is allocated, and power voltage fluctuations caused by coupling with changes in the data voltage can be reduced. The first slew rate SR1A and the second slew rate SR2A can be adjusted by the data driver 500 and can be changed frame-by-frame or pixel-by-pixel.

[0106] Because the first slew rate SR1A can be greater than the second slew rate SR2A, the change in odd-numbered data voltage OVDATA can be faster than the change in even-numbered data voltage EVDATA. By adjusting the slew rate of the data voltage applied to the data line differently, the coupling voltage of the first power voltage ELVDD can be reduced, and the change in the first power voltage ELVDD can be reduced. Therefore, the first power voltage ELVDD can fluctuate less due to coupling with changes in the data voltage. Because the fluctuation of the first power voltage ELVDD can be reduced during the frame period, the driving reliability of the light-emitting element EE can be improved. More specifically, the emission reliability of the light-emitting element EE of the pixel PX can be improved, thereby improving the display quality of the display panel 100.

[0107] Figure 8 This is a timing diagram showing the operation of the display panel 100 during the effective time period ACT.

[0108] Reference Figures 1 to 5 as well as Figure 8 The effective time period ACT may include a first time period TP1C, a second time period TP2C, a third time period TP3C, a fourth time period TP4C, and a fifth time period TP5C. According to an embodiment, by adjusting the conversion rate of the data voltage applied to the data line differently in different pixel rows, fluctuations in the first power voltage ELVDD caused by coupling with changes in the data voltage can be reduced.

[0109] During the first time period TP1C, the first write gate signal GW[1] and the second write gate signal GW[2] may have an active level, and the third write gate signal GW[3] and the fourth write gate signal GW[4] may have an inactive level. During the first time period TP1C, the odd data voltage OVDATA may have a first voltage level V1C, and the even data voltage EVDATA may have a third voltage level V3C.

[0110] During the first time period TP1C, the odd data voltage OVDATA can be applied to the first pixel row in response to the first write gate signal GW[1], and the even data voltage EVDATA can be applied to the second pixel row in response to the second write gate signal GW[2].

[0111] During the second time period TP2C, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. During the second time period TP2C, the odd data voltage OVDATA can change from the first voltage level V1C to the second voltage level V2C at the first conversion rate SR1A, and the even data voltage EVDATA can change from the third voltage level V3C to the fourth voltage level V4C at the second conversion rate SR2A.

[0112] In an embodiment, the first conversion rate SR1A can be greater than the second conversion rate SR2A, and the change of odd data voltage OVDATA can be faster than the change of even data voltage EVDATA.

[0113] During the second time period TP2C, the odd data voltage OVDATA can be applied to the third pixel row in response to the third write gate signal GW[3], and the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4]. The data driver 500 can control the first conversion rate SRA1 of the odd data voltage OVDATA and the second conversion rate SRA2 of the even data voltage EVDATA differently.

[0114] During the third time period TP3C, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. During the third time period TP3C, the odd data voltage OVDATA can maintain the second voltage level V2C, and the even data voltage EVDATA can have the fourth voltage level V4C.

[0115] During the third time period TP3C, the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4], and the fourth voltage level V4C can be applied to the fourth pixel row in response to the fourth write gate signal GW[4].

[0116] In the fourth time period TP4C, the first write gate signal GW[1], the second write gate signal GW[2], the third write gate signal GW[3], and the fourth write gate signal GW[4] can have inactive levels, and the fifth write gate signal GW[5] and the sixth write gate signal GW[6] can have active levels. In the fourth time period TP4C, the odd data voltage OVDATA can change from the second voltage level V2C to the fifth voltage level V5C at the second slew rate SR2A, and the even data voltage EVDATA can change from the fourth voltage level V4C to the sixth voltage level V6C at the first slew rate SR1A.

[0117] Reference Figure 8 In the second time period TP2C, the odd-numbered data voltage OVDATA can be changed at a first conversion rate SR1A, and the even-numbered data voltage EVDATA can be changed at a second conversion rate SR2A. In the fourth time period TP4C, unlike in the second time period TP2C, the odd-numbered data voltage OVDATA can be changed at the second conversion rate SR2A, and the even-numbered data voltage EVDATA can be changed at the first conversion rate SR1A. Because the conversion rates of the odd-numbered data voltage OVDATA and the even-numbered data voltage EVDATA are adjusted differently in different pixels PX during the effective time period ACT, the reliability of the data voltage VDATA applied to the data line DL can be improved. For example, the conversion rate for the odd-numbered data voltage OVDATA can be increased or decreased in different pixels PX, and the change in the odd-numbered data voltage OVDATA can be delayed differently in different pixels PX. Similarly, the conversion rate for the even-numbered data voltage OVDATA can be increased or decreased in different pixels PX, and the even-numbered data voltage EVDATA can be delayed differently in different pixels PX. By adjusting the conversion rate of the data voltage applied to the data line differently in different pixels PX, the power voltage of the pixel PX can be less affected by the coupling with the data voltage variation, thereby improving the reliability of the data voltage VDATA applied to the pixel PX.

[0118] Figure 9 This is a timing diagram showing the operation of the display panel 100 during the effective time period ACT.

[0119] Reference Figures 1 to 5 as well as Figure 9The effective time period ACT can include a first time period TP1D, a second time period TP2D, a third time period TP3D, a fourth time period TP4D, and a fifth time period TP5D. According to an embodiment, by adjusting the conversion rate of the data voltage applied to the data line and applying an opposite data voltage to the data line, the electrical voltage of the pixel PX can be less affected by the coupling with changes in the data voltage.

[0120] During the first time period TP1D, the first write gate signal GW[1] and the second write gate signal GW[2] may have an active level, and the third write gate signal GW[3] and the fourth write gate signal GW[4] may have an inactive level. During the first time period TP1D, the odd data voltage OVDATA may have a first voltage level V1D, and the even data voltage EVDATA may have a third voltage level V3D.

[0121] During the first time period TP1D, the odd data voltage OVDATA can be applied to the first pixel row in response to the first write gate signal GW[1], and the even data voltage EVDATA can be applied to the second pixel row in response to the second write gate signal GW[2].

[0122] During the second time period TP2D, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. During the second time period TP2D, the odd data voltage OVDATA can change from the first voltage level V1D to the second voltage level V2D at the first conversion rate SR1A, and the even data voltage EVDATA can change from the third voltage level V3D to the fourth voltage level V4D at the second conversion rate SR2A.

[0123] The first conversion rate SR1A can be greater than the second conversion rate SR2A, and the change of odd data voltage OVDATA can be faster than the change of even data voltage EVDATA.

[0124] During the second time period TP2D, the odd data voltage OVDATA can be applied to the third pixel row in response to the third write gate signal GW[3], and the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4]. The data driver 500 can control the first conversion rate SRA1 of the odd data voltage OVDATA and the second conversion rate SRA2 of the even data voltage EVDATA differently.

[0125] In the third time period TP3D, the first write gate signal GW[1] and the second write gate signal GW[2] can have inactive levels, and the third write gate signal GW[3] and the fourth write gate signal GW[4] can have active levels. In the third time period TP3D, the odd data voltage OVDATA can maintain the second voltage level V2D, and the even data voltage EVDATA can have the fourth voltage level V4D.

[0126] In the third time period TP3D, the even data voltage EVDATA can be applied to the fourth pixel row in response to the fourth write gate signal GW[4], and the fourth voltage level V4D can be applied to the fourth pixel row in response to the fourth write gate signal GW[4].

[0127] In the fourth time period TP4D, the first write gate signal GW[1], the second write gate signal GW[2], the third write gate signal GW[3], and the fourth write gate signal GW[4] can have inactive levels, and the fifth write gate signal GW[5] and the sixth write gate signal GW[6] can have active levels. In the fourth time period TP4D, the odd data voltage OVDATA can change from the second voltage level V2D to the fifth voltage level V5D at the third slew rate SR3B, and the even data voltage EVDATA can change from the fourth voltage level V4D to the sixth voltage level V6D at the fourth slew rate SR4B. The third slew rate SR3B and the fourth slew rate SR4B can be different from the first slew rate SR1A and the second slew rate SR2A.

[0128] Reference Figure 9In the second time period TP2D, the odd data voltage OVDATA can be changed at a first conversion rate SR1A, and the even data voltage EVDATA can be changed at a second conversion rate SR2A. Furthermore, in the fourth time period TP4D, the odd data voltage OVDATA can increase from a second voltage level V2D to a fifth voltage level V5D, and the even data voltage EVDATA can decrease from a fourth voltage level V4D to a sixth voltage level V6D. Therefore, during the effective time period ACT, the voltage changes of the odd data voltage OVDATA and the even data voltage EVDATA are in opposite directions, and the coupling effect with the first power voltage ELVDD can be canceled. Thus, the reliability of the data voltage VDATA applied to the data line DL can be improved. For example, the conversion rate of the odd data voltage OVDATA can be increased or decreased in different pixels PX, and the change of the even data voltage EVDATA can be delayed differently in different pixels PX. By adjusting the conversion rates of the odd data voltage OVDATA and the even data voltage OVDATA differently, the reliability of the data voltage VDATA applied to the pixel PX can be improved.

[0129] Furthermore, during the fourth time period TP4D, the odd-numbered data voltage OVDATA can increase from the second voltage level V2D to the fifth voltage level V5D, and the even-numbered data voltage EVDATA can decrease from the fourth voltage level V4D to the sixth voltage level V6D. Therefore, during the effective time period ACT, the voltage changes of the odd-numbered data voltage OVDATA and the even-numbered data voltage EVDATA are in opposite directions, thus canceling the coupling effect with the first power voltage ELVDD. The conversion rates SR3B and SR4B of the odd-numbered data voltage OVDATA and even-numbered data voltage EVDATA can be adjusted according to their data voltage conversion directions. By adjusting the conversion rates of the data voltages applied to the data lines differently for different data voltage conversion directions, fluctuations in the first power voltage ELVDD caused by coupling with changes in the data voltage can be reduced.

[0130] Figure 10 This is a timing diagram showing the power voltage fluctuations caused by coupling with changes in data voltage.

[0131] Reference Figures 1 to 10 Even-numbered data voltages (EVDATA) can change after a first delay starting from the time point when odd-numbered data voltages (OVDATA) change. For example, refer to... Figure 10After a first delay following the transition from the first voltage level to the second voltage level of the odd data voltage OVDATA, the even data voltage EVDATA can transition from the third voltage level to the fourth voltage level. The first delay of the even data voltage EVDATA can be controlled by the data driver 500. Therefore, the first timing of the change in the odd data voltage OVDATA and the second timing of the change in the even data voltage EVDATA can be controlled differently by the data driver 500.

[0132] Because the first timing of the odd-numbered data voltage OVDATA change can differ from the second timing of the even-numbered data voltage EVDATA change, the data voltage of the even-numbered data lines can change after the data voltage of the odd-numbered data lines changes. This reduces the fluctuation of the first power voltage ELVDD caused by the voltage change of the data voltage VDATA. Since the fluctuation of the first power voltage ELVDD can be reduced during the frame period, the driving reliability of the light-emitting element EE can be improved. More specifically, the emission reliability of the light-emitting element EE of the pixel PX can be improved, thereby improving the display quality of the display panel 100. For example, as... Figure 10 As shown, the first power voltage ELVDD fluctuation in the "Example" is smaller than that in the "Conventional Example".

[0133] Figure 11 This is a block diagram illustrating an example of a data drive 500 included in a display device 1.

[0134] Reference Figure 11 The data driver 500A may include a data voltage generation block 510 and a buffer block 520.

[0135] The data voltage generation block 510 can receive the gamma reference voltage VGREF and the data signal DATA, and generate a data voltage VDATA based on the gamma reference voltage VGREF and the data signal DATA. The data voltage generation block 510 can provide the data voltage VDATA to the buffer block 520.

[0136] Buffer block 520 can receive data voltage VDATA and delay signal DS. Buffer block 520 can output odd data voltage OVDATA and even data voltage EVDATA based on data voltage VDATA. Buffer block 520 can control the output delay of odd data voltage OVDATA and even data voltage EVDATA based on delay signal DS.

[0137] In this embodiment, buffer block 520 can control the output timing of even-numbered data voltage EVDATA. For example, after buffer block 520 outputs odd-numbered data voltage OVDATA, buffer block 520 can output even-numbered data voltage EVDATA.

[0138] In one embodiment, buffer block 520 can control the conversion rate of changes in even-numbered data voltage EVDATA. For example, when the even-numbered data voltage EVDATA changes, buffer block 520 can change the conversion rate of changes in the even-numbered data voltage EVDATA. In another embodiment, buffer block 520 can control the conversion rate of changes in odd-numbered data voltage OVDATA. For example, when the odd-numbered data voltage OVDATA changes, buffer block 520 can change the conversion rate of changes in the odd-numbered data voltage OVDATA.

[0139] Figure 12 This is a block diagram showing the buffer block 520A included in the data driver 500.

[0140] Reference Figures 1 to 12 The buffer block 520A may include a first amplification block (also referred to as the first amplifier) ​​521A and a second amplification block (also referred to as the second amplifier) ​​522A. The first amplification block 521A may include multiple data amplifiers (DAMPs). The second amplification block 522A may include multiple data amplifiers (DAMPs). The first amplification block 521A may be referred to as the odd-numbered amplification block, and the second amplification block 522A may be referred to as the even-numbered amplification block. The data amplifiers (DAMPs) may be operational amplifiers.

[0141] The first amplification block 521A can be connected to the odd-numbered data lines. For example, the first amplification block 521A can be connected to the first data line DL[1] and the third data line DL[3], and output the odd-numbered data voltage OVDATA to the odd-numbered data lines. The data amplifier DAMP of the first amplification block 521A can receive the first bias voltage OVDD. The data amplifier DAMP of the first amplification block 521A can generate the odd-numbered data voltage OVDATA based on the data voltage VDATA and the first bias voltage OVDD.

[0142] The second amplifier block 522A can be connected to the even-numbered data lines. For example, the second amplifier block 522A can be connected to the second data line DL[2] and the fourth data line DL[4], and output the even-numbered data voltage EVDATA to the even-numbered data lines. The data amplifier DAMP of the second amplifier block 522A can receive the second bias voltage EVDD. The data amplifier DAMP of the second amplifier block 522A can generate the even-numbered data voltage EVDATA based on the data voltage VDATA and the second bias voltage EVDD.

[0143] The first bias voltage OVDD applied to the first amplification block 521A can vary depending on the slew rate of the odd data voltage OVDATA. For example, when the odd data voltage OVDATA changes at a first slew rate, the first bias voltage OVDD can have a first voltage level, and when the odd data voltage OVDATA changes at a second slew rate, the first bias voltage OVDD can have a second voltage level lower than the first voltage level. When the second voltage level is lower than the first voltage level, the second slew rate is controlled to be less than the first slew rate.

[0144] The second bias voltage EVDD applied to the second amplification block 522A can vary depending on the slew rate of the even-number data voltage EVDATA. For example, when the even-number data voltage EVDATA changes at a first slew rate, the second bias voltage EVDD can have a first voltage level, and when the even-number data voltage EVDATA changes at a second slew rate, the second bias voltage EVDD can have a second voltage level lower than the first voltage level. When the second voltage level is lower than the first voltage level, the second slew rate is controlled to be less than the first slew rate.

[0145] In this embodiment, the bias voltages OVDD and EVDD applied to the data amplifier DAMP can be varied. The variation of these bias voltages allows control over the slew rate of change in the data voltages OVDATA and EVDATA output from the data amplifier DAMP. This slew rate control allows the timing of changes in the odd-numbered data voltages OVDATA to differ from the timing of changes in the even-numbered data voltages EVDATA. Therefore, the voltages of the even-numbered data lines can change after the voltages of the odd-numbered data lines change. This allows for a reduction in the coupling voltage of the power supply voltage. For example, the coupling voltage could be the voltage value that couples a change in the first power supply voltage ELVDD to a change in the data voltage VDATA. Reducing the coupling voltage of the first power supply voltage ELVDD reduces the variation in ELVDD. During the frame period, reducing the variation in the first power supply voltage ELVDD improves the driving reliability of the light-emitting element EE. For example, it improves the emission reliability of the light-emitting element EE of the pixel PX. Therefore, the display quality of the display panel 100 can be improved.

[0146] Figure 13 This is a circuit diagram showing the pixel PXA included in the display panel 100.

[0147] Reference Figure 1 and Figure 13 The pixel PXA may include a first transistor T1A, a second transistor T2A, a storage capacitor CSTA, and a light-emitting element EEA.

[0148] The first transistor T1A may include a control electrode connected to a first node N1A, a first electrode receiving a first power voltage ELVDD, and a second electrode connected to a second node N2A. The first transistor T1A can generate a drive current based on the voltage of the first node N1A. The first transistor T1A may be referred to as a drive transistor.

[0149] The second transistor T2A may include a control electrode for receiving the write gate signal GW, a first electrode for receiving the data voltage VDATA, and a second electrode connected to the first node N1A. The second transistor T2A can apply the data voltage VDATA to the first node N1A in response to the write gate signal GW. The second transistor T2A may be referred to as a write gate transistor. When the write gate signal GW has an active level, the second transistor T2A can be turned on, and when the write gate signal GW has an inactive level, the second transistor T2A can be turned off.

[0150] The storage capacitor CSTA may include a first electrode that receives a first electrical voltage ELVDD and a second electrode connected to a first node N1A. The storage capacitor CSTA can store the voltage of the first node N1A.

[0151] The light-emitting element EEA may include a first electrode connected to the second node N2A and a second electrode receiving a second power voltage ELVSS. The light-emitting element EEA may emit light based on a driving current.

[0152] Figure 14 This is a circuit diagram showing the pixel PXB included in the display panel 100.

[0153] Reference Figure 1 and Figure 14 The pixel PXB may include a first transistor T1B, a second transistor T2B, a third transistor T3B, a fourth transistor T4B, a fifth transistor T5B, a sixth transistor T6B, a seventh transistor T7B, a storage capacitor CSTB, and a light-emitting element EEB.

[0154] The first transistor T1B may include a control electrode connected to a first node N1B, a first electrode connected to a second node N2B, and a second electrode connected to a third node N3B. The first transistor T1B can generate a drive current based on the voltage at the first node N1B. The first transistor T1B may be referred to as a drive transistor.

[0155] The second transistor T2B may include a control electrode for receiving the write gate signal GW, a first electrode for receiving the data voltage VDATA, and a second electrode connected to the second node N2B. The second transistor T2B can apply the data voltage VDATA to the second node N2B in response to the write gate signal GW. The second transistor T2B may be referred to as the write gate transistor. When the write gate signal GW has an active level, the second transistor T2B can be turned on, and when the write gate signal GW has an inactive level, the second transistor T2B can be turned off.

[0156] The third transistor T3B may include a control electrode that receives a compensation gate signal GC, a first electrode connected to a third node N3B, and a second electrode connected to a first node N1B. The third transistor T3B may connect the first node N1B and the third node N3B in response to the compensation gate signal GC. The third transistor T3B may operate as a diode in response to the compensation gate signal GC to be connected to the first transistor T1B. The third transistor T3B may be referred to as a compensation transistor.

[0157] The fourth transistor T4B may include a control electrode that receives an initialization gate signal GI, a first electrode that receives an initialization voltage VINIT, and a second electrode connected to the first node N1B. The fourth transistor T4B may apply the initialization voltage VINIT to the first node N1B in response to the initialization gate signal GI. The fourth transistor T4B may be referred to as the initialization transistor.

[0158] The fifth transistor T5B may include a control electrode for receiving a transmit signal EM, a first electrode for receiving a first power voltage ELVDD, and a second electrode connected to the second node N2B. The fifth transistor T5B may apply the first power voltage ELVDD to the second node N2B in response to the transmit signal EM. The fifth transistor T5B may be referred to as the first emitter transistor.

[0159] The sixth transistor T6B may include a control electrode for receiving the transmit signal EM, a first electrode connected to the third node N3B, and a second electrode connected to the fourth node N4B. The sixth transistor T6B may connect the third node N3B and the fourth node N4B in response to the transmit signal EM. The sixth transistor T6B may be referred to as the second emitter transistor.

[0160] The seventh transistor T7B may include a control electrode that receives a bias gate signal GB, a first electrode that receives a light-emitting element initialization voltage VAINT, and a second electrode connected to the fourth node N4B. The seventh transistor T7B may apply the light-emitting element initialization voltage VAINT to the fourth node N4B in response to the bias gate signal GB.

[0161] The storage capacitor CSTB may include a first electrode that receives a first electrical voltage ELVDD and a second electrode connected to a first node N1B. The storage capacitor CSTB can store the voltage of the first node N1B.

[0162] The light-emitting element EEB may include a first electrode connected to the fourth node N4B and a second electrode receiving a second power voltage ELVSS. The light-emitting element EEB can emit light based on a driving current.

[0163] Figure 15 This is a circuit diagram of the pixel PXC included in the display panel 100.

[0164] Reference Figure 1 and Figure 15 A pixel PXC may include a first transistor T1C, a second transistor T2C, a third transistor T3C, a fourth transistor T4C, a fifth transistor T5C, a sixth transistor T6C, a first capacitor C1C, and a light-emitting element EE. A pixel PXC may also include a second capacitor C2C.

[0165] The first transistor T1C may include a control electrode connected to a first node N1C, a first electrode connected to a second node N2C, and a second electrode connected to a third node N3C. The first transistor T1C can generate a drive current based on the voltage at the first node N1C. The first transistor T1C may also include a second control electrode connected to the third node N3C. The first transistor T1C may be referred to as a drive transistor. Although the first transistor T1C is implemented as a P-type transistor, it can also be implemented as an N-type transistor.

[0166] The second transistor T2C may include a control electrode for receiving a write gate signal GW, a first electrode for receiving a data voltage VDATA, and a second electrode connected to the first node N1C. The second transistor T2C may apply the data voltage VDATA to the first node N1C in response to the write gate signal GW. The second transistor T2C may be referred to as a write gate transistor.

[0167] The third transistor T3C may include a control electrode that receives a reset gate signal GR, a first electrode that receives a pixel reference voltage VREF, and a second electrode connected to the first node N1C. The third transistor T3C may apply the pixel reference voltage VREF to the first node N1C in response to the reset gate signal GR. The third transistor T3C may be referred to as an initialization transistor.

[0168] The fourth transistor T4C may include a control electrode for receiving a transmit signal EM, a first electrode for receiving a first power voltage ELVDD, and a second electrode connected to the second node N2C. The fourth transistor T4C may apply the first power voltage ELVDD to the second node N2C in response to the transmit signal EM. The fourth transistor T4C may be referred to as the first emitter transistor.

[0169] The fifth transistor T5C may include a control electrode for receiving another transmit signal EMB, a first electrode connected to the third node N3C, and a second electrode connected to the fourth node N4C. The fifth transistor T5C may connect the third node N3C and the fourth node N4C in response to the other transmit signal EMB. The fifth transistor T5C may be referred to as the second emitter transistor.

[0170] The sixth transistor T6C may include a control electrode that receives the initialization gate signal GI, a first electrode that receives the light-emitting element initialization voltage VAINT, and a second electrode connected to the fourth node N4C. The sixth transistor T6C can apply the light-emitting element initialization voltage VAINT to the fourth node N4C in response to the initialization gate signal GI. The sixth transistor T6C may be referred to as the light-emitting element initialization transistor.

[0171] The first capacitor C1C may include a first electrode connected to a first node N1C and a second electrode connected to a third node N3C. The second capacitor C2C may include a first electrode receiving a first electrical voltage ELVDD and a second electrode connected to a third node N3C.

[0172] The light-emitting element EE may include a first electrode connected to the fourth node N4C and a second electrode receiving a second power voltage ELVSS. The light-emitting element EE may emit light based on a driving current.

[0173] Figure 16 This is a block diagram illustrating an electronic device 1000 according to an embodiment. Figure 17 It is shown Figure 16 A diagram illustrating an example of an electronic device 1000.

[0174] Reference Figure 16 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 1. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices and other electronic devices.

[0175] Reference Figure 17 The electronic device 1000 can be a smartphone. The electronic device 1000 can also be a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0176] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be integrated with other components via address bus, control bus, and data bus. Processor 1010 can be integrated with expansion buses such as the Peripheral Component Interconnect (PCI) bus.

[0177] Processor 1010 can provide input image data IMG and input control signal CONT to Figure 1 The drive controller 200.

[0178] The memory device 1020 can store data for the operation of the electronic device 1000. The memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0179] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc. I / O device 1040 may include input devices such as keyboards, keypads, mice, touchpads, touchscreens, etc., and output devices such as printers, speakers, etc. Display device 1060 may be integrated into I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be connected to other components via a bus or other communication link.

[0180] Reference Figure 17 The electronic device 1000 of this invention is shown as a smartphone, but the invention is not limited thereto. The electronic device 1000 can be a television, monitor, laptop computer, or tablet computer. Additionally, the electronic device 1000 can be a car.

[0181] The display device 1 according to the embodiment can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0182] The embodiments of the inventive concept are not to be construed as limiting it. Although some embodiments of the inventive concept have been described, it will be readily apparent to those skilled in the art that many modifications may be made to the embodiments without substantially departing from the spirit and scope of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the phrase "means plus function" is intended to cover the structure performing the function as described herein, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the description of the inventive concept is not to be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims and the equivalents of the claims included therein.

Claims

1. A display apparatus comprising: a display panel comprising a plurality of pixels; a gate driver configured to output a gate signal to the plurality of pixels; a data driver configured to apply a data voltage to the display panel; and a drive controller configured to control the gate driver and the data driver, wherein the display panel displays based on the data voltage, wherein the display panel comprises a first row of pixels, a second row of pixels, a third row of pixels, and a fourth row of pixels, wherein the data voltage comprises a first data voltage and a second data voltage, wherein the first data voltage is applied to the first row of pixels and the third row of pixels, wherein the second data voltage is applied to the second row of pixels and the fourth row of pixels, wherein the gate signal comprises a first gate signal and a second gate signal, wherein the first gate signal is output to the first row of pixels and the second row of pixels, wherein the second gate signal is output to the third row of pixels and the fourth row of pixels, wherein the data voltage is applied to a corresponding row of pixels when the gate signal has an active level, wherein a period in which the display panel is driven comprises a first period, a second period, and a third period, wherein in the first period, the first gate signal has an active level, the second gate signal has an inactive level, the first data voltage has a first voltage level, and the second data voltage has a third voltage level, and wherein in the second period, the first gate signal has an inactive level, the second gate signal has an active level, the first data voltage changes to a second voltage level, and the second data voltage has the third voltage level. In the third period, the first gate signal has an inactive level, the second gate signal has an active level, the first data voltage has the second voltage level, and the second data voltage changes to a fourth voltage level.

2. The display device of claim 1, wherein, The first data voltage changes at a first transition rate when the first data voltage changes from the first voltage level to the second voltage level, and 3. The display device of claim 2, wherein, wherein the second data voltage changes at a second transition rate different from the first transition rate when the second data voltage changes from the third voltage level to the fourth voltage level. The first transition rate is greater than the second transition rate.

4. The display device of claim 3, wherein, The period in which the display panel is driven further comprises a fourth period, 5. The display device of claim 3, wherein, wherein in the fourth period, the first data voltage changes from the second voltage level to a fifth voltage level different from the second voltage level, wherein in the fourth period, the second data voltage changes from the fourth voltage level to a sixth voltage level different from the fourth voltage level, wherein the first data voltage changes at the second transition rate when the first data voltage changes from the second voltage level to the fifth voltage level, and wherein the second data voltage changes at the first transition rate when the second data voltage changes from the fourth voltage level to the sixth voltage level. wherein the second data voltage changes at the first slew rate when the second data voltage changes from the fourth voltage level to the sixth voltage level.

6. The display device of claim 1, wherein, The data driver includes: a data voltage generation block configured to generate the data voltage based on a data signal; and a buffer block configured to output the first data voltage and the second data voltage based on the data voltage and a delay signal, and wherein the buffer block controls an output delay of at least one of the first data voltage and the second data voltage.

7. The display device of claim 6, wherein, The buffer block outputs the second data voltage with the output delay.

8. The display device of claim 6, wherein, The buffer block includes a plurality of first amplifiers and a plurality of second amplifiers, wherein the first amplifiers output the first data voltage based on a first bias voltage, wherein the second amplifiers output the second data voltage based on a second bias voltage, and wherein the second bias voltage is lower than the first bias voltage when the output delay of the second data voltage is controlled.

9. The display device of claim 8, wherein, The display panel further includes a first data line, a second data line, a third data line, and a fourth data line, and wherein at least one of the first amplifiers is connected to the first data line and the third data line, and at least one of the second amplifiers is connected to the second data line and the fourth data line.

10. The display device of claim 1, wherein, The display panel includes a first data line that receives the first data voltage and a second data line that receives the second data voltage, wherein the first pixel row includes first pixels, the second pixel row includes second pixels, the third pixel row includes third pixels, and the fourth pixel row includes fourth pixels, wherein the first pixels and the third pixels are connected to the first data line, and wherein the second pixels and the fourth pixels are connected to the second data line.

11. The display device of claim 1, wherein, At least one of the plurality of pixels includes: a first transistor configured to generate a driving current based on a voltage of a first node; a second transistor configured to apply the data voltage to the first node in response to the gate signal; and a light emitting element configured to emit light based on the driving current.

12. A display device, the display device comprising: a display panel including a plurality of pixels; a gate driver configured to output a gate signal to the plurality of pixels; a data driver configured to apply a data voltage to the display panel; and a driving controller configured to control the gate driver and the data driver, wherein the display panel displays based on the data voltage, wherein the display panel includes a first pixel row, a second pixel row, a third pixel row, and a fourth pixel row, wherein the data voltage includes a first data voltage and a second data voltage, wherein the first data voltage is applied to the first pixel row and the third pixel row, wherein the second data voltage is applied to the second pixel row and the fourth pixel row, wherein the data driver includes: a data voltage generation block configured to generate the data voltage based on a data signal; and a buffer block configured to output the first data voltage and the second data voltage based on the data voltage and a delay signal, and wherein the buffer block controls an output delay of at least one of the first data voltage and the second data voltage. a buffer block configured to output the first data voltage and the second data voltage based on the data voltage and a delay signal, and wherein the buffer block controls an output delay of at least one of the first data voltage and the second data voltage.

13. The display device of claim 12, wherein, the gate signals include a first gate signal and a second gate signal, wherein the first gate signal is output to the first pixel row and the second pixel row, wherein the second gate signal is output to the third pixel row and the fourth pixel row, and wherein the second gate signal is output after the first gate signal is output.

14. The display device of claim 12, wherein, the buffer block includes a plurality of first amplifiers and a plurality of second amplifiers, wherein the first amplifiers output the first data voltage based on a first bias voltage, wherein the second amplifiers output the second data voltage based on a second bias voltage, and wherein the second bias voltage is lower than the first bias voltage when the output delay of the second data voltage is controlled.

15. An electronic device, the electronic device comprising: a processor configured to output input image data and input control signals; a display panel including a plurality of pixels; a gate driver configured to output gate signals to the plurality of pixels; a data driver configured to apply data voltages to the display panel; and a driving controller configured to control the gate driver and the data driver based on the input image data and the input control signals, wherein the display panel displays based on the data voltages, wherein the display panel includes a first pixel row, a second pixel row, a third pixel row, and a fourth pixel row, wherein the data voltages include a first data voltage and a second data voltage, wherein the first data voltage is applied to the first pixel row and the third pixel row, wherein the second data voltage is applied to the second pixel row and the fourth pixel row, wherein the gate signals include a first gate signal and a second gate signal, wherein the first gate signal is output to the first pixel row and the second pixel row, wherein the second gate signal is output to the third pixel row and the fourth pixel row, wherein the data voltages are applied to corresponding pixel rows when the gate signals have an active level, wherein a period in which the display panel is driven includes a first period, a second period, and a third period, wherein in the first period, the first gate signal has an active level, the second gate signal has an inactive level, the first data voltage has a first voltage level, and the second data voltage has a third voltage level, and wherein in the second period, the first gate signal has an inactive level, the second gate signal has an active level, the first data voltage becomes a second voltage level, and the second data voltage has the third voltage level. ​ 16. The electronic device of claim 15, wherein, In the third time period, the first gate signal has the inactive level, the second gate signal has the active level, the first data voltage has the second voltage level, and the second data voltage becomes a fourth voltage level.

17. The electronic device of claim 16, wherein, When the first data voltage changes from the first voltage level to the second voltage level, the first data voltage changes at a first transition rate, and wherein, when the second data voltage changes from the third voltage level to the fourth voltage level, the second data voltage changes at a second transition rate different from the first transition rate. 18.The electronic device of claim 17, wherein, The first transition rate is greater than the second transition rate.

19. The electronic device of claim 17, wherein, The time period in which the display panel is driven further includes a fourth time period, wherein, in the fourth time period, the first data voltage changes from the second voltage level to a fifth voltage level different from the second voltage level, wherein, in the fourth time period, the second data voltage changes from the fourth voltage level to a sixth voltage level different from the fourth voltage level, wherein, when the first data voltage changes from the second voltage level to the fifth voltage level, the first data voltage changes at the second transition rate, and wherein, when the second data voltage changes from the fourth voltage level to the sixth voltage level, the second data voltage changes at the first transition rate.

20. The electronic device of claim 15, wherein, The data driver includes: a data voltage generation block configured to generate the data voltage based on a data signal; and a buffer block configured to output the first data voltage and the second data voltage based on the data voltage and a delay signal, and wherein the buffer block controls an output delay of at least one of the first data voltage and the second data voltage.

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