Data driver and display device including same

Abstract

A data driver according to an embodiment and a display device including the same are disclosed. The data driver includes: an output circuit configured to alternately output a first image data voltage corresponding to first image data and a second image data voltage corresponding to second image data during one frame period; and a control circuit configured to provide the first image data as pixel data, and provide the second image data such that the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0120783, filed on September 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to data drives and display devices including such data drives. Background Technology

[0004] Various flat panel display devices, such as liquid crystal displays and electroluminescent displays, are known. Electroluminescent displays can display input images by emitting light themselves without backlight, using light-emitting elements disposed on each pixel. Based on the material of the light-emitting layer, the light-emitting elements of electroluminescent displays can be classified into organic light-emitting elements and inorganic light-emitting elements.

[0005] Recently, display devices using light-emitting diodes (LEDs) (inorganic light-emitting elements) as the light-emitting elements of pixels have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect organic materials from moisture, and they are more reliable and have a longer lifespan than organic light-emitting diodes (OLEDs). In addition, LEDs have fast illumination speed, excellent luminous efficiency, and shock resistance. Summary of the Invention

[0006] Multiple LEDs arranged in an LED display device have high luminous efficiency under high drive current. Therefore, it is necessary to drive the LEDs with high current for a short period of time using duty cycle driving. To perform duty cycle driving, a method is used to apply image data voltages sequentially during one frame period, followed by black data voltages sequentially.

[0007] In this driving method, a phenomenon of afterimage retrieval occurs, in which the pattern displayed on the previous screen is observed as an afterimage, and the afterimage retrieval phenomenon is caused by the hysteresis of the PMOS transistors in the pixels.

[0008] Therefore, when a PMOS transistor is used as a driving element, brightness deviation occurs because the driving characteristics of the driving element cannot be stabilized due to hysteresis. Therefore, measures to reduce the hysteresis of PMOS transistors are needed.

[0009] This disclosure is intended to address all of the aforementioned needs and issues.

[0010] This disclosure provides a data driver and a display device including the data driver.

[0011] It should be noted that the object of the present disclosure is not limited to the above-mentioned objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0012] A data driver according to an embodiment of the present disclosure can include an output circuit configured to alternately output a first image data voltage corresponding to first image data and a second image data voltage corresponding to second image data during a frame period, and a control circuit configured to provide the first image data as pixel data and provide the second image data such that the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage.

[0013] A display apparatus according to an embodiment of the present disclosure can include a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged, a data driver configured to output a first image data voltage and a second image data voltage to the plurality of data lines, a gate driver configured to output a gate signal to the plurality of gate lines, and a timing controller configured to control the data driver and the gate driver, wherein the data driver includes an output circuit configured to output the first image data voltage corresponding to first image data and the second image data voltage corresponding to second image data during a frame period, and a control circuit configured to provide the first image data as pixel data and provide the second image data such that the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage.

[0014] The present disclosure can reduce a hysteresis of a PMOS transistor by alternately outputting a first image data voltage and a second image data voltage obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage during a frame period.

[0015] The present disclosure can improve a ghost recovery phenomenon by reducing a hysteresis of a PMOS transistor.

[0016] The present disclosure can achieve low power driving by reducing power consumption through duty driving.

[0017] Effects of the present application are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the attached claims. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to one of ordinary skill in the art from the following detailed description of exemplary embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0021] Figure 3 is a diagram illustrating a configuration of a data driver according to an embodiment of the present disclosure;

[0022] Figure 4 is a diagram illustrating Figure 3 a configuration of a gamma voltage generation circuit illustrated in FIG. 1;

[0023] Figures 5A to 5C is a diagram for explaining a data voltage application principle according to a first embodiment;

[0024] Figures 6A to 6C is a diagram for explaining a data voltage application principle according to a second embodiment;

[0025] Figures 7A to 7C is a diagram for explaining a data voltage application principle according to a third embodiment;

[0026] Figures 8A to 8B is a diagram illustrating simulation results according to an embodiment. DETAILED DESCRIPTION

[0027] The advantages and features of the present application and a method for achieving them will become apparent from the preferred embodiments described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the embodiments described below and can be implemented in different forms, and the embodiments are provided only to completely disclose the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art, the present application being defined by the claims.

[0028] Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the accompanying drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals denote the same components. Also, in describing the present disclosure, when it is determined that a detailed description of the related known technology can unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0029] When "include", "have", "comprise", "composed of", and the like are used in the present application, other parts can be added unless "only" is used. In the case where a component is expressed in singular form, the plural form is included unless explicitly stated otherwise.

[0030] In explaining components, it is understood that an error range is included even if not described separately.

[0031] In the case of describing a positional relationship, for example, when the positional relationship of two parts is described as "on", "in the upper portion", "in the lower portion", "next to", and the like, unless "immediately" or "directly" is used, one or more other parts can also be located between the two parts.

[0032] Although various components are described using first, second, and the like, the components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be a second component within the technical spirit of the present disclosure.

[0033] Throughout the present disclosure, the same reference numerals can refer to substantially the same elements.

[0034] The following embodiments can be partially or entirely combined or combined with each other, and can be connected and operated in various technical ways. Embodiments can be executed independently of each other or in association with each other.

[0035] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] In the display device of the present disclosure, the pixel circuit and the gate driving circuit can include a plurality of transistors. The transistor can be implemented as an oxide thin film transistor (oxide TFT) including an oxide semiconductor, a low temperature polysilicon (LTPS) TFT including low temperature polysilicon, or the like.

[0037] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0038] The transistor is turned on in response to the gate-on voltage, and is turned off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage, and the gate-off voltage can be a gate low voltage. In the case of a p-channel transistor, the gate-on voltage can be a gate low voltage, and the gate-off voltage can be a gate high voltage.

[0039] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0040] Referring to Figure 1 A display device according to an embodiment of the disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. In addition, the display device includes a power supply 150.

[0041] The display panel 100 can be, but is not limited to, a panel having a rectangular structure with a length in an X-axis direction, a width in a Y-axis direction, and a thickness in a Z-axis direction. For example, the display panel 100 can be a heterogeneous panel, at least a portion of which is curved or oval.

[0042] A display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 can further include a power supply line commonly connected to the pixels. The power supply line can be commonly connected to the pixel circuit to supply a voltage required to drive the pixels 101 to the pixels 101.

[0043] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light emitting element. The light emitting element can include an OLED or an inorganic light emitting diode (LED). Each pixel circuit is connected to a data line, a gate line, and a power supply line. In the following description, the pixel can be interpreted as a sub-pixel.

[0044] The pixels can be arranged as true color pixels and pentile pixels. By driving two sub-pixels having different colors as one pixel 101 and using a preset pixel rendering algorithm, the pentile pixel can achieve a higher resolution than the true color pixel. The pixel rendering algorithm can compensate for an insufficient color representation in each pixel using the color of light emitted from an adjacent pixel.

[0045] The display area AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in a row direction (X-axis direction) in the pixel array of the display panel 100. Those pixels arranged in one pixel row share the gate line 103. The sub-pixels arranged in a column direction Y along the data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0046] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on a screen and a real object in the background is visible. The display panel 100 can be made of a flexible display panel.

[0047] The power supply 150 receives an input voltage applied from the host system 300 and outputs a voltage required to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 can include a direct current to direct current converter (DC-DC converter). The DC-DC converter can include a charge pump, a regulator, a step-down converter, a step-up converter, etc. The power supply 150 can output a constant voltage (or a direct current voltage) such as a gate-on voltage, a gate-off voltage, a pixel driving voltage, a cathode voltage, a reference voltage, an IC driving voltage of the display panel driving circuit through the DC-DC converter. The gate-on voltage and the gate-off voltage can be provided to the level shifter 140 and the gate driver 120. The voltages such as the pixel driving voltage, the cathode voltage, and the reference voltage can be provided to the pixels 101 through power supply lines commonly connected to the pixels 101.

[0048] The display panel driving circuit writes pixel data of an input image to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes the data driver 110 and the gate driver 120.

[0049] The display panel driving circuit can further include a touch sensor driver for driving a touch sensor. The touch sensor driver is not shown in Figure 1 The data driver 110 and the touch sensor driver can be integrated into one source driving IC.

[0050] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each gray scale through a voltage dividing circuit. The gamma compensation voltage for each gray scale is provided to a digital to analog converter (hereinafter, referred to as "DAC") disposed in each channel of the data driver 110.

[0051] The data driver 110 samples and latches the digital data received from the timing controller 130 and then inputs the digital data to the DAC. Here, the digital data includes pixel data of an input image. In addition, the digital data can include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data.

[0052] The data driver 110 can alternately output a first image data voltage and a second image data voltage obtained by inverting a phase of the first image data voltage with respect to a reference voltage during each frame period.

[0053] The gate driver 120 can be formed on the display panel 100 together with the circuit elements and the wirings of the display area AA. The gate driver 120 can be disposed in at least one of the left non-display area NA and the right non-display area NA outside the display area AA in the display panel 100, or at least a part of the gate driver 120 can be disposed inside the display area AA.

[0054] The gate driver 120 outputs pulses of a gate signal to the gate lines 103 in sequence under the control of the timing controller 130. The gate driver 120 can sequentially provide the gate signal to the gate lines 103 by shifting the pulses of the gate signal using a shift register. The gate driver 120 can include a plurality of shift registers when a plurality of gate signals are applied to the respective pixels. The gate signal can include a scan signal and an emission signal (or EM signal) input to the pixel circuit through a plurality of gate lines.

[0055] The timing controller 130 receives digital video data of an input image and a timing signal synchronized with the data from the host system 300. The timing signal can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of 1 horizontal period (1H).

[0056] The timing controller 130 can control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE received from the host system 300. The timing controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0057] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gate timing control signal received from the timing controller 130 into a swing width between a gate-on voltage and a gate-off voltage, and provide it to the gate driver 120.

[0058] The host system 300 can include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle-mounted system, a mobile terminal, and a wearable terminal. The host system 300 can scale an image signal from a video source according to the resolution of the display panel 100, and can transmit it to the timing controller 130 together with the timing signal.

[0059] Figure 2 FIG. 1 is a diagram illustrating a pixel circuit according to an embodiment of the disclosure.

[0060] Referring to Figure 2 The pixel circuit according to the embodiment of the disclosure includes a light emitting element LD, a driving element DT that supplies a current to the light emitting element LD, a plurality of switching elements T1 and T2 that switch a current path connected to the driving element DT, and a capacitor Cst. The driving element DT and the switching elements T1 and T2 can be implemented as p-channel transistors, but are not limited thereto.

[0061] The light emitting element LD can include an anode, a cathode, and a light emitting layer. The cathode of the light emitting element LD can be connected to a first power line PL1 to which a pixel driving voltage EVDD is applied. The anode of the light emitting element LD can be connected to the driving element DT. The light emitting element LD can be a light emitting element such as an OLED, a mini-LED, or a micro-LED, but is not limited thereto. In the case of a mini-LED or a micro-LED, the light emitting element LD can have a vertical structure in which electrodes are arranged at upper and lower portions of a semiconductor chip in which the light emitting element LD is integrated, but is not limited thereto. The semiconductor chip in which the light emitting element LD is integrated can be implemented in a lateral structure or a flip chip structure.

[0062] The driving element DT can be turned on by a voltage of the first node n1 to drive the light emitting element LD. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to a second power line PL2 to which a pixel base voltage EVSS is applied.

[0063] The first switching element T1 supplies a data voltage Vdata to the gate electrode of the driving element DT in response to a scan signal SCAN. The first switching element T1 includes a gate electrode to which the scan signal SCAN is applied, a first electrode connected to a data line DL to which the data voltage is applied, and a second electrode connected to the first node n1.

[0064] The second switching element T2 applies a reference voltage Vref to the second node n2 in response to a sensing signal SENSE. The second switching element T2 includes a gate electrode to which the sensing signal SENSE is applied, a first electrode connected to the second node n2, and a second electrode connected to a reference voltage line RL to which the reference voltage Vref is applied. In addition, the second switching element T2 can be implemented as a double transistor including two transistors connected in series, but is not limited thereto.

[0065] A capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst includes a first electrode connected to the first node n1 and a second electrode connected to the second node n2.

[0066] The pixel circuit described herein is merely an example and is not necessarily limited thereto.

[0067] Figure 3 FIG. 1 is a diagram illustrating a configuration of a data driver according to an embodiment of the disclosure, Figure 4 is a diagram illustrating Figure 3 a configuration of the gamma voltage generation circuit shown in FIG. 1.

[0068] Referring to Figure 3 The data driver according to an embodiment of the disclosure can include a control circuit 110a, an output circuit 110b, and a gamma voltage generation circuit 110c.

[0069] The control circuit 110a can receive pixel data and data timing control signals from a timing controller, transfer the pixel data to the output circuit 110b based on the received data timing control signals, and control such that a first image data voltage corresponding to the pixel data and a second image data voltage obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage are output to a corresponding data line DL through output channels OUT(1), OUT(2), …, OUT(N-1), OUT(N).

[0070] The control circuit 110a can control such that the first image data voltage is output during a first period within a frame period and the second image data voltage is output during a second period.

[0071] The control circuit 110a can adjust a high-potential gamma voltage and a low-potential gamma voltage to control a data voltage range in the first period and the second period within a frame period.

[0072] The output circuit 110b can include a shift register SR, a latch LAT, a digital-to-analog converter DAC, and an amplifier AMP. The output circuit 110b can further include a level shifter LS.

[0073] The shift register SR can shift a clock input from the timing controller to generate a sampling clock, and can output the generated sampling clock to the latch LAT in sequence.

[0074] The latch LAT can sample and store pixel data of an input image according to a timing of the sampling clock input in sequence, and can output the stored pixel data simultaneously.

[0075] The level shifter LS can convert the voltage level of the stored pixel data. The level shifter LS can convert the voltage level of the pixel data to a voltage level that can drive the digital-to-analog converter DAC.

[0076] The digital-to-analog converter DAC can convert the pixel data output from the latch LAT or the pixel data whose voltage level has been converted by the level shifter LS into a data voltage in an analog form.

[0077] The amplifier AMP can amplify the voltage level of the data voltage in an analog form, and can output the data voltage having the amplified voltage level to a corresponding data line through the output channels OUT(1), OUT(2), …, OUT(N-1), OUT(N) connected to the output terminals.

[0078] The gamma voltage generation circuit 110c can generate gamma voltages and supply them to the digital-to-analog converter DAC. As shown, the gamma voltage generation circuit 110c can include a voltage adjustment circuit 110c-1 and a voltage generation circuit 110c-2. Figure 4

[0079] The voltage adjustment circuit 110c-1 can adjust the high-potential gamma voltage REF_H and the low-potential gamma voltage REF_L during the first period and the second period, respectively, within a frame period under the control of the control circuit 110a. The voltage adjustment circuit 110c-1 can supply the adjusted high-potential gamma voltage REF_H and the low-potential gamma voltage REF_L to the voltage generation circuit 110c-2.

[0080] The voltage generation circuit 110c-2 can generate gamma voltages for each gray scale based on the adjusted high-potential gamma voltage REF_H and the low-potential gamma voltage REF_L, and supply them to the output circuit 110b.

[0081] Figures 5A to 5C is a diagram for explaining a data voltage application principle according to a first embodiment.

[0082] Referring to Figure 2 and Figure 5A , the data driver according to the first embodiment of the disclosure can apply a first image data voltage Vdata1 during a first period P1 in a frame period, and apply a second image data voltage Vdata2 obtained by inverting a phase of the first image data voltage Vdata1 with respect to a reference voltage Vref during a second period P2.

[0083] As shown in Figure 2 ​As illustrated, when the driving element is implemented as a p-channel transistor, whether or not light emission occurs can be determined by a gate-source voltage Vgs of the driving element. That is, when a first data voltage Vdata1 applied to a gate electrode of the driving element is lower than a reference voltage Vref applied to a source electrode of the driving element, a condition Vgs < 0 is satisfied, and light emission occurs; when a second data voltage Vdata2 applied to the gate electrode of the driving element is higher than the reference voltage Vref applied to the source electrode of the driving element, a condition Vgs > 0 is satisfied, and light emission does not occur. Thus, the light emitting element emits light when the data voltage is lower than the reference voltage Vref, and the light emitting element does not emit light when the data voltage is higher than the reference voltage Vref.

[0084] The first image data voltage Vdata1 can be set to a negative direction, and the second image data voltage Vdata2 can be set to a positive direction. That is, digital data corresponding to the first image data voltage Vdata1 can be set to a negative direction, and digital data corresponding to the second image data voltage Vdata2 can be set to a positive direction. Here, the positive direction can indicate a voltage region higher than the reference voltage, and the negative direction can indicate a voltage region lower than the reference voltage. For example, the first image data voltage Vdata1 can be an image data voltage of a black gray scale, and the second image data voltage Vdata2 can be an image data voltage of a white gray scale.

[0085] In this case, although an example in which the first image data voltage Vdata1 is set to a negative direction and the second image data voltage Vdata2 is set to a positive direction in a pixel circuit in which the driving element is implemented as a p-channel transistor is described, it is not necessarily limited thereto. For example, in a pixel circuit in which the driving element is implemented as an n-channel transistor, the first image data voltage Vdata1 can be set to a positive direction, and the second image data voltage Vdata2 can be set to a negative direction.

[0086] The first image data voltage and the second image data voltage can be voltages symmetrical with respect to the reference voltage Vref.

[0087] The data driver can output the first image data voltage and the second image data voltage based on a gamma voltage of each gray scale generated in advance. In this case, the gamma voltage of each gray scale can be generated based on a high-potential gamma voltage and a low-potential gamma voltage, and the high-potential gamma voltage and the low-potential gamma voltage can be differently set in a first period in which the first image data voltage is applied and a second period in which the second image data voltage is applied. That is, in the first period in which the first image data voltage is applied, the voltages can be set to a first high-potential gamma voltage and a first low-potential gamma voltage, and in the second period in which the second image data voltage is applied, the voltages can be set to a second high-potential gamma voltage and a second low-potential gamma voltage.

[0088] For example, when the reference voltage Vref is 6V, the first high-potential gamma voltage can be 5V, the first low-potential gamma voltage can be 0V, the second high-potential gamma voltage can be 12V, and the second low-potential gamma voltage can be 7V.

[0089] In this case, the first high-potential gamma voltage and the first low-potential gamma voltage can be set to voltage values less than or equal to the reference voltage Vref, and the second high-potential gamma voltage and the second low-potential gamma voltage can be set to voltage values greater than or equal to the reference voltage Vref.

[0090] The data voltage range DR1 output in the first period P1 and the data voltage range DR2 output in the second period P2 can be identical to each other with respect to the reference voltage Vref.

[0091] Reference Figure 2 and Figure 5B According to the first embodiment of the present disclosure, the data driver can apply a first image data voltage Vdata1 during a first period P1 in a frame period, and apply a second image data voltage Vdata2 during a second period P2, the second image data voltage Vdata2 being obtained by inverting a phase of the first image data voltage Vdata1 with respect to a reference voltage Vref at a voltage higher than the reference voltage Vref by a predetermined offset.

[0092] For example, when the reference voltage Vref is 6V, the first high-potential gamma voltage can be 6V, the first low-potential gamma voltage can be 0V, the second high-potential gamma voltage can be 18V, and the second low-potential gamma voltage can be 6V.

[0093] The data voltage range DR1 output in the first period P1 and the data voltage range DR2 output in the second period P2 can be different from each other with respect to the reference voltage Vref. For example, the data voltage range DR2 in the second period P2 can be formed to be larger than the data voltage range DR1 in the first period P1 by a predetermined offset.

[0094] Reference Figure 5C In the first period P1, phases of first image data voltages D1, D2, and D3 in a negative direction with respect to the reference voltage Vref can be inverted to second image data voltages D1', D2', and D3' in a positive direction in the second period P2.

[0095] Specifically, in the first period P1, when the first image data of the black gray scale is 1023 and the first image data voltage D1 is 5V, and the first image data of the white gray scale is 0 and the first image data voltage D3 is 0V, if the phase is inverted with respect to the reference voltage Vref of 6V, in the second period P2, the second image data of the white gray scale becomes 0 and the second image data voltage D1' becomes 7V, and the second image data of the black gray scale becomes 1023 and the second image data voltage D3' becomes 12V.

[0096] In the first embodiment, the first image data voltages D1, D2, and D3 can vary in the range of 0V to 5V, and the second image data voltages D1', D2', and D3' can vary in the range of 7V to 12V.

[0097] Figures 6A to 6C is a diagram for explaining the data voltage application principle according to the second embodiment.

[0098] Referring to Figure 2 and Figure 6A , the data driver according to the second embodiment of the disclosure can apply a first image data voltage Vdata1 during a first period P1 in a frame period, and apply a second image data voltage Vdata2 during a second period P2, the second image data voltage Vdata2 being obtained by inverting the phase of the first image data voltage Vdata1 with respect to a first reference voltage Vref1 at a second reference voltage Vref2.

[0099] In this case, the reference voltage Vref can have different voltage values in the first period P1 and the second period P2. For example, a first reference voltage Vref1 can be applied in the first period P1, and a second reference voltage Vref2 set to be lower than the first reference voltage Vref1 by a predetermined voltage value can be applied in the second period P2.

[0100] In the first period P1 in which the first image data voltage Vdata1 is applied and the second period P2 in which the second image data voltage Vdata2 is applied, the high-potential gamma voltage and the low-potential gamma voltage can be set to the same value.

[0101] For example, when the high-potential gamma voltage is 15V and the low-potential gamma voltage is 10V, the first reference voltage Vref1 in the first period can be set to 15V, and the second reference voltage Vref2 in the second period can be set to 10V.

[0102] The data voltage range DR1 outputted in the first period P1 based on the first reference voltage Vref1 and the data voltage range DR2 outputted in the second period P2 based on the second reference voltage Vref2 can be the same.

[0103] Referring to Figure 2 and Figure 6B According to a second embodiment of the present disclosure, a data driver can apply a first image data voltage Vdata1 during a first period P1 in a frame period and a second image data voltage Vdata2 obtained by inverting a phase of the first image data voltage Vdata1 with respect to a first reference voltage Vref1 at a voltage higher than a second reference voltage Vref2 by a predetermined offset during a second period P2.

[0104] In this case, the reference voltage Vref can have different voltage values in the first period P1 and the second period P2.

[0105] For example, in the first period P1 in which the first reference voltage Vref1 is 15V, the first high potential gamma voltage can be 15V and the first low potential gamma voltage can be 10V, and in the second period P2 in which the second reference voltage Vref2 is 10V, the second high potential gamma voltage can be 20V and the second low potential gamma voltage can be 10V.

[0106] The data voltage range DR1 outputted in the first period P1 based on the first reference voltage Vref1 and the data voltage range DR2 outputted in the second period P2 based on the second reference voltage Vref2 can be different from each other. That is, the data voltage range DR2 in the second period P2 can be larger than the data voltage range DR1 in the first period P1 by a predetermined offset.

[0107] Referring to Figure 6C The first image data voltages D1, D2, and D3 outputted in the first period P1 in the negative direction with respect to the reference voltage Vref can be phase-inverted to the second image data voltages D1', D2', and D3' in the positive direction in the second period P2.

[0108] Specifically, in the first period P1, when the reference voltage Vref is 15V, the first image data of the black gray scale is 1023, the first image data voltage D1 is 15V, the first image data of the white gray scale is 0, and the first image data voltage D3 is 10V, if the reference voltage Vref is changed from 15V to 10V and the phase is inverted with respect to the changed 10V reference voltage, in the second period P2, the second image data of the white gray scale becomes 0 and the second image data voltage D1' becomes 10V, the second image data of the black gray scale becomes 1023 and the second image data voltage D3' becomes 15V.

[0109] In the second embodiment, the first image data voltages D1, D2, and D3 can vary in the range of 10V to 15V, and the second image data voltages D1', D2', and D3' can vary in the range of 10V to 15V.

[0110] Figures 7A to 7C is a diagram for explaining a data voltage application principle according to a third embodiment.

[0111] Referring to Figure 2 and Figure 7A , a data driver according to a third embodiment of the disclosure can apply a first image data voltage Vdata1 during a first period P1 in a frame period, and can apply a second image data voltage Vdata2 during a second period P2, the second image data voltage Vdata2 being obtained by inverting a phase of the first image data voltage Vdata1 with respect to a reference voltage Vref.

[0112] In the first period P1 in which the first image data voltage Vdata1 is applied and the second period P2 in which the second image data voltage Vdata2 is applied, a high-potential gamma voltage and a low-potential gamma voltage can be set to the same value.

[0113] The high-potential gamma voltage is higher than the reference voltage Vref, and the low-potential gamma voltage is lower than the reference voltage Vref. For example, when the reference voltage Vref is 8V, the high-potential gamma voltage can be 13V, and the low-potential gamma voltage can be 3V.

[0114] A data voltage range DR1 output in the first period and a data voltage range DR2 output in the second period can be the same as each other with respect to the reference voltage Vref.

[0115] Referring to Figure 2 and Figure 7BAccording to the third embodiment of the present disclosure, the data driver can apply a first image data voltage Vdata1 during a first period P1 in a frame period, and apply a second image data voltage Vdata2 during a second period P2, the second image data voltage Vdata2 being obtained by inverting a phase of the first image data voltage Vdata1 with respect to a reference voltage Vref at a voltage higher than the reference voltage Vref by a predetermined offset.

[0116] In the first period P1 in which the first image data voltage Vdata1 is applied and the second period P2 in which the second image data voltage Vdata2 is applied, a high-potential gamma voltage and a low-potential gamma voltage can be set to the same value.

[0117] For example, when the reference voltage Vref is 8V, the high-potential gamma voltage can be 13V and the low-potential gamma voltage can be 3V.

[0118] The data voltage range DR1 output in the first period and the data voltage range DR2 output in the second period can be the same as each other with respect to the reference voltage Vref.

[0119] Unlike the data voltage ranges in the first and second embodiments, the data voltage range in the third embodiment can be a range including all data voltages output in the first and second periods.

[0120] Reference Figure 7C In the first period P1, the first image data voltages D1, D2, and D3 in the negative direction with respect to the reference voltage Vref output in the first period P1 can be phase-inverted to the second image data voltages D1', D2', and D3' in the positive direction in the second period P2.

[0121] Specifically, in the first period P1, when the first image data of the black gray scale is 1023 and the first image data voltage D1 is 8V, and the first image data of the white gray scale is 0 and the first image data voltage D3 is 3V, if the phase is inverted with respect to the reference voltage Vref of 8V, in the second period P2, the second image data of the white gray scale becomes 0 and the second image data voltage D1' becomes 8V, the second image data of the black gray scale becomes 1023 and the second image data voltage D3' becomes 13V.

[0122] In the third embodiment, the first image data voltages D1, D2, and D3 can vary in a range of 3V to 13V, and the second image data voltages D1', D2', and D3' can vary in a range of 3V to 13V.

[0123] Figures 8A to 8B is a graph showing simulation results according to an embodiment.

[0124] Reference Figure 8A When a screen in which a black gray scale data pattern and a white gray scale data pattern are repeated is converted into a gray scale pattern, an afterimage recovery phenomenon is evaluated.

[0125] When the driving method according to the embodiment is used, as a result of evaluation of the afterimage recovery phenomenon, it is found that there is no visible afterimage from the previous screen in the gray scale pattern.

[0126] Reference Figure 8B When the comparative example and the embodiment are applied, the comparative example includes a normal driving method (Normal) and a driving method in which image data and black data are alternately applied (Black), and the embodiment includes a driving method in which a first image data voltage and a second image data voltage obtained by inverting the phase of the first image data voltage with respect to a reference voltage are applied (Reverse 1) and a driving method in which a first image data voltage and a second image data voltage obtained by inverting the phase of the first image data voltage with respect to a reference voltage at a voltage higher than the reference voltage by a certain offset are applied (Reverse 2), a difference in luminance deviation is shown.

[0127] When the driving method according to the present embodiment is applied, it can be seen that the luminance deviation is improved.

[0128] Although the embodiments of the present disclosure have been described in greater detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided only for illustrative purposes, and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A data driver comprising: an output circuit configured to alternately output a first image data voltage corresponding to first image data and a second image data voltage corresponding to second image data during a frame period; and a control circuit configured to supply the first image data as pixel data, and supply the second image data so that the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage.

2. The data driver according to claim 1, further comprising: a gamma voltage generation circuit configured to generate a gamma voltage of each gradation based on a high-potential gamma voltage and a low-potential gamma voltage, and supply the generated gamma voltage of each gradation to the output circuit, wherein the output circuit is configured to convert the first image data and the second image data into the first image data voltage and the second image data voltage based on the gamma voltage of each gradation.

3. The data driver of claim 2, wherein, the frame period includes a first period and a second period, wherein the output circuit is configured to: output the first image data voltage during the first period, output the second image data voltage during the second period, wherein the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to a reference voltage.

4. The data driver of claim 3, wherein, the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to the reference voltage at a voltage higher than the reference voltage by a predetermined offset.

5. The data driver of claim 3, wherein, the control circuit is configured to: set the high-potential gamma voltage and the low-potential gamma voltage to a first high-potential gamma voltage and a first low-potential gamma voltage during the first period, set the high-potential gamma voltage and the low-potential gamma voltage to a second high-potential gamma voltage and a second low-potential gamma voltage different from the first high-potential gamma voltage and the first low-potential gamma voltage during the second period.

6. The data driver of claim 5, wherein, the first high-potential gamma voltage and the first low-potential gamma voltage are set to be lower than or equal to the reference voltage, the second high-potential gamma voltage and the second low-potential gamma voltage are set to be higher than or equal to the reference voltage.

7. The data driver of claim 3, wherein, the reference voltage is applied as a first reference voltage during the first period, and the reference voltage is applied as a second reference voltage different from the first reference voltage during the second period.

8. The data driver of claim 3, wherein, the control circuit is configured to set the high-potential gamma voltage and the low-potential gamma voltage identically during the first period and the second period, wherein the high-potential gamma voltage is set to be higher than or equal to the reference voltage, the low-potential gamma voltage is set to be lower than or equal to the reference voltage.

9. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a first image data voltage and a second image data voltage to the plurality of data lines; a gate driver configured to output a gate signal to the plurality of gate lines; and a timing controller configured to control the data driver and the gate driver, wherein the data driver includes: an output circuit configured to output a first image data voltage corresponding to first image data and a second image data voltage corresponding to second image data during a frame period; and a control circuit configured to provide the first image data as pixel data, and provide the second image data such that the second image data is obtained by inverting a phase of the first image data voltage with respect to a predetermined voltage.

10. The display device of claim 9, wherein, the data driver further includes: a gamma voltage generation circuit configured to generate a gamma voltage of each gray scale based on a high-potential gamma voltage and a low-potential gamma voltage, and provide the generated gamma voltage of each gray scale to the output circuit, wherein the output circuit is configured to convert the first image data and the second image data into the first image data voltage and the second image data voltage based on the gamma voltage of each gray scale.

11. The display device of claim 10, wherein, the frame period includes a first period and a second period, wherein the output circuit is configured to: output the first image data voltage during the first period, output the second image data voltage during the second period, wherein the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to a reference voltage.

12. The display device of claim 11, wherein, the second image data voltage is obtained by inverting a phase of the first image data voltage with respect to the reference voltage at a voltage higher than the reference voltage by a predetermined offset.

13. The display device of claim 11, wherein, the control circuit is configured to: set the high-potential gamma voltage and the low-potential gamma voltage to a first high-potential gamma voltage and a first low-potential gamma voltage during the first period, set the high-potential gamma voltage and the low-potential gamma voltage to a second high-potential gamma voltage and a second low-potential gamma voltage different from the first high-potential gamma voltage and the first low-potential gamma voltage during the second period.

14. The display device of claim 13, wherein, the first high-potential gamma voltage and the first low-potential gamma voltage are set to be lower than or equal to the reference voltage, the second high-potential gamma voltage and the second low-potential gamma voltage are set to be higher than or equal to the reference voltage.

15. The display device of claim 11, wherein, the reference voltage is applied as a first reference voltage during the first period, and the reference voltage is applied as a second reference voltage different from the first reference voltage during the second period.

16. The display device of claim 11, wherein, the control circuit is configured to set the high-potential gamma voltage and the low-potential gamma voltage identically during the first period and the second period, wherein the high-potential gamma voltage is set to be higher than or equal to the reference voltage, the low-potential gamma voltage is set to be lower than or equal to the reference voltage.

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