Pixel circuit, display panel and display device

Abstract

The invention discloses a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving module, a compensation module, a data writing module, a light emitting control module, a first initialization module, a second initialization module, a node control module, a coupling module and a light emitting module. The first initialization module is used for responding to conduction of a first scanning signal in an initialization stage and a threshold compensation stage so as to transmit an initialization voltage to a first node; the first end of the second initialization module is connected with initialization voltage, and the second initialization module is used for responding to conduction of a second scanning signal in an initialization stage, a threshold compensation stage and a data writing stage so as to transmit the initialization voltage to the first end of the light emitting module; the data write-in module is used for responding to the fourth scanning signal to be switched on in the data write-in stage so as to transmit the data voltage to the first node. The flicker phenomenon of the display panel can be relieved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, a display panel, and a display device. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for display effects.

[0003] Existing display panels exhibit flickering, especially in wideband applications (such as variable refresh rate), where the flickering is more pronounced and severely impacts the display performance. Summary of the Invention

[0004] The present invention provides a pixel circuit, a display panel, and a display device to alleviate the flickering phenomenon of the display panel and improve the display effect of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a driving module, a compensation module, a data writing module, a light emission control module, a first initialization module, a second initialization module, a node control module, a coupling module, and a light emission module; a first terminal of the first initialization module is connected to an initialization voltage, and a second terminal of the first initialization module, a first terminal of the coupling module, and a first terminal of the data writing module are connected to a first child node. The first initialization module is used to conduct in response to a first scan signal during the initialization phase and the threshold compensation phase, so as to transmit the initialization voltage to the first child node; a first terminal of the second initialization module is connected to the initialization voltage, and a second terminal of the second initialization module is connected to a first terminal of the light emission module. The second initialization module is used to conduct in response to a second scan signal during the initialization phase, the threshold compensation phase, and the data writing phase, so as to transmit the initialization voltage to the first terminal of the light emission module; a first terminal of the compensation module is connected to a first terminal of the driving module, and the compensation module... The second terminal is connected to the control terminal of the drive module. The compensation module is used to respond to the third scan signal during the threshold compensation phase to perform threshold compensation on the drive module. The second terminal of the data writing module is connected to the data voltage. The data writing module is used to respond to the fourth scan signal during the data writing phase to transmit the data voltage to the first child node. The coupling module is used to couple the switching voltage to the control terminal of the drive module. The light emission control module, the drive module, and the light emission module are connected between the first power supply and the second power supply. The light emission control module is used to respond to the light emission control signal during the light emission phase to control the light emission module to emit light according to the drive current output by the drive module. The first terminal of the node control module is connected to the first power supply. The second terminal of the node control module, the second terminal of the coupling module, and the control terminal of the drive module are connected to the second child node. The node control module is used to respond to the fifth scan signal during the initialization phase to transmit the first power supply voltage on the first power supply to the second child node.

[0006] Secondly, embodiments of the present invention provide a display panel, including pixel circuits provided in any embodiment of the present invention arranged in an array; it also includes a plurality of gate driving circuits, including a first gate driving circuit, a second gate driving circuit, and a third gate driving circuit; the first gate driving circuit is connected to the control terminal of a first initialization module, a compensation module, and a node control module of the pixel circuit, and is used to provide a first scan signal, a third scan signal, and a fifth scan signal to the pixel circuit; the second gate driving circuit is connected to the control terminal of a second initialization module and a light emission control module of the pixel circuit, and is used to provide a second scan signal and a light emission control signal to the pixel circuit; the third gate driving circuit is connected to the control terminal of a data writing module of the pixel circuit, and is used to provide a fourth scan signal to the pixel circuit.

[0007] Thirdly, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention, and further including a first input signal line, a second input signal line, a third input signal line, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, and a tenth clock signal line; the first input signal line is used to provide a first input signal to a first-stage first shift register; a first scan signal output from the output terminal of the first output module of the i-th stage first shift register serves as the first input signal of the (i+1)-th stage first shift register; i is an integer greater than or equal to 1; the second input signal line is used to provide a second input signal to a first-stage second shift register; a second scan signal output from the output terminal of the fourth output module of the i-th stage second shift register serves as the second input signal of the (i+1)-th stage second shift register; the third input signal line is used to provide a third input signal to a first-stage third shift register; a fourth scan signal output from the output terminal of the fifth output module of the i-th stage third shift register serves as the third input signal of the (i+1)-th stage third shift register; the first clock signal line... The following clock signal lines are used to provide a first clock signal for the odd-level first shift register and a second clock signal for the even-level first shift register; the second clock signal line is used to provide a second clock signal for the odd-level first shift register and a first clock signal for the even-level first shift register; the third clock signal line is used to provide a third clock signal for the odd-level first shift register; the fourth clock signal line is used to provide a fourth clock signal for the odd-level first shift register; the fifth clock signal line is used to provide a third clock signal for the even-level first shift register; and the sixth clock signal line is used to provide a... The fourth clock signal; the seventh clock signal line is used to provide the fifth clock signal for the odd-level second shift register and the sixth clock signal for the even-level second shift register; the eighth clock signal line is used to provide the sixth clock signal for the odd-level second shift register and the fifth clock signal for the even-level second shift register; the ninth clock signal line is used to provide the seventh clock signal for the odd-level third shift register and the eighth clock signal for the even-level third shift register; the tenth clock signal line is used to provide the eighth clock signal for the odd-level third shift register and the seventh clock signal for the even-level third shift register.

[0008] The pixel circuit provided in this embodiment of the invention achieves independent control of the light emission control signal and the timing-variable scan signal by setting up a functionally independent first initialization module, a second initialization module, a node control module, a data writing module, and a light emission control module, and configuring independent scan control signals for each module. In wideband drive applications, when the refresh frequency of the panel changes, the timing and period of the fourth scan signal used for data refresh can be independently adjusted to adapt to the new frame rate. At the same time, it can ensure that the effective pulse width (i.e., light emission time) of the light emission control signal remains constant. This means that, whether in a high-frequency data refresh frame or a low-frequency data hold (non-refresh) frame, the actual light emission time of each pixel is the same in each display frame cycle. Since the light emission brightness is directly related to the light emission time, the stable light emission time ensures the consistency of brightness between frames, thereby alleviating the display flickering phenomenon caused by fluctuations in light emission time.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2a This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2b This is a simulation diagram provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a first gate driving circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a first shift register provided in an embodiment of the present invention; Figure 10 This is a timing diagram of the drive of a first shift register provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a second gate driving circuit provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of a second shift register provided in an embodiment of the present invention; Figure 13 This is a timing diagram of the drive of a second shift register provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a third gate driving circuit provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of the structure of a third shift register provided in an embodiment of the present invention; Figure 16 This is a driving timing diagram of a third shift register provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of the signals on each clock signal line and each input signal line provided in an embodiment of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0014] As mentioned in the background section, existing display panels are prone to flickering during display. Through careful research, the inventors discovered that the cause of this problem lies in the fact that the initialization and light-emitting phases of the pixel circuit are typically controlled by the same set of gate drive circuits, or that the light-emitting control signal and the initialization signal are often frequency-coupled. That is, the timing relationship between the light-emitting control signal and the initialization signal may change under different drive frequencies, leading to inconsistencies in the light-emitting times of data refresh frames and non-refresh frames in wideband drive applications (such as variable refresh rate). This inconsistency causes brightness fluctuations in the display panel, resulting in flickering and affecting the user experience.

[0015] In view of the inventors' above-mentioned research findings, and in order to solve the problems of the prior art, embodiments of the present invention provide a pixel circuit, a display panel, and a display device. The pixel circuit provided by the embodiments of the present invention will be described first below.

[0016] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 1 As shown, the pixel circuit includes: a driving module 110, a compensation module 120, a data writing module 130, a light emission control module 140, a first initialization module 150, a second initialization module 160, a node control module 170, a coupling module 180, and a light emission module 190.

[0017] The first terminal of the first initialization module 150 is connected to the initialization voltage Vini. The second terminal of the first initialization module 150, the first terminal of the coupling module 180, and the first terminal of the data writing module 130 are connected to the first child node N1. The first initialization module 150 is used to respond to the first scan signal S1 to turn on during the initialization phase and the threshold compensation phase, so as to transmit the initialization voltage Vini to the first child node N1.

[0018] The first terminal of the second initialization module 160 is connected to the initialization voltage Vini, and the second terminal of the second initialization module 160 is connected to the first terminal of the light-emitting module 190. The second initialization module 160 is used to respond to the second scan signal S2 to conduct during the initialization stage, the threshold compensation stage and the data writing stage, so as to transmit the initialization voltage Vini to the first terminal of the light-emitting module 190.

[0019] The first end of the compensation module 120 is connected to the first end A1 of the drive module 110, and the second end of the compensation module 120 is connected to the control end G1 of the drive module 110. The compensation module 120 is used to respond to the third scan signal S3 during the threshold compensation stage to perform threshold compensation on the drive module 110.

[0020] The second terminal of the data writing module 130 is connected to the data voltage Vdata. The data writing module 130 is used to respond to the fourth scan signal S4 during the data writing stage to transmit the data voltage Vdata to the first child node N1. The coupling module 180 is used to couple the switching voltage to the control terminal of the drive module 110.

[0021] The light-emitting control module 140, the driving module 110, and the light-emitting module 190 are connected between the first power supply VDD and the second power supply VSS. The light-emitting control module 140 is used to respond to the light-emitting control signal EM during the light-emitting stage to control the light-emitting module 190 to emit light according to the driving current output by the driving module 110.

[0022] The first end of the node control module 170 is connected to the first power supply VDD, and the second end of the node control module 170 is connected to the second end of the coupling module 180 and the control end of the drive module 110 to the second child node N2. The node control module 170 is used to respond to the fifth scan signal S5 during the initialization phase to conduct the first power supply voltage on the first power supply VDD to the second child node N2.

[0023] Specifically, the driving module 110 may include a transistor, with its first terminal being the drain of the transistor and its second terminal being the source of the transistor. The first initialization voltage may be a DC voltage or a voltage signal with adjustable magnitude.

[0024] Since the second initialization module 160 is connected between the second end of the driving module 110 and the first initialization signal line, during the initialization phase, the second initialization module 160 can be turned on in response to the second scan signal S2, and transmit the first initialization voltage Vini on the first initialization line to the first end of the light-emitting module 190 (i.e., the anode of the light-emitting element) through the turned-on second initialization module 160. Moreover, the first initialization voltage Vini is negative, which can suppress the degradation of the OLED device after long-term operation and improve the short-term image retention caused by the residual charge of the previous frame.

[0025] In traditional circuits, the initialization signal and the light emission control signal may originate from the same driver circuit or be strongly coupled. When the refresh frequency changes, their timing is simultaneously stretched or compressed, causing the light emission time to change. In this embodiment of the invention, since the light emission control signal is independent, and multiple initialization operations are controlled by different signals, the driver circuit designer can flexibly allocate the timing of these signals.

[0026] When using wideband driving (e.g., switching from 120Hz to 60Hz or lower), although the frequency and period of the scan signals used for data writing and compensation (e.g., the third scan signal S3 and the fourth scan signal S4) change accordingly, the timing of the emission control signal EM can be adjusted independently to keep its effective emission time (i.e., pulse width) constant within each frame period. This ensures that the actual emission duration of the pixel is constant regardless of whether it is a high-frequency data refresh frame or a low-frequency non-refresh frame, thereby improving the flickering problem caused by asynchronous emission timing.

[0027] Figure 2a This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. For example... Figure 2a As shown, a screen refresh cycle (i.e., the time required to complete the display of a full screen) can contain one or more large cycles, and each large cycle contains N frame cycles (N is an integer greater than 1). The driving timing of the first frame includes the initialization phase t1, the threshold compensation phase t2, the data writing phase t3, and the emission phase t4; the driving timing of the second to Nth frames includes the data writing phase t3 and the emission phase t4.

[0028] The first frame of each major cycle: During initialization phase t1, the third scan signal S3, the fourth scan signal S4, and the light emission control signal EM are at low levels, and the compensation module 120, the data writing module 130, and the light emission control module 140 are turned off; the first scan signal S1, the second scan signal S2, and the fifth scan signal S5 are at high levels, and the first initialization module 150, the second initialization module 160, and the node control module 170 are turned on. The second electrode plate (i.e., the second child node N2) of the coupling module 181 is charged to the first power supply voltage ELVDD, and the first electrode plate (i.e., the first child node N1) of the coupling module 180 is charged to the initialization voltage Vini.

[0029] During the threshold compensation stage t2, the fourth scan signal S4, the fifth scan signal S5, and the light emission control signal EM are at low levels, and the data writing module 130, the node control module 170, and the light emission control module 140 are turned off; the first scan signal S1, the second scan signal S2, and the third scan signal S3 are at high levels, and the first initialization module 150, the second initialization module 160, and the compensation module 120 are turned on. The second plate of the coupling module 180 discharges to Vini+Vth through the driving module 110, where Vth is the threshold voltage of the driving transistor, thereby realizing threshold voltage latching.

[0030] During the data writing phase t3, the first scan signal S1, the third scan signal S3, the fifth scan signal S5, and the light emission control signal EM are at low levels, and the first initialization module 150, the compensation module 120, the node control module 170, and the light emission control module 140 are turned off; the second scan signal S2 and the fourth scan signal S4 are at high levels, and the second initialization module 160 and the data writing module 130 are turned on. The first plate of the coupling module 180 changes from the initialization voltage Vini to the data voltage Vdata, and the second plate of the coupling module 180 is coupled to Vdata+Vth.

[0031] During the light emission stage t4, the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, and the fifth scan signal S5 are at low levels, and the first initialization module 150, the second initialization module 160, the compensation module 120, the data writing module 130, and the node control module 170 are turned off; the light emission control signal EM is at a high level, the light emission control module 140 is turned on, and the OLED begins to emit light.

[0032] Frames 2 through N of each major cycle: Each frame consists of only the data writing phase t3 and the light emission phase t4.

[0033] During the data writing phase t3, the first plate of the coupling module 180 changes from the data voltage Vdata of the previous frame to the new data voltage Vdata', and the second plate of the coupling module 180 is coupled to Vdata'+Vth. During the light emission phase t4, the voltage of the second child node N2 remains unchanged.

[0034] For example, the driving module 110 includes a driving transistor, such as an NMOS transistor. Figure 2b This is a simulation diagram provided in an embodiment of the present invention, such as... Figure 2b As shown, the voltage at the control terminal (gate) G1 of the drive module 110 is Vg, the voltage at the first terminal (drain) A1 is Vd, and the voltage at the second terminal (source) A2 is Vs. Assume the first power supply voltage is 6V, the initialization voltage Vini is -2V, and the threshold voltage of the drive transistor is 0.2V.

[0035] During the initialization phase t1 of the first frame, the gate voltage Vg of the driving transistor is 6V. Figure 2b The high-level segment starting with the red dashed line in the middle), the source voltage Vs is -2V ( Figure 2b (The low-level segment of the solid red line). At this time, the gate-source voltage difference Vgs = Vg - Vs = 6V - (-2)V = 8V. Since the light-emitting control signal is not conducting at this time, there is no effective current path, therefore no driving current flows through the light-emitting module 190. Figure 2b The solid blue line is close to 0.

[0036] During the threshold compensation phase t2 of the first frame, after the compensation module 120 is turned on, the first terminal of the drive module 110 is short-circuited with the control terminal, forming a diode connection. The fixed initialization voltage Vini of the drive module 110 is applied. According to the conduction condition Vgs≥Vth of the drive module 110, the voltage at the control terminal of the drive module 110 is pulled to Vgs=Vth, Vg=Vs+Vth=-2V+0.2V=-1.8V, and the gate voltage drops rapidly to -1.8V. Figure 2b The red dashed line represents a steep descent. The first child node N1 is still connected to the initialization voltage Vini = -2V via the first initialization module. Figure 2b (The solid red line in the middle is still at a low level), the current I flowing through the light-emitting module during the compensation process. OLED 0 ( Figure 2b The solid blue line remains slightly at 0.

[0037] During the data writing phase t3 of the first frame, the data voltage Vdata = 3V is applied. Through capacitive coupling, the gate voltage is raised to Vdata + Vth, i.e., 3V + 0.2V = 3.2V. The gate voltage jumps from -1.8V to approximately 3.2V. Figure 2b The red dashed line indicates a voltage jump segment; due to parasitic parameters, the actual value is slightly lower than 3.2V. The source voltage Vs remains at -2V. Figure 2b (The solid red line in the middle remains unchanged). No driving current is present during data writing; the current I flowing through the LED module is... OLED 0 ( Figure 2b The solid blue line remains at 0.

[0038] During the first frame emission phase t4, the gate voltage remains at 3.2V, with slight fluctuations due to parasitic capacitance. Figure 2b The small fluctuations in the stable segment of the red dashed line. After the OLED is turned on, the source potential rises and stabilizes at approximately 1.8V. Figure 2b The solid red line in the middle rises from -2V to approximately 1.8V. The gate-source voltage of the driver transistor, Vgs = 3.2V - 1.8V = 1.4V, and the current flowing through the LED module, I... OLED Stable at approximately 0.54 μA ( Figure 2b The solid blue line rises to 0.54 μA and remains there.

[0039] During the data writing phase t3 from the second to the Nth frame, the new data voltage Vdata' = 5V is connected. After coupling, the voltage is "Vdata' + Vth", that is, 5V + 0.2V = approximately 5.2V. The gate voltage Vg jumps from 3.2V to approximately 5.2V. Figure 2bThe red dashed line indicates another jump in voltage; due to parasitic parameters, the actual value is slightly lower than 5.2V. After the first frame of emission ends, the source voltage Vs returns to a low potential and then remains stable. Figure 2b (The solid red line in the middle is stable after adjustment). The current I flowing through the LED module during data writing is... OLED 0μA ( Figure 2b The solid blue line returns to 0.

[0040] During the emission phase t4 from the second frame to the Nth frame, the gate voltage Vg remains at approximately 5.2V, and parasitic capacitance causes slight voltage fluctuations. Figure 2b The red dashed line represents the stable segment. After the OLED is turned on, the source potential rises further and stabilizes at approximately 2.9V. Figure 2b The solid red line in the middle rises from a low potential to approximately 2.9V. The gate-source voltage of the driving transistor is Vgs = 5.2V - 2.9V = 2.3V, and the current flowing through the LED module is I. OLED Stable at approximately 1.5 μA ( Figure 2b The solid blue line rises to 1.5 μA and remains there.

[0041] AMOLED power consumption is divided into dynamic power consumption and static power consumption. Static power consumption is the current consumption when the OLED emits light, while dynamic power consumption includes the switching power consumption of the scan control signal and the charging and discharging power consumption of the capacitors in the pixel circuit. Since the initialization phase t1, threshold compensation phase t2, data writing phase t3, and light emission phase t4 only occur in the first frame (i.e., the Nth frame contains the switching power consumption of all switching transistors and the charging and discharging power consumption of capacitors), and the second to Nth frames only contain the data writing phase t3 and the light emission phase t4 (i.e., the second to Nth frames only contain the switching power consumption of the second transistor T2, the fifth transistor T5, and the sixth transistor T6 and the charging and discharging power consumption of capacitors), the larger N is, the greater the dynamic power consumption savings.

[0042] Specifically, the operating frequencies of the first scan signal S1, the third scan signal S3, and the fifth scan signal S5 are the first operating frequency. ; The operating frequencies of the second scanning signal S2 and the light emission control signal EM are the second operating frequencies. The operating frequency of the fourth scan signal S4 is the same as the third operating frequency.

[0043] In wideband displays, the second operating frequency is generally used. It refers to the maximum data refresh rate, which can prevent the AMOLED display from flickering when switching frequencies.

[0044] The operating frequency of the above scanning control signals is subject to the following constraints: ; ; ; in This indicates that in wideband drive, each data... Refresh once, Indicates that at the threshold voltage per Frame compensation is performed once. Furthermore, the third operating frequency must be an integer multiple of the first operating frequency. This means that after several frames of data refresh, the threshold voltage is compensated once; this is referred to as one compensation + multiple frame refreshes.

[0045] Figure 1 The dynamic power consumption of the pixel circuit during operation can be expressed by the following formula: ; in, It is the power consumption of the scanning signal switching. It is the power consumption of pixel charging and discharging; ; ; It is the parasitic capacitance of the scan line. It is the voltage change of the switching signal. It is the voltage change of the data signal.

[0046] From the above formula, we can see that the dynamic power consumption saved in the single compensation + multi-frame refresh mode compared to the traditional working mode is: ; It is evident that under high-frequency data refresh, the larger the Nc value, the greater the dynamic power consumption savings.

[0047] The pixel circuit provided in this embodiment of the invention achieves independent control of the light emission control signal and the timing-variable scan signal by setting up a functionally independent first initialization module, a second initialization module, a node control module, a data writing module, and a light emission control module, and configuring independent scan control signals for each module. In wideband drive applications, when the refresh frequency of the panel changes, the timing and period of the fourth scan signal used for data refresh can be independently adjusted to adapt to the new frame rate. At the same time, it can ensure that the effective pulse width (i.e., light emission time) of the light emission control signal remains constant. This means that, whether in a high-frequency data refresh frame or a low-frequency data hold (non-refresh) frame, the actual light emission time of each pixel is the same in each display frame cycle. Since the light emission brightness is directly related to the light emission time, the stable light emission time ensures the consistency of brightness between frames, thereby alleviating the display flickering phenomenon caused by fluctuations in light emission time.

[0048] Figure 3This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 3 and Figure 4 As shown, the pixel circuit also includes a storage module 200; the first end of the storage module 200 is connected to the first child node N1, and the second end of the storage module 200 is connected to the first end of the light-emitting module 190 or connected to the initialization voltage Vini. The storage module 200 is used to store the voltage of the first child node N1.

[0049] Specifically, Figure 3 The illustration shows the case where the second terminal of the storage module 200 is connected to the initialization voltage Vini. Figure 4 The diagram illustrates the case where the second end of the storage module 200 is connected to the first end (i.e., the anode of the light-emitting element) of the light-emitting module 190.

[0050] During the data writing phase, when the data writing module 130 writes the data voltage Vdata to the first child node N1, the storage module 200 can effectively store the voltage value. Even after the data writing module 130 is turned off, it can maintain the voltage stability of the first child node N1, preventing it from changing due to charge leakage and ensuring the accuracy of the written data.

[0051] The storage module 200 and the coupling module 180 work together. When the data voltage Vdata changes, the coupling module 180 couples the changing voltage to the gate of the driving transistor (second child node N2) through capacitive coupling. At this time, a stable first child node N1 voltage (maintained by the storage module 200) is an important prerequisite for forming a definite and controllable coupling voltage, which helps to accurately adjust the driving gate voltage and improve brightness uniformity.

[0052] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. The first initialization module 150 includes a first transistor T1, the second initialization module 160 includes a second transistor T2, the compensation module 120 includes a third transistor T3, the data writing module 130 includes a fourth transistor T4, the light emission control module 140 includes a fifth transistor T5, the driving module 110 includes a sixth transistor T6, and the node control module 170 includes a seventh transistor T7.

[0053] The gate of the first transistor T1 is connected to the first scan signal S1, the first terminal of the first transistor T1 is connected to the initialization voltage Vini, and the second terminal of the first transistor T1 is connected to the first terminal of the coupling module 180.

[0054] The gate of the second transistor T2 is connected to the second scan signal S2, the first terminal of the second transistor T2 is connected to the initialization voltage Vini, and the second terminal of the second transistor T2 is connected to the first terminal of the light-emitting module 190.

[0055] The gate of the third transistor T3 is connected to the third scan signal S3, the first terminal of the third transistor T3 is connected to the first terminal of the sixth transistor T6, and the second terminal of the third transistor T3 is connected to the gate of the sixth transistor T6.

[0056] The gate of the fourth transistor T4 is connected to the fourth scan signal S4, the first terminal of the fourth transistor T4 is connected to the data voltage Vdata, and the second terminal of the fourth transistor T4 is connected to the first terminal of the coupling module 180.

[0057] The gate of the fifth transistor T5 is connected to the light-emitting control signal EM, the first terminal of the fifth transistor T5 is connected to the first power supply VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting module 190.

[0058] The gate of the seventh transistor T7 is connected to the fifth scan signal S5, the first terminal of the seventh transistor T7 is connected to the first power supply VDD, and the second terminal of the seventh transistor T7 is connected to the gate of the sixth transistor T6.

[0059] The light-emitting module 190 includes a light-emitting element D1, with the anode of the light-emitting element D1 serving as the first end of the light-emitting module 190 and the cathode of the light-emitting element D1 serving as the second end of the light-emitting module 190.

[0060] Optionally, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all N-type oxide transistors. The sixth transistor T6 is the driving transistor.

[0061] Optionally, the coupling module 180 includes a first capacitor C1, and the storage module 200 includes a second capacitor C2. The first end of the first capacitor C1 serves as the first end of the coupling module 180, and the second end of the first capacitor C1 serves as the second end of the coupling module 180. The first end of the second capacitor C2 serves as the first end of the storage module 200, and the second end of the second capacitor C2 serves as the second end of the storage module 200.

[0062] The driving timing provided in Figure 2 also applies to... Figure 5 and Figure 6 The pixel circuit. Refer to Figure 2 and Figure 5 The first frame of each major cycle: During the initialization phase t1, the third scan signal S3, the fourth scan signal S4, and the light emission control signal EM are at low levels, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off; the first scan signal S1, the second scan signal S2, and the fifth scan signal S5 are at high levels, and the first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on. The second plate of the coupling module 181 (i.e., the second sub-node N2) is charged to the first power supply voltage ELVDD, and the first plate of the first capacitor C1 (i.e., the first sub-node N1) is charged to the initialization voltage Vini.

[0063] During the threshold compensation stage t2, the fourth scan signal S4, the fifth scan signal S5, and the light emission control signal EM are at low levels, and the fourth transistor T4, the seventh transistor T7, and the fifth transistor T5 are turned off; the first scan signal S1, the second scan signal S2, and the third scan signal S3 are at high levels, and the first transistor T1, the second transistor T2, and the third transistor T3 are turned on. The second plate of the first capacitor C1 discharges to Vini+Vth through the driving module 110, where Vth is the threshold voltage of the driving transistor, thereby realizing threshold voltage latching.

[0064] During the data writing phase t3, the first scan signal S1, the third scan signal S3, the fifth scan signal S5, and the light emission control signal EM are at low levels, and the first transistor T1, the third transistor T3, the seventh transistor T7, and the fifth transistor T5 are turned off; the second scan signal S2 and the fourth scan signal S4 are at high levels, and the second transistor T2 and the fourth transistor T4 are turned on. The first plate of the first capacitor C1 changes from the initialization voltage Vini to the data voltage Vdata, and the second plate of the first capacitor C1 is coupled to Vdata+Vth.

[0065] During the light-emitting stage t4, the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, and the fifth scan signal S5 are at low levels, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off; the light-emitting control signal EM is at a high level, the fifth transistor T5 is turned on, and the OLED begins to emit light.

[0066] Figure 5 The expression for the current flowing through the pixel circuit of the OLED is: ; The difference from the diagram is that, Figure 6 The second terminal of the second capacitor C2 is connected to the anode of the light-emitting element D1. This source-follower connection avoids the influence of OLED anode voltage fluctuations on the driving current, thus maintaining constant luminous brightness. During the light-emitting phase, its current expression is: ; Vini is the initial voltage, which can generally be considered as having no current flowing through it. Therefore, the initial voltage Vini has no voltage drop within the display panel, thus solving the problem of uneven display caused by the voltage drop of the first power supply voltage.

[0067] in, Electron mobility; The capacitance per unit area of ​​the insulating layer; W and L are the channel width and length of the sixth transistor T6, respectively. This represents the voltage at the anode of the light-emitting element. It can be seen that the luminous current is independent of the threshold voltage of the sixth transistor T6, meaning that this circuit can compensate for the display non-uniformity caused by the threshold voltage drift of the sixth transistor T6.

[0068] Frames 2 through N of each major cycle: Each frame consists of only the data writing phase t3 and the light emission phase t4.

[0069] During the data writing phase t3, the first plate of the first capacitor C1 changes from the data voltage Vdata of the previous frame to the new data voltage Vdata', and the second plate of the first capacitor C1 is coupled to Vdata'+Vth. During the light emission phase t4, the voltage of the second child node N2 remains unchanged.

[0070] Figure 5 The expression for the current flowing through the pixel circuit of the OLED is: ; Figure 6 The expression for the current flowing through the pixel circuit of the OLED is: ; Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 7 As shown, it includes pixel circuits PX provided in any embodiment of the present invention arranged in an array; it also includes a plurality of gate driving circuits, including a first gate driving circuit 100, a second gate driving circuit 200 and a third gate driving circuit 300.

[0071] The first gate driving circuit 100 is connected to the control terminal of the first initialization module 150, the control terminal of the compensation module 120, and the control terminal of the node control module 170 of the pixel circuit PX, and is used to provide the pixel circuit PX with the first scan signal S1, the third scan signal S3, and the fifth scan signal S5. The second gate driving circuit 200 is connected to the control terminal of the second initialization module 160 of the pixel circuit PX and the control terminal of the light emission control module 140, and is used to provide the second scanning signal S2 and the light emission control signal EM to the pixel circuit PX.

[0072] The third gate drive circuit 300 is connected to the control terminal of the data writing module 130 of the pixel circuit PX, and is used to provide the fourth scan signal S4 to the pixel circuit PX.

[0073] The pixel circuit PX is located in the display area AA of the display panel, and the first gate driving circuit 100, the second gate driving circuit 200 and the third gate driving circuit 300 are located in the non-display area NAA of the display panel.

[0074] Specifically, the first gate driving circuit 100, the second gate driving circuit 200, and the third gate driving circuit 300 can all be located on one side of the display panel, or the first gate driving circuit 100, the second gate driving circuit 200, and the third gate driving circuit 300 can be located on a first side and a second side opposite to each other on the display panel, respectively. The first gate driving circuit 100 and the second gate driving circuit 200 can be located on the same side of the display panel, or they can be located on the same side of the display panel as the third gate driving circuit 300. The second gate driving circuit 200 and the third gate driving circuit 300 can also be located on the same side of the display panel.

[0075] Figure 8 This is a schematic diagram of a first gate driving circuit provided in an embodiment of the present invention. Figure 8 As shown, the first gate drive circuit 100 includes a plurality of cascaded first shift registers 101; The first shift register 101 includes a first input module 11, a first potential control module 12, a second potential control module 13, a first output module 14, a second output module 15, and a third output module 16.

[0076] The output of the first input module 11 is connected to the first node Q1; the first input module 11 is used to respond to the first clock signal SCK1 and transmit the first input signal VIN1 to the first node Q1.

[0077] The output of the first potential control module 12 is connected to the second node Q2; the first potential control module 12 is used to respond to the first potential signal VGH and the first clock signal SCK1, and transmit the first potential signal VGH to the second node Q2.

[0078] The second potential control module 13 is connected to the first node Q1 and the second node Q2 respectively, and is used to transmit the first clock signal SCK1 to the second node Q2 in response to the potential of the first node Q1.

[0079] The first output module 14 is connected to the first node Q1 and the second node Q2 respectively, and is used to output the second clock signal SCK2 as the first scan signal S1 in response to the potential of the first node Q1, and / or output the second potential signal VGL as the first scan signal S1 in response to the potential of the second node Q2.

[0080] The second output module 15 is connected to the first node Q1 and the second node Q2 respectively, and is used to output the third clock signal SCK3 as the fifth scan signal S5 in response to the potential of the first node Q1, and / or output the second potential signal VGL as the fifth scan signal S5 in response to the potential of the second node Q2.

[0081] The third output module 16 is connected to the first node Q1 and the second node Q2 respectively. It is used to respond to the potential of the first node Q1 by outputting the fourth clock signal SCK4 as the third scan signal S3, and / or, respond to the potential of the second node Q2 by outputting the second potential signal VGL as the third scan signal S3. The first scan signal S1 output from the output terminal of the first output module 14 of the i-th stage first shift register 101 is used as the first input signal VIN1 of the (i+1)-th stage first shift register 101; i is an integer greater than or equal to 1.

[0082] Specifically, one of the first potential signal VGH and the second potential signal VGL is a high-level signal, and the other is a low-level signal. For example, the first potential signal VGH is a high-level signal and the second potential signal VGL is a low-level signal; or, the first potential signal VGH is a low-level signal and the second potential signal VGL is a high-level signal. In this embodiment and in the embodiments described below, the example of the first potential signal VGH being a high-level signal and the second potential signal VGL being a low-level signal is used for illustrative purposes.

[0083] The waveform of the second clock signal SCK2 is the same as that of the first clock signal SCK1; the period of the second clock signal SCK2 is the same as that of the first clock signal SCK1. The waveform of the second clock signal SCK2 is delayed relative to the waveform of the first clock signal SCK1. The first clock signal SCK1 and the second clock signal SCK2 can include low and high levels. The high level of the first clock signal SCK1 and the second clock signal SCK2 can be equal to the potential of the first potential signal VGH, and the low level of the first clock signal SCK1 and the second clock signal SCK2 can be equal to the potential of the second potential signal VGL. The duration of the low level in the first clock signal SCK1 and the second clock signal SCK2 is greater than or equal to half a cycle, and the duration of the high level in the first clock signal SCK1 and the second clock signal SCK2 is less than half a cycle.

[0084] The waveform of the fourth clock signal SCK4 is the same as that of the third clock signal SCK3; the period of the fourth clock signal SCK4 is the same as that of the third clock signal SCK3. The waveform of the fourth clock signal SCK4 is delayed relative to the waveform of the third clock signal SCK3. The third clock signal SCK3 and the fourth clock signal SCK4 can include low and high levels. The high level of the third clock signal SCK3 and the fourth clock signal SCK4 can be equal to the potential of the first potential signal VGH, and the low level of the third clock signal SCK3 and the fourth clock signal SCK4 can be equal to the potential of the second potential signal VGL. The duration of the low level in the third clock signal SCK3 and the fourth clock signal SCK4 is greater than or equal to half a cycle, and the duration of the high level in the third clock signal SCK3 and the fourth clock signal SCK4 is less than half a cycle.

[0085] Figure 9 This is a schematic diagram of the structure of a first shift register provided in an embodiment of the present invention. Figure 9 As shown, optionally, the first input module 11 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the first clock signal SCK1, the first terminal of the eighth transistor T8 is connected to the first input signal VIN1, and the second terminal of the eighth transistor T8 is connected to the first node Q1. Optionally, the first potential control module 12 includes a ninth transistor T9, the gate of the ninth transistor T9 is connected to the first clock signal SCK1, the first terminal of the ninth transistor T9 is connected to the first potential signal VGH, and the second terminal of the ninth transistor T9 is connected to the second node Q2. Optionally, the second potential control module 13 includes a tenth transistor T10, the gate of the tenth transistor T10 is connected to the first node Q1, the first terminal of the tenth transistor T10 is connected to the first clock signal, and the second terminal of the tenth transistor T10 is connected to the second node Q2. Optionally, the first output module 14 includes an eleventh transistor T11, a twelfth transistor T12, a third capacitor C3, and a fourth capacitor C4; The gate of the eleventh transistor T11 is connected to the first node Q1 and the first terminal of the third capacitor C1 respectively. The first terminal of the eleventh transistor T11 is connected to the second clock signal SCK2. The second terminal of the eleventh transistor T11 is connected to the second terminal of the third capacitor C3 and serves as the output terminal of the first output module 14. The gate of the twelfth transistor T12 is connected to the second node Q2 and the first terminal of the fourth capacitor C4, respectively. The first terminal of the twelfth transistor T12 is connected to the second terminal of the fourth capacitor C4 and connected to the second potential signal VGL. The second terminal of the twelfth transistor T12 is connected to the second terminal of the third capacitor C3.

[0086] Optionally, the second output module 15 includes a thirteenth transistor T13 and a fourteenth transistor T14.

[0087] The gate of the thirteenth transistor T13 is connected to the first node Q1, the first terminal of the thirteenth transistor T13 is connected to the third clock signal SCK3, and the second terminal of the thirteenth transistor T13 serves as the output terminal of the second output module 15. The gate of the fourteenth transistor T14 is connected to the second node Q2, the first terminal of the fourteenth transistor T14 is connected to the second potential signal, and the second terminal of the fourteenth transistor T14 is connected to the second terminal of the thirteenth transistor T13. Optionally, the third output module 16 includes a fifteenth transistor T15 and a sixteenth transistor T16. The gate of the fifteenth transistor T15 is connected to the first node Q1, the first terminal of the fifteenth transistor T15 is connected to the fourth clock signal SCK4, and the second terminal of the fifteenth transistor T15 serves as the output terminal of the third output module 16. The gate of the sixteenth transistor T16 is connected to the second node Q2, the first terminal of the sixteenth transistor T16 is connected to the second potential signal VGL, and the second terminal of the sixteenth transistor T16 is connected to the second terminal of the fifteenth transistor T15.

[0088] Figure 10 This is a timing diagram for driving a first shift register according to an embodiment of the present invention, which can be used to drive... Figure 9 The shift register shown is referenced. Figure 9 and Figure 10 In this embodiment, the example of each module being turned off at a low level and turned on at a high level is used for illustration; the working process of the shift register may include six stages from J1 to J6.

[0089] In stage J1, the first input signal VIN1 is high, the first clock signal SCK1 is high, and the second, third, and fourth clock signals SCK2, SCK3, and SCK4 are low. The eighth transistor T8 turns on in response to the high level of the first clock signal SCK1, transmitting the first input signal VIN1 to the first node Q1. The ninth transistor T9 turns on in response to the high level of the first clock signal SCK1, transmitting the first potential signal VGH to the second node Q2. The eleventh transistor T11 turns on in response to the potential of the first node Q1, outputting the low level of the second clock signal SCK2 as the first scan signal S1. The tenth transistor T10 responds to the high level of the first node Q1 and transmits the high level of the first clock signal SCK1 to the second node Q2. The twelfth transistor T12 turns on in response to the high level of the second node Q2, outputting the second potential signal VGL as the first scan signal S1. Similarly, the thirteenth transistor T13 responds to the high level of the first node Q1 by outputting the low level of the third clock signal SCK3 as the fifth scan signal S5. The fourteenth transistor T14 responds to the high level of the second node Q2 by outputting the second potential signal VGL as the fifth scan signal S5. The fifteenth transistor T15 responds to the high level of the first node Q1 by outputting the low level of the fourth clock signal as the third scan signal S3. The sixteenth transistor T16 responds to the high level of the second node Q2 by outputting the second potential signal. That is, in stage J1, the first scan signal S1 output by the first output module 14, the fifth scan signal S5 output by the second output module 15, and the third scan signal S3 output by the third output module 16 are all low-level signals.

[0090] In phase J2, the first input signal VIN1 is high, the first clock signal SCK1 is high, and the second, third, and fourth clock signals SCK2, SCK3, and SCK4 are low. The eighth transistor T8 turns on in response to the high level of the first clock signal SCK1, transmitting the first input signal VIN1 to the first node Q1. The ninth transistor T9 turns on in response to the high level of the first clock signal SCK1, transmitting the first potential signal VGH to the second node Q2. The eleventh transistor T11 turns on in response to the potential of the first node Q1, outputting the low level of the second clock signal SCK2 as the first scan signal S1. The tenth transistor T10 responds to the high level of the first node Q1 and transmits the high level of the first clock signal SCK1 to the second node Q2. The twelfth transistor T12 turns on in response to the high level of the second node Q2, outputting the second potential signal VGL as the first scan signal S1. Similarly, the thirteenth transistor T13 responds to the high level of the first node Q1 and outputs the low level of the third clock signal SCK3 as the fifth scan signal S5. The fourteenth transistor T14 responds to the high level of the second node Q2 and outputs the second potential signal VGL as the fifth scan signal S5. The fifteenth transistor T15 responds to the high level of the first node Q1 and outputs the low level of the fourth clock signal SCK4 as the third scan signal S3. The sixteenth transistor T16 responds to the high level of the second node Q2 and outputs the second potential signal. That is, in stage J2, the first scan signal S1 output by the first output module 14, the fifth scan signal S5 output by the second output module 15, and the third scan signal S3 output by the third output module 16 are all low-level signals.

[0091] In stage J3, the first input signal VIN1 is low, and the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 are all low. The eighth transistor T8 and the ninth transistor T9 are off. Due to capacitive coupling, the first node Q1 remains high. The tenth transistor T10 responds to the high level of the first node Q1 and turns on, transmitting the low level of the first clock signal SCK1 to the second node Q2, causing the second node Q2 to switch to a low level. The eleventh transistor T11 responds to the high potential of the first node Q1 and turns on, outputting the low level of the second clock signal SCK2 as the first scan signal S1. The thirteenth transistor T13 responds to the high level of the first node Q1 and outputs the low level of the third clock signal SCK3 as the fifth scan signal S5. The fifteenth transistor T15 responds to the high level of the first node Q1 and outputs the low level of the fourth clock signal SCK4 as the third scan signal S3. That is, in the J3 stage, the first scan signal S1 output by the first output module 14, the fifth scan signal S5 output by the second output module 15, and the third scan signal S3 output by the third output module 16 are all the same, and are all low-level signals.

[0092] In stage J4, the first input signal VIN1 is low, the first clock signal SCK1 and the third clock signal SCK4 are low, and the second clock signal SCK2 and the third clock signal SCK3 are high. The eighth transistor T8 and the ninth transistor T9 are off, the first node Q1 remains high, and the tenth transistor T10 turns on in response to the high level of the first node Q1, transmitting the low level of the first clock signal SCK1 to the second node Q2, causing the second node Q2 to switch low. The eleventh transistor T11 turns on in response to the high potential of the first node Q1, outputting the high level of the second clock signal SCK2 as the first scan signal S1. The thirteenth transistor T13 responds to the high level of the first node Q1, outputting the high level of the third clock signal SCK3 as the fifth scan signal S5. The fifteenth transistor T15 responds to the high level of the first node Q1, outputting the low level of the fourth clock signal SCK4 as the third scan signal S3. That is, in the J4 stage, the first scan signal S1 output by the first output module 14 is the same as the fifth scan signal S5 output by the second output module 15, which is a high-level signal, while the third scan signal S3 output by the third output module 16 is a low-level signal.

[0093] In stage J5, the first input signal VIN1 is low, the first clock signal SCK1 and the third clock signal SCK3 are low, and the second clock signal SCK2 and the fourth clock signal SCK4 are high. The eighth transistor T8 and the ninth transistor T9 are off, the first node Q1 remains high, and the tenth transistor T10 turns on in response to the high level of the first node Q1, transmitting the low level of the first clock signal SCK1 to the second node Q2, i.e., the second node Q2 is low. The eleventh transistor T11 turns on in response to the high potential of the first node Q1, outputting the high level of the second clock signal SCK2 as the first scan signal S1. The thirteenth transistor T13 responds to the high level of the first node Q1, outputting the low level of the third clock signal SCK3 as the fifth scan signal S5. The fifteenth transistor T15 responds to the high level of the first node Q1, outputting the high level of the fourth clock signal SCK4 as the third scan signal S3. That is, in the J5 stage, the first scan signal S1 output by the first output module 14 and the third scan signal S3 output by the third output module 16 are the same, which are high-level signals, while the fifth scan signal S5 output by the second output module 15 is a low-level signal.

[0094] In stage J6, the first input signal VIN1 is low, and the first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 are all low. The eighth transistor T8 and the ninth transistor T9 are off, the first node Q1 remains high, and the tenth transistor T10 turns on in response to the high level of the first node Q1, transmitting the low level of the first clock signal SCK1 to the second node Q2, making the second node Q2 low. The eleventh transistor T11 turns on in response to the high potential of the first node Q1, outputting the low level of the second clock signal SCK2 as the first scan signal S1. The thirteenth transistor T13 responds to the high level of the first node Q1, outputting the low level of the third clock signal SCK3 as the fifth scan signal S5. The fifteenth transistor T15 responds to the high level of the first node Q1, outputting the low level of the fourth clock signal SCK4 as the third scan signal S3. That is, in the J6 stage, the first scan signal S1 output by the first output module 14, the fifth scan signal S5 output by the second output module 15, and the third scan signal S3 output by the third output module 16 are all the same, and are all low-level signals.

[0095] In stage J7, due to the high level of the first clock signal SCK1 and the low level of the first input signal VIN1, the eighth transistor T8 is turned on, transmitting the low level of the first input signal VIN1 to the first node Q1, making the first node Q1 low. The tenth transistor T10 is turned off. The ninth transistor T9 is turned on in response to the high level of the first clock signal SCK1, transmitting the first potential signal VGH to the second node Q2. The twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are turned on in response to the potential of the second node Q2, outputting the second potential signal VGL as the first scan signal S1, the fifth scan signal S5, and the third scan signal S3, respectively, to keep the first scan signal S1, the third scan signal S3, and the fifth scan signal S5 stable at a low level. Stage J7 is then repeated continuously.

[0096] Figure 11 This is a schematic diagram of a second gate driving circuit provided in an embodiment of the present invention. Figure 11 As shown, the second gate drive circuit 200 includes a plurality of cascaded second shift registers 201; The second shift register 102 includes a second input module 21, a third potential control module 22, a fourth potential control module 23, a fourth output module 24, and an inverting module 25; The output of the second input module 21 is connected to the third node Q3; the second input module 21 is used to respond to the fifth clock signal SCK5 and transmit the second input signal VIN2 to the third node Q3; The output of the third potential control module 22 is connected to the fourth node Q4; the third potential control module 22 is used to respond to the first potential signal VGH and the fifth clock signal SCK5, and transmit the first potential signal VGH to the fourth node Q4. The fourth potential control module 23 is connected to the third node Q3 and the fourth node Q4 respectively, and is used to respond to the potential of the third node Q3 and transmit the fifth clock signal SCK4 to the fourth node Q4. The fourth output module 24 is connected to the third node Q3 and the fourth node Q5 respectively, and is used to respond to the potential of the third node Q3 by outputting the second potential signal VGL as the second scan signal S2, and / or, respond to the potential of the fourth node Q4 by outputting the sixth clock signal SCK6 as the second scan signal S2.

[0097] The inverting module 25 is connected to the output terminal of the fourth output module 24 and is used to invert the second scanning signal S2 and output it as the light emission control signal EM.

[0098] Figure 12 This is a schematic diagram of the structure of a second shift register provided in an embodiment of the present invention. Figure 12 As shown, optionally, the second input module 21 includes a seventeenth transistor T17, the gate of the seventeenth transistor T17 is connected to the fifth clock signal SCK5, the first terminal of the seventeenth transistor T17 is connected to the second input signal VIN2, and the second terminal of the seventeenth transistor T17 is connected to the third node Q3.

[0099] Optionally, the third potential control module 22 includes an eighteenth transistor T18, the gate of the eighteenth transistor T18 is connected to the fifth clock signal SCK5, the first terminal of the eighteenth transistor T18 is connected to the first potential signal VGH, and the second terminal of the eighteenth transistor T18 is connected to the third node Q3.

[0100] Optionally, the fourth potential control module 23 includes a nineteenth transistor T19, the gate of the nineteenth transistor T19 is connected to the third node Q3, the first terminal of the nineteenth transistor T19 is connected to the fifth clock signal SCK5, and the second terminal of the nineteenth transistor T19 is connected to the fourth node Q4.

[0101] Optionally, the fourth output module 24 includes a twentieth transistor T20, a twenty-first transistor T21, a fifth capacitor C5, and a sixth capacitor C6.

[0102] The gate of the twentieth transistor T20 is connected to the third node Q3 and the first terminal of the fifth capacitor C5 respectively. The first terminal of the twentieth transistor T20 is connected to the sixth clock signal SCK6. The second terminal of the twentieth transistor T20 is connected to the second terminal of the fifth capacitor C5 and serves as the output terminal of the fourth output module 24. The gate of the 21st transistor T21 is connected to the fourth node Q4 and the first terminal of the sixth capacitor C6, respectively. The first terminal of the 21st transistor T21 is connected to the second terminal of the sixth capacitor C6 and connected to the second potential signal VGL. The second terminal of the 21st transistor T21 is connected to the second terminal of the fifth capacitor C5.

[0103] Optionally, the inverting module 25 includes a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, and a seventh capacitor C7.

[0104] The gate of the twenty-second transistor T22 is connected to the first terminal of the twenty-second transistor T22 and is connected to the first potential signal VGH. The second terminal of the twenty-second transistor T22 is connected to the first terminal of the twenty-third transistor T23, the gate of the twenty-fourth transistor T24, and the first terminal of the seventh capacitor C7. The gate of the 23rd transistor T23 is connected to the output terminal of the fourth output module 24, and the second terminal of the 23rd transistor T23 is connected to the second potential signal VGL.

[0105] The first terminal of the twenty-fourth transistor T24 is connected to the first potential signal VGH. The second terminal of the twenty-fourth transistor T24 is connected to the second terminal of the seventh capacitor C7 and the first terminal of the twenty-fifth transistor T25, and serves as the output terminal of the inverting module 25. The second terminal of the twenty-fifth transistor T25 is connected to the second potential signal VGL.

[0106] Figure 13 This is a driving timing diagram of a second shift register provided in an embodiment of the present invention, which can be used to drive... Figure 12 The shift register shown is referenced. Figure 12 and Figure 13 In this embodiment, the example is that each module is turned on at a low level and turned off at a high level. The working process of the second shift register may include three stages: P1 to P3.

[0107] In phase P1, the second input signal VIN2 is high, the fifth clock signal SCK5 is high, and the sixth clock signal SCK6 is low. The seventeenth transistor T17 turns on in response to the high level of the fifth clock signal SCK5, transmitting the second input signal VIN2 to the third node Q3. The eighteenth transistor T18 turns on in response to the high level of the fifth clock signal SCK5, transmitting the first potential signal VGH to the fourth node Q4. That is, the twentieth transistor T20 turns on in response to the potential of the third node Q3, outputting the low level of the sixth clock signal SCK6 as the second scan signal S2. The nineteenth transistor T19 responds to the high level of the third node Q3 and transmits the high level of the fifth clock signal SCK5 to the fourth node Q4. The twenty-first transistor T21 turns on in response to the high level of the fourth node Q4, outputting the second potential signal VGL as the second scan signal S2. The twenty-third transistor T23 and the twenty-fifth transistor T25 turn off, while the twenty-second transistor T22 and the twenty-fourth transistor T24 turn on, outputting the first potential signal VGH as the light-emitting control signal EM. That is, in the P1 stage, the second scanning signal S2 output by the fourth output module 24 is a low-level signal, and the light emission control signal EM output by the inverting module 25 is a high-level signal.

[0108] In phase P2, the second input signal VIN2 is low, the fifth clock signal SCK5 is low, and the sixth clock signal SCK6 is high. The seventeenth transistor T17 is off, and the third node Q3 remains high. That is, the twentieth transistor T20 responds to the potential of the third node Q3 and turns on, outputting the high level of the sixth clock signal SCK6 as the second scan signal S2. The nineteenth transistor T19 responds to the high level of the third node Q3 and transmits the low level of the fifth clock signal SCK5 to the fourth node Q4. The twenty-third transistor T23 and the twenty-fifth transistor T25 respond to the high level of the second scan signal S2 and turn on, outputting the second potential signal VGL as the light emission control signal EM. The twenty-second transistor T22 and the twenty-fourth transistor T24 are off. In other words, in phase P2, the second scan signal S2 output by the fourth output module 24 is a high-level signal, and the light emission control signal EM output by the inverting module 25 is a low-level signal.

[0109] In stage P3, the second input signal VIN2 is low, the fifth clock signal SCK5 is high, and the sixth clock signal SCK6 is low. The seventeenth transistor T17 turns on in response to the high level of the fifth clock signal SCK5, transmitting the low level of the second input signal VIN2 to the third node Q3. The nineteenth transistor T19 turns off. The eighteenth transistor T18 turns on in response to the high level of the fifth clock signal SCK5, transmitting the first potential signal VGH to the fourth node Q4. The twenty-first transistor T21 turns on in response to the high level of the fourth node Q4, outputting the second potential signal VGL as the second scan signal S2. The twenty-third transistor T23 and the twenty-fifth transistor T25 turn off, while the twenty-second transistor T22 and the twenty-fourth transistor T24 turn on, outputting the first potential signal VGH as the light emission control signal EM. That is, in stage P3, the second scan signal S2 output by the fourth output module 24 is a low-level signal, and the light emission control signal EM output by the inverting module 25 is a high-level signal.

[0110] Figure 14 This is a schematic diagram of a third gate driving circuit provided in an embodiment of the present invention. Figure 14 As shown, the third gate drive circuit 300 includes multiple cascaded third shift registers 301; The third shift register 301 includes a third input module 31, a fifth potential control module 32, a sixth potential control module 33, and a fifth output module 34.

[0111] The output of the third input module 31 is connected to the fifth node Q5; the third input module 31 is used to respond to the seventh clock signal SCK7 and transmit the third input signal VIN3 to the fifth node Q5; The output of the fifth potential control module 32 is connected to the sixth node Q6; the fifth potential control module 32 is used to respond to the first potential signal VGH and the seventh clock signal SCK7, and transmit the first potential signal VGH to the sixth node Q6.

[0112] The sixth potential control module 33 is connected to the fifth node Q5 and the sixth node Q6 respectively, and is used to respond to the potential of the fifth node Q5 and transmit the seventh clock signal SCK7 to the sixth node Q6.

[0113] The fifth output module 34 is connected to the fifth node Q5 and the sixth node Q6 respectively, and is used to respond to the potential of the fifth node Q5 by outputting the second potential signal VGL as the fourth scan signal S4, and / or, respond to the potential of the sixth node Q6 by outputting the eighth clock signal SCK8 as the fourth scan signal S4.

[0114] Figure 15 This is a schematic diagram of the structure of a third shift register provided in an embodiment of the present invention. Figure 15As shown, the third input module 31 includes a twenty-sixth transistor T26. The gate of the twenty-sixth transistor T26 is connected to the seventh clock signal SCK7. The first terminal of the twenty-sixth transistor T26 is connected to the third input signal VIN3. The second terminal of the twenty-sixth transistor T26 is connected to the fifth node Q5.

[0115] Optionally, the fifth potential control module 32 includes a twenty-seventh transistor T27, the gate of the twenty-seventh transistor T27 is connected to the seventh clock signal SCK7, the first terminal of the twenty-seventh transistor T27 is connected to the first potential signal VGH, and the second terminal of the twenty-seventh transistor T27 is connected to the fifth node Q5. Optionally, the sixth potential control module 33 includes a twenty-eighth transistor T28, the gate of which is connected to the fifth node Q5, the first terminal of which is connected to the seventh clock signal SCK7, and the second terminal of which is connected to the sixth node Q6.

[0116] Optionally, the fifth output module 34 includes the twenty-ninth transistor T29, the thirtieth transistor T30, the seventh capacitor C7, and the eighth capacitor C8.

[0117] The gate of the 29th transistor T29 is connected to the fifth node Q5 and the first terminal of the seventh capacitor C7 respectively. The first terminal of the 29th transistor T29 is connected to the eighth clock signal SCK8. The second terminal of the 29th transistor T29 is connected to the second terminal of the seventh capacitor C7 and serves as the output terminal of the fifth output module 34. The gate of the thirtieth transistor T30 is connected to the sixth node Q6 and the first terminal of the eighth capacitor C8, respectively. The first terminal of the thirtieth transistor T30 is connected to the second terminal of the eighth capacitor C8 and connected to the second potential signal VGL. The second terminal of the thirtieth transistor T30 is connected to the second terminal of the seventh capacitor C7.

[0118] Figure 16 This is a driving timing diagram of a third shift register provided in an embodiment of the present invention, which can be used to drive... Figure 15 The shift register shown is referenced. Figure 15 and Figure 16 In this embodiment, the example is that each module is turned on at a low level and turned off at a high level; the working process of the third shift register may include five stages from A1 to A5.

[0119] In stage A1, the third input signal VIN3 is high, the seventh clock signal SCK7 is high, and the eighth clock signal SCK8 is low. The twenty-sixth transistor T26 turns on in response to the high-level seventh clock signal SCK7, transmitting the third input signal VIN3 to the fifth node Q5. The twenty-seventh transistor T27 turns on in response to the high-level seventh clock signal SCK7, transmitting the first potential signal VGH to the sixth node Q6. That is, the twenty-ninth transistor T29 turns on in response to the potential of the fifth node Q5, outputting the low level of the eighth clock signal SCK8 as the fourth scan signal S4. The twenty-eighth transistor T28 responds to the high level of the fifth node Q5 and transmits the high level of the seventh clock signal SCK7 to the sixth node Q6. The thirtieth transistor T30 turns on in response to the high level of the sixth node Q6, outputting the second potential signal VGL as the fourth scan signal S4. In other words, in stage A1, the fourth scan signal S4 output by the fifth output module 34 is a low-level signal.

[0120] In stage A2, the third input signal VIN3 is low, and the seventh clock signal SCK7 and the eighth clock signal SCK8 are also low. The twenty-sixth transistor T26 and the twenty-seventh transistor T27 are off. Node Q5 remains high. The twenty-ninth transistor T29 responds to the potential of node Q5 by turning on and outputting the low level of the eighth clock signal SCK8 as the fourth scan signal S4. The twenty-eighth transistor T28 responds to the high level of node Q5 and transmits the low level of the seventh clock signal SCK7 to node Q6. That is, in stage A2, the fourth scan signal S4 output by the fifth output module 34 is a low-level signal.

[0121] In stage A3, the third input signal VIN3 is low, the seventh clock signal SCK7 is low, and the eighth clock signal SCK8 is high. The twenty-sixth transistor T26 and the twenty-seventh transistor T27 are off. Due to capacitive coupling, the fifth node Q5 remains high. The twenty-eighth transistor T28 responds to the high level of the fifth node Q5 and turns on, transmitting the low level of the seventh clock signal SCK7 to the sixth node Q6, causing the sixth node Q6 to switch to a low level. The twenty-ninth transistor T29 responds to the high potential of the fifth node Q5 and turns on, outputting the high level of the eighth clock signal SCK8 as the fourth scan signal S4. That is, in stage A3, the fourth scan signal S4 output by the fifth output module 34 is a high-level signal.

[0122] In stage A4, the third input signal VIN3 is low, and the seventh clock signal SCK7 and the eighth clock signal SCK8 are also low. The twenty-sixth transistor T26 and the twenty-seventh transistor T27 are off, the fifth node Q5 remains high, and the twenty-eighth transistor T28 turns on in response to the high level of the fifth node Q5, transmitting the low level of the seventh clock signal SCK7 to the sixth node Q6, making the sixth node Q6 low. The twenty-ninth transistor T29 turns on in response to the high potential of the fifth node Q5, outputting the low level of the eighth clock signal SCK8 as the fourth scan signal S4. That is, in stage A4, the fourth scan signal S4 output by the fifth output module 34 is a low-level signal.

[0123] In stage A5, the third input signal VIN3 is low, the seventh clock signal SCK7 is high, and the eighth clock signal SCK8 is low. The twenty-sixth transistor T26 turns on in response to the high-level seventh clock signal SCK7, transmitting the low level of the third input signal VIN3 to the fifth node Q5. The fifth node Q5 is low. The twenty-seventh transistor T27 turns on in response to the high-level seventh clock signal SCK7, transmitting the first potential signal VGH to the sixth node Q6. The thirtieth transistor T30 turns on in response to the high level of the sixth node Q6, outputting the second potential signal VGL as the fourth scan signal S4. That is, in stage A5, the fourth scan signal S4 output by the fifth output module 34 is a low-level signal.

[0124] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention. Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 18 This is a schematic diagram of the signals on each clock signal line and each input signal line provided in an embodiment of the present invention. Figure 17 and Figure 18 As shown, the display device also includes a first input signal line SIN1, a second input signal line SIN2, a third input signal line SIN3, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, and a tenth clock signal line CLK10.

[0125] The first input signal line SIN1 is used to provide the first input signal VIN1 to the first stage first shift register 101. The first scan signal S1 output by the first output module of the i-th stage first shift register 101 is used as the first input signal VIN1 of the (i+1)-th stage first shift register 101; i is an integer greater than or equal to 1.

[0126] The second input signal line SIN2 is used to provide the second input signal VIN2 to the first-stage second shift register 201. The second scan signal S2 output from the output terminal of the fourth output module of the i-th stage second shift register 201 serves as the second input signal VIN2 of the (i+1)-th stage second shift register 201.

[0127] The third input signal line SIN3 is used to provide the third input signal VIN3 to the first-stage third shift register 301; the fourth scan signal S4 output by the fifth output module of the i-th stage third shift register 203 is used as the third input signal VIN3 of the (i+1)-th stage third shift register 301.

[0128] The first clock signal line CLK1 is used to provide the first clock signal SCK1 for the odd-level first shift register 101 and the second clock signal SCK2 for the even-level first shift register 101.

[0129] The second clock signal line CLK2 is used to provide the second clock signal SCK2 for the odd-level first shift register 101 and the first clock signal SCK1 for the even-level first shift register.

[0130] The third clock signal line CLK3 is used to provide the third clock signal SCK3 for the odd-level first shift register 101; The fourth clock signal line CLK4 is used to provide the fourth clock signal SCK4 for the odd-level first shift register 101; The fifth clock signal line CLK5 is used to provide the third clock signal SCK3 for the even-level first shift register 101; The sixth clock signal line CLK6 is used to provide the fourth clock signal SCK4 for the even-level first shift register 101; The seventh clock signal line CLK7 is used to provide the fifth clock signal SCK5 for the odd-level second shift register 201 and the sixth clock signal SCK6 for the even-level second shift register 201; The eighth clock signal line CLK8 is used to provide the sixth clock signal SCK6 for the odd-level second shift register 201 and the fifth clock signal SCK5 for the even-level second shift register 201; The ninth clock signal line CLK9 is used to provide the seventh clock signal SCK7 for the odd-level third shift register 301 and the eighth clock signal SCK8 for the even-level third shift register 301. The tenth clock signal line CLK9 is used to provide the eighth clock signal SCK8 for the odd-level third shift register 301 and the seventh clock signal SCK7 for the even-level third shift register.

[0131] Optionally, the display device further includes a first potential signal line V1 and a second potential signal line V2, wherein the first potential signal line V1 is used to provide a first potential signal VGH to the first shift register 101, the second shift register 201 and the third shift register 301.

[0132] The second potential signal line V2 is used to provide the second potential signal VGL to the first shift register 101, the second shift register 201 and the third shift register 301.

[0133] Optionally, the display device further includes a display driver integrated circuit (DDIC), which provides data voltage to the pixel circuit and provides clock signals to the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5, the sixth clock signal line CLK6, the seventh clock signal line CLK7, the eighth clock signal line CLK8, the ninth clock signal line CLK9, and the tenth clock signal line CLK10.

[0134] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, The display panel comprises a driving module, a compensation module, a data writing module, a light emitting control module, a first initialization module, a second initialization module, a node control module, a coupling module and a light emitting module. The first end of the first initialization module is connected to an initialization voltage, the second end of the first initialization module, the first end of the coupling module and the first end of the data writing module are connected to a first sub-node, and the first initialization module is configured to be turned on in response to a first scanning signal in an initialization stage and a threshold compensation stage, so as to transmit the initialization voltage to the first sub-node. The first end of the second initialization module is connected to the initialization voltage, and the second end of the second initialization module is connected to the first end of the light emitting module. The second initialization module is configured to be turned on in response to a second scanning signal in the initialization stage, the threshold compensation stage and a data writing stage, so as to transmit the initialization voltage to the first end of the light emitting module. The first end of the compensation module is connected to the first end of the driving module, and the second end of the compensation module is connected to the control end of the driving module. The compensation module is configured to be turned on in response to a third scanning signal in the threshold compensation stage, so as to perform threshold compensation on the driving module. The second end of the data writing module is connected to a data voltage, and the data writing module is configured to be turned on in response to a fourth scanning signal in a data writing stage, so as to transmit the data voltage to the first sub-node. The coupling module is configured to couple a jump voltage to the control end of the driving module. The light emitting control module, the driving module and the light emitting module are connected between a first power supply and a second power supply. The light emitting control module is configured to be turned on in response to a light emitting control signal in a light emitting stage, so as to control the light emitting module to emit light according to a driving current output by the driving module. The first end of the node control module is connected to the first power supply, and the second end of the node control module, the second end of the coupling module and the control end of the driving module are connected to a second sub-node. The node control module is configured to be turned on in response to a fifth scanning signal in the initialization stage, so as to transmit a first power supply voltage on the first power supply to the second sub-node. The first initialization module comprises a first transistor, the second initialization module comprises a second transistor, the compensation module comprises a third transistor, the data writing module comprises a fourth transistor, the light emitting control module comprises a fifth transistor, the driving module comprises a sixth transistor, and the node control module comprises a seventh transistor.

2. The pixel circuit of claim 1, wherein, The gate of the first transistor is connected to the first scanning signal, the first end of the first transistor is connected to the initialization voltage, and the second end of the first transistor is connected to the first end of the coupling module. The gate of the second transistor is connected to the second scanning signal, the first end of the second transistor is connected to the initialization voltage, and the second end of the second transistor is connected to the first end of the light emitting module. ​ A gate of the third transistor is connected to the third scan signal, a first electrode of the third transistor is connected to a first electrode of the sixth transistor, and a second electrode of the third transistor is connected to a gate of the sixth transistor; A gate of the fourth transistor is connected to the fourth scan signal, a first electrode of the fourth transistor is connected to the data voltage, and a second electrode of the fourth transistor is connected to a first end of the coupling module; A gate of the fifth transistor is connected to the light-emitting control signal, a first electrode of the fifth transistor is connected to a first power supply, a second electrode of the fifth transistor is connected to the first electrode of the sixth transistor, and a second electrode of the sixth transistor is connected to the first end of the light-emitting module; A gate of the seventh transistor is connected to the fifth scan signal, a first electrode of the seventh transistor is connected to the first power supply, and a second electrode of the seventh transistor is connected to the gate of the sixth transistor.

3. The pixel circuit of claim 2, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are N-type oxide transistors.

4. The pixel circuit of claim 1, wherein, The display panel further comprises a storage module, a first end of the storage module is connected to the first sub-node, and a second end of the storage module is connected to the first end of the light-emitting module or connected to the initialization voltage, and the storage module is configured to store the voltage of the first sub-node.

5. The pixel circuit of claim 4, wherein, The coupling module comprises a first capacitor, and the storage module comprises a second capacitor; A first end of the first capacitor serves as the first end of the coupling module, and a second end of the first capacitor serves as a second end of the coupling module; A first end of the second capacitor serves as the first end of the storage module, and a second end of the second capacitor serves as the second end of the storage module.

6. A display panel, characterized by, The display panel comprises a plurality of pixel circuits arranged in an array, each of the pixel circuits comprising the pixel circuit according to any one of claims 1 to 5. The display panel further comprises a plurality of gate drive circuits, the plurality of gate drive circuits comprising a first gate drive circuit, a second gate drive circuit and a third gate drive circuit. The first gate drive circuit is connected to a control end of the first initialization module, a control end of the compensation module and a control end of the node control module of the pixel circuit, and is configured to provide the first scan signal, the third scan signal and the fifth scan signal to the pixel circuit. The second gate drive circuit is connected to a control end of the second initialization module and a control end of the light-emitting control module of the pixel circuit, and is configured to provide the second scan signal and the light-emitting control signal to the pixel circuit. The third gate drive circuit is connected to a control end of the data writing module of the pixel circuit, and is configured to provide the fourth scan signal to the pixel circuit.

7. The display panel of claim 6, wherein, The first gate drive circuit comprises a plurality of cascaded first shift registers. The first shift register comprises a first input module, a first potential control module, a second potential control module, a first output module, a second output module and a third output module. An output end of the first input module is connected to a first node. The first input module is configured to transmit a first input signal to the first node in response to a first clock signal. An output end of the first potential control module is connected to a second node. An output end of the second potential control module is connected to a third node. The first potential control module is configured to transmit the first potential signal to the second node in response to the first potential signal and the first clock signal; The second potential control module is connected with the first node and the second node respectively, and configured to transmit the first clock signal to the second node in response to the potential of the first node; The first output module is connected with the first node and the second node respectively, and configured to output the second clock signal as the first scan signal in response to the potential of the first node, and / or output the second potential signal as the first scan signal in response to the potential of the second node; The second output module is connected with the first node and the second node respectively, and configured to output the third clock signal as the fifth scan signal in response to the potential of the first node, and / or output the second potential signal as the fifth scan signal in response to the potential of the second node; The third output module is connected with the first node and the second node respectively, and configured to output the fourth clock signal as the third scan signal in response to the potential of the first node, and / or output the second potential signal as the third scan signal in response to the potential of the second node; Preferably, the first input module comprises an eighth transistor, a gate of the eighth transistor is connected with the first clock signal, a first pole of the eighth transistor is connected with the first input signal, and a second pole of the eighth transistor is connected with the first node; Preferably, the first potential control module comprises a ninth transistor, a gate of the ninth transistor is connected with the first clock signal, a first pole of the ninth transistor is connected with the first potential signal, and a second pole of the ninth transistor is connected with the second node; Preferably, the second potential control module comprises a tenth transistor, a gate of the tenth transistor is connected with the first node, a first pole of the tenth transistor is connected with the first clock signal, and a second pole of the tenth transistor is connected with the second node; Preferably, the first output module comprises an eleventh transistor, a twelfth transistor, a third capacitor and a fourth capacitor; A gate of the eleventh transistor is connected with the first node and a first end of the third capacitor respectively, a first pole of the eleventh transistor is connected with the second clock signal, a second pole of the eleventh transistor is connected with a second end of the third capacitor, and the second end of the third capacitor is an output end of the first output module; A gate of the twelfth transistor is connected with the second node and a first end of the fourth capacitor respectively, a first pole of the twelfth transistor is connected with a second end of the fourth capacitor and the second potential signal, and a second pole of the twelfth transistor is connected with the second end of the third capacitor; Preferably, the second output module comprises a thirteenth transistor and a fourteenth transistor; A gate of the thirteenth transistor is connected with the first node, a first pole of the thirteenth transistor is connected with the third clock signal, and a second pole of the thirteenth transistor is an output end of the second output module; A gate of the fourteenth transistor is connected with the second node, a first electrode of the fourteenth transistor is connected with the second potential signal, and a second electrode of the fourteenth transistor is connected with a second electrode of the thirteenth transistor; Preferably, the third output module comprises a fifteenth transistor and a sixteenth transistor; A gate of the fifteenth transistor is connected with the first node, a first electrode of the fifteenth transistor is connected with the fourth clock signal, and a second electrode of the fifteenth transistor is used as an output terminal of the third output module; A gate of the sixteenth transistor is connected with the second node, a first electrode of the sixteenth transistor is connected with the second potential signal, and a second electrode of the sixteenth transistor is connected with the second electrode of the fifteenth transistor.

8. The display panel of claim 6, wherein, The second gate drive circuit comprises a plurality of cascaded second shift registers; The second shift register comprises a second input module, a third potential control module, a fourth potential control module, a fourth output module and an inverting module; An output terminal of the second input module is connected with a third node, and the second input module is configured to transmit a second input signal to the third node in response to a fifth clock signal; An output terminal of the third potential control module is connected with a fourth node; The third potential control module is configured to transmit a first potential signal to the fourth node in response to the first potential signal and the fifth clock signal; The fourth potential control module is connected with the third node and the fourth node respectively, and is configured to transmit the fifth clock signal to the fourth node in response to a potential of the third node; The fourth output module is connected with the third node and the fourth node respectively, and is configured to output a sixth clock signal as the second scanning signal in response to the potential of the third node, and / or output a second potential signal as the second scanning signal in response to a potential of the fourth node; The inverting module is connected with an output terminal of the fourth output module, and is configured to output the second scanning signal as the light-emitting control signal after inverting the second scanning signal; Preferably, the second input module comprises a seventeenth transistor, a gate of the seventeenth transistor is connected with the fifth clock signal, a first electrode of the seventeenth transistor is connected with the second input signal, and a second electrode of the seventeenth transistor is connected with the third node; Preferably, the third potential control module comprises an eighteenth transistor, a gate of the eighteenth transistor is connected with the fifth clock signal, a first electrode of the eighteenth transistor is connected with the first potential signal, and a second electrode of the eighteenth transistor is connected with the third node; Preferably, the fourth potential control module comprises a nineteenth transistor, a gate of the nineteenth transistor is connected with the third node, a first electrode of the nineteenth transistor is connected with the fifth clock signal, and a second electrode of the nineteenth transistor is connected with the fourth node; Preferably, the fourth output module comprises a twentieth transistor, a twenty-first transistor, a fifth capacitor and a sixth capacitor. The gate of the twentieth transistor is connected with the third node and the first end of the fifth capacitor respectively, the first electrode of the twentieth transistor is connected with the sixth clock signal, the second electrode of the twentieth transistor is connected with the second end of the fifth capacitor and serves as the output end of the fourth output module; The gate of the twenty-first transistor is connected with the fourth node and the first end of the sixth capacitor respectively, the first electrode of the twenty-first transistor is connected with the second end of the sixth capacitor and the second potential signal, and the second electrode of the twenty-first transistor is connected with the second end of the fifth capacitor; Preferably, the inverting module comprises a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a seventh capacitor; The gate of the twenty-second transistor is connected with the first electrode of the twenty-second transistor and the first potential signal, and the second electrode of the twenty-second transistor is connected with the first electrode of the twenty-third transistor, the gate of the twenty-fourth transistor and the first end of the seventh capacitor; The gate of the twenty-third transistor is connected with the output end of the fourth output module, and the second electrode of the twenty-third transistor is connected with the second potential signal; The first electrode of the twenty-fourth transistor is connected with the first potential signal, the second electrode of the twenty-fourth transistor is connected with the second end of the seventh capacitor and the first electrode of the twenty-fifth transistor, and serves as the output end of the inverting module; The second electrode of the twenty-fifth transistor is connected with the second potential signal.

9. The display panel of claim 6, wherein, The third gate drive circuit comprises a plurality of cascaded third shift registers; The third shift register comprises a third input module, a fifth potential control module, a sixth potential control module and a fifth output module; The output end of the third input module is connected with a fifth node, and the third input module is configured to transmit a third input signal to the fifth node in response to a seventh clock signal; The output end of the fifth potential control module is connected with a sixth node; The fifth potential control module is configured to transmit the first potential signal to the sixth node in response to the first potential signal and the seventh clock signal; The sixth potential control module is connected with the fifth node and the sixth node respectively, and is configured to transmit the seventh clock signal to the sixth node in response to the potential of the fifth node; The fifth output module is connected with the fifth node and the sixth node respectively, and is configured to output an eighth clock signal as the fourth scanning signal in response to the potential of the fifth node, and / or output a second potential signal as the fourth scanning signal in response to the potential of the sixth node; Preferably, the third input module comprises a twenty-sixth transistor, the gate of the twenty-sixth transistor is connected with the seventh clock signal, the first electrode of the twenty-sixth transistor is connected with the third input signal, and the second electrode of the twenty-sixth transistor is connected with the fifth node. Preferably, the fifth potential control module comprises a twenty-seventh transistor, a gate of the twenty-seventh transistor being connected to the seventh clock signal, a first pole of the twenty-seventh transistor being connected to the first potential signal, and a second pole of the twenty-seventh transistor being connected to the fifth node; Preferably, the sixth potential control module comprises a twenty-eighth transistor, a gate of the twenty-eighth transistor being connected to the fifth node, a first pole of the twenty-eighth transistor being connected to the seventh clock signal, and a second pole of the twenty-eighth transistor being connected to the sixth node; Preferably, the fifth output module comprises a twenty-ninth transistor, a thirtieth transistor, a seventh capacitor and an eighth capacitor; a gate of the twenty-ninth transistor being connected to the fifth node and a first end of the seventh capacitor respectively, a first pole of the twenty-ninth transistor being connected to the eighth clock signal, a second pole of the twenty-ninth transistor being connected to a second end of the seventh capacitor, and the second pole of the twenty-ninth transistor serving as an output end of the fifth output module; a gate of the thirtieth transistor being connected to the sixth node and a first end of the eighth capacitor respectively, a first pole of the thirtieth transistor being connected to a second end of the eighth capacitor and the second potential signal, and a second pole of the thirtieth transistor being connected to the second end of the seventh capacitor.

10. A display device, characterized by comprising: The display panel comprises the display panel according to any one of claims 6-9, further comprising a first input signal line, a second input signal line, a third input signal line, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line and a tenth clock signal line; the first input signal line is configured to provide a first input signal to a first-stage first shift register; a first scanning signal output by an output end of a first output module of the first shift register at an i-th stage is used as a first input signal of the first shift register at an (i+1)-th stage; i is an integer greater than or equal to 1; the second input signal line is configured to provide a second input signal to a first-stage second shift register; a second scanning signal output by an output end of a fourth output module of the second shift register at an i-th stage is used as a second input signal of the second shift register at an (i+1)-th stage; the third input signal line is configured to provide a third input signal to a first-stage third shift register; a fourth scanning signal output by an output end of a fifth output module of the third shift register at an i-th stage is used as a third input signal of the third shift register at an (i+1)-th stage; the first clock signal line is configured to provide a first clock signal to the first shift register at an odd-numbered stage and a second clock signal to the first shift register at an even-numbered stage; the second clock signal line is configured to provide a second clock signal to the first shift register at an odd-numbered stage and a first clock signal to the first shift register at an even-numbered stage; the third clock signal line is configured to provide a third clock signal to the first shift register at an odd-numbered stage; The fourth clock signal line is configured to provide a fourth clock signal for the first shift register of odd-numbered stages; The fifth clock signal line is configured to provide a third clock signal for the first shift register of even-numbered stages; The sixth clock signal line is configured to provide a fourth clock signal for the first shift register of even-numbered stages; The seventh clock signal line is configured to provide a fifth clock signal for the second shift register of odd-numbered stages, and a sixth clock signal for the second shift register of even-numbered stages; The eighth clock signal line is configured to provide a sixth clock signal for the second shift register of odd-numbered stages, and a fifth clock signal for the second shift register of even-numbered stages; The ninth clock signal line is configured to provide a seventh clock signal for the third shift register of odd-numbered stages, and an eighth clock signal for the third shift register of even-numbered stages; The tenth clock signal line is configured to provide an eighth clock signal for the third shift register of odd-numbered stages, and a seventh clock signal for the third shift register of even-numbered stages.

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