Voltage regulation circuit and memory

Abstract

The present disclosure provides a voltage regulation circuit and a memory. The voltage regulation circuit comprises a power supply generation module, a selection control signal generation module and a voltage selection module. The power supply generation module is configured to generate a plurality of groups of transistor substrate voltages, wherein each group of transistor substrate voltages corresponds to at least one state of a sensitive amplifier. The selection control signal generation module is configured to generate a corresponding selection control signal based on the current state of the sensitive amplifier. The voltage selection module is configured to receive the plurality of groups of transistor substrate voltages and the selection control signal, and to select a corresponding group of transistor substrate voltages to output to the substrate end of a transistor in the sensitive amplifier in response to the selection control signal.

Description

Technical Field

[0001] This application relates to, but is not limited to, a voltage regulation circuit and a memory. Background Technology

[0002] In the field of semiconductor memory, especially dynamic random access memory (DRAM), the sense amplifier (SA) is used to detect and amplify minute voltage differences in memory cells, and is a key component to ensure the accuracy of data read / write. As process nodes continue to shrink, the reduction in device size brings higher integration, but also exacerbates leakage current problems, especially leakage current at the junction of transistors (junction leakage), which has become an important factor affecting power consumption and performance.

[0003] In related technologies, junction leakage current is typically suppressed by optimizing the manufacturing process, such as improving gate-drain leakage current (GIDL), off-state leakage current (Ioff), or gate leakage current (Igate). However, these methods lack a mechanism that can flexibly adjust the transistor substrate voltage to effectively suppress junction leakage current for sensitive amplifiers in different states. In other words, the related technical solutions struggle to dynamically adjust the transistor substrate voltage according to the actual operating state of the sensitive amplifier, resulting in insufficiently precise leakage current control. This is particularly evident in high-density, low-power products such as LPDDR, where the overall static leakage current accumulation effect is significant, severely impacting the chip's energy efficiency and market competitiveness. Summary of the Invention

[0004] This disclosure provides a voltage regulation circuit, comprising: a power generation module configured to generate multiple sets of transistor substrate voltages; wherein each set of transistor substrate voltages corresponds to at least one state of the sensitive amplifier; each set of transistor substrate voltages includes: PMOS transistor substrate voltage and NMOS transistor substrate voltage; a selection control signal generation module configured to generate a corresponding selection control signal based on the current state of the sensitive amplifier; and a voltage selection module connected to the power generation module and the selection control signal generation module, configured to receive the multiple sets of transistor substrate voltages and the selection control signal, and, in response to the selection control signal, select a corresponding set of transistor substrate voltages to output to the substrate of the transistor in the sensitive amplifier.

[0005] In some embodiments of this disclosure, the power generation module is configured to generate three sets of transistor substrate voltages; wherein, the first set of transistor substrate voltages includes: a first-level PMOS substrate voltage and a first-level NMOS substrate voltage; the second set of transistor substrate voltages includes: a second-level PMOS substrate voltage and a second-level NMOS substrate voltage; the third set of transistor substrate voltages includes: a third-level PMOS substrate voltage and a third-level NMOS substrate voltage; the first-level PMOS substrate voltage, the second-level PMOS substrate voltage, and the third-level PMOS substrate voltage increase sequentially; the first-level NMOS substrate voltage, the second-level NMOS substrate voltage, and the third-level NMOS substrate voltage decrease sequentially.

[0006] In some embodiments of this disclosure, the selection control signal generation module is further configured to generate a first value of the selection control signal when the sensitive amplifier is in a standby state; the voltage selection module is further configured to select a first group of transistor substrate voltages to be output to the sensitive amplifier in response to the first value of the selection control signal.

[0007] In some embodiments of this disclosure, the selection control signal generation module is further configured to generate a second value of the selection control signal when the sensitive amplifier is in operation; the voltage selection module is further configured to select a second group of transistor substrate voltages to be output to the sensitive amplifier in response to the second value of the selection control signal.

[0008] In some embodiments of this disclosure, the selection control signal generation module is further configured to generate a third value of the selection control signal when the sensitive amplifier is in a working state; the voltage selection module is further configured to select a third group of transistor substrate voltages to be output to the sensitive amplifier in response to the third value of the selection control signal.

[0009] In some embodiments of this disclosure, the selection control signal generation module is further configured to generate and maintain the selection control signal of the second value until the refresh state ends when the memory block where the sensitive amplifier is located is in a refresh state; the voltage selection module is further configured to select the second group of transistor substrate voltages to be output to the sensitive amplifier in response to the selection control signal of the second value.

[0010] In some embodiments of this disclosure, the selection control signal generation module is further configured to receive and determine the current state of the sensitive amplifier based on a standby command, an activation command, and a memory block enable command; the selection control signal generation module is further configured to receive and determine that the memory block where the sensitive amplifier is located is in a refresh state based on a refresh command and a self-refresh command.

[0011] In some embodiments of this disclosure, the voltage regulation circuit further includes: a process detection control unit; the process detection control unit is configured to detect the process corner of the transistor in the sensitive amplifier; the power generation module is further configured to generate a corresponding transistor substrate voltage based on the process corner of the transistor in the sensitive amplifier; wherein the PMOS transistor substrate voltage corresponding to the SS process corner, TT process corner, and FF process corner increases sequentially; the NMOS transistor substrate voltage corresponding to the SS process corner, TT process corner, and FF process corner decreases sequentially.

[0012] In some embodiments of this disclosure, the voltage regulation circuit further includes: a temperature detection and control unit; the temperature detection and control unit is configured to detect the real-time ambient temperature of the sensitive amplifier; the power generation module is further configured to adjust the transistor substrate voltage based on changes in the ambient temperature; wherein the PMOS transistor substrate voltage increases with increasing ambient temperature; and the NMOS transistor substrate voltage decreases with increasing ambient temperature.

[0013] This disclosure also provides a memory comprising: a sensitive amplifier and a voltage regulation circuit as described above; the voltage regulation circuit is configured to output a corresponding transistor substrate voltage to the substrate of the transistor in the sensitive amplifier based on the current state of the sensitive amplifier.

[0014] It is understood that in this embodiment of the present disclosure, multiple sets of different transistor substrate voltages are set. Then, according to different states of the sensitive amplifier, corresponding substrate voltages are dynamically provided to the transistors in the sensitive amplifier. This effectively reduces the leakage current of the transistors in the sensitive amplifier and adjusts the speed performance of the sensitive amplifier during operation. In other words, this embodiment of the present disclosure balances reducing the static power consumption of the sensitive amplifier with increasing its operating speed, thereby significantly improving the performance of the sensitive amplifier. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the voltage regulation circuit provided in the embodiments of this disclosure;

[0016] Figure 2 This is a schematic diagram of the structure of the sensitive amplifier provided in the embodiments of this disclosure;

[0017] Figure 3 This is a schematic diagram of the signal of the sensitive amplifier provided in the embodiments of this disclosure;

[0018] Figure 4 This is a schematic diagram of the NMOS transistor substrate voltage switching and driving unit in the voltage regulation circuit provided in this embodiment of the present disclosure;

[0019] Figure 5 This is a schematic diagram of the structure of the PMOS transistor substrate voltage switching and driving unit in the voltage regulation circuit provided in the embodiments of this disclosure;

[0020] Figure 6 This is a schematic diagram of the transistor substrate voltage output by the voltage regulation circuit provided in this embodiment. Figure 1 ;

[0021] Figure 7 This is a schematic diagram of the transistor substrate voltage output by the voltage regulation circuit provided in this embodiment. Figure 2 ;

[0022] Figure 8 This is a schematic diagram of the transistor substrate voltage output by the voltage regulation circuit provided in this embodiment. Figure 3 ;

[0023] Figure 9 This is a schematic diagram of the structure of the memory provided in an embodiment of this disclosure. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] Figure 1 This is a schematic diagram of an optional structure for the voltage regulation circuit of the sensitive amplifier provided in an embodiment of this disclosure. For example... Figure 1As shown, the voltage regulation circuit 100 includes a power generation module 110, a selection control signal generation module 120, and a voltage selection module 130. The power generation module 110 is configured to generate multiple sets of transistor substrate voltages (including VSubN1 and VSubP1, VSubN2 and VSubP2, VSubN3 and VSubP3); wherein each set of transistor substrate voltages corresponds to at least one state of the sensitive amplifier 200. The selection control signal generation module 120 is configured to generate a corresponding selection control signal Sel<2:0> based on the current state of the sensitive amplifier 200. The voltage selection module 130 is connected to both the power generation module 110 and the selection control signal generation module 120. The voltage selection module 130 is configured to receive multiple sets of transistor substrate voltages and the selection control signal Sel<2:0>, and in response to the selection control signal Sel<2:0>, select a corresponding set of transistor substrate voltages VBN and VBP and output them to the substrate terminals of the transistors in the sensitive amplifier 200.

[0026] In this embodiment of the disclosure, each group of transistor substrate voltages includes: PMOS substrate voltage and NMOS substrate voltage. The PMOS substrate voltage is used to transmit data to the substrate terminal of the PMOS transistor in the sensitive amplifier 200, and the NMOS substrate voltage is used to transmit data to the substrate terminal of the NMOS transistor in the sensitive amplifier 200.

[0027] In some embodiments of this disclosure, reference is made to Figure 1 The voltage selection module 130 may include an NMOS substrate voltage switching and driving unit 131 and a PMOS substrate voltage switching and driving unit 132. The NMOS substrate voltage switching and driving unit 131 can switch and drive the NMOS substrate voltages VSubN1, VSubN2 and VSubN3 among multiple sets of transistor substrate voltages. Correspondingly, the PMOS substrate voltage switching and driving unit 132 can switch and drive the PMOS substrate voltages VSubP1, VSubP2 and VSubP3 among multiple sets of transistor substrate voltages.

[0028] Figure 2 This is a schematic diagram of an optional structure of the sensitive amplifier in an embodiment of this disclosure. (Reference) Figure 2 The sensitive amplifier 200 consists of multiple transistors. These transistors include: multiple NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10, and two PMOS transistors MP1 and MP2. Figure 1 and Figure 2The substrate of the NMOS transistor in the sensitive amplifier 200 receives the substrate voltage VBN of the NMOS transistor from the voltage regulation circuit 100, and the substrate of the PMOS transistor in the sensitive amplifier 200 receives the substrate voltage VBP of the PMOS transistor from the voltage regulation circuit 100.

[0029] Continue to refer to Figure 2 The gates of transistors MN1 and MN2 serve as the two input terminals of the sensitive amplifier 200, used to receive a pair of voltages with a difference. Transistors MP1 and MP2 form a cross-coupled circuit, which amplifies the difference between voltages Sabla and Sablb, realizing the amplification function of the sensitive amplifier 200. Transistors MN7 and MN8 are turned on or off in response to the column select signal Csl, used to transmit data signals Io and Ion to the bit line Bla and complementary bit line Blb, respectively. Transistors MN3 and MN4 are turned on or off in response to the offset cancellation signal Nc, used to cancel voltage offset. Transistors MN5 and MN6 are turned on or off in response to the isolation signal Iso; wherein, during the voltage difference amplification process of the sensitive amplifier 200, transistors MN5 and MN6 are off to ensure the operation of the cross-coupled circuit; after the sensitive amplifier 200 completes the voltage difference amplification, transistors MN5 and MN6 are turned on, transmitting the amplified difference voltages Sabla and Sablb to the bit line Bla and complementary bit line Blb, respectively. Transistors MN9 and MN10 are turned on or off in response to the equalization signal Eq, and are used to pull the voltage of bit line Bla and complementary bit line Blb back to Vdd / 2 after the sensitive amplifier 200 completes the voltage difference amplification.

[0030] Figure 3 for Figure 2 The signal waveform corresponding to the sensitive amplifier is shown below. Combined with... Figure 2 and Figure 3 The states of the sensitive amplifier 200 can include: standby state St1, working state St2, and working completed state St3.

[0031] Combination Figure 2 and Figure 3 During the standby phase St1, bit line Bla and complementary bit line Blb do not transmit data signals, and bit line Bla and complementary bit line Blb maintain basically the same voltage.

[0032] Combination Figure 2 and Figure 3In operating state St2, due to the data signal, a voltage difference exists between bit line Bla and complementary bit line Blb. This results in a voltage difference between the gate voltages of transistors MN1 and MN2, causing them to turn on at different degrees. Consequently, a pair of voltages with a difference, Sabla and Sablb, are formed in the sensitive amplifier 200. The cross-coupled circuit composed of transistors MP1 and MP2 amplifies the difference between Sabla and Sablb, further increasing the higher voltage and further decreasing the lower voltage. Then, under the control of the isolation signal Iso, transistors MN5 and MN6 turn on, and the amplified voltage difference Sabla and Sablb are transmitted to bit line Bla and complementary bit line Blb respectively, thereby amplifying the data signal.

[0033] Combination Figure 2 and Figure 3 In the completed state St3, bit line Bla and complementary bit line Blb transmit the amplified data signal. After the data signal transmission is complete, the voltages of bit line Bla and complementary bit line Blb are pulled back to be basically the same, thus entering the standby stage St1 again.

[0034] It is understood that in this embodiment, multiple sets of different transistor substrate voltages are set. Then, according to different states of the sensitive amplifier 200, corresponding substrate voltages are dynamically provided to the transistors in the sensitive amplifier 200. This effectively reduces the leakage current of the transistors in the sensitive amplifier 200 and adjusts the speed performance of the sensitive amplifier 200 during operation. In other words, this embodiment balances reducing the static power consumption of the sensitive amplifier 200 and increasing its operating speed, thereby significantly improving the performance of the sensitive amplifier 200.

[0035] In some embodiments of this disclosure, combined with Figure 1 and Figure 3 The power generation module 110 can generate three sets of transistor substrate voltages. The first set of transistor substrate voltages includes: a first-level PMOS substrate voltage VSubP1 and a first-level NMOS substrate voltage VSubN1; the second set of transistor substrate voltages includes: a second-level PMOS substrate voltage VSubP2 and a second-level NMOS substrate voltage VSubN2; and the third set of transistor substrate voltages includes: a third-level PMOS substrate voltage VSubP3 and a third-level NMOS substrate voltage VSubN3.

[0036] Continue to combine Figure 1 and Figure 3The first set of transistor substrate voltages VSubN1 and VSubP1 corresponds to the standby state St1 of the sensitive amplifier 200; the second set of transistor substrate voltages VSubN2 and VSubP2 corresponds to the operating state St2 of the sensitive amplifier 200; and the third set of transistor substrate voltages VSubN3 and VSubP3 corresponds to the completed operating state St3 of the sensitive amplifier 200. In other words, when the sensitive amplifier is in standby state St1, the voltage regulation circuit 100 outputs the first set of transistor substrate voltages VSubN1 and VSubP1 to the substrate terminals of the transistors in the sensitive amplifier 200; when the sensitive amplifier is in operating state St2, the voltage regulation circuit 100 outputs the second set of transistor substrate voltages VSubN2 and VSubP2 to the substrate terminals of the transistors in the sensitive amplifier 200; and when the sensitive amplifier is in the completed operating state St3, the voltage regulation circuit 100 outputs the third set of transistor substrate voltages VSubN3 and VSubP3 to the substrate terminals of the transistors in the sensitive amplifier 200.

[0037] In some embodiments of this disclosure, reference is made to Figure 6 The substrate voltages of the first-level PMOS transistor, VsubP1, the second-level PMOS transistor, VSubP2, and the third-level PMOS transistor, VSubP3, increase sequentially; while the substrate voltages of the first-level NMOS transistor, VsubN1, the second-level NMOS transistor, VsubN3, and the third-level NMOS transistor, VsubN3, decrease sequentially.

[0038] Understandably, by designing three sets of gradient-varying PMOS and NMOS transistor substrate voltages, the transistors in the sensitive amplifier 200 can achieve the optimal substrate voltage under different states. This gradient design facilitates flexible adaptation to various states of the sensitive amplifier 200 and optimizes the balance between power consumption and performance.

[0039] In some embodiments of this disclosure, reference is made to Figure 4 and Figure 5 Both the NMOS substrate voltage switching and driving unit 131 and the PMOS substrate voltage switching and driving unit 132 include multiple switching transistors to control the output of the substrate voltage of each group of transistors respectively. The value of the selection control signal Sel<2:0> represents a specific digital or analog level to activate the corresponding transmission channel in the voltage selection module 130.

[0040] In this embodiment of the disclosure, reference is made to Figure 4The first value selection control signal Sel <0> After passing through buffer 1311, level shifter 1312, and delay unit 1313, the voltage is transmitted to the gate of switching transistor M1, causing switching transistor M1 to turn on. Thus, NMOS substrate voltage switching and driving unit 131 outputs the first-level NMOS substrate voltage VsubN1 as the substrate voltage VBN of the NMOS transistor in the sensitive amplifier. Correspondingly, refer to... Figure 5 The first value selection control signal Sel <0> After passing through buffer 1321, level converter 1322 and delay unit 1323, the voltage is transmitted to the gate of switching transistor M4, causing switching transistor M4 to turn on. As a result, PMOS transistor substrate voltage switching and driving unit 132 outputs the first PMOS transistor substrate voltage VsubP1 as the substrate voltage VBP of the PMOS transistor in the sensitive amplifier.

[0041] In this embodiment of the disclosure, reference is made to Figure 4 The second value selection control signal Sel <1> After passing through buffer 1314, level shifter 1315, and delay unit 1316, the voltage is transmitted to the gate of switching transistor M2, causing switching transistor M2 to turn on. Thus, NMOS substrate voltage switching and driving unit 131 outputs the second-level NMOS substrate voltage VsubN2 as the substrate voltage VBN of the NMOS transistor in the sensitive amplifier. Correspondingly, refer to... Figure 5 The second value selection control signal Sel <1> After passing through buffer 1324, level converter 1325 and delay unit 1326, the voltage is transmitted to the gate of switching transistor M5, causing switching transistor M5 to turn on. As a result, PMOS transistor substrate voltage switching and driving unit 132 outputs the second-level PMOS transistor substrate voltage VsubP2 as the substrate voltage VBP of the PMOS transistor in the sensitive amplifier.

[0042] In this embodiment of the disclosure, reference is made to Figure 4 The third value selection control signal Sel <2> After passing through buffer 1317, level shifter 1318, and delay unit 1319, the voltage is transmitted to the gate of switching transistor M3, causing switching transistor M3 to turn on. Thus, NMOS substrate voltage switching and driving unit 131 outputs the third-level NMOS substrate voltage VsubN3 as the substrate voltage VBN of the NMOS transistor in the sensitive amplifier. Correspondingly, refer to... Figure 5 The third value selection control signal Sel <2> After passing through buffer 1327, level converter 1328 and delay unit 1329, the signal is transmitted to the gate of switching transistor M6, causing switching transistor M6 to turn on. As a result, PMOS transistor substrate voltage switching and driving unit 132 outputs the third-level PMOS transistor substrate voltage VsubP3 as the substrate voltage VBP of the PMOS transistor in the sensitive amplifier.

[0043] In this embodiment of the disclosure, reference is made to Figure 4 and Figure 5 Each buffer is used to buffer the selection control signals Sel<2:0>. Each level shifter is used to increase the level of the selection control signals Sel<2:0> to ensure that the switching transistor is fully turned on. Each delay is used to adjust the delay of the selection control signals Sel<2:0>.

[0044] In some embodiments of this disclosure, combined with Figure 1 and Figure 6 The selection control signal generation module 120 is also configured to generate a first value selection control signal Sel when the sensitive amplifier 200 is in standby state St1. <0> Accordingly, the voltage selection module 130 is also configured to respond to the selection control signal Sel of the first value. <0> The first set of transistor substrate voltages VSubN1 and VSubP1 are selected and output to the sensitive amplifier 200.

[0045] In this embodiment, when the sensitive amplifier 200 is in standby state St1, a first-level PMOS substrate voltage VsubP1 and a first-level NMOS substrate voltage VsubN1 can be provided to the transistors in the sensitive amplifier 200. At this time, the source / drain voltage of the transistors in the sensitive amplifier 200 can be 0.45V, the first-level PMOS substrate voltage VsubP1 can be 0.5V, and the first-level NMOS substrate voltage VsubN1 can be 0.4V. Thus, when the sensitive amplifier 200 is in standby state St1, the source-substrate voltage difference Vsb of the PMOS transistor in the sensitive amplifier 200 is -50mV, and the source-substrate voltage difference Vsb of the NMOS transistor in the sensitive amplifier 200 is 50mV. In this way, the source-substrate voltage difference Vsb of both the PMOS and NMOS transistors is controlled to be small, thereby effectively reducing junction leakage current.

[0046] Understandably, when the sensitive amplifier 200 is in standby mode, the voltage regulation circuit 100 can select the first set of substrate voltages VSubN1 and VSubP1 to transmit to the sensitive amplifier 200. That is, the voltage regulation circuit 100 can provide the sensitive amplifier 200 with the minimum PMOS substrate voltage VsubP1 and the maximum NMOS substrate voltage VsubN1. In this way, when the sensitive amplifier 200 is not operating, the source / drain potentials of the transistors in the sensitive amplifier 200 are kept close to the substrate potential, thereby significantly reducing the junction leakage current of the transistors and achieving low-power operation.

[0047] In some embodiments of this disclosure, combined with Figure 1 and Figure 6 The selection control signal generation module 120 is also configured to generate a second-value selection control signal Sel when the sensitive amplifier 200 is in the operating state St2. <1> Accordingly, the voltage selection module 130 is also configured to respond to the selection control signal Sel of the second value. <1> The second set of transistor substrate voltages VSubN2 and VSubP2 are selected and output to the sensitive amplifier 200.

[0048] In this embodiment of the present disclosure, when the sensitive amplifier 200 is in the working state St2, a second PMOS substrate voltage VsubP2 and a second NMOS substrate voltage VsubN2 can be provided to the transistors in the sensitive amplifier 200. At this time, the second PMOS substrate voltage VsubP2 can be 0.95V and the second NMOS substrate voltage VsubN2 can be 0V.

[0049] Understandably, when the sensitive amplifier 200 is in operation, the voltage regulation circuit 100 can select the second set of substrate voltages VSubN2 and VSubP2 to be transmitted to the sensitive amplifier 200. That is, the voltage regulation circuit 100 can provide the sensitive amplifier 200 with an intermediate-range PMOS substrate voltage VsubP2 and an intermediate-range NMOS substrate voltage VsubN2. This ensures that the transistors in the sensitive amplifier 200 have a smaller threshold voltage Vt during operation, thereby improving the switching speed and response capability of the transistors and enhancing the performance of the sensitive amplifier 200.

[0050] In some embodiments of this disclosure, combined with Figure 1 and Figure 6 The selection control signal generation module 120 is also configured to generate a third-value selection control signal Sel when the sensitive amplifier 200 is in the completed operation state St3. <2> Accordingly, the voltage selection module 130 is also configured to respond to the selection control signal Sel of the third value. <2> The substrate voltages VSubN3 and VSubP3 of the third group of transistors are selected and output to the sensitive amplifier 200.

[0051] In this embodiment of the present disclosure, when the sensitive amplifier 200 is in the working completed state St3, a third-level PMOS substrate voltage VsubP3 and a third-level NMOS substrate voltage VsubN3 can be provided to the transistors in the sensitive amplifier 200. At this time, the third-level PMOS substrate voltage VsubP3 can be 1.4V and the third-level NMOS substrate voltage VsubN3 can be -0.5V.

[0052] Understandably, when the sensitive amplifier 200 is in its operational state, the voltage regulation circuit 100 can select the third set of substrate voltages VSubN3 and VSubP3 to transmit to the sensitive amplifier 200. That is, the voltage regulation circuit 100 can provide the sensitive amplifier 200 with the maximum PMOS substrate voltage VsubP3 and the minimum NMOS substrate voltage VsubN3. In this way, after the sensitive amplifier 200 completes voltage amplification, the threshold voltage Vt of the transistor in the sensitive amplifier 200 can be maintained at a high level, thereby reducing the transistor's off-state current Ioff, and thus reducing the source-drain leakage current of the transistor.

[0053] In this embodiment of the disclosure, reference is made to Figure 1 The selection control signal generation module 120 can receive the standby command, the activation command, and the memory block enable command, SecEn, and determine the current state of the sensitive amplifier 200 based on these commands. In other words, the selection control signal generation module 120 can determine whether the sensitive amplifier 200 is currently in standby, working, or working completed state based on these commands, and outputs a corresponding value from the selection control signal Sel<2:0>.

[0054] It should be noted that the Standby command, Act command, and SecEn command are command signals in the memory used to control memory operation. Specifically, the Standby command puts the memory into a low-power state to reduce energy consumption. The Act command wakes the memory from standby mode and restores it to normal operation. The SecEn command enables or configures a specific memory block or region.

[0055] In this embodiment of the disclosure, reference is made to Figure 6The rising edge of the memory block enable command SecEn is faster than the switching time of the sensitive amplifier 200 from standby state St1 to operating state St2, and the falling edge of the memory block enable command SecEn is faster than the switching time of the sensitive amplifier 200 from operating state St3 to standby state St1. In other words, the selection control signal generation module 120 can apply a certain delay based on the changing edge of the memory block enable command SecEn to determine the switching time from standby state St1 to operating state St2, and the switching time from operating state St3 to standby state St1. Furthermore, the selection control signal generation module 120 can apply a certain delay (determined according to the amplification phase time of the amplifier) ​​based on the switching time from standby state St1 to operating state St2 to determine the switching time from operating state St2 to operating state St3.

[0056] In some embodiments of this disclosure, combined with Figure 1 and Figure 7 The selection control signal generation module 120 is also configured to generate and maintain a second value of the selection control signal Sel when the memory block (Section) where the sensitive amplifier 200 is located is in refresh state St4. <1> This continues until the refresh state St4 ends. Correspondingly, the voltage selection module 130 is also configured to respond to the selection control signal Sel of the second value. <1> The second set of transistor substrate voltages VSubN2 and VSubP2 are selected and output to the sensitive amplifier 200.

[0057] In this embodiment of the disclosure, when the memory block where the sensitive amplifier 200 is located enters refresh state St4, it indicates that the memory block is performing a data hold or restore operation. In the refresh state, since data is not read or written, and related command signals (e.g., the memory block enable command SecEn) frequently switch levels, the selection control signal generation module 120 can generate and maintain a second value selection control signal Sel. <1> The delay control of the transistor substrate voltage is achieved until the refresh state ends.

[0058] It is understandable that when the memory block where the sensitive amplifier 200 is located enters refresh state St4, the selection control signal generation module 120 outputs a selection control signal Sel with a fixed value. <1> This allows for delayed control of the substrate voltage of the transistors in the sensitive amplifier 200, preventing frequent switching of the substrate voltage. This maintains the circuit's operating speed during refresh while avoiding the additional power consumption caused by frequent switching.

[0059] In this embodiment of the disclosure, reference is made to Figure 1The selection control signal generation module 120 is also configured to receive refresh command Ref and self-refresh command SelfRef, and determine the memory block where the sensitive amplifier 200 is located is in a refresh state based on refresh command Ref and self-refresh command SelfRef.

[0060] It should be noted that the stored charge in memory gradually dissipates over time, leading to data loss. Therefore, periodic refresh or self-refresh is necessary to reload this charge and maintain data stability. The refresh command Ref is externally input to the memory to activate the refresh operation; while the self-refresh command SelfRef is generated internally by the memory to activate the self-refresh operation. Both the refresh command Ref and the self-refresh command SelfRef can specify a particular number of memory blocks to perform the refresh. Therefore, the selection control signal generation module 120 can determine whether the memory block where the sensitive amplifier 200 is located is in a refresh state by using the refresh command Ref and the self-refresh command SelfRef.

[0061] In some embodiments of this disclosure, reference is made to Figure 1 The voltage regulation circuit 100 further includes a process detection control unit 141. The process detection control unit 141 is configured to detect the process corner of the transistors in the sensitive amplifier 200. The power generation module 110 is also configured to generate a corresponding transistor substrate voltage based on the process corner of the transistors in the sensitive amplifier 200.

[0062] In this embodiment of the disclosure, the process detection control unit 141 can determine the process corner of the transistors by detecting key electrical parameters (such as threshold voltage, transconductance, etc.) of the transistors in the sensitive amplifier 200.

[0063] It's important to note that process corners describe the performance range of a transistor and can include: SS (Slow-Slow), TT (Typical-Typical), or FF (Fast-Fast). SS, TT, and FF process corners represent transistors with different speeds and performance characteristics, thus exhibiting differences during operation. Specifically, SS process corners indicate a slower transistor with weaker drive capability; TT process corners indicate a medium-speed transistor; and FF process corners indicate a faster transistor with stronger drive capability.

[0064] In this embodiment of the disclosure, combined with Figure 1 and Figure 8The power generation module 110 can adjust the magnitude of the generated transistor substrate voltage based on the process corner information detected by the process detection and control unit 141. Specifically, the PMOS transistor substrate voltage VBP corresponding to the SS, TT, and FF process corners increases sequentially, while the NMOS transistor substrate voltage VBN corresponding to the SS, TT, and FF process corners decreases sequentially.

[0065] In other words, if the process detection control unit 141 detects that the PMOS transistor in the sensitive amplifier 200 is at the SS process corner, then the power generation module 110 outputs a smaller PMOS transistor substrate voltage VBP; if the process detection control unit 141 detects that the PMOS transistor in the sensitive amplifier 200 is at the TT process corner, then the power generation module 110 outputs a middle PMOS transistor substrate voltage VBP; if the process detection control unit 141 detects that the PMOS transistor in the sensitive amplifier 200 is at the FF process corner, then the power generation module 110 outputs a larger PMOS transistor substrate voltage VBP.

[0066] Correspondingly, if the process detection control unit 141 detects that the NMOS transistor in the sensitive amplifier 200 is at the SS process corner, then the power generation module 110 outputs a larger NMOS transistor substrate voltage VBN; if the process detection control unit 141 detects that the NMOS transistor in the sensitive amplifier 200 is at the TT process corner, then the power generation module 110 outputs a middle NMOS transistor substrate voltage VBN; if the process detection control unit 141 detects that the NMOS transistor in the sensitive amplifier 200 is at the FF process corner, then the power generation module 110 outputs a smaller NMOS transistor substrate voltage VBN.

[0067] Understandably, by introducing the process detection control unit 141, the power generation module 110 can adjust the output transistor substrate voltage according to the transistor characteristics under different process corners, providing a more suitable substrate voltage for the transistors in the sensitive amplifier 200, thereby further improving the performance of the sensitive amplifier 200.

[0068] In some embodiments of this disclosure, reference is made to Figure 1 The voltage regulation circuit 100 also includes a temperature detection and control unit 142. The temperature detection and control unit 142 is configured to detect the real-time ambient temperature of the sensitive amplifier 200. The power generation module 110 is further configured to adjust the output transistor substrate voltage based on changes in ambient temperature.

[0069] In this embodiment of the disclosure, combined with Figure 1 and Figure 8The power generation module 110 can adjust the magnitude of the generated transistor substrate voltage based on the ambient temperature information detected by the temperature detection and control unit 142. Specifically, the PMOS transistor substrate voltage VBP increases with increasing ambient temperature, while the NMOS transistor substrate voltage VBN decreases with increasing ambient temperature.

[0070] In other words, if the ambient temperature detected by the temperature detection and control unit 142 increases, the power generation module 110 will increase the output PMOS substrate voltage VBP and decrease the output NMOS substrate voltage VBN. Conversely, if the ambient temperature detected by the temperature detection and control unit 142 decreases, the power generation module 110 will decrease the output PMOS substrate voltage VBP and increase the output NMOS substrate voltage VBN.

[0071] Understandably, by introducing the temperature detection and control unit 142, the power generation module 110 can dynamically adjust the output transistor substrate voltage in response to changes in ambient temperature, providing a more suitable substrate voltage for the transistors in the sensitive amplifier 200, thereby further improving the performance of the sensitive amplifier 200.

[0072] It should be noted that, Figure 8 The PMOS transistor substrate voltage VBP shown includes Figure 1 The three PMOS transistor substrate voltages VSubP1, VSubP2, and VSubP3 are shown. Figure 8 The NMOS transistor substrate voltage VBN shown includes Figure 1 The diagram shows three NMOS transistor substrate voltage levels: VSubN1, VSubN2, and VSubN3. This means that the substrate voltage is adjusted for each level depending on the process corner or ambient temperature, and the adjustment direction is consistent for each level.

[0073] This disclosure also provides a memory, such as... Figure 9 As shown, the memory 300 includes a voltage regulation circuit 100 and a sensitive amplifier 200. The voltage regulation circuit 100 is configured to output corresponding transistor substrate voltages VBN and VBP to the substrate terminals of the transistors in the sensitive amplifier 200 based on the current state of the sensitive amplifier 200. This effectively reduces leakage current in the transistors of the sensitive amplifier 200 and adjusts the speed performance of the sensitive amplifier 200 during operation, thereby significantly improving the performance of the sensitive amplifier 200.

[0074] It should be understood that in the various embodiments of this disclosure, the sequence numbers of the processes described above do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the embodiments of this disclosure are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0075] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0076] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A voltage regulation circuit for a sensitive amplifier, characterized in that, The voltage regulation circuit includes: A power generation module is configured to generate multiple sets of transistor substrate voltages; wherein each set of transistor substrate voltages corresponds to at least one state of the sensitive amplifier; each set of transistor substrate voltages includes: PMOS transistor substrate voltage and NMOS transistor substrate voltage; The selection control signal generation module is configured to generate a corresponding selection control signal based on the current state of the sensitive amplifier. The voltage selection module, which is connected to the power generation module and the selection control signal generation module respectively, is configured to receive the multiple sets of transistor substrate voltages and the selection control signal, and select a corresponding set of transistor substrate voltages to be output to the substrate terminal of the transistor in the sensitive amplifier in response to the selection control signal.

2. The voltage regulation circuit according to claim 1, characterized in that, The power generation module is configured to generate three sets of transistor substrate voltages; The first group of transistor substrate voltages includes: a first-level PMOS substrate voltage and a first-level NMOS substrate voltage; the second group of transistor substrate voltages includes: a second-level PMOS substrate voltage and a second-level NMOS substrate voltage; the third group of transistor substrate voltages includes: a third-level PMOS substrate voltage and a third-level NMOS substrate voltage. The substrate voltage of the first-level PMOS transistor, the substrate voltage of the second-level PMOS transistor, and the substrate voltage of the third-level PMOS transistor increase sequentially; the substrate voltage of the first-level NMOS transistor, the substrate voltage of the second-level NMOS transistor, and the substrate voltage of the third-level NMOS transistor decrease sequentially.

3. The voltage regulation circuit according to claim 2, characterized in that, The selection control signal generation module is further configured to generate the selection control signal of the first value when the sensitive amplifier is in standby mode; The voltage selection module is also configured to select a first group of transistor substrate voltages to be output to the sensitive amplifier in response to the selection control signal of the first value.

4. The voltage regulation circuit according to claim 2, characterized in that, The selection control signal generation module is further configured to generate a second value of the selection control signal when the sensitive amplifier is in operation. The voltage selection module is also configured to select a second set of transistor substrate voltages to be output to the sensitive amplifier in response to the selection control signal of the second value.

5. The voltage regulation circuit according to claim 2, characterized in that, The selection control signal generation module is further configured to generate the selection control signal of a third value when the sensitive amplifier is in the working completed state; The voltage selection module is also configured to select a third group of transistor substrate voltages to be output to the sensitive amplifier in response to the selection control signal of the third value.

6. The voltage regulation circuit according to claim 2, characterized in that, The selection control signal generation module is further configured to generate and maintain the second value of the selection control signal until the refresh state ends when the memory block where the sensitive amplifier is located is in a refresh state. The voltage selection module is also configured to select a second set of transistor substrate voltages to be output to the sensitive amplifier in response to the selection control signal of the second value.

7. The voltage regulation circuit according to claim 1, characterized in that, The selection control signal generation module is also configured to receive and determine the current state of the sensitive amplifier based on standby commands, activation commands, and memory block enable commands; The selection control signal generation module is also configured to receive and determine, based on refresh commands and self-refresh commands, that the memory block where the sensitive amplifier is located is in a refresh state.

8. The voltage regulation circuit according to claim 1, characterized in that, The voltage regulation circuit further includes: a process detection and control unit; The process detection and control unit is configured to detect the process corner of the transistor in the sensitive amplifier; The power generation module is further configured to generate the corresponding transistor substrate voltage based on the process corner of the transistor in the sensitive amplifier; wherein the PMOS transistor substrate voltage corresponding to the SS process corner, TT process corner and FF process corner increases sequentially; and the NMOS transistor substrate voltage corresponding to the SS process corner, TT process corner and FF process corner decreases sequentially.

9. The voltage regulation circuit according to claim 1, characterized in that, The voltage regulation circuit further includes: a temperature detection and control unit; The temperature detection and control unit is configured to detect the real-time ambient temperature of the sensitive amplifier; The power generation module is further configured to adjust the transistor substrate voltage based on changes in the ambient temperature; wherein the PMOS transistor substrate voltage increases with increasing ambient temperature; and the NMOS transistor substrate voltage decreases with increasing ambient temperature.

10. A memory, characterized in that, The memory includes: a sensitive amplifier and a voltage regulation circuit as described in any one of claims 1 to 9; The voltage regulation circuit is configured to output a corresponding transistor substrate voltage to the substrate of the transistor in the sensitive amplifier based on the current state of the sensitive amplifier.

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