Semiconductor device having selection element

Abstract

The invention relates to a semiconductor device with a selection element. The semiconductor device includes: a cell region including a first subcell region and a second subcell region; a first peripheral circuit region adjacent to one side of the cell region in the first direction; and a second peripheral circuit region adjacent to the other side of the cell region in a second direction perpendicular to the first direction. The first subcell region includes a first memory cell disposed closer to the first and second peripheral circuit regions than the second memory cell. The second subcell region includes a second memory cell disposed farther from the first and second peripheral circuit regions. The first and second memory cells include first and second selection element layers, each selection element layer including a dielectric material containing a dopant. A dopant concentration of the first selection element layer is lower than a dopant concentration of the second selection element layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0123272, filed on September 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to semiconductor devices, and more specifically, to semiconductor devices including memory cells having a select element layer, and methods of manufacturing the semiconductor device. Background Technology

[0004] In recent years, with the increasing demand for miniaturization, low power consumption, high performance, and diversification of electronic devices, various electronic devices (such as computers and portable communication devices) require semiconductor devices capable of storing data. Researchers and industry are actively developing such semiconductor devices. These semiconductor devices include those that can store data by utilizing the characteristic of switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses (E-fuse). Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor devices capable of uniformizing the threshold voltage of memory cells regardless of their location.

[0006] Furthermore, embodiments of this disclosure relate to semiconductor devices capable of homogenizing the characteristics of memory cells.

[0007] According to one embodiment of this disclosure, a semiconductor device includes: a cell region comprising a first sub-cell region and a second sub-cell region; a first peripheral circuit region adjacent to a first side of the cell region in a first direction; and a second peripheral circuit region adjacent to a second side of the cell region in a second direction perpendicular to the first direction. The first sub-cell region includes a first memory cell disposed closer to the first and second peripheral circuit regions than a second memory cell, and the second sub-cell region includes a second memory cell disposed farther from the first and second peripheral circuit regions. The first memory cell includes a first select element layer, and the second memory cell includes a second select element layer, both of which include a dielectric material containing dopant. The dopant concentration of the first select element layer is lower than the dopant concentration of the second select element layer.

[0008] According to another embodiment of this disclosure, a semiconductor device includes: a cell region comprising a first memory cell and a second memory cell; and a first peripheral circuit region disposed adjacent to the cell region in a first direction. The first memory cell is disposed closer to the first peripheral circuit region than the second memory cell, and the first memory cell includes a first select element layer having a first threshold voltage, and the second memory cell includes a second select element layer having a second threshold voltage lower than the first threshold voltage. Attached Figure Description

[0009] Figure 1A This is a perspective view schematically illustrating a cell array of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 1B This is a top view showing the block arrangement of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 2A to 2D A cell region of a semiconductor device comprising multiple sub-cell regions according to an embodiment of the present disclosure is shown.

[0012] Figure 3 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 4A to 4H This is a cross-sectional view illustrating a method for forming a memory cell structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figures 5A to 5D This is a cross-sectional view illustrating a method for forming a memory cell structure of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0015] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more comprehensive and to fully convey the scope of the disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals denote the same parts in the various drawings and embodiments.

[0016] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0017] The accompanying drawings are not necessarily drawn to scale, and in some cases the scale may be exaggerated to clearly illustrate the features of the embodiments. When referring to the first layer as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that a third layer exists between the first layer and the second layer or the substrate.

[0018] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element described below may also be referred to as the second or third element without departing from the spirit and scope of this disclosure.

[0019] Furthermore, it should be understood that when an element is referred to as being located “between” two elements, it can be the only element between the two elements, or there may be one or more intermediate elements.

[0020] When a first element is referred to as being "on top of" a second element, it means not only that the first element is directly formed on the second element, but also that a third element exists between the first and second elements. When it is said that the first element is "on top of" a second element, it means that the first element is formed directly or indirectly on the second element or substrate.

[0021] As used herein, a “layer” refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire bottom or top layer structure, or its extent may be less than that of the bottom or top layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between or above any pair of horizontal planes between or above the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, may include one or more layers, or may have one or more layers located on, above, and / or below it.

[0022] Figure 1A A perspective view of a cell array of a semiconductor device according to an embodiment of the present disclosure is shown for illustrative purposes. Figure 1B This is a top view showing the block arrangement of the semiconductor device. (Reference) Figure 1A and 1B The cell array of the semiconductor device may include: a plurality of row interconnects RL extending parallel to a first direction X; a plurality of column interconnects CL extending parallel to a second direction Y intersecting the first direction X; and a memory cell MC disposed at the intersection between the row interconnects RL and the column interconnects CL. The memory cell MC may be configured as a column, extending along a third direction Z between the row interconnects RL and the column interconnects CL. The first direction X, the second direction Y, and the third direction Z may be perpendicular to each other.

[0023] The semiconductor device may include a cell region CA, a first peripheral circuit region PA1, and a second peripheral circuit region PA2. The first peripheral circuit region PA1 may be disposed adjacent to a first side of the cell region CA in a first direction X. For example, the first peripheral circuit region PA1 may include row interconnect driving circuitry. The second peripheral circuit region PA2 may be disposed adjacent to a second side of the cell region CA in a second direction Y. For example, the second peripheral circuit region PA2 may include column interconnect driving circuitry. Therefore, a row interconnect RL may extend from the first peripheral circuit region PA1 and pass through the cell region CA in the first direction X. A column interconnect CL may extend from the second peripheral circuit region PA2 and pass through the cell region CA in the second direction Y. The row interconnect RL and the column interconnect CL may intersect each other in the cell region CA. In one embodiment, the row interconnect RL may correspond to a word line, and the column interconnect CL may correspond to a bit line. In another embodiment, the row interconnect RL may correspond to a bit line, and the column interconnect CL may correspond to a word line. The row interconnect RL may have substantially uniform and identical resistance in the cell region CA. For example, the row interconnect RL may have the same structure, the same material, the same width, and the same thickness in the cell region CA. Column interconnects CL can have substantially uniform and identical resistance within the cell region CA. For example, column interconnects CL can have the same structure, the same material, the same width, and the same thickness within the cell region CA.

[0024] Figures 2A to 2D A cell region CA of a semiconductor device is shown, which includes sub-cell regions A1 to A4. For example, cell region CA can be divided into sub-cell regions A1 to A4. (Reference) Figures 2A to 2C The cell region CA may include a first sub-cell region A1, a second sub-cell region A2, a third sub-cell region A3, and a fourth sub-cell region A4. Sub-cell regions A1 to A4 may be divided according to their distances from a reference point P, d1 to d3, r1 to r3, and dx to dy. The reference point P may be the memory cell in cell region CA that is closest to the first peripheral circuit region PA1 and the second peripheral circuit region PA2. For example, the reference point P may be located near a first corner (e.g., the upper left corner) of cell region CA. This first corner may be closest to the first peripheral circuit region PA1 and the second peripheral circuit region PA2.

[0025] refer to Figure 2AThe cell region CA may include multiple sub-cell regions A1 to A4, which are divided by multiple boundary lines L1 to L3. Boundary lines L1 to L3 may extend along a second diagonal direction D2 to a distance of a first spacing d1, a second spacing d2, and a third spacing d3 from the reference point P in a first diagonal direction D1. Therefore, the first sub-cell region A1 may include a first storage cell MCa disposed within the first boundary line L1 from the reference point P; the second sub-cell region A2 may include a second storage cell MCb disposed between the first boundary line L1 and the second boundary line L2 from the reference point P; the third sub-cell region A3 may include a third storage cell MCc disposed between the second boundary line L2 and the third boundary line L3 from the reference point P; and the fourth sub-cell region A4 may include a fourth storage cell MCd disposed outside the third boundary line L3 from the reference point P. In one embodiment of this disclosure, the boundary lines L1 to L3 may have a serpentine shape so as not to intersect with the first to fourth storage cells MCa to MCd from a microscopic perspective.

[0026] refer to Figure 2B The cell region CA may include multiple sub-cell regions A1 to A4, which are divided by multiple concentric circular boundary curves C1 to C3. Boundary curves C1 to C3 may have a concentric circular arc shape centered on a reference point P. Therefore, the first to fourth sub-cell regions A1 to A4 may all have a fan-shaped or orbital fan-shaped shape. The first sub-cell region A1 may include a first storage cell MCa disposed within the first boundary curve C1, which has a radius r1 from the reference point P along a first diagonal direction D1. The second sub-cell region A2 may include a second storage cell MCb disposed between the first boundary curve C1 and the second boundary curve C2, where the first boundary curve C1 has a radius r1 from the reference point P, and the second boundary curve C2 has a radius r2 from the reference point P. The third sub-cell region A3 may include a third memory cell MCc disposed between the second boundary curve C2 and the third boundary curve C3. The second boundary curve C2 has a radius of a second distance r2 from the reference point P, and the third boundary curve C3 has a radius of a third distance r3 from the reference point P. The fourth sub-cell region A4 may include a fourth memory cell MCd disposed outside the third boundary curve C3. The third boundary curve C3 has a radius of a third distance r3 from the reference point P. Boundary curves C1 to C3 may also have a serpentine shape so that they do not intersect with the first to fourth memory cells MCa to MCd from a microscopic perspective.

[0027] refer to Figure 2CThe cell region CA may include multiple sub-cell regions A1 to A4, which are divided based on predetermined distances dx and dy from the reference point P in the first direction X and the second direction Y. Sub-cell regions A1 to A4 may include: a first sub-cell region A1, comprising a first storage unit MCa, disposed within a first distance dx from the reference point P in the first direction X and within a second distance dy from the reference point P in the second direction Y; a second sub-cell region A2, comprising a second storage unit MCb, disposed after the first distance dx from the reference point P in the first direction X and within the second distance dy from the reference point P in the second direction Y; a third sub-cell region A3, comprising a third storage unit MCc, disposed within the first distance dx from the reference point P in the first direction X and after the second distance dy from the reference point P in the second direction Y; and a fourth sub-cell region A4, comprising a fourth storage unit MCd, disposed after the first distance dx from the reference point P in the first direction X and after the second distance dy from the reference point P in the second direction Y.

[0028] refer to Figure 2D The cell region CA may include multiple sub-cell regions A1 to A4, which are divided based on a first distance dxa, a second distance dxb and a third distance dxc from the reference point P in the first direction X, and based on a first distance dya, a second distance dyb and a third distance dyc from the reference point P in the second direction Y. Sub-unit regions A1 to A4 may include: a first sub-unit region A1, which includes a first storage unit MCa, which is located within a first distance dxa from the reference point P in the first direction X and within a first distance dya from the reference point P in the second direction Y; a second sub-unit region A2, which includes a second storage unit MCb, which is located after the first distance dxa from the reference point P in the first direction X and within a second distance dxb, and after the first distance dya from the reference point P in the second direction Y and within a second distance dyb; a third sub-unit region A3, which includes a third storage unit MCc, which is located after the second distance dxb from the reference point P in the first direction X and within a third distance dxc, and after the second distance dyb from the reference point P in the second direction Y and within a third distance dyc; and a fourth sub-unit region A4, which includes a fourth storage unit MCd, which is located after the third distance dxc from the reference point P in the first direction X and after the third distance dyc from the reference point P in the second direction Y.

[0029] According to embodiments of this disclosure, the cell region CA may include at least two or more sub-cell regions A1 to A4. The cell region CA may be divided into at least two or more sub-cell regions. According to embodiments of this disclosure, the cell region CA may be divided into multiple sub-cell regions A1 to A4, from the sub-cell region A1 closest to the reference point P to the sub-cell region A4 furthest from the reference point P.

[0030] Figure 3 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown. (Reference) Figure 3 The semiconductor device may include first to fourth memory cell structures 100a to 100d. The first to fourth memory cell structures 100a to 100d may include a lower interconnect 10, first to fourth memory cells MCa to MCd disposed above the lower interconnect 10, and upper interconnects 70 respectively disposed above the first to fourth memory cells MCa to MCd. The first to fourth memory cells 100a to 100d may all have a columnar shape.

[0031] The lower interconnect 10 can correspond to Figure 1A and Figure 1B The row interconnect RL in the middle. The upper interconnect 70 can correspond to the row interconnect RL in the middle. Figure 1A and Figure 1B The column interconnect CL. Both the lower interconnect 10 and the upper interconnect 70 may include at least one of the following: a metal layer such as tungsten (W), a metal compound layer such as titanium nitride (TiN), a metal alloy layer, and a metal silicide layer.

[0032] refer to Figures 2A to 2D The first storage cell structure 100a can be set in the first sub-cell area A1, the second storage cell structure 100b can be set in the second sub-cell area A2, the third storage cell structure 100c can be set in the third sub-cell area A3, and the fourth storage cell structure 100d can be set in the fourth sub-cell area A4.

[0033] The first memory cell MCa may include a lower electrode 20, a first selection element layer 30a disposed above the lower electrode 20, an intermediate electrode 40 disposed above the first selection element layer 30a, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50. The second memory cell MCb may include a lower electrode 20, a second selection element layer 30b disposed above the lower electrode 20, an intermediate electrode 40 disposed above the second selection element layer 30b, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50. The third memory cell MCc may include a lower electrode 20, a third selection element layer 30c disposed above the lower electrode 20, an intermediate electrode 40 disposed above the third selection element layer 30c, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50. The fourth memory cell MCd may include a lower electrode 20, a fourth selection element layer 30d disposed above the lower electrode 20, an intermediate electrode 40 disposed above the fourth selection element layer 30d, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50.

[0034] The lower electrode 20, the upper electrode 60, and the intermediate electrode 40 can all comprise various conductive materials, such as metals like tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), and titanium (Ti), metal nitrides like titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof. Additionally, the lower electrode 20, the intermediate electrode 40, and the upper electrode 60 can all comprise carbon electrodes.

[0035] The storage element layer 50 may include a variable resistance element. For example, the storage element layer 50 may include at least one of the following: a transition metal oxide layer, a metal oxide layer such as a perovskite-based material, a phase change material layer such as a chalcogenide-based material, a ferroelectric material layer, and a ferromagnetic material layer.

[0036] The first to fourth selector layers 30a to 30d may each contain a doped dielectric material. In one embodiment, the first to fourth selector layers 30a to 30d may each contain a doped oxide, a doped nitride, or a doped oxynitride. The first to fourth selector layers 30a to 30d may each contain at least one of doped silicon oxide, doped silicon nitride, doped silicon oxynitride, doped metal oxide, doped metal nitride, and doped metal oxynitride. The dopant may include at least one of aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic.

[0037] The first selectable element layer 30a may contain a dopant with a first dopant concentration. The second selectable element layer 30b may contain a dopant with a second dopant concentration. The second dopant concentration may be higher than the first dopant concentration. The third selectable element layer 30c may contain a dopant with a third dopant concentration. The third dopant concentration may be higher than the second dopant concentration. The fourth selectable element layer 30d may contain a dopant with a fourth dopant concentration. The fourth dopant concentration may be higher than the third dopant concentration. In one embodiment, the concentrations of the first to fourth dopants may be approximately 1E15 / cm². 3 Up to 1E16 / cm 3 Choose appropriately within the specified range.

[0038] Both the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 may have driving circuits. Therefore, the first to fourth memory cells MCa to MCd in cell region CA can provide voltages or currents at different levels than those in the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2. The memory cell closest to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 among the first to fourth memory cells MCa to MCd (e.g., the first memory cell MCa) can provide a relatively higher voltage or current compared to the other memory cells MCb to MCd. The memory cell furthest from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 among the first to fourth memory cells MCa to MCd (e.g., the fourth memory cell MCd) can provide a relatively lower voltage or current compared to the other memory cells MCa to MCc.

[0039] Therefore, memory cells closer to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 can be easily turned on compared to memory cells farther from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2. In fact, memory cells closer to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 can have a relatively lower threshold voltage (Vth) compared to memory cells farther from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2. Specifically, the first select element layer 30a of the memory cell closest to the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the first memory cell MCa) can have a relatively higher threshold voltage, while the fourth select element layer 30d of the memory cell furthest from the first peripheral circuit region PA1 and / or the second peripheral circuit region PA2 (e.g., the fourth memory cell MCd) can have a relatively lower threshold voltage. Therefore, the operation of all memory cells MCa to MCd can be inconsistent due to the difference in threshold voltage.

[0040] According to one embodiment of this disclosure, the threshold voltages of the selector elements 30a to 30d can be adjusted separately based on the dopant concentrations of the selector layers 30a to 30d contained in the memory cells MCa to MCd. The threshold voltages vary depending on the distance difference between the peripheral circuit region and the memory cells MCa to MCd, and can be substantially homogenized based on the dopant concentration differences of the selector layers 30a to 30d. Therefore, all memory cells MCa to MCd can be substantially simultaneously turned on and / or off, thereby achieving stable operation.

[0041] Figures 4A to 4H Cross-sectional views illustrating a method for forming memory cell structures 100a to 100d of a semiconductor device according to embodiments of the present disclosure. (Refer to...) Figure 4A The method may include forming a lower interconnect 10, a lower electrode material layer 20p, and an initial selection element material layer 30p on a lower layer 5 having a first sub-unit region A1 to a fourth sub-unit region A4.

[0042] The lower layer 5 may include a single or multiple dielectric layers disposed above the silicon layer. For example, the lower layer 5 may include a silicon oxide layer or a silicon nitride layer.

[0043] Forming the lower interconnect 10 may include forming a plurality of interconnects extending parallel to the horizontal direction by performing a deposition process, a photolithography process, and a patterning process. The material of the lower interconnect 10 may include a metal, such as tungsten (W). In one embodiment of this disclosure, the lower interconnect 10 may include a metal compound, such as titanium nitride (TiN).

[0044] Forming the lower electrode material layer 20p may include forming a metal compound, such as titanium nitride (TiN), on the lower interconnect 10 by performing a deposition process. In one embodiment of this disclosure, the lower interconnect electrode material layer 20p may include a metal layer or a metal silicide layer.

[0045] Forming the initial selected element material layer 30p may include forming a dielectric layer by performing a deposition process. The dielectric layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, and metal oxynitride.

[0046] refer to Figure 4B The method may further include performing a first doping process to dope an initial selected element material layer 30p with a dopant. Thereby, the initial selected element material layer 30p may be modified into a first selected element material layer 31 having a first dopant concentration. The dopant may include at least one selected from aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic.

[0047] refer to Figure 4CThe method may further include: forming a first doped mask pattern M1, the first doped mask pattern M1 covering a first selectable element material layer 31 in a first sub-cell region A1 and exposing the first selectable element material layer 31 in second to fourth sub-cell regions A2 to A4; and performing a second doping process to further dope the exposed first selectable element material layer 31 in the second to fourth sub-cell regions A2 to A4 with a dopant. The first selectable element material layer 31 in the second to fourth sub-cell regions A2 to A4 may be modified into a second selectable element material layer 32. The dopant may include at least one of aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic. The second selectable element material layer 32 may have a second dopant concentration, and the second dopant concentration may be higher than the first dopant concentration. The first doped mask pattern M1 may include an organic pattern (e.g., photoresist) or an inorganic dielectric pattern. The method may further include: performing a first stripping process to remove the first doped mask pattern M1.

[0048] refer to Figure 4D The method may further include: forming a second doped mask pattern M2, the second doped mask pattern M2 covering a first selective element material layer 31 of a first sub-cell region A1 and a second selective element material layer 32 of a second sub-cell region A2, and exposing second selective element material layers 32 of third and fourth sub-cell regions A3 and A4; and performing a third doping process to further dope dopant into the second selective element material layers 32 exposed in the third and fourth sub-cell regions A3 and A4. The second selective element material layers 32 in the third and fourth sub-cell regions A3 and A4 may be modified into a third selective element material layer 33. The dopant may include at least one of aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic. The third selective element material layer 33 may have a third dopant concentration, and the third dopant concentration may be higher than the second dopant concentration. The second doped mask pattern M2 may contain the same material as the first doped mask pattern M1. The method may further include: performing a second stripping process to remove the second doped mask pattern M2.

[0049] refer to Figure 4EThe method may further include: forming a third doped mask pattern M3, which covers a first selective element material layer 31 of a first sub-cell region A1, a second selective element material layer 32 of a second sub-cell region A2, and a third selective element material layer 33 of a third sub-cell region A3, and exposes a third selective element material layer 33 of a fourth sub-cell region A4; and performing a fourth doping process to further dope the exposed third selective element material layer 33 in the fourth sub-cell region A4 with a dopant. The third selective element material layer 33 in the fourth sub-cell region A4 may be modified into a fourth selective element material layer 34. The dopant may include at least one of aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic. Therefore, the fourth selective element material layer 34 may have a fourth dopant concentration, and the fourth dopant concentration may be higher than the third dopant concentration. The third doped mask pattern M2 may contain the same material as the first doped mask pattern M1 and / or the second doped mask pattern M2. The method may further include performing a third stripping process to remove the third doped mask pattern M3.

[0050] refer to Figure 4F The method may further include performing a deposition process on the first to fourth selectable element material layers 31 to 34 in the first to fourth sub-unit regions A1 to A4 to form an intermediate electrode material layer 40p, a storage element material layer 50p, and an upper electrode material layer 60p. Forming the intermediate electrode material layer 40p may include performing a deposition process to form a carbon layer. Forming the storage element material layer 50p may include performing a deposition process to form one of a transition metal oxide layer, a metal oxide layer (e.g., a perovskite-based material), a phase change material layer (e.g., a chalcogenide-based material), a ferroelectric material layer, and a ferromagnetic material layer. Forming the upper electrode material layer 60p may include performing a deposition process to form at least one of a metal layer such as tungsten (W), a metal compound layer such as titanium nitride (TiN), a metal alloy layer, and a metal silicide layer.

[0051] refer to Figure 4GThe method may further include: forming a hard mask pattern HM on the upper electrode material layer 60p in the first to fourth sub-cell regions A1 to A4, and performing a patterning process to form first to fourth memory cells MCa to MCd in the first to fourth sub-cell regions A1 to A4, respectively. The first memory cell MCa may be formed in the first sub-cell region A1, the second memory cell MCb may be formed in the second sub-cell region A2, the third memory cell MCc may be formed in the third sub-cell region A3, and the fourth memory cell MCd may be formed in the fourth sub-cell region A4. The first memory cell MCa may include a lower electrode 20, a first selection element layer 30a disposed on the lower electrode 20, an intermediate electrode 40 disposed on the first selection element layer 30a, a memory element layer 50 disposed on the intermediate electrode 40, and an upper electrode 60 disposed on the memory element layer 50. The second memory cell MCb may include a lower electrode 20, a second select element layer 30b disposed above the lower electrode 20, an intermediate electrode 40 disposed above the second select element layer 30b, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50. The third memory cell MCc may include a lower electrode 20, a third select element layer 30c disposed above the lower electrode 20, an intermediate electrode 40 disposed above the third select element layer 30c, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50. The fourth memory cell MCd may include a lower electrode 20, a fourth select element layer 30d disposed above the lower electrode 20, an intermediate electrode 40 disposed above the fourth select element layer 30d, a memory element layer 50 disposed above the intermediate electrode 40, and an upper electrode 60 disposed above the memory element layer 50. The first select element layer 30a may include a dopant of a first dopant concentration. The second select element layer 30b may include a dopant of a second dopant concentration. The third selectable element layer 30c may include a dopant with a third dopant concentration. The fourth selectable element layer 30d may include a dopant with a fourth dopant concentration. The hard mask pattern HM may include an organic layer (e.g., photoresist), an inorganic layer (including silicon nitride or silicon oxide), or a metal material layer (including metal or metal compound).

[0052] refer to Figure 4H The method may further include: removing the hard mask pattern HM, forming the interlayer dielectric layer 80, and performing a planarization process. Removing the hard mask pattern HM may include performing a stripping process or a wet etching process. The hard mask pattern HM may be partially removed. For example, a portion of the hard mask pattern HM may remain on each upper electrode 60 and may be part of each upper electrode 60. The interlayer dielectric layer 80 may include silicon oxide or silicon nitride formed by performing a deposition process. The planarization process may include a chemical mechanical polishing (CMP) process. The upper surface of the interlayer dielectric layer 80 and the upper surface of the upper electrode 60 may be coplanar.

[0053] Subsequently, the method may further include forming an upper interconnect 70 on the upper electrode 60 of the first to fourth memory cells MCa to MCd (further reference). Figure 3 ).

[0054] Figures 5A to 5D Cross-sectional views illustrating a method for forming a memory cell structure 100a to 100d of a semiconductor device according to embodiments of the present disclosure.

[0055] refer to Figure 5A The method for forming the storage cell structures 100a to 100d according to embodiments of the present disclosure may include: performing a previously referenced... Figure 4A The described process includes: forming a first mask pattern M1 that exposes an initial selected element material layer 30p in a first sub-cell region A1 and covers the initial selected element material layers 30p in second to fourth sub-cell regions A2 to A4; and performing a first doping process to implant a dopant into the exposed initial selected element material layers 30p in the first sub-cell region A1. The initial selected element material layer 30p in the first sub-cell region A1 may be modified into a first selected element material layer 31. The method may further include removing the first mask pattern M1.

[0056] refer to Figure 5B The method may further include: forming a second mask pattern M2 that exposes an initial selected element material layer 30p in a second sub-cell region A2 and covers a first selected element material layer 31 in a first sub-cell region A1 and initial selected element material layers 30p in third and fourth sub-cell regions A3 and A4; and performing a second doping process to implant dopant into the exposed initial selected element material layer 30p in the second sub-cell region A2. The initial selected element material layer 30p in the second sub-cell region A2 may be modified into a second selected element material layer 32. The method may further include: removing the second mask pattern M2.

[0057] refer to Figure 5C The method may further include: forming a third mask pattern M3 that exposes an initial selected element material layer 30p of a third sub-cell region A3 and covers a first selected element material layer 31 of a first sub-cell region A1, a second selected element material layer 32 of a second sub-cell region A2, and an initial selected element material layer 30p of a fourth sub-cell region A4; and performing a third doping process to implant dopant into the exposed initial selected element material layer 30p in the third sub-cell region A3. The initial selected element material layer 30p of the third sub-cell region A3 may be modified into a third selected element material layer 33. The method may further include: removing the third mask pattern M3.

[0058] refer to Figure 5D The method may include: forming a fourth mask pattern M4 that exposes an initial selected element material layer 30p of a fourth sub-cell region A4 and covers the first to third selected element material layers 31 to 33 of the first to third sub-cell regions A1 to A3; and performing a fourth doping process to implant dopant into the exposed initial selected element material layer 30p in the fourth sub-cell region A4. The initial selected element material layer 30p of the fourth sub-cell region A4 may be modified into a fourth selected element material layer 34. The method may further include: removing the fourth mask pattern M4.

[0059] Subsequently, the method may further include: performing a previously referenced... Figures 4F to 4H The described process, and further references Figure 3 Upper interconnects 70 are formed on the upper electrodes 60 of the first to fourth memory cells MCa to MCd.

[0060] According to embodiments of this disclosure, the threshold voltage (Vth) of a memory cell can be uniformized regardless of its location.

[0061] According to embodiments of this disclosure, the characteristics and operation of the storage cells can be made more uniform and stable.

[0062] Although this disclosure has been described in conjunction with specific embodiments, those skilled in the art will understand that various modifications and improvements can be made without departing from the spirit and scope defined by the claims of this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device comprising: a cell region including a first sub-cell region and a second sub-cell region; a first peripheral circuit region adjacent to a first side of the cell region in a first direction; and a second peripheral circuit region adjacent to a second side of the cell region in a second direction perpendicular to the first direction, wherein: the first sub-cell region includes a first memory cell disposed closer to the first peripheral circuit region and the second peripheral circuit region than a second memory cell; the second sub-cell region includes the second memory cell disposed farther from the first peripheral circuit region and the second peripheral circuit region; the first memory cell includes a first selection element layer, and the second memory cell includes a second selection element layer, each of the first selection element layer and the second selection element layer including a dielectric material containing a dopant; and a dopant concentration of the first selection element layer is lower than a dopant concentration of the second selection element layer. each of the first selection element layer and the second selection element layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, a metal oxide, a metal nitride, and a metal oxynitride.

2. The semiconductor device of claim 1, wherein, the dopant includes at least one of aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic.

3. The semiconductor device of claim 1, wherein, 4. The semiconductor device according to claim 1, wherein: the cell region further includes a third sub-cell region including a third memory cell disposed farther from the first peripheral circuit region than the second memory cell; the third memory cell includes a third selection element layer including a dielectric material containing a dopant; and a dopant concentration of the third selection element layer is higher than the dopant concentration of the second selection element layer.

5. The semiconductor device according to claim 1, wherein: the first memory cell includes a first lower electrode, the first selection element layer disposed over the first lower electrode, a first intermediate electrode disposed over the first selection element layer, a first storage element layer disposed over the first intermediate electrode, and a first upper electrode disposed over the first storage element layer; and the second memory cell includes a second lower electrode, the second selection element layer disposed over the second lower electrode, a second intermediate electrode disposed over the second selection element layer, a second storage element layer disposed over the second intermediate electrode, and a second upper electrode disposed over the second storage element layer. each of the first intermediate electrode and the second intermediate electrode includes a carbon layer.

6. The semiconductor device of claim 5, wherein, each of the first storage element layer and the second storage element layer includes a variable resistance element.

7. The semiconductor device of claim 5, wherein, each of the first lower electrode, the first upper electrode, the second lower electrode, and the second upper electrode includes at least one of a metal and a metal compound.

8. The semiconductor device of claim 5, wherein, a thickness of the first selection element layer is the same as a thickness of the second selection element layer.

9. The semiconductor device of claim 1, wherein, 10. The semiconductor device according to claim 1, wherein: the first selection element layer has a first threshold voltage; and the second selection element layer has a second threshold voltage. The second selection element layer has a second threshold voltage lower than the first threshold voltage.

11. A semiconductor device comprising: a cell region including a first memory cell and a second memory cell; and a first peripheral circuit region disposed adjacent to the cell region in a first direction, wherein: the first memory cell is disposed closer to the first peripheral circuit region than the second memory cell; the first memory cell includes a first selection element layer having a first threshold voltage; and the second memory cell includes a second selection element layer having a second threshold voltage lower than the first threshold voltage.

12. The semiconductor device of claim 11, wherein, The first selection element layer and the second selection element layer each include a dielectric material containing a dopant, the dielectric material including one of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, and metal oxynitride containing the dopant.

13. The semiconductor device of claim 12, wherein, The dopant includes at least one of aluminum, lanthanum, niobium, vanadium, tantalum, tungsten, chromium, molybdenum, boron, nitrogen, carbon, phosphorus, and arsenic.

14. The semiconductor device according to claim 11, further comprising a second peripheral circuit region disposed adjacent to the cell region in a second direction perpendicular to the first direction, wherein, the first memory cell is disposed closer to the second peripheral circuit region than the second memory cell.

15. The semiconductor device according to claim 11, wherein: the cell region further includes a third memory cell disposed farther from the first peripheral circuit region than the second memory cell; and the third memory cell has a third threshold voltage lower than the second threshold voltage. The first selection element layer has a thickness identical to a thickness of the second selection element layer.

16. The semiconductor device of claim 11, wherein, 17. The semiconductor device according to claim 11, wherein: the first selection element layer includes a dielectric material containing a dopant at a first dopant concentration; and the second selection element layer includes a dielectric material containing a dopant at a second dopant concentration higher than the first dopant concentration.

18. The semiconductor device according to claim 11, wherein: the first memory cell includes a first lower electrode, the first selection element layer disposed over the first lower electrode, a first intermediate electrode disposed over the first selection element layer, a first storage element layer disposed over the first intermediate electrode, and a first upper electrode disposed over the first storage element layer; and the second memory cell includes a second lower electrode, the second selection element layer disposed over the second lower electrode, a second intermediate electrode disposed over the second selection element layer, a second storage element layer disposed over the second intermediate electrode, and a second upper electrode disposed over the second storage element layer.

19. The semiconductor device according to claim 18, wherein: the first intermediate electrode and the second intermediate electrode each include a carbon layer; and the first storage element layer and the second storage element layer each include a variable resistance element. ​ 20. The semiconductor device of claim 18, wherein, The first lower electrode, the first upper electrode, the second lower electrode, and the second upper electrode each include at least one of a metal and a metal compound. The first lower electrode, the first upper electrode, the second lower electrode, and the second upper electrode each include at least one of a metal and a metal compound. The first lower electrode, the first upper electrode, the second lower electrode

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