Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The plurality of memory cells correspond to intersection positions of the plurality of word lines and the plurality of bit lines, and are configured using an oxide semiconductor. The word line control circuit activates or deactivates the first word line by changing the voltage of the first word line selected in accordance with the first address. The sense amplifier circuit detects and latches data of a plurality of first memory cells connected to a first word line. The readout circuit continuously reads out the data latched in the sense amplifier circuit to the outside in accordance with a plurality of second addresses. In the read operation, after the first word line is activated, the sense amplifier circuit latches the data of the plurality of first memory cells. The word line control circuit deactivates the first word line before the readout circuit ends a continuous readout operation of continuously reading out data of the plurality of first memory cells from the sense amplifier circuit in accordance with the plurality of second addresses.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Technology

[0002] In DRAM (Dynamic Random Access Memory), memory cells consist of capacitors and transistors. Research on using oxide semiconductors for the transistors in this type of memory cell is ongoing.

[0003] However, there is a problem that the threshold voltage of transistors using oxide semiconductors varies significantly due to high temperature conditions or applied voltage. Summary of the Invention

[0004] A semiconductor memory device is provided that suppresses fluctuations in the threshold voltage of the transistors in the memory cell and has high reliability.

[0005] The semiconductor memory device of this embodiment includes multiple word lines and multiple bit lines. Multiple memory cells are arranged at intersections with the multiple word lines and multiple bit lines, and are constructed using oxide semiconductor. A word line control circuit activates or deactivates a first word line by changing the voltage of a first word line selected from the multiple word lines according to a first address. A sense amplifier circuit is connected to the multiple bit lines and detects and latches data from the multiple first memory cells connected to the first word lines. A readout circuit reads the data latched by the sense amplifier circuit to the outside according to multiple second addresses. During the readout operation, after the first word line is activated, the sense amplifier circuit latches the data from the multiple first memory cells. Before the readout circuit finishes its continuous readout operation of continuously reading data from the multiple first memory cells from the sense amplifier circuit according to multiple second addresses, the word line control circuit deactivates the first word line. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating a configuration example of the memory device according to the first embodiment.

[0007] Figure 2 This is a circuit diagram illustrating an example of the configuration of a memory cell array.

[0008] Figure 3 This is a block diagram illustrating an example of the configuration of a sense amplifier and bit lines.

[0009] Figure 4 This is a block diagram illustrating an example of the configuration of a sense amplifier and bit lines.

[0010] Figure 5 This is a timing diagram illustrating an example of the operation of the memory device according to the first embodiment.

[0011] Figure 6This is a diagram showing the voltage applied to the memory cell during the read and write operations in the first embodiment.

[0012] Figure 7 This is a diagram showing the voltage applied to the memory cell in the standby state of the first embodiment.

[0013] Figure 8 This is a timing diagram illustrating an example of the operation of the memory device according to the second embodiment.

[0014] Figure 9 This is a block diagram illustrating a configuration example of a memory device according to the third embodiment.

[0015] Figure 10 This is a timing diagram illustrating the refresh operation of the memory device in the fourth embodiment.

[0016] Figure 11 This is a table representing an example of the refresh operation in the fourth embodiment.

[0017] Figure 12 This is a block diagram illustrating an example of the configuration of the row control circuit, column control circuit, and storage unit in the fifth embodiment. Detailed Implementation

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual. In the description and drawings, the same reference numerals are used for the same elements.

[0019] (First Embodiment) Figure 1 This is a block diagram illustrating a configuration example of the memory device 100 according to the first embodiment. The memory device 100 of the first embodiment is, for example, DRAM (Dynamic Random Access Memory).

[0020] Memory device 100, as a semiconductor memory device, is electrically connected to an external memory controller 200. Memory device 100 is configured to read and write data based on commands from memory controller 200. Memory device 100 receives, for example, address ADR, instruction CMD, data DQ, and control signal CNT from memory controller 200. Furthermore, memory device 100 sends control signal CNT and data DQ to memory controller 200. Memory device 100 includes, for example, a memory cell array 110, row control circuitry 120, column control circuitry 130, read / write circuitry 140, input / output circuitry 150, and control circuitry 160.

[0021] Memory cell array 110 is a circuit for storing data. Memory cell array 110 includes multiple subarrays 111. The multiple subarrays 111 are classified, for example, into groups of two subarrays 111. The multiple subarrays 111 include a first subarray 111A and a second subarray 111B corresponding to groups of two subarrays 111. In addition, each subarray 111 includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL. Each memory cell MC can store more than one bit of data. Each memory cell MC is configured corresponding to the intersection of one word line WL and one bit line BL, and connected between them. Row addresses are assigned to each word line WL. Column addresses are assigned to each bit line BL. Each memory cell MC can be specified by row address and column address.

[0022] The row control circuit 120, acting as a word line control circuit, controls the wiring (e.g., word lines WL) allocated to the row direction in the memory cell array 110. The row control circuit 120 selects at least one word line WL (activated) from a plurality of word lines WL based on the row address in the address ADR. Furthermore, the row control circuit 120 sets the unselected word lines WL to a non-selected state (inactive). The row control circuit 120 applies a predetermined voltage to each of the selected and unselected word lines WL. The row control circuit 120 includes, for example, a driver circuit 121 and an address decoder 122. The driver circuit 121 generates the voltage applied to the word line WL. The address decoder 122 decodes the row address. The row control circuit 120 selects the word line WL based on the decoding result of the address decoder 122. Additionally, the row control circuit 120 may be referred to as a row decoder.

[0023] Column control circuit 130 controls the wiring (e.g., bit lines BL) allocated in the column direction within the memory cell array 110. Column control circuit 130 includes, for example, an address decoder 131, a column selection circuit 132, and a sense amplifier circuit 133. Address decoder 131 decodes the column address in the address ADR. The sense amplifier circuit 133 is provided for each subarray and connected to the bit lines BL contained in that subarray. The sense amplifier circuit 133 includes multiple sense amplifiers SA corresponding to the number of subarrays and the number of bit lines BL contained in each subarray. The bit lines BL can be configured as either open-BL or folded-BL.

[0024] During the read operation, when the word line WL selected by the row control circuit 120 is activated, the data stored in the multiple memory cells MC connected to the selected word line WL is transferred to the corresponding bit lines BL of each column. The sense amplifier circuit 133 of each column detects (amplifies) the voltage change of its corresponding bit line BL and latches it. On the other hand, since the data in the memory cell MC is lost due to the data read, the sense amplifier circuit 133 writes (restores) the original data back to the memory cell MC by amplifying and latching the voltage. This read and restore operation is performed simultaneously on the bit lines BL of all columns contained in the selected subarray. In addition, the column selection circuit 132 outputs the data of one or more columns of bit lines BL selected according to the column address from all the data latched by the sense amplifier circuit 133 to the read / write circuit 140.

[0025] On the other hand, during the write operation, when write data is received from the read / write circuit 140, the column selection circuit 132 transmits the write data to the sense amplifier SA of the column selected according to the column address. The selected sense amplifier SA latches the write data and passes the write data to the bit line BL. Thus, the sense amplifier SA writes updated data to the memory cell MC. Additionally, the column control circuit 130 can be referred to as a sense amplifier or a column decoder.

[0026] The read / write circuit 140 is a circuit capable of reading data from the memory cell array 110 and writing data to the memory cell array 110. During the data read operation, the read / write circuit 140 receives read data (voltage or current) latched by the sense amplifier circuit 133 from the column control circuit 130. At this time, the read / write circuit 140 continuously reads the data latched by the sense amplifier circuit 133 to the outside according to a series of consecutively issued column addresses (burst read).

[0027] When writing data, the read / write circuit 140 receives the write data (voltage or current) to the memory cell array 110 from the outside via the input / output circuit 150 and sends it to the sense amplifier circuit 133 of the column control circuit 130. At this time, the read / write circuit 140 causes the sense amplifier circuit 133 to continuously latch the write data (burst write) according to a plurality of consecutively issued column addresses. Alternatively, the write circuit and the read circuit can be configured separately and independently.

[0028] Input / output circuit 150 is an interface circuit between memory device 100 and memory controller 200. Input / output circuit 150 receives instructions CMD, address ADR, data DQ (e.g., write data) and control signals CNT from memory controller 200. Input / output circuit 150 sends control signals CNT and data DQ (e.g., read data) to memory controller 200.

[0029] The control circuit 160 controls the row control circuit 120, column control circuit 130, and read / write circuit 140 based on the instruction CMD and control signal CNT. When the memory device 100 is DRAM, the control circuit 160, in addition to writing and reading data, also performs a refresh operation on the data within the memory cell array 110. The refresh operation involves sequentially activating multiple word lines WL according to the row address, temporarily reading the data stored in each memory cell MC and latching it into the sense amplifier circuit 133, and then writing (restoring) the data back to the memory cell MC. Furthermore, the control circuit 160 controls the row control circuit 120, column control circuit 130, and read / write circuit 140 in a timing synchronized with the clock signal CLK. In other words, in the memory device 100, data writing and data reading are performed in a timing synchronized with the clock signal CLK. The clock signal CLK can be generated internally in the memory device 100 or supplied externally. Additionally, the control circuit 160 can be referred to as a sequencer, internal controller, etc.

[0030] Furthermore, the memory device 100 is not limited to the configuration described above. For example, the memory device 100 may include a control circuit for controlling the refresh operation, a clock generation circuit, or an internal voltage generation circuit. The refresh operation is performed by a refresh command generated internally by the memory device 100 or by a signal from outside the memory device 100.

[0031] Next, the circuit configuration of the memory device 100 will be described.

[0032] Figure 2 This is a circuit diagram illustrating an example of the configuration of the memory cell array 110. Figure 2 This represents a portion of the subarray 111 contained in the storage cell array 110. Figure 2 The 3D orthogonal coordinate system shown corresponds to the extension direction of the wiring. Multiple memory cells MC are arranged in a matrix on a plane including the X and Y directions (XY plane). The memory cells MC can also be arranged in three dimensions along the X, Y, and Z directions. Furthermore, the subarray 111 also includes board lines PL. Similar to a DRAM with memory cells MC arranged in 2D, the Z direction can also be a vertical direction relative to the substrate on which the memory device 100 is disposed. Alternatively, similar to a DRAM with memory cells MC arranged in 3D, either the X or Y direction can be a vertical direction relative to the substrate.

[0033] A board line PL is a plate-shaped wiring extending along the XY plane. A board voltage, such as half the voltage of BL, is applied to the board line PL. One end of each of the multiple memory cells MC is connected to the board line PL. The other end of each of the multiple memory cells MC is connected to the corresponding bit line BL. The board line PL can also be called a board electrode or a board layer. The board line PL can be segmented according to the control unit of the subarray 111.

[0034] Each memory cell MC contains a cell transistor CT and a cell capacitor CC. The cell transistor CT and cell capacitor CC of each memory cell MC are connected in series between the corresponding bit line BL and the plate line PL. In each memory cell MC, one of the source or drain terminals of the cell transistor CT is connected to the corresponding bit line BL. The other of the source or drain terminals of the cell transistor CT is connected to node ND. The gate of the cell transistor CT is connected to the corresponding word line WL. One electrode of the cell capacitor CC is connected to node ND and to the other of the source or drain terminals of the cell transistor CT. The other electrode of the cell capacitor CC is connected to the plate line PL. The cell transistor CT is a field-effect transistor (FET) that uses oxide semiconductor at least for the channel region. The cell capacitor CC is a capacitive element such as a MIM (Metal-Insulator-Metal). The cell transistor CT can be simply referred to as a "transistor". The cell capacitor CC can be simply referred to as a "capacitor".

[0035] The unit transistor (CT) is constructed using oxide semiconductors. The channel material of the CT is made of an oxide semiconductor material, for example, comprising n-type or p-type material systems. The channel material may contain all or part of indium, gallium, zinc, and oxygen (e.g., indium gallium zinc oxide (IGZO)), and this channel material can exhibit n-type conductivity. The channel material may contain, for example, tin and oxygen (e.g., tin oxide), antimony and oxygen (e.g., antimony oxide), indium and oxygen (e.g., indium oxide), indium, tin, and oxygen (e.g., indium tin oxide), titanium and oxygen (e.g., titanium oxide), zinc and oxygen (e.g., zinc oxide), indium, zinc, and oxygen (e.g., indium zinc oxide), gallium and oxygen (e.g., gallium oxide), titanium, oxygen, and nitrogen (e.g., titanium oxynitride), ruthenium and oxygen (e.g., ruthenium oxide), or tungsten and oxygen (e.g., tungsten oxide). The thickness of the channel material is, for example, 5 nanometers to 30 nanometers.

[0036] The material constituting the channel region of the unit transistor CT is preferably a crystalline oxide semiconductor, but it can also be an amorphous oxide semiconductor. Specific examples of oxide semiconductors include zinc tin oxide (ZTO), IGZO (also known as gallium indium zinc oxide (GIZO)), indium zinc oxide (IZO), ZnOx, InOx, In2O3, SnO2, TiOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaxSiyOz, and other similar materials.

[0037] The subarray 111 contains multiple word lines WL extending along the X direction and arranged in the Y direction. Each word line WL is connected to the gate of the cell transistor CT of each of the multiple memory cells MC arranged in the X direction. In other words, each word line WL is connected to the gate of the cell transistor CT of each of the multiple memory cells MC assigned the same row address. In addition, the gate of the cell transistor CT can be referred to as the "control electrode of the memory cell MC".

[0038] Subarray 111 contains multiple bit lines BL that extend along the Y direction and are arranged in the X direction. Each bit line BL is connected to the source or drain of the cell transistor CT of each of the multiple memory cells MC arranged in the Y direction. In other words, each bit line BL is connected to the source or drain of the cell transistor CT of each of the multiple memory cells MC that are assigned the same column address.

[0039] The cell transistor CT is a switch that toggles the electrical connection or electrical isolation between the cell capacitor CC and the bit line BL. The cell transistor CT functions as the selection element for the memory cell MC. The cell capacitor CC holds the charge corresponding to data of one or more bits. The cell capacitor CC functions as a memory element within the memory cell MC. The cell capacitor CC is a ferroelectric capacitor and can also be a polarization-retained non-volatile memory.

[0040] Figure 3 and Figure 4 This is a block diagram illustrating an example of the configuration of the sense amplifier SA and the bit line BL. This embodiment has a configuration of 1 unit / bit, where 1 storage unit MC stores 1 bit of data.

[0041] exist Figure 3In this configuration, memory cells MC are arranged in a ratio of one cell at the intersection of two word lines WL and bit lines BL. Within a subarray 111, two adjacent bit lines BL in the Y direction are connected to one sense amplifier SA. That is, a sense amplifier SA (with folded bit line configuration) is provided for each pair of bit lines BL within the same subarray 111. In this case, data is read out from two readout cells of the two bit lines BL one by one. The sense amplifier SA compares and detects the data from one of the pair of bit lines BL with the data from the reference bit line BL of the other.

[0042] exist Figure 4 In this configuration, each of the two adjacent subarrays 111 in the X direction contains two bit lines BL connected to a sense amplifier SA. That is, the sense amplifier SA is positioned between two adjacent subarrays 111, configured for each pair of bit lines BL contained in the two subarrays 111 (open bit line configuration). In this case, the word line WL of either the left or right subarray is selected to read data. The sense amplifier SA compares and detects the data from one pair of bit lines BL with the data from a reference bit line BL of the other.

[0043] The memory device 100 in this embodiment can be used Figure 3 and Figure 4 It can be composed of any type of bit line.

[0044] Here, the PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability) characteristics of transistors using oxide semiconductors are explained.

[0045] If a positive or negative bias voltage is continuously applied between the gate and drain, or between the gate and source, of an oxide semiconductor transistor for an extended period, its threshold voltage will fluctuate significantly. For example, if a positive bias voltage is continuously applied to the transistor for an extended period, the threshold voltage of the transistor will increase with the application time (PBTI characteristic). On the other hand, if a negative bias voltage is continuously applied to the transistor for an extended period, the threshold voltage of the transistor will decrease with the application time (NBTI characteristic). If the threshold voltage of the cell transistor CT of the memory cell MC fluctuates significantly, the memory cell MC will not operate and will become a faulty bit. Therefore, it is preferable that the fluctuation of the threshold voltage of the cell transistor CT be as small as possible. In addition, the change in threshold voltage occurs due to the capture or non-capture of charge at the interface between the channel region of the oxide semiconductor and the gate insulating film. When the movement of hydrogen ions (H+) or the like is the cause, the polarity of the change in threshold voltage is often opposite to that of the capture of charge at the interface.

[0046] If the application of either a positive or negative bias voltage is stopped and the transistor is set to no bias voltage, the fluctuation of the threshold voltage of the oxide semiconductor transistor decreases and recovers over time. Furthermore, if, after applying one of the positive or negative bias voltages to the transistor, another bias voltage of opposite polarity is applied, the fluctuation of the threshold voltage decreases and returns to its original direction over time. In other words, the PBTI and NBTI characteristics of the oxide semiconductor transistor can be restored by applying a bias voltage of one polarity, stopping the application of that bias voltage, and then applying the opposite bias voltage or setting it to no bias voltage.

[0047] Therefore, although it depends on the gate-drain voltage Vgd or gate-source voltage Vgs in the active and deactivated states, the important factor in preventing degradation of PBTI and NBTI characteristics is the ratio of the activation time to the deactivation time of the word line WL (Duty). The duty cycle is the ratio of the time a positive bias is applied to the word line WL to the time a negative bias is applied (or the time without bias) (activation time / deactivation time).

[0048] For example, when the voltages Vgd and Vgs in the active and deactivated states are of opposite polarities and have equal absolute values, the duty cycle is preferably 1. Therefore, since positive and negative bias voltages are applied equally to the transistor, transistor characteristic degradation (change) can be suppressed. Furthermore, in this embodiment, the row control circuit 120 sets the voltage of the non-select word line WL (other than the select word line WL1) to be of opposite polarity to the voltage of the select word line WL1. That is, the voltages of the word lines WL in the active and deactivated states are set to opposite polarities. Therefore, the gate-drain voltage Vgd or the gate-source voltage Vgs in the active and deactivated states are set to have opposite polarities. Thus, the duty cycle is preferably close to 1.

[0049] When the voltages Vgd or Vgs in the deactivated state are unbiased, the duty cycle is preferably as small as possible. This extends the unbiased state of the transistor, thus mitigating the degradation of PBTI and NBTI characteristics caused by bias in the active state.

[0050] Next, the operation of the memory device 100 will be explained. Hereinafter, the explanation will focus on the bit line BL, which reads data from the memory cell MC and writes it to the bit line BL.

[0051] Figure 5 This is a timing diagram illustrating an example of the operation of the memory device 100 according to the first embodiment. In this example, as a case of PBTI characteristic degradation, burst write operations are performed consecutively after a burst read operation. A burst read operation is an operation in which the read / write circuit 140 continuously reads data transferred from the memory cell MC and latched to the sense amplifier circuit 133 according to a plurality of consecutively issued column addresses and sends it to the outside. The data read at one time can be 1 bit or multiple bits (e.g., 8 bits). A burst write operation is an operation in which the read / write circuit 140 causes the sense amplifier circuit 133 to continuously latch write data from the outside according to a plurality of consecutively issued column addresses. The data latched by the sense amplifier circuit 133 follows the latch and is written to the memory cell MC at the row address selected via the bit lines BL of each column. The data written at one time can be 1 bit or multiple bits (e.g., 8 bits).

[0052] Figure 5 CLK is a clock signal generated externally or internally and supplied to the control circuit 160. CA specifies the memory bank, row address, column address, etc., using the instruction address. An instruction (Command) is a control signal that instructs the actions (read, write, refresh, etc.) to be performed in the memory cell array 110. DQ represents the data output from or input to the input / output circuit 150.

[0053] (Burst read action) control circuit 160 synchronizes with externally or internally generated clock signal CLK to activate memory device 100.

[0054] When a read instruction (READ) is issued, along with the row address of the object to be read, the row control circuit 120 selectively activates the word line WL1 according to the row address. For example, at t1, the row control circuit 120 raises the word line WL1 to a high-level voltage. Consequently, corresponding to the row address, a plurality of first memory cells MC connected to the word line WL1 are connected to the bit lines BL1 to BLn (where n is an integer of 2 or more) of their respective columns.

[0055] Data from multiple first-order memory cells is transferred to their respective bit lines BL1 to BLn. For example, in Figure 5 For t2 to t3, the voltage of bit lines BL1 to BLn increases or decreases according to the logic of the data in the first memory cell.

[0056] Next, between t3 and t4, the sense amplifier circuit 133 detects (amplifies) the data transmitted to each bit line BL. Furthermore, between t4 and t5, the sense amplifier circuit 133 latches the data transmitted to each bit line BL. At this time, the data in the first memory cell MC of all columns specified by the row address is detected and latched almost simultaneously in the sense amplifier circuit 133. By amplifying and latching the data through the sense amplifier circuit 133, the same data in each column is written back (recovered) to each first memory cell MC via bit lines BL1 to BLn.

[0057] Thus, from t1 to t5, the recovery of the first memory cell MC is terminated by detecting and latching the data of the multiple memory cells MC connected to word line WL1 by the sensing amplifier circuit 133. Therefore, in this embodiment, after the sensing amplifier circuit 133 latches the data, the row control circuit 120 deactivates word line WL1. For example, at t5, the row control circuit 120 lowers word line WL1 to a low-level voltage. As a result, the multiple first memory cells MC are disconnected from bit lines BL1 to BLn. On the other hand, the sensing amplifier circuit 133 maintains the state of latching the data of the multiple first memory cells MC.

[0058] The control circuit 160 continuously issues multiple column addresses. During t6 to t7, the read / write circuit 140 continuously reads the data DQ latched by the sense amplifier circuit 133 to the outside according to the issued multiple column addresses. That is, the read / write circuit 140 performs a burst read operation. As long as the sense amplifier circuit 133 latches data, a burst read operation can be performed. Therefore, as long as the sense amplifier circuit 133 restores the data to the first memory cell MC, there is no problem even if the word line WL1 is deactivated midway through the burst read operation. In other words, there is no problem even if the row control circuit 120 deactivates the word line WL1 before t7, when the read / write circuit 140 ends the burst read operation.

[0059] (Burst Write Operation) After issuing the WRITE instruction, the control circuit 160 continuously issues multiple column addresses.

[0060] Between t8 and t11, write data DQ is input from the outside via input / output circuit 150. Read / write circuit 140 latches the data DQ continuously in the sense amplifier circuit 133 according to multiple column addresses retrieved by instruction address CA. At this time, the write data DQ is passed to any one of the bit lines (BL1 to BLn) connected to the sense amplifier circuit 133 that latches the write data DQ.

[0061] For example, when the sense amplifier SA corresponding to bit line BL1 latches the write data DQ, at t9_1, bit line BL1 transmits a voltage according to the write data DQ. Figure 5 In the example, which represents writing data different from the data originally stored in the memory cell, the latched data corresponding to the sense amplifier SA of bit line BL1 is logically inverted, and the data of bit line BL1 is also logically inverted. However, if the latched data corresponding to the sense amplifier SA of bit line BL1 is not inverted, the data of bit line BL1 is non-inverted.

[0062] For example, when the sense amplifier SA corresponding to bit line BL2 latches the write data DQ, at t9_2, bit line BL2 transmits the voltage according to the write data DQ. Figure 5 In the example, the latched data of the sense amplifier SA corresponding to bit line BL2 is also logically inverted, and consequently, the data of bit line BL2 is also logically inverted. However, if the latched data of the sense amplifier SA corresponding to bit line BL2 is not inverted, the data of bit line BL2 is non-inverted.

[0063] The data for the other columns of sense amplifier SA and bit lines BL3 to BLn are also continuously updated according to the write data DQ. In other words, the read / write circuit 140 performs a burst write operation.

[0064] In addition, Figure 5 In this configuration, for convenience, the data on bit lines BL1 to BLn are updated sequentially column by column. That is, one column address corresponds to one column of sense amplifier SA and bit line BL. However, one column address can also correspond to multiple columns of sense amplifier SA and bit lines BL. For example, when one column address corresponds to 8 bits of data, the 8 bits of data DQ are latched simultaneously by 8 sense amplifier SAs and simultaneously transmitted to their respective 8 bit lines BL.

[0065] With the issuance of the WRITE instruction, the row control circuit 120 selectively activates the word line WL1 according to the row address extracted during the read operation. For example, at t10, the row control circuit 120 raises the word line WL1 to a high-level voltage. Consequently, corresponding to the row address, multiple first memory cells MC connected to the word line WL1 are connected to the bit lines BL1 to BLn of their respective columns. Therefore, data on bit lines BL1 to BLn is written to the multiple first memory cells MC. Even if t10 is during the execution of a burst write operation, there is no problem. When the word line WL1 is activated during a burst write operation, whenever data is written to the sense amplifier SA of a certain column, the data is written to the first memory cell MC via the bit line BL of that column.

[0066] At t11, at the point when the burst write operation for the sense amplifier circuit 133 ends, the row control circuit 120 maintains the word line WL1 active. Therefore, the data latched by the sense amplifier circuit 133 at the end of the burst write operation can also be written to the first memory cell MC via the bit line BL. In other words, during the write operation, at the point when the burst write ends, the row control circuit 120 only needs to activate the word line WL1 specified by the row address.

[0067] At t12, the row control circuit 120 deactivates the word line WL1. From t12 to t13, precharging of bit lines BL, etc., is performed.

[0068] Thus, during a burst write operation, if word line WL1 is active at the moment all write data DQ is latched into the sense amplifier circuit 133, the write data DQ can be written to multiple first memory cells MC. Therefore, the row control circuit 120 needs to activate word line WL1 before the burst write operation ends, but it can also activate word line WL1 after the burst write operation begins. Furthermore, the row control circuit 120 deactivates word line WL1 after the burst write operation ends.

[0069] like Figure 5As shown, when a READ instruction is followed by a WRITE instruction, at t4, after the data of multiple first memory cells MC are latched into the sense amplifier circuit 133, the row control circuit 120 keeps the word line WL1 inactive until at least t8 when a burst write operation begins. Furthermore, before the burst write operation ends at t11, the row control circuit 120 activates the word line WL1. That is, the row control circuit 120 pulses the voltage of the word line WL1 according to each READ instruction or WRITE instruction.

[0070] Figure 6 This is a diagram showing the voltage applied to the storage cell MC during the read and write operations in the first embodiment. Figure 7 This diagram shows the voltage applied to the memory cell MC in the standby state according to the first embodiment. Furthermore, the voltage of word line WL1 in the deactivated state is -1V to -0.5V, and the voltage of word line WL1 in the activated state is 2.5V. Additionally, the voltage of node ND is 0V when data is "0", and the voltage of node ND is 1.2V when data is "1". In the standby state, bit line BL maintains an intermediate voltage of 0.6V between data "0" and data "1".

[0071] In this case, such as Figure 6 As shown, the maximum value of the voltage Vgd or Vgs of the unit transistor CT is 2.5V when reading or writing data "0". If Figure 6 If the state persists for an extended period, the characteristics will degrade due to the PBTI of the unit transistor CT. Furthermore, as... Figure 7 As shown, the minimum value of the voltage Vgd or Vgs of the unit transistor CT becomes -2.2V in the standby state with data "1". If Figure 7 If the standby state is maintained for a long time, the characteristics will degrade due to the NBTI of the unit transistor CT.

[0072] In the example described, a maximum positive bias voltage of 2.5V and a minimum negative bias voltage of -2.2V are applied to the unit transistor CT. Thus, when the voltages Vgd and Vgs in the active and deactivated states have opposite polarities, the duty cycle is preferably close to approximately 1. Therefore, because positive and negative bias voltages are applied equally to the transistor, characteristic degradation of the unit transistor CT can be suppressed.

[0073] In the memory device 100 of this embodiment, such as Figure 5As shown, word line WL1 is activated upon receiving the READ command and deactivated before the burst read operation ends. The activation period (t1 to t5) of word line WL1 for the READ command is, for example, 50 ns. Subsequently, word line WL1 receives the WRITE command and is reactivated before the burst write to the sense amplifier circuit 133 ends, becoming active at the end of the burst write and deactivated after the burst write ends. The activation period (t10 to t12) of word line WL1 for the WRITE command is, for example, 50 ns. After the READ command is issued, the deactivation period (t5 to t10) from the deactivation of word line WL1 until the WRITE command activates word line WL1 is, for example, approximately 1100 ns. After the burst write, the precharge period (t12 to t13) is, for example, approximately 14 ns. These t1 to t13 constitute the operation unit for continuous read and write operations. In this case, the duty cycle becomes approximately 0.09((50ns×2) / (1100ns+14ns)).

[0074] As a comparative example, when continuously issuing READ and WRITE instructions using a conventional method, the line control circuit 120 keeps the word line WL1 continuously active during the period from the start of the burst read to the end of the burst write. In this case, the duty cycle (activation time / deactivation time) becomes very large. Therefore, the threshold voltage of the unit transistor CT fluctuates significantly, and the characteristic degradation caused by PBTI becomes significant. Applying this comparative example to… Figure 5 For example, if word line WL1 is kept active from the time it is activated by the READ instruction (t1) until it is deactivated (t12), the duty cycle is approximately 86 ((50ns×2+1100ns) / 14ns)).

[0075] The duty cycle of this embodiment is closer to 1 than that of the comparative example, indicating that the degradation of the PBTI characteristics of the suppression unit transistor CT is possible.

[0076] Next, refer to Figure 5 This section explains the cases where the READ or WRITE command is issued separately.

[0077] For example, in the case of issuing a separate read instruction (READ), with Figure 5Similarly for t1 to t5, the row control circuit 120 activates word line WL1, and after the sense amplifier circuit 133 latches the data, it deactivates word line WL1. The activation time of word line WL1 is, for example, 50 ns. Subsequently, a burst read of data is performed from the sense amplifier circuit 133, entering the precharge operation. The burst read period depends on the number of column addresses issued, and the shortest is a read of only one column address (e.g., 8 ns). Furthermore, the precharge operation is the same as the period for t12 to t13, for example, set to 14 ns. In this case, the deactivation time of word line WL1 is, for example, 22 ns (8 ns + 14 ns). Therefore, the duty cycle becomes approximately 2.3 (50 ns / (8 ns + 14 ns)). Thus, even if the duty cycle is relatively large, it is only about 2.3, which is very small compared to the comparative example 86, and close to 1. Therefore, it can be seen that the characteristic degradation of the suppression unit transistor CT caused by PBTI is effectively achieved. As a result, the lifespan of the memory cell MC can be extended, and the reliability of the memory device 100 can be improved.

[0078] (Second Implementation) Figure 8 This is a timing diagram illustrating an example of the operation of the memory device 100 according to the second embodiment. In the second embodiment, the row control circuit 120 makes the voltage of word line WL1 during the data detection period t1 to t2_1 of the sense amplifier circuit 133 during the read operation lower than the voltage of word line WL1 during the period t2_1 to t5 of the sense amplifier circuit 133 latching data and restoring it to the memory cell MC. The voltage of word line WL1 during the data detection period t1 to t2_1 is, for example, 1.3V. The voltage of word line WL1 during the period t2_1 to t5 of the sense amplifier circuit 133 latching data and restoring it to the memory cell MC is, for example, 2.5V. The reason why the voltage of word line WL1 during the read operation can be lower than the voltage of word line WL1 during the write operation is as follows. If it is only an operation of reading data from the memory cell MC to the sense amplifier SA, the potential of word line WL can be relatively low. In contrast, during the write operation, a data "1" that raises the potential of the bit line needs to be written to the memory cell MC. Furthermore, the potential of the word line WL needs to be at least a threshold voltage higher than the potential of the bit line BL. Therefore, the voltage of the word line WL1 during the read operation can be lower than the voltage of the word line WL1 during the write operation. Additionally, if the potential of the bit line BL in the standby state drops to 0V, the potential of the word line WL during the read operation can be further reduced. The row control circuit 120 sets the voltage of the first word line up until the sense amplifier circuit latches the data of the plurality of first memory cells to a voltage lower than the voltage of the second word line after latching the data of the plurality of first memory cells.

[0079] As described above, in order to suppress the characteristic degradation caused by PBTI, it is preferable to make the duty cycle close to or decrease to 1. In addition, in order to suppress the characteristic degradation caused by PBTI, the bias voltage (voltage Vgd, Vgs) applied to the unit transistor CT can be decreased.

[0080] For example, if Figure 6 If the voltage of word line WL1 is set from 2.5V to 1.3V, then the voltage Vgd or Vgs will drop from 2.5V to 1.3V. This can suppress the characteristic degradation of the unit transistor CT caused by PBTI.

[0081] If word lines WL1 from t1 to t2_1 are set to inactive, then the duty cycle for continuously issuing READ and WRITE instructions is approximately 0.07((25ns+50ns) / (1100ns+25ns+14ns)). This is because applying 1.3V significantly improves reliability compared to applying 2.5V.

[0082] The duty cycle for reading a single column of address using either the READ or WRITE instruction is approximately 0.53 (25ns / (25ns+8ns+14ns)).

[0083] In the second embodiment, the value is also very small compared to 86 in the comparative example, and is close to 1. Therefore, according to the second embodiment, the characteristic degradation of the unit transistor CT caused by PBTI can be suppressed. The configuration and other operations of the second embodiment are the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0084] (Third Implementation) Figure 9 This is a block diagram illustrating a configuration example of the memory device 100 according to the third embodiment. The memory device 100 of the third embodiment also includes a cache memory 170. The cache memory 170 temporarily stores data read from the read / write circuit 140, associating it with the row address and column address of the first memory cell MC storing the data. Furthermore, when the control circuit 160 reads data from the first memory cell MC at the same row and column addresses, the control circuit 160 reads the data stored in the cache memory 170 to the outside.

[0085] This reduces the number of accesses to the same first memory cell MC. In the comparative example, according to conventional methods, when consecutively issuing READ and WRITE instructions, the word line WL1 is continuously kept active for the period from the start of a burst read to the end of a burst write. Even in this case, the duty cycle can be reduced by decreasing the number of accesses. Therefore, according to the third embodiment, it helps to suppress characteristic degradation caused by PBTI.

[0086] The configuration and other operations of the third embodiment may be the same as those of the first embodiment. Alternatively, other operations of the third embodiment may also be the same as those of the comparative example.

[0087] (Fourth implementation) Figure 10 This is a timing diagram illustrating the refresh operation of the memory device 100 according to the fourth embodiment. In the refresh operation of the fourth embodiment, after latching the data of a plurality of first memory cells MC into the sense amplifier circuit 133, the data is logically inverted and written back (restored) to the plurality of first memory cells MC. In memory devices such as DRAM 100, even in standby mode, the charge on the cell capacitor CC disappears over time. Therefore, in order to maintain data, the memory device 100 needs to periodically perform a refresh operation in standby mode.

[0088] The memory device 100 of the fourth embodiment performs a refresh operation once every 100 ms in standby mode, for example. The refresh operation period is, for example, 64 ns, which is a negligible time compared to the refresh operation period. Therefore, in standby mode, the bias voltage (Vgd, Vgs) applied to the cell transistor CT depends on the data stored in the memory cell MC (the voltage of node ND).

[0089] For example, such as Figure 7 As shown, when memory cell MC stores data "1" and the voltage at node ND is 1.2V, the bias voltage applied to the cell transistor CT is -2.2V. On the other hand, when memory cell MC stores data "0" and the voltage at node ND is 0V, the bias voltage applied to the cell transistor CT is -1V. Therefore, the degradation of the NBTI characteristics of the cell transistor CT storing data "1" is more severe than that of the cell transistor CT storing data "0".

[0090] Here, during the refresh operation, when writing back data to memory cell MC in a non-inverted state, memory cell MC with data "1" is continuously subjected to a -2.2V bias voltage in standby mode. If the standby state continues for a long time, the duty cycle on the negative bias side becomes very large, and the threshold voltage of the cell transistor CT drops significantly. In other words, the NBTI characteristics of the cell transistor CT deteriorate significantly.

[0091] To suppress the degradation of the NBTI characteristics of this unit transistor CT, in the fourth embodiment, during the refresh operation, the data latched in the sense amplifier circuit 133 is logically inverted and written back (restored) to the first memory cell MC. The refresh operation is an operation that sequentially specifies the row addresses within the subarray and restores the data of multiple first memory cells MC corresponding to each row address. The refresh operation is completed by performing it on all row addresses within the subarray. Furthermore, in Figure 10 For convenience, the voltages of word line WL1, bit line BL, and node ND are shown one by one.

[0092] For example, in Figure 10 In the example, let's assume that before t1, the first storage unit MC stores the data "0" shown by the solid line.

[0093] At t1, for the refresh operation, the row control circuit 120 activates the word line WL1 corresponding to a certain row address. As a result, the data stored in the first memory cell MC is transferred to bit line BL. If the first memory cell MC stores data "0" (solid line), the voltage of node ND (e.g., 0V) is transferred to bit line BL. If the first memory cell MC stores data "1" (dashed line), the voltage of node ND (e.g., 1.2V) is transferred to bit line BL.

[0094] The sensing amplifier circuit 133 detects and latches the data of each first memory cell MC via the bit line BL.

[0095] At t2, the read / write circuit 140 inverts the data in each of the first storage cells MC latched by the sense amplifier circuit 133. The inverted data is latched by the sense amplifier circuit 133, and each of the first storage cells MC stores the inverted data.

[0096] At t3, after the data in the plurality of first memory cells MC corresponding to the row address is inverted in the sensing amplifier circuit 133, the row control circuit 120 deactivates the word line WL1 corresponding to the row address. Thus, the refresh operation of the row address ends.

[0097] Although not illustrated, the memory device 100 then performs a refresh operation on multiple memory cells MC at the next row address.

[0098] In this way, by performing refresh operations on the memory cells MC of all row addresses in the order of row addresses, one refresh operation is completed.

[0099] Subsequently, after remaining in standby mode for approximately 100ms, the next refresh operation is executed. In this next refresh operation, the inverted data stored in each memory cell (MC) is further inverted. Therefore, each memory cell (MC) stores the original data (non-inverted data).

[0100] Thus, in the fourth embodiment, whenever a refresh operation is performed, the data in each memory cell (MC) is reversed and written back. Consequently, in standby mode, each memory cell (MC) stores approximately 50% of the data "1"s and "0"s. That is, the duty cycle of the data "1"s and "0"s becomes almost 1. This helps to suppress characteristic degradation caused by NBTI.

[0101] exist Figure 10 In the example, the voltage applied to the cell transistor CT is negative (-2.2V, -1V) for both data "1" and data "0". Therefore, although the characteristic degradation of NBTI cannot be avoided, the variation is significantly suppressed compared to the variation of the threshold voltage of the memory cell MC when -2.2V (data "1") is continuously applied in standby mode. Therefore, the overall lifespan of the memory device 100 can be extended.

[0102] Furthermore, during each access in a normal read or write operation, as described above, it is considered to invert and restore the data in the memory cell MC. However, in this case, due to random access, the duty cycle may not be close to 1. That is, there is a concern that the threshold voltage of the memory cell MC may fluctuate more, and the characteristics may actually deteriorate due to NBTI. In addition, access speed or power consumption also deteriorates. Furthermore, for each row address, it is necessary to store the inverted / non-inverted flag and read the flag.

[0103] In contrast, the memory device 100 of the fourth embodiment, in its periodic refresh operation performed in standby mode, reverses and restores the data in the memory cell MC with each refresh operation. Therefore, the duty cycle becomes almost 1. That is, it can reduce fluctuations in the threshold voltage of the memory cell MC and suppress characteristic degradation caused by NBTI.

[0104] In the fourth embodiment, a reverse / non-reverse flag is required. However, the refresh operation is performed on the entire memory cell array 110 or all subarrays (111A, 111B). Therefore, only one bit of data is needed for the reverse / non-reverse flag for the memory cell array 110 or each subarray. The flag indicates whether the data of multiple memory cells MC within the memory cell array 110 or each subarray is reversed from the original data to the opposite logical data, or restored from the opposite logical data to the original data. The flag is shown below, and it is only necessary to know which word line of memory cell MC is currently being refreshed. One flag (1 bit of data) is stored for the memory cell array 110, or one flag is stored for each of the subarrays 111A, 111B. The flag can be stored in a memory (not shown) within the control circuit 160, such as a flip-flop in the peripheral circuit. Thus, in the fourth embodiment, although a reverse / non-reverse flag is required, its number of bits is very small, and it has almost no impact on the data capacity of the memory cell array 110.

[0105] Furthermore, when refreshing operations are performed sequentially according to row addresses, the memory device 100 needs to store the row address of the most recently refreshed row (the most recent row address). The original refreshed row address is stored in DRAM, so including the flag in the row address does not increase the data capacity. Alternatively, the refreshed row address can be stored in a memory (not shown) within the control circuit 160, such as a flip-flop in the peripheral circuit.

[0106] Figure 11 This is a table illustrating an example of the refresh operation in the fourth embodiment. Figure 11 The table represents the refresh actions for row addresses R1 to R3. When FLG is set to 1, it indicates a refresh action from non-reverse state N to reverse state I. When FLG is set to 0, it indicates a refresh action from reverse state I to non-reverse state N. In other words, when FLG is set to 1, the memory cell MC of the memory cell array 110 stores the original data (non-reverse data). When FLG is set to 0, the memory cell MC of the memory cell array 110 stores data reversed relative to the original data (reverse data).

[0107] t11 indicates the state before the refresh action.

[0108] At t12, refresh operations are performed on multiple first memory cells MC corresponding to row address R1. As a result, the data at row address R1 is inverted from non-inverted state N to inverted state I. At this time, row address R1 and the data marked FLG are stored in memory.

[0109] At t13, a refresh operation is performed on multiple first memory cells MC corresponding to row address R2. As a result, the data at row address R2 is inverted from non-inverted state N to inverted state I. At this time, row address R2 and the data marked FLG are stored in memory.

[0110] At t14, a refresh operation is performed on multiple first memory cells MC corresponding to row address R3. As a result, the data at row address R3 is inverted from non-inverted state N to inverted state I. At this time, the data at row address R3 and the data marked FLG are stored in memory.

[0111] When the refresh operation of all row addresses R1 to R3 is completed, the flag FLG is changed from 1 to 0. Therefore, it can be seen that the storage cell MC of the storage cell array 110 stores the data that has been reversed relative to the original data (reverse data).

[0112] At t15, a refresh operation is performed on multiple first memory cells MC corresponding to row address R1. As a result, the data at row address R1 is reversed (restored) from the inverted state I to the non-inverted state N. At this time, the data at row address R1 and the data marked FLG are stored in memory.

[0113] At t16, a refresh operation is performed on multiple first memory cells MC corresponding to row address R2. As a result, the data at row address R2 is reversed (restored) from the inverted state I to the non-inverted state N. At this time, the data at row address R2 and the data marked FLG are stored in memory.

[0114] At t17, a refresh operation is performed on multiple first memory cells MC corresponding to row address R3. As a result, the data at row address R3 is reversed (restored) from inverted state I to non-inverted state N. At this time, the data at row address R3 and the data marked FLG are stored in memory.

[0115] Thus, we return to the initial state of t11. When the refresh operation of all row addresses R1 to R3 is completed, the flag FLG is changed from 0 to 1. Therefore, it can be seen that the storage cell MC of the storage cell array 110 stores the original data (non-reversed data).

[0116] Then, repeat t12 to t17.

[0117] As one method, after the refresh operations of all row addresses R1 to R3 are completed, read and write operations (after FLG inversion) are performed. At this time, when FLG is marked as 1, the storage cell array 110, which stores the original non-inverted data, can be directly read or written. When FLG is marked as 0, the storage cell array 110, which stores inverted data, can invert (restore) the data and then read or write it.

[0118] Alternatively, read and write operations can be performed during the refresh of each word line (WL). In this case, all that is needed is the refreshed row address stored in the current memory, the data marked FLG, and the row address for which normal random access read and write operations are desired. For example, if the refresh is complete up to t13 and the refresh completion address is R2, the FLG mark is 1. Therefore, if the normal random access address number is below the refresh completion address R2, that is, if the random access address number is R1 or R2, it can be determined that the data is inverted. If the random access address number is greater than the refresh completion address R2, that is, if the random access address number is R3, it can be determined that the data is non-inverted. Similarly, for example, if the refresh is complete up to t15 and the refresh completion address is R1, the FLG mark is 0. Therefore, if the normal random access address number is below the refresh completion address R1, that is, if the random access address number is R1, it can be determined that the data is non-inverted. If the address number of the random access is greater than the refresh completion address R1, that is, if the address number of the random access is R2 or R3, it can be determined that the data is reversed.

[0119] The fourth embodiment can be combined with any of the first to third embodiments. Therefore, it is possible to suppress the degradation of both characteristics caused by PBTI and NBTI.

[0120] (Fifth Embodiment) Figure 12 This is a block diagram illustrating an example of the configuration of the row control circuit 120, column control circuit 130, and memory cell MC according to the fifth embodiment. According to the fifth embodiment, not only is oxide semiconductor used for the memory cell MC, but oxide semiconductor is also used for the channel regions of the transistors constituting the row control circuit 120 and column control circuit 130.

[0121] The transistors Tgwl and Tsink constituting the row control circuit 120 are transistors that drive the voltage of the word line WL. Transistor Tgwl applies the word drive line WDRV to the word line WL (the gate of the unit transistor CT) according to the gate voltage GWC. Furthermore, transistor Tsink applies the voltage of the reference voltage source Vss to the word line WL according to the gate voltage Sink. When using oxide semiconductors in the channel regions of transistors Tgwl and Tsink, there are concerns about their characteristic degradation. Therefore, in the fifth embodiment, the gate voltages GWC and Sink of transistors Tgwl and Tsink are pulse-driven in the same way as the word line WL. This allows the duty cycle of transistors Tgwl and Tsink to decrease, suppressing characteristic degradation caused by PBTI. For example, to set the word line WL to a high voltage, transistor Tgwl is briefly turned on (ON), and then turned off (OFF), thereby setting the word line WL to an electrically floating state under the high voltage condition. To set the word line WL to a low voltage, transistor Tsink is briefly turned on and then turned off, thus setting the word line WL to an electrically floating state under low voltage. When both transistors Tgwl and Tsink are off in standby mode or other states, and the voltage of the floating word line WL fluctuates unstablely, short pulses are periodically applied to transistor Tsink to maintain the word line WL in a low voltage state.

[0122] Furthermore, when the word line WL is separated from the word drive line WDRV, the word line WL is in a floating state. Therefore, even if transistor Tgwl is pulse-driven, the voltage of the word line WL maintains the voltage of the word drive line WDRV until transistor Tsink is turned on. Moreover, even if transistor Tsink is pulse-driven, as long as a reference voltage source Vss (or a negative voltage source) is connected to the word line WL, the voltage of the word line WL can be reduced to Vss (or a negative voltage). Therefore, there is no problem even if transistors Tgwl and Tsink are pulse-driven.

[0123] For example, the gate voltage GWC of transistor Tgwl is 3.5V in the active state and -0.5V in the deactivated state. In this case, by pulse-driving transistor Tgwl, the duty cycle of transistor Tgwl can be reduced, suppressing the characteristic degradation caused by PBTI. The same applies to transistor Tsink.

[0124] Furthermore, when the deactivation period of transistor Tgwl is much longer than the activation period, the gate voltage GWC in the deactivation state is preferably slightly close to a negative voltage or 0V (no bias). This allows the duty cycle of transistor Tgwl to decrease, suppressing characteristic degradation caused by PBTI. Additionally, when the activation and deactivation periods of transistor Tgwl are equal, it is preferable that the gate voltage GWC of transistor Tgwl has opposite polarities in the activation and deactivation states. This allows the duty cycle of transistor Tgwl to decrease, suppressing characteristic degradation caused by PBTI.

[0125] Furthermore, when the memory cell array 110 is a three-dimensional array formed by arranging memory cells MC in three dimensions, the bit lines may be configured in a hierarchical manner, where one global bit line GBL is set for each of the multiple local bit lines LBL. In this case, the select transistor Tgbc is connected between each local bit line LBL and the global bit line GBL. The transistor Tgbc constituting the column control circuit 130 selectively connects one of the multiple local bit lines LBL, specified by the column address, to the global bit line GBL. When an oxide semiconductor is used for the select transistor Tgbc, the column control circuit 130 only pulses the gate voltage of the select transistor Tgbc for a short time when needed. As a result, the duty cycle of the transistor Tgbc can be reduced, suppressing characteristic degradation caused by PBTI.

[0126] For example, the gate voltage GBC of transistor Tgbc is 2.5V in the active state and -0.5V in the deactivated state. In this case, by pulse-driving transistor Tgbc, the duty cycle of transistor Tgbc can be reduced, suppressing characteristic degradation caused by PBTI. Thus, in order to suppress the threshold voltage variation caused by PBTI and NBTI, it is preferable to set voltages Vgs and Vds to positive voltages when transistor Tgbc is in the on state and negative voltages when transistor Tgbc is in the off state, and to combine the positive and negative voltages.

[0127] Therefore, it can not only suppress the degradation of the memory cell array 110, but also suppress the degradation of the row control circuit 120 and the column control circuit 130, thus extending the lifespan of the memory device 100.

[0128] Furthermore, when the deactivation period of the transistor Tgbc is much longer than the activation period, the gate voltage GBC in the deactivation state is preferably a low negative voltage or close to 0V (no bias). This allows the duty cycle of the transistor Tgbc to decrease, suppressing characteristic degradation caused by PBTI. Additionally, when the activation and deactivation periods of the transistor Tgbc are equal, it is preferable that the gate voltage GBC of the transistor Tgbc has opposite polarities in the activation and deactivation states. This allows the duty cycle of the transistor Tgbc to decrease, suppressing characteristic degradation caused by PBTI.

[0129] The fifth embodiment can be combined with any of the first to fourth embodiments. Therefore, it is possible to suppress the degradation of the characteristics of the memory cell array 110, the row control circuit 120, and the column control circuit 130.

[0130] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, as well as the scope of the invention described in the claims of the patent application and its equivalents.

[0131] [Explanation of Symbols]

[0132] 100 memory devices

[0133] 110 memory cell array

[0134] 120-line control circuit

[0135] 130-column control circuit

[0136] 131 Address Decoder

[0137] 132-column selection circuit

[0138] 133 Sensing Amplifier Circuit

[0139] 140 Read / Write Circuit

[0140] 150 Input / Output Circuit

[0141] 160 Control Circuit

[0142] MC storage unit

[0143] CT unit transistor

[0144] CC unit capacitor

[0145] WL lettering

[0146] BL bitline

[0147] PL board line.

Claims

1. A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells provided corresponding to intersecting positions of the plurality of word lines and the plurality of bit lines, configured using an oxide semiconductor; a word line control circuit that causes a voltage of a first word line selected from the plurality of word lines in accordance with a first address to change so as to activate or deactivate the first word line; a sense amplifier circuit connected to the plurality of bit lines and that detects and latches data of a plurality of first memory cells connected to the first word line; and a read circuit that successively reads out data latched by the sense amplifier circuit to an outside in accordance with a plurality of second addresses; and wherein in a read operation, the sense amplifier circuit latches data of the plurality of first memory cells after the first word line is activated, and wherein the word line control circuit deactivates the first word line before the read circuit ends a successive read operation of successively reading out data of the plurality of first memory cells from the sense amplifier circuit in accordance with the plurality of second addresses.

2. The semiconductor memory device according to claim 1, further comprising: a write circuit that causes the sense amplifier circuit to successively latch data from the outside in accordance with the plurality of second addresses; and wherein in a write operation, the word line control circuit reactivates the first word line before the write circuit ends a successive write operation of successively writing the data from the outside to the sense amplifier circuit in accordance with the plurality of second addresses.

3. The semiconductor memory device according to claim 2, wherein in the write operation, the word line control circuit reactivates the first word line after the write circuit starts the successive write operation.

4. The semiconductor memory device according to claim 2, wherein in a case where a write operation is performed, the word line control circuit sets the first word line to a deactivated state until the successive write operation is started after data of the plurality of first memory cells is latched in the sense amplifier circuit.

5. The semiconductor memory device according to claim 1 or 2, wherein each of the memory cells includes: a transistor whose gate is connected to any one of the plurality of word lines, one of a source and a drain is connected to any one of the plurality of bit lines, and a channel region includes the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

6. The semiconductor memory device according to any one of claims 1 to 4, wherein the word line control circuit sets a voltage of the first word line until the sense amplifier circuit detects data of the plurality of first memory cells to be lower than a voltage of the first word line after data of the plurality of first memory cells is latched.

7. The semiconductor memory device according to claim 1, further comprising: a memory that temporarily holds data corresponding to the first and second addresses read out from the read circuit; and wherein data held in the memory is read out to the outside when data corresponding to the first and second addresses is read out.

8. The semiconductor memory device according to claim 1, wherein the plurality of first memory cells are provided in a plurality of memory cell groups, and the word line control circuit deactivates the first word line before the read circuit ends the successive read operation of successively reading out data of the plurality of first memory cells from the sense amplifier circuit in accordance with the plurality of second addresses, and wherein the word line control circuit reactivates the first word line before the write circuit ends the successive write operation of successively writing the data from the outside to the sense amplifier circuit in accordance with the plurality of second addresses.

9. The semiconductor memory device according to claim 1, wherein the plurality of first memory cells are provided in a plurality of memory cell groups, and the word line control circuit deactivates the first word line before the read circuit ends the successive read operation of successively reading out data of the plurality of first memory cells from the sense amplifier circuit in accordance with the plurality of second addresses, and wherein the word line control circuit reactivates the first word line before the write circuit ends the successive write operation of successively writing the data from the outside to the sense amplifier circuit in accordance with the plurality of second addresses. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 8. The semiconductor storage device according to claim 1 or 2, wherein the word line control circuit sets the voltage of the word line other than the first word line among the plurality of word lines to the polarity opposite to that of the first word line.

9. The semiconductor storage device according to claim 1 or 2, wherein the word line control circuit has a mechanism for driving the voltage of the first word line to the positive polarity, a mechanism for driving the voltage of the first word line to the negative polarity, and a mechanism for setting the first word line to be floating for a longer time than the time for driving the first word line to the positive or negative polarity.

10. The semiconductor storage device according to claim 1 or 2, wherein the word line control circuit has a transistor including an oxide semiconductor in a channel region.

11. The semiconductor storage device according to claim 1 or 2, wherein the plurality of bit lines correspond to one global bit line, further comprising: a selection transistor connected between the plurality of bit lines and the global bit line and including an oxide semiconductor in a channel region; and the selection transistor is driven so that the voltage of its gate changes between two potentials of different polarities.

12. The semiconductor storage device according to claim 8, wherein each of the memory cells includes: a transistor having a gate connected to any of the plurality of word lines, one of a source and a drain connected to any of the plurality of bit lines, and a channel region including the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

13. The semiconductor storage device according to claim 9, wherein each of the memory cells includes: a transistor having a gate connected to any of the plurality of word lines, one of a source and a drain connected to any of the plurality of bit lines, and a channel region including the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

14. The semiconductor storage device according to claim 10, wherein each of the memory cells includes: a transistor having a gate connected to any of the plurality of word lines, one of a source and a drain connected to any of the plurality of bit lines, and a channel region including the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

15. The semiconductor storage device according to claim 11, wherein each of the memory cells includes: a transistor having a gate connected to any of the plurality of word lines, one of a source and a drain connected to any of the plurality of bit lines, and a channel region including the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

16. A semiconductor storage device comprising: a plurality of memory cells provided corresponding to the intersection positions of a plurality of word lines and a plurality of bit lines, and configured using an oxide semiconductor; a word line control circuit that changes the voltage of a first word line selected from the plurality of word lines in accordance with a first address to activate or deactivate the first word line; a sense amplifier circuit connected to the plurality of bit lines and detecting and latching data of a plurality of first memory cells connected to the first word line, and after the latching, performing a restoring operation of writing back to the plurality of first memory cells; a read circuit continuously reading out data latched to the sense amplifier circuit to the outside in accordance with a plurality of second addresses; and a write circuit continuously writing data latched to the sense amplifier circuit in accordance with a plurality of second addresses; and in the restoring operation in the refresh command of an internal generation signal or an external signal, inverting each data of the plurality of first memory cells latched by the sense amplifier circuit and writing back to the plurality of first memory cells.

17. The semiconductor storage device according to claim 16, comprising: a storage section storing a flag indicating whether data of the plurality of first memory cells is inverted from original data to opposite logic data or restored from the opposite logic data to the original data in the restoring operation in the refresh command.

18. The semiconductor storage device according to claim 16, comprising: a storage section storing a first address of execution of the refresh command in which the restoring operation is most recently performed, in a case where the restoring operation is performed in the order of sequentially designating the plurality of word lines in accordance with the first address.

19. The semiconductor storage device according to claim 16 or 17, wherein the word line control circuit sets a voltage of a word line other than the first word line among the plurality of word lines to a polarity opposite to that of the first word line.

20. The semiconductor storage device according to claim 16 or 17, wherein the word line control circuit comprises a mechanism of driving a voltage of the first word line to a positive polarity, a mechanism of driving a voltage of the first word line to a negative polarity, and a mechanism of floating the first word line for a longer time than a time of driving the first word line to the positive polarity or the negative polarity.

21. The semiconductor storage device according to claim 16 or 17, wherein the word line control circuit comprises a transistor including an oxide semiconductor in a channel region.

22. The semiconductor storage device according to claim 16 or 17, wherein the plurality of bit lines correspond to one global bit line, further comprising: a selection transistor connected between the plurality of bit lines and the global bit line and including an oxide semiconductor in a channel region; and the selection transistor is driven so that a voltage of a gate thereof is changed between two potentials different in polarity.

23. The semiconductor storage device according to claim 16 or 17, wherein each of the memory cells comprises: a transistor whose gate is connected to any one of the plurality of word lines, one of a source and a drain is connected to any one of the plurality of bit lines, and a channel region includes the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

24. The semiconductor storage device according to claim 19, wherein each of the memory cells comprises: a transistor whose gate is connected to any one of the plurality of word lines, one of a source and a drain is connected to any one of the plurality of bit lines, and a channel region includes the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

25. The semiconductor storage device according to claim 20, wherein each of the memory cells includes: a transistor whose gate is connected to any one of the plurality of word lines, one of a source and a drain is connected to any one of the plurality of bit lines, and a channel region includes the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

26. The semiconductor storage device according to claim 21, wherein each of the memory cells includes: a transistor whose gate is connected to any one of the plurality of word lines, one of a source and a drain is connected to any one of the plurality of bit lines, and a channel region includes the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

27. The semiconductor storage device according to claim 22, wherein each of the memory cells includes: a transistor whose gate is connected to any one of the plurality of word lines, one of a source and a drain is connected to any one of the plurality of bit lines, and a channel region includes the oxide semiconductor; and a capacitor connected to the other of the source and the drain of the plurality of transistors.

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