A resistance calibration circuit, memory and electronic device

Abstract

The present disclosure relates to the field of semiconductor technology, and aims to solve the problem of resistance calibration code locking error caused by improper sending timing of ZQ latching command. A resistance calibration circuit, a memory and an electronic device are provided. The resistance calibration circuit comprises: a main calibration circuit configured to adjust the resistance calibration code in a ZQ calibration process; a state machine configured to generate a calibration state signal; a latching control circuit configured to receive a ZQ latching command, perform logical processing on the ZQ latching command and the calibration state signal, and generate a target latching command; a pulse trailing edge of the target latching command is synchronized with or delayed from a target edge of the calibration state signal; and a latching circuit configured to latch the resistance calibration code in response to the pulse trailing edge of the target latching command, and generate a target calibration code. Thus, the target latching command is used instead of the ZQ latching command directly for latching, the locking correctness of the resistance calibration code is improved, and the stability of the memory is improved.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a resistance calibration circuit, a memory, and an electronic device. Background Technology

[0002] The memory contains adjustable resistors used for output driving and signal termination. The resistance values ​​of these resistors need to be calibrated to match different operating environments; this calibration process is called ZQ calibration, and the signal used to adjust the adjustable resistors is called the resistance calibration code. After ZQ calibration is performed on the memory, it needs to wait for a ZQ latch command from the System on Chip (SoC) and latch the resistance calibration code based on the ZQ latch command. However, due to the imperfections of the ZQ calibration mechanism, the timing of the ZQ latch command may be inappropriate in some scenarios, leading to the latching of incorrect resistance calibration codes and affecting memory performance. Summary of the Invention

[0003] This disclosure provides a resistance calibration circuit, a memory, and an electronic device.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a resistance calibration circuit, the resistance calibration circuit comprising:

[0006] The main calibration circuit is configured to adjust the resistance calibration code during the ZQ calibration process until the resistance value of the target resistor meets the preset conditions; wherein the resistance calibration code is used to adjust the resistance value of the target resistor.

[0007] The state machine is configured to generate a calibration status signal in the first state during the ZQ calibration process and a calibration status signal in the second state after the ZQ calibration is completed.

[0008] A latch control circuit, connected to the state machine, is configured to receive a ZQ latch command and the calibration state signal, perform logical processing on the ZQ latch command and the calibration state signal, and generate a target latch command; wherein the trailing edge of the pulse of the target latch command is synchronized with or delayed by the target edge of the calibration state signal, and the target edge refers to the change from the first state to the second state;

[0009] A latching circuit, connected to the latching control circuit and the main calibration circuit, is configured to receive the target latching command and the resistance calibration code, and latch the resistance calibration code in response to the trailing edge of the pulse of the target latching command to generate the target calibration code.

[0010] In some embodiments, the main calibration circuit is further configured to output an update code pulse when the ZQ calibration process meets a preset calibration end condition; wherein the leading edge of the update code pulse is earlier than the target edge of the calibration status signal; the latch circuit includes;

[0011] The first latching circuit, connected to the main calibration circuit, is configured to receive the update code pulse and the resistance calibration code, and latch the resistance calibration code in response to the leading edge of the update code pulse to generate an update calibration code.

[0012] The second latch circuit, connected to the first latch circuit, is configured to receive the target latch command and the update calibration code, and latch the update calibration code in response to the trailing edge of the pulse of the target latch command to generate the target calibration code.

[0013] In some embodiments, the latch control circuit is specifically configured to, if the ZQ latch command is received during the period when the calibration state signal is in the first state, pulse widen the ZQ latch command using the calibration state signal to generate the target latch command; or, if the ZQ latch command is received during the period when the calibration state signal is in the second state, output the ZQ latch command as the target latch command.

[0014] In some embodiments, the latch control circuit includes: a logic circuit configured to pulse broaden the ZQ latch command using the calibration state signal and output an intermediate broadened signal; and a selection circuit connected to the logic circuit, configured to output the received intermediate broadened signal as the target latch command during the period when the calibration state signal is in a first state, and to output the received ZQ latch command as the target latch command during the period when the calibration state signal is in a second state.

[0015] In some embodiments, the logic circuit is specifically configured to adjust the intermediate broadening signal to a third state in response to the ZQ latch command during the period when the calibration state signal is in a first state; and to adjust the intermediate broadening signal to a fourth state when the calibration state signal changes from the first state to a second state.

[0016] In some embodiments, when both the first state and the third state are high: the logic circuit includes a first NAND gate and a first flip-flop; the two inputs of the first NAND gate receive the calibration status signal and the ZQ latch command, respectively; the input of the first flip-flop receives a preset level signal; the clock terminal of the first flip-flop receives a calibration clock signal; the set terminal of the first flip-flop is connected to the output of the first NAND gate; and the reset terminal of the first flip-flop receives the calibration status signal; both the set terminal and the reset terminal are active low.

[0017] In some embodiments, the resistance calibration code includes a pull-up calibration code and a pull-down calibration code; the target resistor includes a pull-up resistor and a pull-down resistor; the main calibration circuit is specifically configured to adjust the pull-down calibration code in response to a pull-down enable signal in an enable state until the pull-down resistor meets a preset condition; and to adjust the pull-up calibration code in response to a pull-up enable signal in an enable state until the pull-up resistor meets a preset condition; the state machine is specifically configured to adjust the calibration state signal to a first state in response to the pull-down enable signal changing from a disabled state to an enabled state; and to adjust the calibration state signal to a second state in response to the pull-up enable signal changing from an enabled state to a disabled state; wherein, the ZQ calibration process includes a pull-down calibration stage and a pull-up calibration stage, wherein in the pull-down calibration stage, the pull-down enable signal is in an enabled state and the pull-up enable signal is in a disabled state; and in the pull-up calibration stage, the pull-down enable signal is in a disabled state and the pull-up enable signal is in an enabled state.

[0018] In some embodiments, the main calibration circuit includes: a resistor and comparison module, including the pull-down resistor, configured to receive and adjust the resistance value of the pull-down resistor using the pull-down calibration code; comparing the resistance value of the pull-down resistor with a standard resistance value during the period when the pull-down enable signal is enabled, and outputting a comparison signal; an adjustment module, connected to the resistor and comparison module, configured to receive the comparison signal; and adjusting the pull-down calibration code once based on the comparison signal in each calibration cycle during the period when the pull-down enable signal is enabled; the resistor and comparison module further includes the pull-up resistor, and is further configured to receive and adjust the resistance value of the pull-up resistor using the pull-up calibration code; comparing the resistance value of the pull-up resistor with a standard resistance value during the period when the pull-up enable signal is enabled, and outputting the comparison signal; the adjustment module is configured to receive the comparison signal; and adjusting the pull-up calibration code once based on the comparison signal in each calibration cycle during the period when the pull-up enable signal is enabled.

[0019] In some embodiments, the main calibration circuit includes:

[0020] A control module, connected to the adjustment module, is configured to output a calibration clock signal; and to perform periodic counting on the calibration clock signal, and, when the count value is a preset threshold, output an update code pulse based on the rising edge of the calibration clock signal; the first latch circuit includes a second flip-flop and a third flip-flop; the second latch circuit includes a fourth flip-flop and a fifth flip-flop; the input terminal of the second flip-flop receives a pull-up calibration code, and the clock terminal of the second flip-flop receives the update code pulse; the input terminal of the third flip-flop receives a pull-down calibration code, and the clock terminal of the third flip-flop receives the update code pulse; the input terminal of the fourth flip-flop is connected to the output terminal of the second flip-flop, the clock terminal of the fourth flip-flop receives the target latch command, and the fourth flip-flop outputs a target pull-up calibration code; the input terminal of the fifth flip-flop is connected to the output terminal of the third flip-flop, the clock terminal of the fifth flip-flop receives the target latch command, and the clock terminal of the fifth flip-flop outputs a target pull-down calibration code; wherein, the target pull-up calibration code and the target pull-down calibration code together constitute the target calibration code.

[0021] In some embodiments, the resistor and comparison module includes: a resistor module including the pull-up resistor, the pull-down resistor, and the standard resistor, configured to output a first voltage and a second voltage; wherein the first voltage indicates the voltage division result of the pull-down resistor and the standard resistor, and the second voltage indicates the voltage division result of the pull-up resistor and the pull-down resistor; and a comparison circuit configured to, in response to the pull-down enable signal in an enabled state, compare the pull-down reference voltage and the first voltage to generate the comparison signal; and, in response to the pull-up enable signal in an enabled state, compare the pull-up reference voltage and the second voltage to generate the comparison signal.

[0022] In a second aspect, embodiments of this disclosure provide a memory that includes the resistance calibration circuit described in the first aspect.

[0023] Thirdly, embodiments of this disclosure provide an electronic device, which includes the memory described in the second aspect.

[0024] This disclosure provides a resistor calibration circuit, a memory, and an electronic device that can avoid the problem of incorrect latching of resistance calibration codes due to improper timing of ZQ latch command transmission, improve the latching accuracy of resistance calibration codes, and meet the relevant provisions of industry standard documents. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the first resistance calibration circuit provided in the embodiments of this disclosure;

[0026] Figure 2This is a signal schematic diagram of the first resistance calibration circuit provided in the embodiments of this disclosure;

[0027] Figure 3 This is a schematic diagram of the structure of the second resistance calibration circuit provided in the embodiments of this disclosure;

[0028] Figure 4 This is a signal schematic diagram of the second type of resistance calibration circuit provided in the embodiments of this disclosure;

[0029] Figure 5 This is a schematic diagram of the third type of resistance calibration circuit provided in this embodiment. Figure 1 ;

[0030] Figure 6 This is a signal schematic diagram of the third type of resistance calibration circuit provided in the embodiments of this disclosure;

[0031] Figure 7 This is a schematic diagram of the third type of resistance calibration circuit provided in this embodiment. Figure 2 ;

[0032] Figure 8 This is a schematic diagram of the third type of resistance calibration circuit provided in this embodiment. Figure 3 . Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0034] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0036] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0038] First, the nouns and terms used in the embodiments of this disclosure will be explained:

[0039] Dynamic Random Access Memory (DRAM);

[0040] Synchronous Dynamic Random Access Memory (SDRAM);

[0041] Double Data Rate SDRAM (DDR);

[0042] Low-power DDR (LPDDR);

[0043] Joint Electron Device Engineering Council (JEDEC).

[0044] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0045] The memory's input / output ports are connected to pull-up and pull-down resistors for output driving and signal termination. Both pull-up and pull-down resistors are adjustable. Because the performance of circuit components varies under different operating environments (temperature, voltage), pull-up calibration codes are needed to calibrate the pull-up resistors, and pull-down calibration codes are needed to calibrate the pull-up and pull-down resistors to ensure their resistance values ​​meet expectations.

[0046] Please see Figure 1 This illustrates a schematic diagram of the structure of a first type of resistance calibration circuit provided in an embodiment of this disclosure. Figure 1As shown, the resistor calibration circuit includes a main calibration circuit, a first latch circuit, and a second latch circuit. The main calibration circuit is used to adjust the pull-up calibration code pucnt<5:0> and the pull-down calibration code pdcnt<5:0> so that the resistance values ​​of the pull-up and pull-down resistors meet the expectations. After the pull-up calibration codes pucnt<5:0> and pdcnt<5:0> are adjusted, the control module in the main calibration circuit will generate an update code pulse update_pulse synchronized with the calibration clock signal ZqClk. The first latch circuit uses the update code pulse update_pulse to latch the pull-up calibration codes pucnt<5:0> and pdcnt<5:0>, generating update calibration codes Zq_pucode<5:0> and Zq_pdcode<5:0>. Then, it waits for the ZQ Latch Command sent by the SoC to the memory to latch Zq_pucode<5:0> and Zq_pdcode<5:0>, thereby generating the final calibration codes ZQpucode<5:0> and ZQpdcnt<5:0>.

[0047] However, since the ZQ latch command is generated by an external clock (also known as the Host clock) of the ZQ calibration circuit, and is asynchronous with the update code pulse (update_pulse), the timing of their transmission may not meet expectations. See also... Figure 2 It shows a signal timing diagram of the first resistor calibration circuit in some scenarios. Figure 2 The Zq_code<5:0> shown can be considered as either Zq_pdcode<5:0> or Zq_pucode<5:0>. Figure 2 The ZQcode<5:0> shown can be considered as either the aforementioned ZQpucode<5:0> or the aforementioned ZQpdcode<5:0>.

[0048] like Figure 2 As shown, under severe conditions, the calibration latch command ZQ latch command and the update code pulse update_pulse may be too close together, causing the locking process of the update calibration code Zq_code<5:0> to occur simultaneously with the locking process of the target calibration code ZQcode<5:0>, resulting in latching the wrong calibration code.

[0049] Please see Figure 3 This illustration shows a partial structural diagram of a second resistance calibration circuit provided in an embodiment of this disclosure. Figure 3 As shown, the resistor calibration circuit includes a main calibration circuit ( Figure 3 (Omitted), first latch circuit, second latch circuit, and decision circuit. It should be understood that... Figure 3 In this context, `cnt<5:0>` can be understood as either `pdcnt<5:0>` or `pucnt<5:0>`. Since the latching logic of pull-up and pull-down calibration codes is similar, only one latching device is shown for each of the first and second latching circuits. Their specific structures can be found in [reference needed]. Figure 1 To understand.

[0050] like Figure 3 As shown, this resistor calibration circuit introduces a decision circuit, which includes multiple logic devices: AND gate, OR gate, NOT gate, driver, delay unit, flip-flop, and selection output gate. It determines whether to latch the calibration code by detecting the positional relationship between the update code pulse `update_pulse` and the decision window `zq_latch_ext` generated by the ZQ Latch Command.

[0051] (1) If the update code pulse update_pulse is far from the decision window zq_latch_ext, then the delayed calibration latch command zq_clk_delay is used to latch the update calibration code Zq_code<5:0>;

[0052] (2) Please see Figure 4 If the update code pulse update_pulse and the ZQ Latch Command occur within the same decision window, i.e., the rising edge of the update code pulse update_pulse is located in the decision window zq_latch_ext, then it is considered that the ZQ Latch Command may latch an unstable calibration code. In this case, the decision window zq_latch_ext is delayed by one clock cycle (i.e., the period of the calibration clock signal ZqClk) to generate a delayed latch window zq_latch_clk_gate. The delayed latch window zq_latch_clk_gate is used to latch the update calibration code Zq_code<5:0>.

[0053] The circuit design described above can, to some extent, ensure that ZQ calibration can latch the correct result. However, its circuit design is complex, and the accuracy of the latched result is heavily dependent on the period of the calibration clock signal ZqClk. When the period of ZqClk is long, the overall latch time is long, which may not meet the JEDEC specification for ZQ calibration LatchTime (tZQLAT).

[0054] In yet another embodiment of this disclosure, please refer to Figure 5The diagram illustrates a third type of resistance calibration circuit 10 provided in this embodiment. This resistance calibration circuit 10 can be applied to a memory, which can be LPDDR, such as LPDDR4, LPDDR5, or LPDDR6 memory; the memory can also be other types of DRAM, such as DDR4, DDR5, or DDR6 memory.

[0055] like Figure 5 As shown, the resistor calibration circuit 10 includes:

[0056] The main calibration circuit 11 includes a target resistor 111 and is configured to adjust the resistance calibration code cnt<5:0> during the ZQ calibration process until the resistance value of the target resistor 111 meets the preset conditions; wherein, the resistance calibration code cnt<5:0> is used to adjust the resistance value of the target resistor 111.

[0057] State machine 12 is configured to generate and output a calibration state signal Busystate for the first state during ZQ calibration; and to generate and output a calibration state signal Busystate for the second state after ZQ calibration is completed.

[0058] The latch control circuit 13, connected to the state machine 12, is configured to receive the ZQ Latch Command and the calibration state signal Busystate, perform logical processing on the ZQ Latch Command and the calibration state signal Busystate, and generate the target latch command ZqlatchOut; wherein, the trailing edge of the pulse of the target latch command ZqlatchOut is synchronized with or delayed by the target edge of the calibration state signal Busystate, and the target edge refers to the change from the first state to the second state;

[0059] The latch circuit 14 is connected to the latch control circuit 13 and the main calibration circuit 11, and is configured to receive the target latch command ZqlatchOut and the resistance calibration code cnt<5:0>; in response to the target latch command ZqlatchOut, it latches the resistance calibration code cnt<5:0> and generates the target calibration code ZQcode<5:0>.

[0060] In this embodiment of the disclosure, the preset condition means that the difference between the target resistance 111 and the standard resistance value (e.g., 240 ohms) is within a preset error range.

[0061] It should be noted that the ZQ Latch Command is sent by the memory controller (e.g., SoC) to the resistor calibration circuit 10 in the memory. It should be understood that the memory controller sends a command address signal CA to the memory to instruct the memory to perform what operation. The ZQ Latch Command mentioned here is a signal generated by decoding the instruction portion of the command address signal CA, not the original command address signal CA. See also... Figure 6 This illustrates a signal diagram of a resistance calibration circuit 10 provided in this embodiment of the present disclosure. Figure 6 As shown, the ZQ LatchCommand is specifically represented by a pulse on the corresponding line.

[0062] In this embodiment of the disclosure, a calibration status signal Busystate is introduced to indicate whether the current process is in ZQ calibration. Specifically, if the calibration status signal Busystate is in a first state, it indicates that the current process is in ZQ calibration; if the calibration status signal Busystate is in a second state, it indicates that the current process is not in ZQ calibration.

[0063] The first state can be either a high level 1 or a low level 0, and the second state can be the other of a high level 1 or a low level 0. The embodiments disclosed herein will be described and illustrated as "the first state is a high level 1, and the second state is a low level 0," but this does not constitute a limitation.

[0064] Figure 6 (a) shows a case where the ZQ Latch Command arrives prematurely; Figure 6 (b) shows the normal arrival of the ZQ Latch Command. Regardless of Figure 6 In (a) or (b), the trailing edge of the target latch command ZqlatchOut pulse is no earlier than the target edge of the calibration status signal Busystate, and therefore no earlier than the end of the ZQ calibration process. In other words, at the trailing edge of the target latch command ZqlatchOut pulse, the resistance calibration code cnt<5:0> has already been calibrated. At this time, the ZQcode<5:0> generated by latching the resistance calibration code cnt<5:0> will necessarily be the accurate value of the calibrated value, thus avoiding erroneous latching.

[0065] In some embodiments, the main calibration circuit 11 is further configured to output an update code pulse update_pulse when the ZQ calibration process meets a preset calibration end condition. See also Figure 6 The pulse leading edge of the update code pulse update_pulse is ahead of the target edge of the calibration state signal Busystate.

[0066] It should be understood that the ZQ calibration process includes multiple calibration cycles. In each calibration cycle, the resistance calibration code is adjusted once based on the magnitude of the target resistance and the standard resistance value until the difference between the target resistance 111 and the standard resistance value is within the preset error range.

[0067] It should be understood that the preset calibration end condition indicates that "the resistance value of the target resistor meets the preset condition". In other words, if "the ZQ calibration process meets the preset calibration end condition", it can be considered that "the resistance value of the target resistor meets the preset condition", that is, the resistance value calibration code has been calibrated and will not change again, so the resistance value calibration code can be latched.

[0068] Furthermore, since the "ZQ calibration process" is a holistic process, its completion is actually determined by the "calibration status signal." In other words, "the ZQ calibration process meeting the preset calibration end conditions" may trigger a determination of whether the ZQ calibration process has ended, but this does not in itself represent the end of the ZQ calibration process.

[0069] In one example, the preset calibration termination condition can be: the number of calibration cycles equals a preset threshold. For example, if the preset threshold is 6, then ZQ calibration is considered complete after 6 calibration cycles. This is just an example; the preset threshold can also be 3, 4, 5, 6... 12, 13, 14, 15, 16...

[0070] In another example, the preset calibration end condition can be that the comparison signal (indicating the comparison result between the target resistor value and the standard resistor value) exhibits a preset change pattern in multiple calibration cycles, such as the comparison signal exhibiting a change of "010" or a change of "101".

[0071] Please see Figure 7 This illustrates a partial structural schematic of a third type of resistance calibration circuit 10 according to an embodiment of this disclosure. Figure 7 As shown, the latch circuit 14 includes a first latch circuit 141 and a second latch circuit 142;

[0072] The first latch circuit 141 is connected to the main calibration circuit 11 and is configured to receive the update code pulse update_pulse and the resistance calibration code cnt<5:0>. In response to the leading edge of the update code pulse update_pulse, the resistance calibration code cnt<5:0> is latched to generate the update calibration code Zq_code<5:0>.

[0073] The second latch circuit 142 is connected to the first latch circuit 141 and is configured to receive the update code pulse update_pulse and the update calibration code Zq_code<5:0>, latch the update calibration code Zq_code<5:0> using the target latch command ZqlatchOut, and generate the target calibration code ZQcode<5:0>.

[0074] It should be understood that the resistance calibration code cnt<5:0> is generated and adjusted by a counter (see further description below), and the counter cannot stably and for a long time retain the count value. Therefore, after calibration to an accurate value, the main calibration circuit 11 will issue an update code pulse update_pulse to latch the resistance calibration code cnt<5:0> before the ZQ Latch Command arrives, generating an update calibration code Zq_code<5:0>; subsequently, in response to the ZQ Latch Command, the target latch command ZqlatchOut will latch the update calibration code Zq_code<5:0> to obtain the final target calibration code ZQcode<5:0>.

[0075] However, since the ZQ Latch Command and the update pulse are asynchronous, the following two possibilities exist:

[0076] (1) Please see Figure 6 In (a) of this document, under adverse conditions, the ZQ Latch Command and the update code pulse update_pulse are sent at close intervals. Directly using the ZQ Latch Command to latch the update calibration code may result in latching an incorrect value. However, this embodiment introduces a calibration state signal Busystate. The target latch command ZqlatchOut, generated jointly by the ZQ Latch Command and Busystate, latches the update calibration code. Since the leading edge of the update code pulse update_pulse precedes the target edge of the Busystate, while the trailing edge of the target latch command ZqlatchOut lags behind (or coincides with) the target edge of the Busystate, the update calibration code is latched only after the leading edge of the update code pulse update_pulse, thus ensuring the correct latching result.

[0077] (2) Please see Figure 6In (b), when the ZQ Latch Command and the update pulse are sent at relatively far intervals, the delayed ZQ Latch Command can be used directly. Figure 6 (b) in the text omits the delay) and uses it as the target latch command ZqlatchOut, which does not affect the normal latching in this case.

[0078] Thus, on the one hand, for the resistor calibration circuit 10 provided in this embodiment, the calibration status signal Busystate is introduced to indicate whether the ZQ calibration process is complete. At the same time, the calibration status signal Busystate is used to perform logical processing on the ZQ Latch Command sent by the SoC. Even in harsh scenarios (e.g., the clock point of the ZQ Latch Command sent by the SoC is too early), it can be ensured that the latching operation is performed only after the ZQ calibration process is completed, avoiding latching into an incorrect value. On the other hand, the generation of the target latch command ZqlatchOut does not depend on the clock period of the calibration clock signal ZqClk, which can meet the requirements of JEDEC regarding ZQ calibration Latch Time (tZQLAT).

[0079] In some embodiments, the latch control circuit 13 is specifically configured as follows:

[0080] Please see Figure 6 In (a) of the calibration state signal Busystate, if a ZQ Latch Command is received during the period when Busystate is in the first state (e.g., high level 1), the ZQ Latch Command is pulse-broadened using Busystate to generate a target latch command ZqlatchOut. In this case, the leading edge of the target latch command ZqlatchOut is generated based on the ZQ Latch Command, and the trailing edge is generated based on the target edge of Busystate. For example, the pulse width of the target latch command ZqlatchOut is approximately in the range of 2 to 5 ns.

[0081] Please see Figure 6 In (b), if a ZQ Latch Command is received during the period when the calibration state signal Busystate is in the second state (e.g., low level 0), then the ZQ Latch Command is output as the target latch command ZqlatchOut.

[0082] In some implementations, please refer to Figure 7 The latch control circuit 13 includes:

[0083] Logic circuit 131 is configured to use the calibration status signal Busystate to pulse widen the ZQ latch command ZQ LatchCommand and output the intermediate widening signal ZqlatchSync.

[0084] Selection circuit 132, connected to logic circuit 131, is configured to output the received intermediate widening signal ZqlatchSync as the target latch command ZqlatchOut during the period when the calibration state signal Busystate is in the first state; and to output the received ZQ latch command as the target latch command ZqlatchOut during the period when the calibration state signal Busystate is in the second state.

[0085] It should be understood that the selection circuit 132 requires a certain processing time, therefore the target latch command ZqlatchOut has a certain delay compared to the ZQ latch command ZQ Latch Command (but...). Figure 6 (Not shown, please understand on your own).

[0086] In some embodiments, logic circuit 131 is specifically configured to adjust intermediate widening signal ZqlatchSync to a third state in response to ZQ Latch Command during the period when calibration state signal Busystate is in a first state.

[0087] Furthermore, when the calibration status signal Busystate changes from the first state to the second state, the intermediate widening signal ZqlatchSync is adjusted to the fourth state.

[0088] Here, the third state can be either high level 1 or low level 0, and the fourth state can be either high level 1 or low level 0.

[0089] Due to the diversity of circuit components, logic circuit 131 can be implemented in various structures. The following example provides an example where "both the first and third states are high." Please refer to [link / reference]. Figure 7 The logic circuit 131 includes a first NAND gate 1311 and a first flip-flop 1312. The two input terminals of the first NAND gate 1311 receive the calibration state signal Busystate and the ZQ latch command ZQ Latch Command respectively. The first NAND gate 1311 outputs an intermediate decision signal ZqlatchIn.

[0090] The input terminal of the first flip-flop 1312 receives a preset level signal ( Figure 7(Vss is the ground signal); the clock terminal of the first flip-flop 1312 receives the calibration clock signal ZqClk; the set terminal SN of the first flip-flop 1312 is connected to the output terminal of the first NAND gate 1311; the reset terminal RN of the first flip-flop 1312 receives the calibration status signal Busystate; both the set terminal SN and the reset terminal RN are active low.

[0091] Please see below. Figure 6 In (a), assuming that the ZQ Latch Command is received during the period when the calibration state signal Busystate is high, the intermediate decision signal ZqlatchIn is low during the corresponding period, the set terminal SN of the first flip-flop 1312 is valid, and the intermediate widening signal ZqlatchSync flips to high. After the calibration state signal Busystate is adjusted to low, the intermediate decision signal ZqlatchIn flips to high. At this time, the reset terminal RN of the first flip-flop 1312 is valid, and the intermediate widening signal ZqlatchSync flips to low. At the same time, the selection circuit 132 outputs the intermediate widening signal ZqlatchSync as the target latch command ZqlatchOut.

[0092] Conversely, please see Figure 6 In (b), assuming that the ZQ Latch Command is not received during the period when the calibration state signal Busystate is high, the intermediate decision signal ZqlatchIn will always be high, the reset terminal RN and the set terminal SN of the first flip-flop 1312 will be invalid, the first flip-flop 1312 will sample the ground signal Vss, so that the intermediate widening signal ZqlatchSync will remain low; at the same time, the selection circuit 132 will output the received ZQ Latch Command as the target latch command ZqlatchOut.

[0093] In some embodiments, see Figure 7 The logic circuit 131 also includes a first driver 1315. On the one hand, the first driver 1315 can enhance the driving capability of the intermediate broadening signal ZqlatchSync. On the other hand, the first driver 1315 further delays the intermediate broadening signal ZqlatchSync, so that the pulse trailing edge of the intermediate broadening signal ZqlatchSync is delayed compared to the target edge of the calibration state signal Busystate, ensuring that the latching result is correct.

[0094] like Figure 7As shown, the selection circuit 132 can be implemented by a two-to-one data selector Mux. The first terminal of the data selector receives the ZQ Latch Command, the second terminal of the data selector receives the intermediate widening signal ZqlatchSync, and the control terminal of the data selector receives the calibration status signal Busystate.

[0095] In other embodiments, the logic circuit 131 may also include a delay device, through which the first terminal of the data selector 132 receives the ZQ Latch Command.

[0096] Thus, during the period when the calibration status signal Busystate is high, the intermediate widening signal ZqlatchSync is output as the target latch command ZqlatchOut; during the period when the calibration status signal Busystate is low, the ZQ latch command ZQ Latch Command (or after a delay) is output as the target latch command ZqlatchOut.

[0097] In some embodiments, see Figure 8 The target resistor 111 includes a pull-down resistor 201 and a pull-up resistor 202. The target resistor's resistance value meets the preset conditions, specifically: (1) the difference between the resistance value of the pull-down resistor 201 and the standard resistance value is less than or equal to the preset error range; (2) the difference between the resistance value of the pull-up resistor 202 and the standard resistance value is less than or equal to the preset error range. The resistance calibration code includes the pull-up calibration code pucnt<5:0> and the pull-down calibration code pdcnt<5:0>. In the attached figure, cnt<5:0> can be regarded as either pucnt<5:0> or pdcnt<5:0>.

[0098] In this embodiment, the ZQ calibration process includes at least a pull-down calibration stage and a pull-up calibration stage, distinguished by a pull-up enable signal `pucalen` and a pull-down enable signal `pdcalen`. In the pull-down calibration stage, the pull-up enable signal `pucalen` is disabled, and the pull-down enable signal `pdcalen` is enabled; in the pull-up calibration stage, the pull-up enable signal `pucalen` is enabled, and the pull-down enable signal `pdcalen` is disabled.

[0099] Please see Figure 8 The main calibration circuit 11 is specifically configured to adjust the pull-down calibration code pdcnt<5:0> in response to the pull-down enable signal pdcalen in the enable state until the pull-down resistor 201 meets the preset conditions; and to adjust the pull-up calibration code pucnt<5:0> in response to the pull-up enable signal puccalen in the enable state until the pull-up resistor 202 meets the preset conditions.

[0100] State machine 12 is specifically configured to adjust the calibration state signal Busystate to the first state in response to the pull-down enable signal pdcalen changing from the disabled state to the enabled state; and to adjust the calibration state signal Busystate to the second state in response to the pull-up enable signal pucalen changing from the enabled state to the disabled state.

[0101] It should be noted that the enable state can be either low level 0 or high level 1, while the disable state can be either low level 0 or high level 1. The enable states of different signals may be the same or different.

[0102] Thus, in this embodiment of the disclosure, the pull-down resistor calibration is performed first, and then the pull-up resistor calibration is performed; at the same time, the calibration status signal Busystate can be generated using the enable signals of the two calibration stages.

[0103] In other embodiments, the pull-up resistor calibration can be performed first, followed by the pull-down resistor calibration, depending on the circuit structure in the actual application scenario.

[0104] In some embodiments, see Figure 8 The main calibration circuit 11 includes:

[0105] The resistor and comparison module 20 includes a pull-down resistor 201, configured to receive and adjust the resistance value of the pull-down resistor 201 using the pull-down calibration code pdcnt<5:0>; during the period when the pull-down enable signal pdcalen is enabled, the resistance value of the pull-down resistor 201 is compared with the standard resistance value, and a comparison signal is output.

[0106] The adjustment module 30 is connected to the resistor and comparison module 20 and is configured to receive the comparison signal and the calibration clock signal ZqClk; while the pull-down enable signal pdcalen is in the enabled state, the pull-down calibration code pdcnt<5:0> is adjusted based on the comparison signal.

[0107] The resistor and comparison module 20 also includes a pull-up resistor 202, and is configured to receive and adjust the resistance value of the pull-up resistor using the pull-up calibration code pucnt<5:0>; during the period when the pull-up enable signal pucart is in the enabled state, the resistance value of the pull-up resistor 202 is compared with the standard resistance value, and a comparison signal is output.

[0108] The adjustment module 30 is configured to receive a comparison signal and a calibration clock signal ZqClk; during the period when the pull-up enable signal pucalen is in the enabled state, the pull-up calibration code pucnt<5:0> is adjusted based on the comparison signal.

[0109] In some embodiments, see Figure 8The resistor and comparator module 20 includes:

[0110] The resistor module 200 specifically includes a pull-up resistor 202, pull-down resistors 201 / 201' and a standard resistor 203; it is configured to output a first voltage ZqPd and a second voltage ZqPu; wherein, the first voltage ZqPd indicates the voltage division result of the pull-down resistor 201 and the standard resistor 203, and the second voltage ZqPu indicates the voltage division result of the pull-up resistor 202 and the pull-down resistor 201';

[0111] The comparator circuit 210 is configured to, in response to the pull-down enable signal pdcalen in the enable state, compare the pull-down reference voltage RefPd and the first voltage ZqPd to generate a comparison signal; and in response to the pull-up enable signal in the enable state, compare the pull-up reference voltage RefPu and the second voltage ZqPu to generate a comparison signal.

[0112] It should be understood that there may be multiple pull-up resistors and multiple pull-down resistors in the memory. Different pull-up resistors have the same structure and share the same pull-up calibration code pucnt<5:0>; different pull-down resistors have the same structure and share the same pull-down calibration code pdcnt<5:0>.

[0113] Furthermore, the resistance value of standard resistor 203 is the same as the aforementioned standard resistance value. Standard resistor 203 and pull-down resistor 201 form a connection point ZQ, which outputs a first voltage ZqPd. Pull-down resistor 201' and pull-up resistor 202 form a connection point, which outputs a second voltage ZqPu.

[0114] Please refer to Figure 8 The comparator circuit 210 includes a reference voltage unit 211, a first selector 212, a second selector 213, and a comparator 214, as detailed below:

[0115] Reference voltage unit 211 is configured to output pull-up reference voltage RefPu and pull-down reference voltage RefPd. Here, the pull-up reference voltage RefPu can be regarded as "the voltage value of the first voltage ZqPd when the resistance values ​​of standard resistor 203 and pull-down resistor 201 are the same", and the pull-down reference voltage RefPd can be regarded as "the voltage value of the second voltage ZqPu when the resistance values ​​of pull-up resistor 202 and pull-down resistor 201' are the same".

[0116] The two inputs of the first selector 212 receive the pull-down reference voltage RefPd and the pull-up reference voltage RefPu, respectively. The two inputs of the second selector 213 receive the first voltage ZqPd and the second voltage ZqPu, respectively. The control terminals of both the first selector 212 and the second selector 213 receive the pull-up enable signal pucalen. The two inputs of the comparator 214 are connected to the outputs of the first selector 212 and the second selector 213, respectively, and the comparator 214 outputs a comparison signal.

[0117] Thus, during the pull-down calibration phase, the pull-up enable signal `pucalen` is disabled, the first selector 212 outputs the pull-down reference voltage `RefPd`, and the second selector 213 outputs the first voltage `ZqPd`. Therefore, the comparison signal output by comparator 214 can indicate the resistance relationship between the pull-down resistor 201 and the standard resistor 203. During the pull-up calibration phase, the pull-up enable signal `pucalen` is enabled, the first selector 212 outputs the pull-up reference voltage `RefPu`, and the second selector 213 outputs the second voltage `ZqPu`. Therefore, the comparison signal output by comparator 214 can indicate the resistance relationship between the pull-up resistor 202 and the pull-down resistor 201' (which is the standard resistance value at this time, as the pull-down calibration code has been completed).

[0118] In some embodiments, see Figure 8 The resistor and comparison module 20 also includes AND gate 220, AND gate 230, and sixth flip-flop 240.

[0119] (1) AND gate 220 receives pull-up enable signal pucalen and pull-up calibration code pucnt<5:0> respectively. The output of AND gate 230 is connected to pull-up resistor 202, so that the adjusted pull-up calibration code pucnt<5:0> is sent to pull-up resistor 202 during the pull-up calibration stage.

[0120] (2) AND gate 230 receives the pull-down enable signal pdcalen and the pull-down calibration code pdcnt<5:0> respectively. The output of AND gate 230 is connected to pull-down resistor 201, so that the adjusted pull-down calibration code pdcnt<5:0> is sent to pull-down resistor 201 during the pull-down calibration phase; AND gate;

[0121] (3) The input of the sixth flip-flop 240 receives the pull-down calibration code pdcnt<5:0>, the clock terminal of the sixth flip-flop 240 receives the pull-up enable signal pucalen, and the output of the sixth flip-flop 240 is connected to the pull-down resistor 201'. Thus, when transitioning from the pull-down calibration phase to the pull-up calibration phase, the sixth flip-flop 240 locks the pull-down calibration code pdcnt<5:0> and uses it to adjust the resistance value of the pull-down resistor 201' so that its resistance value during the pull-up calibration phase is the standard resistance value. Therefore, the second voltage ZqPu can also be regarded as the voltage divider result of the pull-up resistor 202 and the standard resistor;

[0122] In some embodiments, see Figure 8 The adjustment module 30 includes a seventh flip-flop 301, a first counter 302, and a second counter 303. The seventh flip-flop 301 receives a comparison signal, and its clock input receives a calibration clock signal ZqClk. The output of the seventh flip-flop 301 is connected to the first counter 302, which also receives a pull-up enable signal pucalen. Figure 8 (omitted), so that during the pull-up adjustment phase, the pull-up calibration code pucnt<5:0> is adjusted based on the comparison signal; the output of the seventh flip-flop 301 is also connected to the second counter 303, which also receives the pull-down enable signal pdcalen ( Figure 8 (omitted), thus during the pull-down adjustment phase, the pull-down calibration code pdcnt<5:0> is adjusted based on the comparison signal.

[0123] Please see below. Figure 8 The overall ZQ calibration process is as follows:

[0124] (1) During the pull-down calibration phase, the pull-down enable signal pdcalen is in the enabled state. Assuming the resistance of pull-down resistor 201 is greater than the resistance of standard resistor 203, then the first voltage ZqPd is greater than the pull-down reference voltage RefPd, causing the pull-down calibration code pdcnt<5:0> output by the first counter 302 to decrease (this is just an example; it can also be designed to increase, depending on the specific circuit design), thereby decreasing the resistance of pull-down resistor 201 until the pull-down calibration phase ends, at which point the pull-down enable signal pdcalen changes to the disabled state. The case where the resistance of pull-down resistor 201 is less than the resistance of standard resistor 203 can be understood through operation.

[0125] (2) During the pull-up calibration phase, the pull-up enable signal pucalen is in the enabled state. The calibrated pull-down calibration code pdcnt<5:0> is latched and output to the pull-down resistor 201'. At this time, the resistance value of the pull-down resistor 201' can be considered as the standard resistance value, so the second voltage ZqPu can indicate the relationship between the resistance value of the pull-up resistor 202 and the standard resistance value. Assuming that the resistance value of the pull-up resistor 202 is greater than the resistance value of the standard resistor 203, then the first voltage ZqPd is greater than the pull-up reference voltage RefPu, which causes the pull-up calibration code pucnt<5:0> output by the first counter 302 to decrease (this is just an example; it can also be designed to increase, depending on the specific circuit design), thereby decreasing the resistance value of the pull-up resistor 202 until the pull-up calibration phase ends, and the pull-up enable signal pucalen changes to the disabled state.

[0126] In some embodiments, see Figure 8 The main calibration module 11 also includes a control module 40. When the preset calibration end condition is "the number of calibration cycles is a preset threshold", the control module 40, connected to the adjustment module 30, is configured to output a calibration clock signal ZqClk; and to count the cycles of the calibration clock signal ZqClk, and when the count value indicates a preset threshold, to output an update code pulse update_pulse based on the rising edge of the calibration clock signal ZqClk.

[0127] In simple terms, during the ZQ calibration process, each clock cycle of the calibration clock signal ZqClk can be regarded as a calibration cycle. In each calibration cycle, the pull-down calibration code pdcnt<5:0> or the pull-up calibration code pucnt<5:0> is adjusted once.

[0128] In some embodiments, the pull-up calibration phase and the pull-down calibration phase each include 6 calibration cycles. Therefore, the states of the pull-up enable signal and the pull-down enable signal can be adjusted by counting the cycles of the calibration clock signal ZqClk. Specifically, after the ZQ calibration process begins, during the 1st to 6th cycles of the calibration clock signal ZqClk, the pull-down enable signal pdcalen is in the enabled state and the pull-up enable signal pdcalen is in the disabled state; during the 7th to 12th cycles of the calibration clock signal ZqClk, the pull-down enable signal pdcalen is in the disabled state and the pull-up enable signal pdcalen is in the enabled state.

[0129] In one embodiment, such as Figure 6As shown, taking a preset threshold of 6 as an example, the leading edge of the update code pulse update_pulse is generated based on the rising edge of the calibration clock signal ZqClk in the 12th clock cycle, and the two are approximately aligned. In addition, the calibration clock signal ZqClk in the 12th clock cycle will also trigger (in the circuit, it may not be triggered directly but rather the corresponding information is triggered by other signals) the pull-up enable signal pullalen to change to the disabled state, which in turn triggers the calibration state signal Busystate to change to a low level (i.e., the occurrence of the target edge). However, due to the logic delay of the hardware circuit, the target edge of the calibration state signal Busystate will be delayed by the rising edge of the calibration clock signal ZqClk in the 12th clock cycle, that is, delayed by the leading edge of the update code pulse update_pulse.

[0130] Please see Figure 8 The first latch circuit 141 includes a second flip-flop 1411 and a third flip-flop 1412; the second latch circuit 142 includes a fourth flip-flop 1421 and a fifth flip-flop 1422.

[0131] The input of the second flip-flop 1411 receives the pull-up calibration code pucnt<5:0>, and the clock terminal of the second flip-flop 1411 receives the update code pulse update_pulse; the input of the third flip-flop 1412 receives the pull-down calibration code pdcnt<5:0>, and the clock terminal of the third flip-flop 1412 receives the update code pulse update_pulse.

[0132] The input of the fourth flip-flop 1421 is connected to the output of the second flip-flop 1411, and the clock terminal of the fourth flip-flop 1421 receives the target latch command ZqlatchOut; the input of the fifth flip-flop 1422 is connected to the output of the third flip-flop 1412, and the clock terminal of the fifth flip-flop 1422 receives the target latch command ZqlatchOut.

[0133] The second trigger 1411 outputs the pull-up update calibration code Zq_pucode, and the third trigger outputs the pull-down update calibration code Zq_pdcode. The aforementioned update calibration codes include pull-up update calibration codes and pull-down update calibration codes, and Zq_code<5:0> in the attached diagram can be regarded as either Zq_pucode or Zq_pdcode. The fourth trigger 1421 outputs the target pull-up calibration code pucnt<5:0>, and the fifth trigger 1422 outputs the target pull-down calibration code pdcnt<5:0>. The aforementioned target calibration codes include target pull-up calibration codes and target pull-down calibration codes, and pdcnt<5:0> in the attached diagram can be regarded as either pucnt<5:0> or pdcnt<5:0>.

[0134] It should be understood that in this embodiment, pull-up resistor 202 and pull-down resistors 201 / 201' each contain multiple transistors, and the doping type is determined according to the actual application scenario. Furthermore, the example given is that both the pull-up calibration code and the pull-down calibration code each contain 6-bit sub-signals, but this does not constitute a limitation.

[0135] In another embodiment of this disclosure, a memory is provided that includes the aforementioned resistance calibration circuit 10. This memory can avoid the problem of erroneous latched resistance calibration codes caused by latch instability due to the asynchronous relationship between the update code pulse update_pulse and the ZQ Latch Command, thereby improving the accuracy of the latched ZQ calibration results and meeting the JEDEC requirements regarding tZQLAT.

[0136] In yet another embodiment of this disclosure, an electronic device is provided that includes the aforementioned memory.

[0137] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0138] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0139] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0140] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0142] The features disclosed in the several method or circuit embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or circuit embodiments.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A resistance calibration circuit, characterized in that, The resistance calibration circuit includes: The main calibration circuit is configured to adjust the resistance calibration code during the ZQ calibration process until the resistance value of the target resistor meets the preset conditions; wherein the resistance calibration code is used to adjust the resistance value of the target resistor. The state machine is configured to generate a calibration status signal in the first state during the ZQ calibration process and a calibration status signal in the second state after the ZQ calibration is completed. A latch control circuit, connected to the state machine, is configured to receive a ZQ latch command and the calibration state signal, perform logical processing on the ZQ latch command and the calibration state signal, and generate a target latch command; wherein the trailing edge of the pulse of the target latch command is synchronized with or delayed by the target edge of the calibration state signal, and the target edge refers to the change from the first state to the second state; A latching circuit, connected to the latching control circuit and the main calibration circuit, is configured to receive the target latching command and the resistance calibration code, and latch the resistance calibration code in response to the trailing edge of the pulse of the target latching command to generate the target calibration code.

2. The resistance calibration circuit according to claim 1, characterized in that, The main calibration circuit is further configured to output an update code pulse when the ZQ calibration process meets the preset calibration end conditions; wherein the pulse leading edge of the update code pulse is earlier than the target edge of the calibration status signal. The latching circuit includes: The first latching circuit, connected to the main calibration circuit, is configured to receive the update code pulse and the resistance calibration code, and latch the resistance calibration code in response to the leading edge of the update code pulse to generate an update calibration code. The second latch circuit, connected to the first latch circuit, is configured to receive the target latch command and the update calibration code, and latch the update calibration code in response to the trailing edge of the pulse of the target latch command to generate the target calibration code.

3. The resistance calibration circuit according to claim 2, characterized in that, The latch control circuit is specifically configured to, if the ZQ latch command is received during the period when the calibration state signal is in the first state, use the calibration state signal to pulse widen the ZQ latch command to generate the target latch command. Alternatively, if the ZQ latch command is received during the period when the calibration status signal is in the second state, the ZQ latch command is output as the target latch command.

4. The resistance calibration circuit according to claim 2, characterized in that, The latch control circuit includes: The logic circuit is configured to use the calibration status signal to pulse broaden the ZQ latch command and output an intermediate broadened signal. The selection circuit, connected to the logic circuit, is configured to output the received intermediate broadening signal as the target latch command during the period when the calibration state signal is in the first state; and to output the received ZQ latch command as the target latch command during the period when the calibration state signal is in the second state.

5. The resistance calibration circuit according to claim 4, characterized in that, The logic circuit is specifically configured to adjust the intermediate broadening signal to a third state in response to the ZQ latch command during the period when the calibration state signal is in the first state. When the calibration status signal changes from the first state to the second state, the intermediate broadening signal is adjusted to the fourth state.

6. The resistance calibration circuit according to claim 4, characterized in that, When both the first and third states are high: The logic circuit includes a first NAND gate and a first flip-flop. The two inputs of the first NAND gate receive the calibration status signal and the ZQ latch command, respectively. The input of the first flip-flop receives a preset level signal. The clock terminal of the first flip-flop receives a calibration clock signal, the set terminal of the first flip-flop is connected to the output terminal of the first NAND gate, and the reset terminal of the first flip-flop receives the calibration status signal; both the set terminal and the reset terminal are active low.

7. The resistance calibration circuit according to any one of claims 2-6, characterized in that, The resistance calibration code includes a pull-up calibration code and a pull-down calibration code; the target resistor includes a pull-up resistor and a pull-down resistor. The main calibration circuit is specifically configured to adjust the pull-down calibration code in response to a pull-down enable signal in the enable state until the pull-down resistor meets a preset condition; and to adjust the pull-up calibration code in response to a pull-up enable signal in the enable state until the pull-up resistor meets a preset condition. The state machine is specifically configured to adjust the calibration state signal to a first state in response to the pull-down enable signal changing from a disabled state to an enabled state; and to adjust the calibration state signal to a second state in response to the pull-up enable signal changing from an enabled state to a disabled state. The ZQ calibration process includes a pull-down calibration phase and a pull-up calibration phase. In the pull-down calibration phase, the pull-down enable signal is in an enabled state and the pull-up enable signal is in a disabled state. In the pull-up calibration phase, the pull-down enable signal is in a disabled state and the pull-up enable signal is in an enabled state.

8. The resistance calibration circuit according to claim 7, characterized in that, The main calibration circuit includes: The resistor and comparison module includes the pull-down resistor and is configured to receive and adjust the resistance value of the pull-down resistor using the pull-down calibration code; during the period when the pull-down enable signal is in the enabled state, the resistance value of the pull-down resistor is compared with a standard resistance value, and a comparison signal is output. An adjustment module, connected to the resistor and comparison module, is configured to receive the comparison signal; during the period when the pull-down enable signal is enabled, the pull-down calibration code is adjusted once based on the comparison signal in each calibration cycle; The resistor and comparison module further includes the pull-up resistor and is configured to receive and adjust the resistance value of the pull-up resistor using the pull-up calibration code; during the period when the pull-up enable signal is in the enabled state, compare the resistance value of the pull-up resistor with the standard resistance value and output the comparison signal; The adjustment module is configured to receive the comparison signal; and during the period when the pull-up enable signal is in the enabled state, adjust the pull-up calibration code once based on the comparison signal in each calibration cycle.

9. The resistance calibration circuit according to claim 8, characterized in that, The main calibration circuit includes: A control module, connected to the adjustment module, is configured to output a calibration clock signal; and to perform periodic counting on the calibration clock signal, and when the count value is a preset threshold, to output an update code pulse based on the rising edge of the calibration clock signal. The first latch circuit includes a second flip-flop and a third flip-flop; the second latch circuit includes a fourth flip-flop and a fifth flip-flop. The input of the second flip-flop receives a pull-up calibration code, and the clock terminal of the second flip-flop receives the update code pulse; the input of the third flip-flop receives a pull-down calibration code, and the clock terminal of the third flip-flop receives the update code pulse. The input of the fourth flip-flop is connected to the output of the second flip-flop, the clock terminal of the fourth flip-flop receives the target latch command, and the fourth flip-flop outputs the target pull-up calibration code; the input of the fifth flip-flop is connected to the output of the third flip-flop, the clock terminal of the fifth flip-flop receives the target latch command, and the clock terminal of the fifth flip-flop outputs the target pull-down calibration code. The target pull-up calibration code and the target pull-down calibration code together constitute the target calibration code.

10. The resistance calibration circuit according to claim 8, characterized in that, The resistor and comparison module includes: A resistor module, including the pull-up resistor, the pull-down resistor, and a standard resistor, is configured to output a first voltage and a second voltage; wherein the first voltage indicates the voltage division result of the pull-down resistor and the standard resistor, and the second voltage indicates the voltage division result of the pull-up resistor and the pull-down resistor; The comparator circuit is configured to, in response to the pull-down enable signal in the enable state, compare the pull-down reference voltage and the first voltage to generate the comparison signal; and in response to the pull-up enable signal in the enable state, compare the pull-up reference voltage and the second voltage to generate the comparison signal.

11. A memory, characterized in that, Includes the resistance calibration circuit as described in any one of claims 1-10.

12. An electronic device, characterized in that, Includes the memory as described in claim 11.

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