Automatic identification method for resolution and frame rate of coaxial video signal

Abstract

The invention discloses an automatic identification method for resolution and frame rate of a coaxial video signal, which belongs to the technical field of signal processing, and comprises the following steps: filtering the coaxial video signal to obtain a filtered signal; generating a line synchronization pulse and a width thereof based on a zero-crossing judgment level value and the filtering signal, the zero-crossing judgment level value being configured to be adaptively adjustable; generating a point counting reset signal according to the line synchronization pulse, and obtaining the total sample point number of each line; carrying out stability verification on the total sample point number of multiple continuous rows; identifying a frame synchronization identifier, and obtaining the total line number of each frame; performing stability verification on the total line number of the continuous multiple frames; and matching the total line number which tends to be stable and the verified total sample point number with a preset video system parameter, and determining the resolution and the frame rate of the coaxial video signal. According to the method and the device, the resolution and the frame rate of the input coaxial video signal can be accurately and quickly identified, so that a decoder can conveniently configure correct decoding parameters, and normal picture output of decoding is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and in particular to a method for automatically identifying the resolution and frame rate of a coaxial video signal. BACKGROUND

[0002] In the fields of video monitoring, broadcast point and multimedia processing, analog coaxial video signals (such as CVBS) are still widely used due to their reliable transmission and low cost. In order to digitize, store, display or further process these analog signals, a digital video recorder (DVR) or a video acquisition device needs to first decode the input analog signal. Accurate identification of the resolution and frame rate of the video signal is a prerequisite for ensuring that the video image can be correctly decoded and restored with high quality.

[0003] Currently, the existing identification and matching methods mainly have the following problems:

[0004] 1. Relying on manual presetting and configuration: the device operator needs to manually select the corresponding mode at the DVR end according to the known standard (such as PAL, NTSC) or known output format of the front-end camera. This method is inefficient, has poor flexibility, and is prone to decoding failure and image abnormalities due to incorrect mode selection.

[0005] 2. Poor compatibility: many DVRs only have a few standard format decoding schemes built-in (such as only supporting standard PAL 625 lines / 50 fields or NTSC 525 lines / 60 fields). When a camera with a non-standard or custom resolution / frame rate is connected, the device cannot adapt, resulting in incompatibility or poor image quality.

[0006] 3. Low accuracy of automatic identification: some improved schemes attempt to estimate the frame rate and line number by detecting the number of field synchronization pulses or line synchronization pulses. However, this method is easily disturbed by signal noise, pulse jitter and complex video content (such as strong bright and dark changes), and can only roughly estimate, cannot accurately obtain the line number and point number of the effective image, and the result is unreliable.

[0007] Therefore, the existing technology cannot meet the needs of automatically, quickly and accurately identifying coaxial video signals, resulting in problems such as complicated configuration, poor compatibility and unstable decoding quality in the decoding process of DVR devices. SUMMARY

[0008] The present application aims to provide a method for automatically identifying the resolution and frame rate of a coaxial video signal, to solve the problem of relying on manual presetting and fixed decoding mode in the prior art, which cannot automatically and accurately identify the resolution and frame rate of a coaxial video signal, thereby causing low decoding efficiency of a DVR.

[0009] To achieve the above object, the application adopts the following technical solutions:

[0010] The application discloses an automatic identification method for resolution and frame rate of a coaxial video signal, which comprises the following steps:

[0011] Filtering processing is performed on the input digital coaxial video signal to obtain a filtered signal containing synchronization timing information;

[0012] Based on a zero-crossing judgment level value and the filtered signal, a horizontal synchronization pulse is generated, and the width of the horizontal synchronization pulse is counted, wherein the zero-crossing judgment level value is configured to be adaptively adjusted based on the width of the horizontal synchronization pulse;

[0013] A dot count reset signal is generated according to the horizontal synchronization pulse, and a dot counter is controlled to continuously count samples based on the dot count reset signal, so as to obtain the total number of samples per line;

[0014] The total number of samples of continuous multiple lines is verified for stability, so as to output the verified total number of samples;

[0015] A frame synchronization identifier is identified based on the width of the horizontal synchronization pulse, and a line counter is controlled to continuously count lines based on the frame synchronization identifier, so as to obtain the total number of lines per frame;

[0016] The total number of lines of continuous multiple frames is verified for stability, so as to output the total number of lines that tends to be stable;

[0017] The total number of lines that tends to be stable and the verified total number of samples are matched with preset video system parameters, so as to determine the resolution and frame rate of the coaxial video signal.

[0018] Preferably, the filtering processing is mean filtering, and the calculation formula is:

[0019] ,

[0020] wherein flt_s(i) represents the filtering output value of the current sample i, S in (i-k) represents the value of the kth input signal sample before the current sample, round() represents rounding off the calculation result in the parentheses, and N represents the filtering length.

[0021] Preferably, based on the zero-crossing judgment level value and the filtered signal, the horizontal synchronization pulse is generated, and the width of the horizontal synchronization pulse is counted, which comprises:

[0022] The filtered signal is subtracted by the zero-crossing judgment level value to obtain a differential signal;

[0023] A line synchronization pulse is generated by comparing the differential signal with zero. When the differential signal is less than zero, the line synchronization pulse is at an active level; otherwise, it is at an inactive level.

[0024] The line synchronization pulses are accumulated, and the accumulated value is cleared to zero when the falling edge is detected. The accumulated value at the moment before clearing is used as the line synchronization pulse width of that line.

[0025] Preferably, the adaptive adjustment based on the line synchronization pulse width includes:

[0026] The first difference is obtained by subtracting the line synchronization pulse width of this line from the standard line synchronization pulse width;

[0027] Initialize the first counter, and update the value of the first counter based on the comparison result between the absolute value of the first difference and the preset zero-crossing judgment level error tolerance;

[0028] Based on the updated value of the first counter, the first difference, and the preset maximum value of the zero-crossing judgment level adjustment step, the adjustment amount of the current row's zero-crossing judgment level is calculated;

[0029] The adjustment amount of the zero-crossing judgment level of the current row is added to the zero-crossing judgment level value used for that row to obtain the zero-crossing judgment level value used for the next row.

[0030] Preferably, updating the value of the first counter includes:

[0031] When the absolute value of the first difference is less than or equal to the preset zero-crossing judgment level error tolerance, the value of the first counter is incremented by 1;

[0032] Otherwise, decrement the value of the first counter by 1.

[0033] Preferably, the calculation of the adjustment amount for the zero-crossing judgment level of the current row includes:

[0034] Compare the updated value of the first counter with its zero value;

[0035] When the updated value of the first counter is greater than or equal to 0, if the first difference is greater than the negative of the preset zero-crossing judgment level adjustment step size and the first difference is less than 0, then the negative of the first difference is used as the adjustment amount; if the first difference is less than the negative of the preset zero-crossing judgment level adjustment step size, then the preset zero-crossing judgment level adjustment step size is used as the adjustment amount of the current row zero-crossing judgment level.

[0036] Otherwise, the adjustment amount is 0.

[0037] Preferably, the step of generating a point count reset signal based on the row synchronization pulse, and controlling the point counter to continuously count the sample points based on the point count reset signal to obtain the total number of sample points for each row, includes:

[0038] Initialize the point counter;

[0039] A point count reset signal is generated based on the line synchronization pulse, the current value of the point counter, and the line synchronization lock state.

[0040] The value of the point counter is updated under the control of the point counter reset signal. When the point counter reset signal is valid or the current value of the point counter reaches the maximum value, the point counter is reset; otherwise, the value of the point counter is incremented by 1.

[0041] When the point counter is reset by a transition from invalid to valid in the point count reset signal, the value of the point counter before the reset is captured as the total number of samples for that row.

[0042] Preferably, generating a point count reset signal based on the line synchronization pulse, the current value of the point counter, and the line synchronization lock state includes:

[0043] When the line synchronization pulse is valid, if the current value of the point counter is greater than or equal to the total number of sample points in the previous line minus the first preset value, or if the line synchronization lock flag is invalid, a valid point count reset signal is generated.

[0044] Preferably, the stability verification of the total number of sample points across multiple consecutive rows includes:

[0045] Subtract the total number of sample points in this row from the total number of sample points in the previous row to obtain the second difference;

[0046] Initialize the second counter, and update the value of the second counter based on the comparison result of the absolute value of the second difference with the preset error range;

[0047] When the updated value of the second counter reaches the second preset value, the row synchronization is determined to be stable, and a row lock flag is output.

[0048] Preferably, updating the value of the second counter based on the comparison result between the absolute value of the second difference and a preset error range includes:

[0049] When the absolute value of the second difference is less than or equal to the preset error range, the value of the second counter is incremented by 1;

[0050] Otherwise, decrement the value of the second counter by 1.

[0051] Preferably, the step of identifying the frame synchronization identifier based on the line synchronization pulse width includes:

[0052] The line synchronization pulse widths of two consecutive lines are compared with thresholds determined based on the verified total number of samples.

[0053] When the line synchronization pulse width of the previous line is less than the threshold and the line synchronization pulse width of the current line is greater than or equal to the threshold, the frame synchronization flag is set to valid; otherwise, it is set to invalid.

[0054] Preferably, the step of controlling the line counter to continuously count lines based on the frame synchronization identifier to obtain the total number of lines in each frame includes:

[0055] Configure the row counter and its DC bias;

[0056] When the frame synchronization flag is valid, the line counter is reset to the DC bias; otherwise, the value of the line counter is incremented by 1.

[0057] When a transition from invalid to valid frame synchronization flag is detected, the current value of the transition-before-the-break counter is captured, and the DC bias is subtracted from the current value to obtain the total number of lines in the previous frame.

[0058] Preferably, the identification frame synchronization identifier further includes a misjudgment filtering step:

[0059] When the detected frame synchronization flag is set to valid, if the current value of the line counter is greater than or equal to the average total number of lines in historical multi-frames minus the third preset value, or if the average total number of lines in historical multi-frames is less than the fourth preset value, then the frame synchronization flag is confirmed to be valid; otherwise, the frame synchronization flag is determined to be a misjudgment and is removed.

[0060] Preferably, the stability verification of the total number of lines in multiple consecutive frames includes:

[0061] If the difference between the total number of rows in any two adjacent frames in a series of consecutive frames is not greater than a preset tolerance, then the total number of rows is determined to be stable.

[0062] Preferably, the step of matching the stable total number of lines and the verified total number of samples with preset video standard parameters to determine the resolution and frame rate of the coaxial video signal includes:

[0063] The stable total number of rows is matched with multiple preset numerical ranges to determine the video resolution format, wherein the video resolution formats include cvbs pal (625i), cvbs ntsc (525i), 1M (720p), 2M (1080p), 3M (1536p), 4M (1440p), 5M (1944p) and 8M (2160p);

[0064] After the video resolution standard is determined, the verified total number of sample points is matched with multiple preset frame rate threshold ranges to determine the video frame rate, wherein the video frame rate includes 7.5fps, 12.5fps, 15fps, 20fps, 18.75fps, 25fps, 30fps, 18fps, 50fps and 60fps.

[0065] The present invention has the following beneficial effects:

[0066] The method provided in this application can accurately and quickly identify the resolution and frame rate of the input coaxial video signal, so as to ensure that the DVR can quickly and accurately match and provide the corresponding decoding feature parameters during the decoding process, thereby ensuring that the video image can be decoded quickly and correctly based on the input coaxial video signal. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 This is a flowchart of an automatic identification method for coaxial video signal resolution and frame rate provided in an embodiment of this application;

[0069] Figure 2 This is a schematic diagram of the structure of the Slice module provided in an embodiment of this application;

[0070] Figure 3 This is a flowchart illustrating the generation of line synchronization pulses and their widths, provided in an embodiment of this application.

[0071] Figure 4 This is a flowchart illustrating the adaptive adjustment of the zero-crossing judgment level value provided in an embodiment of this application;

[0072] Figure 5 This is a flowchart illustrating the process of obtaining the total number of sample points for each row, as provided in an embodiment of this application.

[0073] Figure 6 This is a flowchart of the stability verification of the total number of sample points provided in the embodiments of this application;

[0074] Figure 7 This is a flowchart for obtaining the total number of rows provided in an embodiment of this application. Detailed Implementation

[0075] To make the technical solution of this application clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The terms "first," "second," etc., in the claims and specification of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate. This is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0076] like Figure 1 As shown, this disclosure provides an automatic method for identifying the resolution and frame rate of a coaxial video signal, including the following steps:

[0077] S110. Filter the input digital coaxial video signal to obtain a filtered signal containing synchronization timing information;

[0078] After acquiring the analog coaxial video signal, it is first converted into a digital coaxial video signal using an analog-to-digital converter (ADC), and then the obtained digital coaxial video signal is input into the system for automatic identification of resolution and frame rate.

[0079] During the automatic recognition process, the input digital coaxial video signal is first filtered to obtain a filtered signal containing synchronization timing information. This filtering process aims to remove high-frequency noise and interference components from the signal, thereby highlighting key timing information such as horizontal and vertical synchronization edges, providing a stable foundation for subsequent resolution and frame rate detection.

[0080] In this embodiment, the filtering process preferentially employs a mean filtering algorithm, the core of which is to smooth the signal by calculating the average value of consecutive samples. Mean filtering can effectively suppress random noise while preserving the DC and low-frequency components of the signal, making it particularly suitable for extracting synchronization timing from coaxial video signals. The filter length N is an adjustable parameter that can be flexibly set according to actual application requirements (such as signal sampling rate, noise level, etc.) and system performance requirements; the default value is 16.

[0081] The specific calculation formula for mean filtering is as follows:

[0082] ,

[0083] Where flt_s(i) represents the filtered output value of the current sample point i, and S in(ik) represents the value of the kth input signal sample point before the current sample point, and round() rounds the calculation result within the parentheses to ensure that the output value is an integer, which conforms to the specifications of digital signal processing.

[0084] This mean filtering process removes high-frequency information from the digital coaxial video signal, retaining only low-frequency synchronization timing information, such as horizontal and vertical sync edges. This helps subsequent steps accurately detect the signal's resolution and frame rate, improving the robustness and accuracy of the automatic recognition system.

[0085] S120. Based on the zero-crossing judgment level value and the filtered signal, a horizontal synchronization pulse is generated, and the width of the horizontal synchronization pulse is calculated. The zero-crossing judgment level value is configured to be adaptively adjusted based on the width of the horizontal synchronization pulse.

[0086] This disclosure also includes a Slice module, the structure of which is as follows: Figure 2 As shown. The Slice module is an automatic adjustment and update process that performs cyclic feedback on a line-by-line basis. Its function is to obtain the line synchronization pulse Hsyn and the line synchronization pulse width wd_syn from the low-frequency signal containing line synchronization timing information in the filtered output, and adaptively adjust the zero-crossing judgment level value based on the line synchronization pulse width to ensure accurate extraction of the line synchronization signal.

[0087] The Slice module first generates a row synchronization pulse Hsyn based on the zero-crossing judgment level value of the previous row (denoted as slice_val, with an initial value of 0) and the mean filter signal flt_s of the current row, and then calculates the row synchronization pulse width wd_syn.

[0088] In some embodiments, such as Figure 3 As shown, based on the zero-crossing judgment level value and the filtered signal, a horizontal synchronization pulse is generated, and the width of the horizontal synchronization pulse is calculated. Specifically, the process includes the following steps:

[0089] S210. Subtract the zero-crossing judgment level value from the filtered signal to obtain the differential signal;

[0090] S220. A horizontal synchronization pulse is generated by comparing the differential signal with zero. When the differential signal is less than zero, the horizontal synchronization pulse is at an active level; otherwise, it is at an inactive level.

[0091] S230. Accumulate the horizontal synchronization pulses and clear the accumulated value to zero when the falling edge is detected. Use the accumulated value just before clearing to be the width of the horizontal synchronization pulse for that line.

[0092] Specifically, the zero-crossing judgment level value slice_val is first subtracted from the mean-filtered signal flt_s to obtain the differential signal slice_signal, that is:

[0093] .

[0094] The horizontal synchronization pulse Hsyn is then generated by comparing the differential signal slice_signal with zero. Specifically, when the differential signal is less than zero, the horizontal synchronization pulse is at an active level (e.g., high level 1); otherwise, it is at an inactive level (e.g., low level 0).

[0095] The expression for generating the line synchronization pulse, using sample point i as the unit, is:

[0096] ;

[0097] Where i represents the index of the current sample point.

[0098] Next, the horizontal synchronization pulse Hsyn is accumulated in real time, and the accumulated value is cleared to zero when the falling edge of Hsyn is detected. At the same time, the accumulated value just before clearing is used as the horizontal synchronization pulse width for that line, denoted as wd_syn. This width value reflects the effective duration of the horizontal synchronization pulse and is used for subsequent adaptive adjustment.

[0099] After obtaining the line synchronization pulse width wd_syn for the current line, the Slice module adaptively updates the zero-crossing judgment level value to optimize the extraction of line synchronization for the next line.

[0100] In some embodiments, such as Figure 4 As shown, adaptive adjustment based on the line synchronization pulse width specifically includes the following steps:

[0101] S310. Subtract the line synchronization pulse width of this line from the standard line synchronization pulse width to obtain the first difference value;

[0102] S320. Initialize the first counter and update the value of the first counter based on the comparison result between the absolute value of the first difference and the preset zero-crossing judgment level error tolerance.

[0103] S330. Based on the updated value of the first counter, the first difference, and the preset maximum value of the zero-crossing judgment level adjustment step, calculate the adjustment amount of the current row's zero-crossing judgment level;

[0104] S340. Add the adjustment amount of the zero-crossing judgment level of the current row to the zero-crossing judgment level value used for the current row to obtain the zero-crossing judgment level value used for the next row.

[0105] Specifically, the line synchronization pulse width wd_syn of the current line is first subtracted from the preset standard line synchronization pulse width std_wd_syn to obtain the first difference err, which is used to measure the error of the current line synchronization width, i.e. err = wd_syn - std_wd_syn.

[0106] A first counter, cnt, is initialized with an initial value of -16 and a range of [-16, 15]. The value of the first counter is updated based on the comparison between the absolute value of the first difference err and the preset zero-crossing error tolerance slice_error. The update rules are as follows:

[0107] ;

[0108] Where j represents the current signal line number, cnt j cnt is the value of the first counter in the current row j. j-1 The value of the first counter on the previous line is err. j This represents the line synchronization width error for the current line j. The zero-crossing level error tolerance `slice_error` is a configurable parameter used to define the acceptable error range.

[0109] Then, based on the value of the first counter cnt, the first difference err, and the preset zero-crossing judgment level adjustment step size slice_step, the adjustment amount err0 of the current row's zero-crossing judgment level is calculated. The specific calculation process includes:

[0110] 1. Compare cnt with zero;

[0111] 2. If cnt ≥ 0, and err > -slice_step and err < 0, then the adjustment amount err = -err (i.e., take the negative of the error to reduce negative errors). If err ≤ -slice_step, then the adjustment amount err0 = slice_step (i.e., use the maximum step size for rapid adjustment). Otherwise (i.e., err ≥ 0), the adjustment amount err0 = 0 (positive errors are not adjusted).

[0112] If cnt < 0, then the adjustment amount err0 = 0 (the counter has not reached the threshold, so no adjustment is made).

[0113] The expression for err0 is as follows:

[0114] .

[0115] Among them, err 0j This represents the value of err0, which indicates the adjustment amount of the zero-crossing judgment level for the current row with row number j.

[0116] This logic ensures that adjustments are made only when the first counter is non-negative and the error is negative, and the adjustment amount is limited by slice_step to avoid over-adjustment.

[0117] Next, the adjustment value err0 is compared with the zero-crossing level value slice_val of the current row. j-1The sums are used to obtain the zero-crossing level value slice_val for the next line. j That is, slice_val j = slice_val j-1 +err 0j .

[0118] The updated zero-crossing detection level will be used to generate the next line's line synchronization pulse, forming a closed-loop feedback mechanism.

[0119] Through the above process, the Slice module can dynamically adapt to changes in the input signal, accurately extract the horizontal synchronization pulse, and optimize the zero-crossing judgment level. This adaptive adjustment improves the system's robustness to noise and signal fluctuations, ensuring the stability of the horizontal synchronization signal. The entire process iterates line by line, achieving efficient and reliable real-time processing.

[0120] S130. Generate a point count reset signal based on the line synchronization pulse, and control the point counter to continuously count the sample points based on the point count reset signal to obtain the total number of sample points for each line.

[0121] After acquiring the horizontal synchronization pulse and its width, the system enters the horizontal sample counting stage. Its core purpose is to accurately count the total number of samples for each video line, which is a key parameter for subsequent calculations of resolution and frame rate. This counting process is accomplished using a point counter.

[0122] In some embodiments, such as Figure 5 As shown, a point count reset signal is generated based on the line synchronization pulse, and the point counter is controlled to continuously count the sample points based on the point count reset signal to obtain the total number of sample points for each line, including:

[0123] S410, Initialize the point counter;

[0124] S420: Generates a point count reset signal based on the line synchronization pulse, the current value of the point counter, and the line synchronization lock status;

[0125] S430. Update the value of the point counter under the control of the point counter reset signal, wherein the point counter is reset when the point counter reset signal is valid or the current value of the point counter reaches the maximum value; otherwise, the value of the point counter is incremented by 1.

[0126] S440. When the reset operation of the dot counter is triggered by the dot counter reset signal transitioning from invalid to valid, the value of the dot counter before the reset is captured as the total number of samples for that row.

[0127] First, a 14-bit dot counter, denoted as point_cnt, is initialized and its initial value is set to 0. This bit width design ensures that the dot counter has a sufficient counting range to accommodate the maximum number of samples that may be contained in a single line of a video signal at different resolutions.

[0128] Taking into account the current horizontal synchronization pulse Hsyn i The real-time value of the point counter, point_cnt, and the system's line synchronization lock status, H_lock, generate the point counter reset signal Hsyn0.

[0129] The specific rules for generating the point count reset signal Hsyn0 are as follows: 1) When the horizontal synchronization pulse is valid (i.e., Hsyn... i When =1), further determine if the current value of the point counter, point_cnt(i), is greater than or equal to "the total number of sample points finally determined in the previous row" minus a first preset value (128 in this embodiment). This design acts as a dynamic tolerance window, allowing the line length to fluctuate normally within a small range, but effectively filtering out abnormal line synchronization pulses caused by signal jitter or noise. 2) The line synchronization lock flag H_lock is invalid (i.e., H_lock=0), which usually occurs during system startup or the re-acquisition phase after synchronization loss. In this state, any valid line synchronization pulse will be responded to immediately to quickly establish synchronization.

[0130] When either of the above two conditions is met, a valid point count reset signal will be generated (i.e., Hsyn0=1); otherwise, Hsyn0 remains invalid (i.e., Hsyn0=0).

[0131] The mathematical expression for Hsyn0 is:

[0132] .

[0133] Where Hsyn0(i) is the point count reset signal corresponding to point i, Hsyn(i) is the line synchronization pulse corresponding to point i, and point_cnt(i) is the point counter value corresponding to point i.

[0134] The point counter point_cnt is updated according to the reset signal Hsyn0 in each sample clock cycle, and its state transition rule is as follows:

[0135] If the dot counter reset signal is valid (Hsyn0=1) or the current value of the dot counter has reached its maximum value, the dot counter is reset to 0; if the above reset conditions are not met, the value of the dot counter is incremented by 1.

[0136] The expression for this update rule is:

[0137] .

[0138] This design ensures the correct behavior of the dot counter in three scenarios: normal counting, normal row end reset, and prevention of count overflow.

[0139] The capture of the total sample count max_H for each row mainly depends on the valid transition of the point counter reset signal Hsyn0. The specific determination logic is as follows: continuously monitor the state of Hsyn0. When Hsyn0 is detected to transition from the invalid state (0) of the previous row to the valid state (1) of the current row, it is determined that this is a valid row end event. At the moment when this transition triggers the point counter reset, the final value of the point counter before the reset is immediately captured and latched, and this value is determined as the total sample count max_H of the row. If the above transition from "0" to "1" does not occur, max_H remains unchanged from the value of the previous row.

[0140] The logical expression for this process is:

[0141] .

[0142] Here, point_cnt(i-1) represents the point counter value corresponding to the point i.

[0143] Through this logical judgment rule, the system can accurately record the number of samples contained in each complete row cycle.

[0144] S140. Perform stability verification on the total number of samples in multiple consecutive rows, and output the verified total number of samples.

[0145] This embodiment also includes a line synchronization stability verification mechanism, the core of which is to monitor and judge the total number of sample points across multiple consecutive lines to ensure that the line synchronization signal has been stably locked. As a decision-maker, this mechanism can effectively filter out random errors caused by signal jitter or interference, and finally output a reliable line lock flag (H_lock).

[0146] The stability verification process is centered around a configurable second counter, which makes a decision by monitoring the fluctuation of the total number of samples across multiple consecutive rows.

[0147] In some embodiments, such as Figure 6 As shown, stability verification is performed on the total number of sample points across multiple consecutive rows, including:

[0148] S510. Subtract the total number of sample points in this row from the total number of sample points in the previous row to obtain the second difference;

[0149] S520. Initialize the second counter, and update the value of the second counter based on the comparison result between the absolute value of the second difference and the preset error range;

[0150] S530. When the updated value of the second counter reaches the second preset value, it is determined that the row synchronization is stable and a row lock flag is output.

[0151] In this embodiment, after obtaining the total number of sample points in the current row, it is subtracted from the total number of sample points in the previous row (i.e., the row before), to obtain the second difference value err_pt. This difference value reflects the degree of fluctuation in the row period between adjacent rows.

[0152] Simultaneously, a second counter, cnt0, is initialized with an initial value of -16 and a range of [-16, 15]. The value of this counter is updated based on a comparison between the absolute value of the second difference, err_pt, and a preset error range. This error range defines the upper limit of normal line-cycle jitter allowed by the system.

[0153] The update logic for the second counter is as follows:

[0154] ,

[0155] Among them, cnt 0j cnt is the second counter value for the current row with row number j. 0j-1 This is the value of the second counter in the row preceding j.

[0156] In other words, when the difference in the total number of samples between adjacent rows is within the allowable tolerance range, the comparison result is considered "stable," and the second counter is incremented by 1; conversely, if the difference exceeds the tolerance range, it is considered "unstable," and the second counter is decremented by 1. This increment-decrement mechanism forms an integrator, and the second counter can only accumulate to a positive threshold when there are enough consecutive stable rows.

[0157] Then, update the value cnt of the second counter. 0j It is compared with a second preset value (which is 0 in this logic). When the value of the second counter increases and reaches or exceeds the preset value, it is determined that the row synchronization has entered a stable state.

[0158] The expression for the lock flag H_lock is:

[0159] .

[0160] When H_lock is 1, it indicates that the system has successfully locked the line synchronization. At this time, the total number of output samples is considered stable and reliable, and can be used by subsequent circuits (such as image buffering, timing generation, etc.). When H_lock is 0, it indicates that the line synchronization has not yet stabilized or has been lost, and the system is still in the capture and adjustment state.

[0161] This stability verification mechanism is implemented through a digital filter (the second counter) with hysteresis characteristics, and has beneficial effects such as strong anti-interference ability, reliable judgment, and quick response to loss of lock. It works in coordination with the aforementioned Slice module to jointly form a complete, adaptive, and stable horizontal synchronization signal extraction and verification system.

[0162] S150. Identify the frame synchronization identifier based on the horizontal synchronization pulse width, and control the row counter to continuously count the rows based on the frame synchronization identifier to obtain the total number of rows per frame;

[0163] After the horizontal synchronization signal Hsyn is stably locked, the system enters the frame synchronization identification and frame total row number statistics stage. The core task of this stage is to accurately identify the starting position of the frame (i.e., the frame synchronization identifier), and use this to control the row counter to perform continuous counting, ultimately obtaining the total number of rows in each frame.

[0164] The frame synchronization identifier Fsyn0 is used to mark the starting row of a frame of image (usually a specific row in the vertical blanking period). Its identification does not rely on additional dedicated pulses, but is achieved by analyzing the jump of the horizontal synchronization pulse widths wd_syn of two consecutive rows.

[0165] Its determination logic is as follows: First, set a determination threshold (max_H / 2), which is used to distinguish normal horizontal synchronization pulses and the horizontally synchronized pulses with abnormal widths unique to frame synchronization. Here, max_H is based on the total number of samples after stability verification. Then compare the horizontal synchronization pulse widths of two consecutive rows with this threshold respectively. When the horizontal synchronization pulse width of the previous row is less than the threshold (i.e., wd_syn j-1 <max_H / 2) and the horizontal synchronization pulse width of the current row is greater than or equal to the threshold (i.e., wd_syn j >= max_H / 2), it is determined that a unique sequence marking the start of the frame appears. At this time, set the frame synchronization identifier Fsyn0 to be valid (such as high level 1), otherwise, set the frame synchronization identifier Fsyn0 to be invalid (such as low level 0).

[0166] That is, the mathematical expression of this determination logic is:

[0167] .

[0168] Among them, Fsyn0(j) is the frame synchronization identifier of the current row with row number j, wd_syn j is the horizontal synchronization width of the current row, and wd_syn j-1 is the horizontal synchronization width of the row above j.

[0169] Then perform row counting according to the frame synchronization identifier Fsyn0.

[0170] In some embodiments, such asFigure 7 As shown, the frame synchronization flag controls the line counter to continuously count the lines to obtain the total number of lines in each frame, including:

[0171] S610, Set the row counter and its DC bias;

[0172] S620. When the frame synchronization flag is valid, reset the line counter to DC bias; otherwise, increment the value of the line counter by 1.

[0173] S630. When a transition from invalid to valid frame synchronization flag is detected, the current value of the line counter before the transition is captured, and the DC bias is subtracted from the current value to obtain the total number of lines of the previous frame.

[0174] First, initialize a 12-bit row counter, denoted as row_cnt, and set its initial value to 0. At the same time, set its DC bias A, which is usually a non-zero initial value (default is 1). Its purpose is to provide a buffer when the counter is reset, to ensure that the counting range can completely cover all rows from the start of the field blanking period to the end of the field positive period, and to avoid zero or negative values, thus simplifying the subsequent logic design.

[0175] It should be noted that, due to the potential presence of noise or interference in the signal, the initially determined frame synchronization flag Fsyn0 may be misjudged. To ensure the reliability of frame synchronization identification, the system also introduces a dedicated misjudgment filtering mechanism. Specifically, when the detected frame synchronization flag Fsyn0(j) is valid, the system will not immediately confirm it as the final frame synchronization signal. Instead, it will check whether the current value of the line counter row_cnt falls within a preset reasonable range. If the current value of the line counter is greater than or equal to the average total number of rows in historical multi-frames minus a third preset value (e.g., 16), or if the average total number of rows in historical multi-frames is less than a fourth preset value (e.g., 16), then the frame synchronization detection is determined to be valid, and the final frame synchronization flag Fsyn is set to valid. Otherwise, the detection is considered a misjudgment caused by interference, and the system will ignore the trigger, leaving the final frame synchronization flag Fsyn invalid.

[0176] The mathematical expression for the misjudgment filtering logic is:

[0177] .

[0178] Where Fsyn(j) is the final frame synchronization identifier of the current row with row number j, row_cnt(j) is the value of the row counter of the current row, and max_V0 is the average of the total number of rows max_V of the previous 8 frames.

[0179] After filtering, the row counter `row_cnt` is updated based on the final frame synchronization flag `Fsyn`. The update rule is as follows: when the frame synchronization flag `Fsyn` is valid, indicating the detection of the start of a new frame, the value of the row counter `row_cnt` is immediately reset to a preset DC bias value. When the frame synchronization flag (`Fsyn`) is invalid, at the end of the valid period of each row (e.g., at the falling edge of the row synchronization pulse), the current value of the row counter `row_cnt` is incremented by 1. Thus, the row counter starts from the DC bias and increments with each new row until the next frame synchronization arrives.

[0180] The mathematical expression for this update rule is as follows:

[0181] .

[0182] Finally, the total number of rows in the frame, max_V, is calculated based on the frame synchronization flags of two consecutive lines. Specifically, when a rising edge transition from invalid to valid is detected in the frame synchronization flag Fsyn, the current value of the row counter row_cnt is immediately captured immediately before the transition occurs. This value represents the total number of rows counted from the beginning of the previous frame to the beginning of the current frame. Subtracting the preset DC bias from this captured value yields the actual total number of rows in the previous frame, denoted as max_V.

[0183] That is, the expression for max_V is:

[0184] .

[0185] Through this closed-loop control mechanism, the system can accurately count the total number of lines of the video signal frame by frame, continuously and precisely.

[0186] S160. Perform stability verification on the total number of lines in multiple consecutive frames to output a stable total number of lines.

[0187] To ensure that the total number of frames acquired is stable and reliable, and to avoid misjudgment due to transient signal interference, the system introduces a stability verification mechanism for the total number of frames.

[0188] This mechanism continuously monitors the total number of lines in the latest consecutive frames (e.g., four consecutive frames, denoted as N=4) and determines whether the difference in the total number of lines between any two adjacent frames within these N consecutive frames is no greater than a preset tolerance (e.g., ±16 lines). If the above condition is met, meaning the fluctuation in the number of lines across consecutive frames is within the allowable range, then the total number of lines is considered to have stabilized. At this point, the system can confirm that the frame structure of the video signal has been reliably identified and can output a final, stable total number of lines for subsequent processing.

[0189] It should be noted that the number of consecutive verification frames N and the preset tolerance are parameters that can be adjusted according to the actual application scenario and signal characteristics, so as to achieve a balance between reliability and convergence speed.

[0190] S170. Match the stable total number of lines and the verified total number of samples with the preset video standard parameters to determine the resolution and frame rate of the coaxial video signal.

[0191] After successfully obtaining a stable total number of lines (max_V) and a verified total number of samples (max_H), the system enters the final determination stage for resolution and frame rate. The core purpose of this stage is to match these measured parameters with a preset standard video format parameter database, thereby automatically identifying the resolution format and frame rate of the input coaxial video signal.

[0192] First, the stable total number of lines max_V is matched with a series of preset total number of lines ranges corresponding to different resolution formats. The resolution formats include, but are not limited to, common formats such as cvbs pal (625i), cvbs ntsc (525i), 1M (720p), 2M (1080p), 3M (1536p), 4M (1440p), 5M (1944p) and 8M (2160p).

[0193] The mathematical expression for its matching logic is as follows:

[0194] ,

[0195] Here, represents the output resolution index value, and each index value uniquely maps to a specific resolution standard (e.g., 0 represents PAL, 1 represents NTSC, etc.).

[0196] After successfully determining the video resolution format (i.e., resolution_idx is determined), the system further uses the verified total number of samples max_H, which can effectively reflect the line period length, to determine the frame rate of the signal.

[0197] Specifically, based on the determined resolution standard, a set of frame rate determination threshold ranges corresponding to it is selected, and max_H is matched with these ranges. The frame rate includes, but is not limited to, common frame rate formats such as 7.5fps, 12.5fps, 15fps, 20fps, 18.75fps, 25fps, 30fps, 18fps, 50fps, and 60fps.

[0198] The mathematical expression for this decision logic is as follows:

[0199] ,

[0200] Where fps_idx is the output frame rate index value, and each index value uniquely maps to a specific frame rate, H_thL0~H_thL 16 This represents the lower limit of the range of the total number of signal line samples at a specific resolution and frame rate, H_thR0~H_thR 16 This represents the upper limit of the range of the total number of signal line samples at a specific resolution and frame rate.

[0201] It should be noted here that the frame rate determination threshold is H_thL0~H_thL 16 (Lower limit of the interval) and H_thR0~H_thR 16 The upper limit of the range is not a fixed value; its specific value is closely related to the sampling clock frequency of the system's analog-to-digital converter (ADC). This system pre-calculates and stores the theoretical range of max_H (i.e., the aforementioned threshold) for each combination of resolution and frame rate for the ADC sampling clock used, thereby ensuring the accuracy and adaptability of frame rate determination.

[0202] Through the above two-level, progressive matching process, the system finally outputs a combination of resolution_idx and fps_idx, thereby uniquely and accurately determining the resolution and frame rate of the coaxial video signal.

[0203] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for automatic identification of resolution and frame rate of a coaxial video signal, characterized in that, The method comprises the following steps: filtering an input digital coaxial video signal to obtain a filtered signal containing synchronization timing information; generating a horizontal synchronization pulse based on a zero-crossing judgment level value and the filtered signal, and counting the width of the horizontal synchronization pulse, wherein the zero-crossing judgment level value is configured to be adaptively adjusted based on the width of the horizontal synchronization pulse; generating a dot count reset signal according to the horizontal synchronization pulse, and controlling a dot counter to continuously count samples based on the dot count reset signal to obtain the total number of samples per row; verifying the stability of the total number of samples of multiple consecutive rows to output a verified total number of samples; identifying a frame synchronization identifier based on the width of the horizontal synchronization pulse, and controlling a row counter to continuously count rows based on the frame synchronization identifier to obtain the total number of rows per frame; verifying the stability of the total number of rows of multiple consecutive frames to output a total number of rows that tends to be stable; matching the total number of rows that tends to be stable and the verified total number of samples with preset video format parameters to determine the resolution and frame rate of the coaxial video signal.

2. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 1, characterized in that, The filtering is mean filtering, and the calculation formula is: ， Wherein, flt_s(i) represents the filter output value of the current sample i, S in (i-k) represents the value of the kth input signal sample before the current sample, round() represents rounding the calculation result in the parentheses, and N represents the filter length.

3. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 1, characterized in that, The generation of the horizontal synchronization pulse based on the zero-crossing judgment level value and the filtered signal, and the counting of the width of the horizontal synchronization pulse, comprises: subtracting the zero-crossing judgment level value from the filtered signal to obtain a difference signal; generating the horizontal synchronization pulse by comparing the difference signal with zero, wherein the horizontal synchronization pulse is at a valid level when the difference signal is less than zero, and is at an invalid level otherwise; accumulating the horizontal synchronization pulse, and resetting the accumulated value when a falling edge of the horizontal synchronization pulse is detected, wherein the accumulated value at the moment before the resetting is taken as the width of the horizontal synchronization pulse of the row.

4. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 3, characterized in that, The adaptive adjustment based on the width of the horizontal synchronization pulse comprises: subtracting the width of the horizontal synchronization pulse of the row from a standard width of the horizontal synchronization pulse to obtain a first difference value; initializing a first counter, and updating the value of the first counter according to the comparison result of the absolute value of the first difference value and a preset zero-crossing judgment level error tolerance; calculating an adjustment amount of the current row zero-crossing judgment level based on the updated value of the first counter, the first difference value, and a preset zero-crossing judgment level adjustment step maximum value; adding the adjustment amount of the current row zero-crossing judgment level to the zero-crossing judgment level value used for the row to obtain the zero-crossing judgment level value used for the next row.

5. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 4, characterized in that, The updating of the value of the first counter comprises: when the absolute value of the first difference value is less than or equal to the preset zero-crossing judgment level error tolerance, increasing the value of the first counter by 1; otherwise, decreasing the value of the first counter by 1.

6. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 5, characterized in that, The calculation of the adjustment amount of the current row zero-crossing judgment level comprises: comparing the updated value of the first counter with zero; When the updated value of the first counter is greater than or equal to 0, if the first difference is greater than the opposite of the preset maximum adjustment step of the zero-crossing judgment level and the first difference is less than 0, the opposite of the first difference is taken as the adjustment amount; if the first difference is less than the opposite of the preset maximum adjustment step of the zero-crossing judgment level, the preset maximum adjustment step of the zero-crossing judgment level is taken as the adjustment amount of the current line zero-crossing judgment level; Otherwise, the adjustment amount is 0.

7. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 1, characterized in that, The point counter is initialized. The point count reset signal is generated based on the line synchronization pulse, the current value of the point counter and the line synchronization lock state. The value of the point counter is updated under the control of the point count reset signal, wherein when the point count reset signal is valid or the current value of the point counter reaches the maximum value, the point counter is reset, otherwise the value of the point counter is increased by 1. When the reset operation of the point counter is triggered by the jump of the point count reset signal from invalid to valid, the value of the point counter before the reset is captured as the total sample number of the line. The point count reset signal is generated based on the line synchronization pulse, the current value of the point counter and the line synchronization lock state, including:

8. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 7, characterized in that, When the line synchronization pulse is valid, if the current value of the point counter is greater than or equal to the total sample number of the previous line minus a first preset value or the line synchronization lock state is invalid, a valid point count reset signal is generated. The stability of the total sample number of the continuous multiple lines is verified, including:

9. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 8, characterized in that, The second difference is obtained by subtracting the total sample number of the line from the total sample number of the previous line. The second counter is initialized, and the value of the second counter is updated based on the comparison result of the absolute value of the second difference and the preset error range. When the updated value of the second counter reaches a second preset value, it is determined that the line synchronization is stable, and a line lock identifier is output. The value of the second counter is updated based on the comparison result of the absolute value of the second difference and the preset error range, including:

10. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 9, characterized in that, When the absolute value of the second difference is less than or equal to the preset error range, the value of the second counter is increased by 1; Otherwise, the value of the second counter is decreased by 1. The frame synchronization identifier is identified based on the line synchronization pulse width, including:

11. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 1, characterized in that, The line synchronization pulse widths of the continuous two lines are compared with the threshold value determined based on the verified total sample number, respectively. When the line synchronization pulse width of the previous line is less than the threshold value and the line synchronization pulse width of the line is greater than or equal to the threshold value, the frame synchronization identifier is set to valid, otherwise it is set to invalid. The total line number of each frame is obtained by continuously counting the lines based on the frame synchronization identifier, including:

12. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 11, characterized in that, The line counter and its direct current bias are set; When the frame synchronization identifier is valid, the line counter is reset to the direct current bias, otherwise the value of the line counter is increased by 1; ​ When detecting the jump of the frame synchronization identifier from invalid to valid, the current value of the line counter before the jump is captured and the current value is subtracted by the DC offset to obtain the total line number of the previous frame.

13. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 12, characterized in that, The identifying of the frame synchronization identifier further comprises a false identification screening step: When the detected frame synchronization identifier is set to valid, if the current value of the line counter is greater than or equal to the historical multi-frame average total line number minus a third preset value or the historical multi-frame average total line number is less than a fourth preset value, it is confirmed that the frame synchronization identifier is valid, otherwise, it is determined that the frame synchronization identifier is a false identification and is rejected.

14. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 1, wherein, The stability verification of the total line number of the continuous multiple frames comprises: It is determined whether the difference between the total line numbers of any two adjacent frames in the continuous multiple frames is not greater than a preset tolerance, if yes, it is determined that the total line number tends to be stable.

15. The method of automatic identification of resolution and frame rate of a coaxial video signal according to claim 1, wherein, The matching of the stable total line number and the verified total sample number with the preset video format parameters to determine the resolution and frame rate of the coaxial video signal comprises: The stable total line number is matched with a plurality of preset numerical intervals to determine the video resolution format, wherein the video resolution format comprises cvbs pal (625i), cvbs ntsc (525i), 1M (720p), 2M (1080p), 3M (1536p), 4M (1440p), 5M (1944p) and 8M (2160p); After the video resolution format is determined, the verified total sample number is matched with a plurality of preset frame rate threshold intervals to determine the video frame rate, wherein the video frame rate comprises 7.5fps, 12.5fps, 15fps, 20fps, 18.75fps, 25fps, 30fps, 18fps, 50fps and 60fps.

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