Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, the semiconductor device comprises a plurality of layers of memory cell arrays which are stacked along a direction vertical to a substrate, and each memory cell array comprises at least one column of memory cells; a plurality of vertically extending bit lines; a plurality of horizontally extending word lines; the word line surrounds a semiconductor layer of a column of transistors, and the semiconductor layer extends along the first direction; the size of the end face, facing the bit line, of the semiconductor layer in the second direction is smaller than the minimum size of the area, surrounded by the word line, of the semiconductor layer in the second direction. The size of the end face, away from the bit line, of the semiconductor layer in the second direction is smaller than the minimum size of the area, surrounded by the word line, of the semiconductor layer in the second direction. According to the scheme provided by the embodiment of the invention, the word line with a smaller size can be supported, and the coupling capacitance between the word line and the bit line is reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which reduces parasitic capacitance.

[0006] This application provides a semiconductor device, including:

[0007] A multilayer array of memory cells stacked perpendicular to the substrate, the array comprising at least one column of multiple memory cells distributed along a second direction parallel to the substrate;

[0008] Multiple bit lines, which extend through multiple layers of the memory cells along a direction perpendicular to the substrate;

[0009] Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction parallel to the substrate, and the word lines extend along a second direction. The first direction and the second direction intersect.

[0010] The memory cell includes a transistor, the transistor including a semiconductor layer extending along the first direction; the word line surrounds a portion of the side surface of a plurality of the semiconductor layers of a column of the memory cells; the dimension of the end face of the semiconductor layer facing the bit line along the second direction is smaller than the minimum dimension of the region of the semiconductor layer surrounded by the word line along the second direction, and the dimension of the end face of the semiconductor layer away from the bit line along the second direction is smaller than the minimum dimension of the region of the semiconductor layer surrounded by the word line along the second direction.

[0011] In some embodiments, each of the two opposing side surfaces of the semiconductor layer along a second direction includes a first surface, a second surface, and a third surface distributed sequentially along a first direction. A portion of the first surface and the second surface are surrounded by the word line. The third surface is located between the region of the semiconductor layer surrounded by the word line and the end face of the semiconductor layer facing the bit line. The connection between the first surface and the second surface protrudes toward the adjacent semiconductor layer along the second direction.

[0012] In some embodiments, the junction of the second surface and the third surface protrudes toward an adjacent semiconductor layer along a second direction.

[0013] In some embodiments, the word lines are formed in arc-shaped recesses on two side surfaces located between adjacent semiconductor layers along a second direction and opposite each other along a first direction.

[0014] In some embodiments, the dimension of the cross section of the bit line parallel to the substrate along the second direction is smaller than the dimension of the cross section along the first direction.

[0015] In some embodiments, a gate insulating layer is disposed between the semiconductor layer and the word line, the gate insulating layer surrounds the semiconductor layer, and on two opposing side surfaces of the semiconductor layer along a second direction, the gate insulating layer is distributed on the first surface and the second surface but not on the third surface.

[0016] In some embodiments, the gate insulating layer extends continuously on both the surface of the semiconductor layer away from the substrate and the surface facing the substrate.

[0017] In some embodiments, the semiconductor layer comprises monocrystalline silicon, and the gate insulating layer is silicon oxide formed by oxidizing monocrystalline silicon.

[0018] In some embodiments, the semiconductor device further includes a first connecting sublayer connected to an end face of the semiconductor layer facing the bit line, and a second connecting sublayer connected to an end face of the semiconductor layer away from the bit line. The first connecting sublayer and the second connecting sublayer are metal silicides formed by metallizing single-crystal silicon, and the first connecting sublayer is connected to the bit line.

[0019] In some embodiments, the memory cell further includes a capacitor, the capacitor including a first capacitor electrode and a second capacitor electrode, the second capacitor electrode including a first sub-electrode, the semiconductor device further including a capacitor aperture penetrating multiple layers of the memory cell, multiple first capacitor electrodes of multiple memory cells at the same position in different layers being disposed on the sidewall of the capacitor aperture and spaced apart along a direction perpendicular to the substrate, the first sub-electrode filling the capacitor aperture, and multiple first capacitor electrodes surrounding the first sub-electrode through a first dielectric layer.

[0020] In some embodiments, the capacitor aperture exposes multiple second connection sublayers to which multiple semiconductor layers of multiple memory cells stacked perpendicular to the substrate direction are respectively connected, and the first capacitor electrode is connected to the exposed second connection sublayers.

[0021] In some embodiments, the first capacitor electrode includes a first portion extending in a direction perpendicular to the substrate and a second portion extending from both ends of the first portion toward the first sub-electrode; the first portion is connected to the second connection sub-layer.

[0022] In some embodiments, the second capacitor electrode further includes a second sub-electrode that surrounds the first portion via a second dielectric layer portion.

[0023] In some embodiments, the distance between the surface of the word line away from the substrate and the surface facing the substrate is equal to the length of the first capacitor electrode extending in the direction perpendicular to the substrate.

[0024] In some embodiments, the semiconductor device further includes a first isolation via disposed between adjacent semiconductor layers along a second direction, between a column of capacitors distributed along the second direction and the word lines, penetrating the multilayer memory cell array, and an insulating film layer filling the first isolation via; and a second isolation via disposed between adjacent bit lines along the second direction, between adjacent word lines along the first direction, penetrating the multilayer memory cell array, and an insulating film layer filling the second isolation via.

[0025] This disclosure provides a method for manufacturing a semiconductor device, including:

[0026] A stacked structure comprising multiple alternating semiconductor structural layers and sacrificial layers is formed on a substrate;

[0027] A plurality of first holes are formed that penetrate the stacked structure along a second direction perpendicular to the substrate;

[0028] A second hole is formed between adjacent first holes, extending through the stacked structure in a direction perpendicular to the substrate, and the diameter of the second hole in a first direction is larger than the diameter of the first hole in the first direction; the first direction and the second direction are parallel to the substrate and intersect.

[0029] The semiconductor structure layer is etched laterally based on the second hole, such that the second hole and the first hole intersect, and a semiconductor structure layer is retained between adjacent second holes along the second direction;

[0030] A first trench is formed that penetrates the stacked structure and extends along the second direction;

[0031] A plurality of third holes are formed between the first trench and the first hole, extending through the stacked structure perpendicular to the substrate and spaced apart along the second direction, and a transistor region is defined between the plurality of third holes and the plurality of first holes;

[0032] Based on the first trench, the semiconductor structure layer is etched along the direction parallel to the substrate to remove the semiconductor structure layer outside the transistor region and part of the semiconductor structure layer in the transistor region. The semiconductor structure layer remaining in the transistor region is connected to a part of the sidewall of the third hole facing the first hole to form a fifth lateral groove.

[0033] A plurality of first word line vias spaced apart along a second direction through the stacked structure in a direction perpendicular to the substrate are formed in the transistor region; and a plurality of second word line vias spaced apart along a second direction through the stacked structure in a direction perpendicular to the substrate, wherein the sidewalls of the first word line vias and the second word line vias expose each of the semiconductor structure layers; the first word line vias and the second word line vias are spaced apart along a first direction, and the second word line vias are located in the region where the second vias are located;

[0034] Based on the first word line hole and the second word line hole, the semiconductor structure layer is etched along a direction parallel to the substrate to form a channel that connects the first word line hole and the second word line hole adjacent along the first direction, so as to divide the semiconductor structure layer to form a plurality of semiconductor layers corresponding to a plurality of transistors that extend along the first direction and are spaced apart along the second direction.

[0035] A gate insulating layer is sequentially formed around the semiconductor layer, and word lines are formed around a portion of the side surfaces of a plurality of semiconductor layers surrounding a row of transistors distributed along the second direction;

[0036] A bit line is formed in the first hole, extending in a direction perpendicular to the substrate.

[0037] In some embodiments, before forming the first letter hole and the second letter hole, the method further includes:

[0038] An isolation layer film is deposited to fill the fifth transverse groove, and the isolation layer film is etched to the side of the third hole facing the first hole outside the transistor region, forming an isolation layer that extends along the second direction and is distributed in the area of ​​the third hole facing the first hole that does not contact the semiconductor layer.

[0039] The isolation layer is exposed on the sidewall of the first letter hole.

[0040] In some embodiments, before laterally etching the semiconductor structure layer based on the second hole, the method further includes etching away the sacrificial layer of a predetermined length along a direction parallel to the substrate based on the second hole, and sequentially forming a first barrier layer covering the inner wall of the area where the etched sacrificial layer is located and an insulating layer filling the area where the etched sacrificial layer is located in the region.

[0041] After forming multiple semiconductor layers corresponding to multiple transistors extending along a first direction and spaced apart along a second direction, the process further includes forming a gate insulating layer surrounding the semiconductor layers sequentially before:

[0042] The first barrier layer is etched away, so that the semiconductor layer forms a suspended structure with exposed side surfaces, and the thickness of the semiconductor layer along the direction perpendicular to the substrate is reduced.

[0043] The word lines, which sequentially form a gate insulating layer surrounding the semiconductor layers and a plurality of semiconductor layers surrounding a row of transistors distributed along a second direction, include:

[0044] The exposed side surface of the semiconductor layer is oxidized to form the gate insulating layer;

[0045] Word lines are formed to fill the channels and the gaps left after the semiconductor layer is thinned;

[0046] The word lines are etched based on the first and third holes, preserving the word lines surrounding the channel region of the semiconductor layer.

[0047] In some embodiments, after etching the word lines based on the first and third holes, retaining the word lines surrounding the channel region of the semiconductor layer, the process further includes...

[0048] Metallization is performed on one end of the semiconductor layer near the first hole and the other end near the third hole to form a first connecting sublayer disposed on the side of the semiconductor layer near the first hole and a second connecting sublayer disposed on the side of the semiconductor layer near the third hole.

[0049] In some embodiments, before forming the first trench that penetrates the stacked structure and extends along the second direction, the method further includes:

[0050] A second barrier layer is formed to cover the sidewall of the first hole, and a first dummy layer is formed to fill the first hole;

[0051] The second barrier layer is etched toward the two sidewalls of the second hole adjacent to it along the second direction, exposing the sidewalls of the first dummy layer and thinning the thickness of the first dummy layer along the second direction;

[0052] The step of forming a bit line extending in a direction perpendicular to the substrate in the first hole includes:

[0053] The first dummy layer and the second barrier layer are etched away to form a bit line hole, and a bit line is formed to fill the bit line hole.

[0054] In some embodiments, before etching the word line based on the first hole and the third hole, the method further includes:

[0055] Based on the third hole, the semiconductor structure layer is etched along a direction parallel to the substrate to form a second lateral groove;

[0056] A third barrier layer is formed that covers the inner wall of the second transverse groove and the third hole, and a second dummy layer is formed that fills the third hole and the second transverse groove;

[0057] The second dummy layer is etched away while the first dummy layer is removed, and the third barrier layer is etched away while the second barrier layer is removed.

[0058] After forming the first interconnect sublayer disposed on the side of the semiconductor layer near the first via and the second interconnect sublayer disposed on the side of the semiconductor layer near the third via, the method further includes:

[0059] A first conductive film is deposited to cover the inner wall of the third hole and the second transverse groove. The first conductive film on the sidewall of the third hole is etched away, and the conductive film located on the inner wall of the second transverse groove is retained to form a first capacitor electrode.

[0060] The formation of the bit line filling the bit line hole includes: depositing a first conductive film covering the inner wall of the third hole and the second transverse groove, and simultaneously depositing a first conductive film covering the inner wall of the bit line hole to form a first conductive sublayer of the bit line;

[0061] A second conductive sublayer of the bit line is formed by depositing a second conductive film to fill the bit line hole where the first conductive film is formed.

[0062] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed by any of the manufacturing methods of the semiconductor devices described above.

[0063] This application includes a semiconductor device and a method for manufacturing the same, and an electronic device. The semiconductor device includes: a multilayer array of memory cells stacked along a direction perpendicular to a substrate, the memory cell array including at least one column of multiple memory cells distributed along a second direction parallel to the substrate; multiple bit lines extending through the multilayer memory cells along a direction perpendicular to the substrate; multiple word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction parallel to the substrate, the word lines extending along the second direction, the first direction and the second direction intersecting; each memory cell including a transistor, the transistor including a semiconductor layer extending along the first direction; the word lines surrounding a portion of the side surface of the multiple semiconductor layers of a column of memory cells; the dimension of the end face of the semiconductor layer facing the bit line along the second direction is smaller than the minimum dimension of the region of the semiconductor layer surrounded by the word line along the second direction, and the dimension of the end face of the semiconductor layer away from the bit line along the second direction is smaller than the minimum dimension of the region of the semiconductor layer surrounded by the word line along the second direction. The solution provided in this embodiment implements a structure with vertical bit lines, horizontal word lines, and word lines surrounding the semiconductor layer. Compared to horizontal bit lines, the vertical word line solution allows for a smaller word line thickness, thereby reducing the parasitic capacitance between the word lines and bit lines. Furthermore, the smaller end faces and larger center faces of the semiconductor layer help to reduce device area and increase device density.

[0064] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0065] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0066] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0067] Figures 1A-1D Cross-sectional views of a semiconductor device along the AA', BB', DD', and FF' directions provided in some embodiments are shown respectively.

[0068] Figures 2A-2D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first hole, provided in some embodiments.

[0069] Figures 3A-3C Cross-sectional views along the AA' direction, B1B1' direction, and CC' direction after the second hole is formed, provided in some embodiments;

[0070] Figures 4A-4C These are cross-sectional views along the AA', B1B1', and CC' directions after the bit line region has been thinned according to some embodiments.

[0071] Figures 5A-5D These are cross-sectional views along the AA', B1B1', CC', and DD' directions after the formation of the first trench, provided in some embodiments.

[0072] Figures 6A-6D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the third hole, provided in some embodiments.

[0073] Figures 7A-7E Cross-sectional views along the AA', BB', B1B1', CC', and DD' directions after the formation of the second isolation layer are provided in some embodiments;

[0074] Figures 8A-8D Cross-sectional views along the AA', BB', DD', and EE' directions respectively, provided in some embodiments after the formation of the first and second letter holes;

[0075] Figures 9A-9D Cross-sectional views along the AA', BB', DD', and EE' directions after the semiconductor layer is formed, provided in some embodiments;

[0076] Figures 10A-10D These are cross-sectional views along the AA', BB', DD', and EE' directions after the word lines are formed, provided in some embodiments.

[0077] Figures 11A-11D Cross-sectional views along the AA', BB', DD', and FF' directions after disconnecting word lines of different layers, provided in some embodiments;

[0078] Figures 12A-12C Cross-sectional views along the AA', BB', and DD' directions after exposing the first and third holes, respectively, provided in some embodiments;

[0079] Figures 13A-13C These are cross-sectional views along the AA', BB', and DD' directions after etching away the word lines in the non-channel region, as provided in some embodiments.

[0080] Figures 14A-14C These are cross-sectional views along the AA', BB', and DD' directions after the connection layer is formed, provided in some embodiments.

[0081] Figures 15A-15CCross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first capacitor electrode and the first conductive layer;

[0082] Figures 16A-16C Cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first dielectric layer and the first sub-electrode;

[0083] Figure 17A and Figure 17B These are cross-sectional views along the BB' and DD' directions after the formation of the thirteenth insulating layer, provided in some embodiments.

[0084] Figure 18A and Figure 18B These are cross-sectional views along the AA' and BB' directions after the formation of the second conductive sublayer, provided in some embodiments.

[0085] Figure 19 A cross-sectional view along the BB' direction after the formation of the fourteenth insulating layer, provided for some embodiments;

[0086] Figures 20A-20C These are cross-sectional views along the AA', BB', and DD' directions after the formation of the second dielectric layer, provided in some embodiments. Detailed Implementation

[0087] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0088] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0089] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0090] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0091] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0092] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0093] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0094] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0095] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0096] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0097] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0098] Figures 1A-1D These are cross-sectional views of a semiconductor device provided in some embodiments along the AA', BB', DD', and FF' directions. The AA' direction is parallel to the substrate 1 and passes through the film layer containing semiconductor layer 23, while the BB', DD', and FF' directions are perpendicular to the substrate 1. Figures 1A-1D As shown, this disclosure provides a semiconductor device, which may include a multilayer memory cell array stacked on a substrate 1 along a direction perpendicular to the substrate 1.

[0099] The memory cell array may include multiple memory cells, multiple bit lines 30, and multiple word lines 40. Each layer of the memory cell array may include multiple memory cells distributed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0100] The bit line 30 can extend in a direction perpendicular to the substrate 1, and multiple memory cells stacked in the vertical direction at the same position in different layers are connected to the same bit line 30.

[0101] In some embodiments, adjacent memory cells along the first direction X are connected to the same bit line 30. Every two columns of memory cells can be grouped together, and memory cells within the same group are connected to the same bit line 30.

[0102] The word lines 40 can extend along a second direction Y parallel to the substrate 1. Multiple word lines 40 of the same memory cell array can be spaced apart from each other, and the multiple word lines 40 of the same memory cell array can be distributed at intervals along a first direction X. The word lines 40 of memory cell arrays of different layers can be stacked in a direction perpendicular to the substrate 1.

[0103] The storage unit can be a 1T1C storage unit, or it can be a storage unit with other structures.

[0104] Taking a 1T1C memory cell as an example, the memory cell may include a transistor and a capacitor connected to the transistor. The transistor and capacitor in the same memory cell may be distributed along a first direction X. The capacitor, the word line 40, and the bit line 30 are distributed along the first direction X.

[0105] The transistor may include a semiconductor layer 23 extending along a first direction X, and a word line 40 surrounding a portion of the side surface of a plurality of semiconductor layers 23 in a row of memory cells; the dimension of the end face of the semiconductor layer 23 facing the bit line 30 along the second direction Y is smaller than the minimum dimension of the region of the semiconductor layer 23 surrounded by the word line 40 along the second direction Y, and the dimension of the end face of the semiconductor layer 23 away from the bit line 30 along the second direction Y is smaller than the minimum dimension of the region of the semiconductor layer 23 surrounded by the word line 40 along the second direction Y. The region of the semiconductor layer 23 surrounded by the word line 40 is a channel region, and the semiconductor layer 23 also includes a first region and a second region (one of which is a source region and the other is a drain region) distributed along the first direction X at both ends of the channel region.

[0106] The solution provided in this embodiment implements a structure with vertical bit lines, horizontal word lines, and word lines surrounding the semiconductor layer. Compared to horizontal bit lines, the vertical word line solution allows for a smaller word line thickness, thereby reducing the parasitic capacitance between the word lines and bit lines. Furthermore, the smaller end faces and larger center faces of the semiconductor layer help to reduce device area and increase device density.

[0107] In some embodiments, each of the two opposing side surfaces of the semiconductor layer 23 along the second direction Y includes a first surface, a second surface, and a third surface distributed sequentially along the first direction X. A portion of the first surface and the second surface are surrounded by the word line 40. The third surface is located between the region of the semiconductor layer 23 surrounded by the word line 40 and the end face of the semiconductor layer 23 facing the bit line 30. The connection between the first surface and the second surface protrudes toward the adjacent semiconductor layer 23 along the second direction.

[0108] In some embodiments, the semiconductor layer 23 is a solid structure.

[0109] In some embodiments, the distance between the first surfaces of the semiconductor layer 23 opposite each other in the second direction Y varies from large to small in the direction away from the bit line 30.

[0110] In some embodiments, the distance between the third surfaces of the semiconductor layer 23 opposite each other in the second direction Y varies from large to small in the direction toward the bit line 30.

[0111] In some embodiments, the distance between the junction of the first and second surfaces opposite to each other in the second direction Y of the semiconductor layer 23 is the maximum distance of the semiconductor layer 23 along the second direction Y.

[0112] In some embodiments, the junction of the second surface and the third surface protrudes toward the adjacent semiconductor layer 23 along the second direction Y.

[0113] In some embodiments, the two side surfaces of the word line 40 located between adjacent semiconductor layers 23 along the second direction Y and opposite each other along the first direction X can form arc-shaped recesses. That is, cavities can be created by etching from both sides toward the area where the word line is to be formed, so as to form the word line.

[0114] In some embodiments, the dimension of the cross section of the bit line 30 parallel to the substrate 1 along the second direction Y is smaller than the dimension of the cross section along the first direction X. That is, in this embodiment of the present disclosure, the dimension of the bit line 30 along the second direction Y can be reduced as much as possible, thereby increasing the distance between adjacent bit lines along the second direction Y and reducing the coupling capacitance between adjacent bit lines.

[0115] In some embodiments, a gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40. The gate insulating layer 24 surrounds the semiconductor layer 23 and is distributed on the first surface and the second surface but not on the third surface on two opposite side surfaces of the semiconductor layer 23 along the second direction Y.

[0116] In some embodiments, the gate insulating layer 24 extends continuously on both the surface of the semiconductor layer 23 facing away from the substrate 1 and the surface of the semiconductor layer 23 facing the substrate 1. That is, the gate insulating layer 24 covers both the surface of the semiconductor layer 23 facing away from the substrate 1 and the surface of the semiconductor layer 23 facing the substrate 1.

[0117] In some embodiments, the semiconductor layer 23 comprises monocrystalline silicon, and the gate insulating layer 24 is silicon oxide formed by oxidizing the monocrystalline silicon. That is, the semiconductor layer 23 is formed from monocrystalline silicon, and then the gate insulating layer 24 is formed by oxidizing the surface of the semiconductor layer 23.

[0118] In some embodiments, the semiconductor device may further include a first connecting sublayer 251 connected to the end face of the semiconductor layer 23 facing the bit line 30, and a second connecting sublayer 252 connected to the end face of the semiconductor layer 23 away from the bit line 30. The first connecting sublayer 251 and the second connecting sublayer 252 are metal silicides formed by metallizing single-crystal silicon. The first connecting sublayer 251 is connected to the bit line 30, and the second connecting sublayer 252 is connected to the first capacitor electrode 41 of the capacitor.

[0119] In some embodiments, the gate insulating layer 24 further extends to the surface of the first connection sublayer 251 opposite to the substrate 1 and the surface facing the substrate 1, and extends to the surface of the second connection 252 opposite to the substrate 1 and the surface facing the substrate 1.

[0120] In some embodiments, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode, the second capacitor electrode including a first sub-electrode 421. The semiconductor device may also include a capacitor aperture penetrating multiple layers of the memory cells, a plurality of first capacitor electrodes 41 of a plurality of memory cells at the same position in different layers being disposed on the sidewall of the capacitor aperture and spaced apart along a direction perpendicular to the substrate 1, the first sub-electrode 421 filling the capacitor aperture, and a plurality of first capacitor electrodes 41 surrounding the first sub-electrode 421 through a first dielectric layer 431.

[0121] In some embodiments, the capacitor aperture exposes a plurality of second connection sublayers 242 to which a plurality of semiconductor layers 23 of a plurality of memory cells stacked along a direction perpendicular to the substrate 1 are respectively connected, and the first capacitor electrode 41 is connected to the exposed second connection sublayers 252.

[0122] In some embodiments, the first capacitor electrode 41 includes a first portion extending along a direction perpendicular to the substrate 1 and a second portion extending from both ends of the first portion toward the first sub-electrode 421; the first portion is connected to the second connecting sub-layer 252. That is, the first capacitor electrode 41 can form an annular groove, which may include a bottom wall perpendicular to the substrate 1 and two side walls parallel to the substrate 1. The bottom wall includes an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove. The second connecting sub-layer 252 is connected to a portion of the outer bottom wall. The orthographic projection of the annular groove onto the substrate 1 can be a closed ring.

[0123] In some embodiments, the first sub-electrodes 421 of memory cells at the same location in different layers can be connected to form an integral structure extending in a direction perpendicular to the substrate 1.

[0124] In some embodiments, the first dielectric layer 431 of capacitors at the same location on different layers can be connected to form an integral structure.

[0125] In some embodiments, the sidewall of the annular groove includes an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode 421 is also distributed on the outer sidewall of the annular groove. That is, the first sub-electrode 421 can be distributed on the inner wall (including the inner bottom wall and the inner sidewall) of the annular groove, or it can be distributed on the outer sidewall of the annular groove, thereby maximizing the area facing the first capacitor electrode 41 and increasing the capacitance of the capacitor. However, the embodiments of this disclosure are not limited to this, and the first sub-electrode 421 may not be distributed on the outer sidewall surrounding the groove.

[0126] In some embodiments, the second capacitor electrode may further include a second sub-electrode 422, which partially surrounds a first portion of the first capacitor electrode 41 via a second dielectric layer 432. The solution provided in this embodiment, by providing an electrode outside the first capacitor electrode 41, can further increase the capacitance of the capacitor.

[0127] In some embodiments, the second sub-electrodes 422 of a plurality of memory cells distributed in the same layer and column along the second direction Y can be connected to form an integral structure.

[0128] In some embodiments, the second dielectric layers 432 of capacitors distributed in the same layer and column along the second direction Y can be connected to form an integral structure.

[0129] In some embodiments, the second dielectric layer 432 of capacitors at the same location on different layers can be connected to form an integral structure.

[0130] In some embodiments, the distance between the surface of the word line 40 facing away from the substrate 1 and the surface facing the substrate 1 can be equal to the length of the first capacitor electrode 41 extending in the direction perpendicular to the substrate, that is, equal to the distance between the surface of the first capacitor electrode 41 facing away from the substrate 1 and the surface facing the substrate 1. In other words, the word line 40 and the first capacitor electrode 41 are substantially at the same film position in the vertical direction.

[0131] In some embodiments, the semiconductor device may further include a first isolation via (refer to the first word line via K41 described in a later embodiment) disposed between adjacent semiconductor layers 23 along the second direction Y, between a column of capacitors distributed along the second direction Y and the word lines 40, penetrating the multilayer memory cell array, and an insulating film layer filling the first isolation via; and a second isolation via (refer to the second via K2 described in a later embodiment) disposed between adjacent bit lines 30 along the second direction Y and between adjacent word lines 40 along the first direction X, penetrating the multilayer memory cell array, and an insulating film layer filling the second isolation via.

[0132] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0133] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0134] 1) Form the first hole K1;

[0135] Single-crystal silicon and sacrificial layer films are alternately grown on substrate 1 to form a stacked structure including multiple alternately arranged semiconductor structure layers 23' and sacrificial layers 10;

[0136] A first insulating film is deposited to form a first insulating layer 11 covering the stacked structure;

[0137] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of first holes K1 spaced apart along the second direction Y; when manufacturing the memory array, the first holes K1 spaced apart along the second direction Y are referred to as a column of first holes K1, and multiple columns of first holes K1 spaced apart along the first direction X can be formed.

[0138] A second insulating film is deposited to form a second insulating layer 12 covering the bottom wall and side wall of the first hole K1;

[0139] A first dummy layer film is deposited to form a first dummy layer 91 that fills the first hole K1; as shown Figure 2A , Figure 2B , Figure 2C , Figure 2D As shown. Among them, Figures 2A-2D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first hole K1, as provided in some embodiments. The CC' direction is perpendicular to the substrate 1.

[0140] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0141] In some embodiments, the sacrificial layer film may be silicon germanium (SiGe).

[0142] In some embodiments, the first insulating film and the second insulating film may be low-K dielectric layers, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent fourth to fourteenth insulating films are similar and will not be described again.

[0143] In some embodiments, the first dummy layer film may be a material with an etching selectivity ratio to the first insulating film and the first sacrificial layer film, such as polysilicon. The materials of the subsequent second to fourth dummy layer films are similar to those of the first dummy layer film and will not be described again.

[0144] 2) Formation of the second hole K2;

[0145] The stacked structure is etched from top to bottom along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of second holes K2 spaced apart along the second direction Y. The second holes K2 are disposed between adjacent first holes K1 along the second direction Y. The size of the second hole K2 along the first direction X is larger than the size of the first hole K1 along the first direction X. The second hole K2 exposes part of the outer wall of the second insulating layer 12 in the two first holes K1 adjacent to the second hole K2.

[0146] Based on the second hole K2, the sacrificial layer 10 is etched laterally (etched along a direction parallel to the substrate 1) to remove the sacrificial layer 10 in the transistor region and retain the sacrificial layer 10 in the capacitor region; thus forming the first lateral groove A1.

[0147] A third insulating film is deposited at low temperature to form a third insulating layer 13, which may be silicon dioxide or silicon nitride (SiN), etc. The third insulating layer 13 covers the bottom wall and sidewalls of the first transverse groove A1 and the sidewalls of the second hole K2; the temperature of the low-temperature atomic layer deposition is, for example, 50°C to 60°C.

[0148] A fourth insulating film is deposited to form a fourth insulating layer 14 that fills the first lateral groove A1 and the second hole K2. There is a certain etching selectivity between the fourth insulating layer 14 and the third insulating layer 13, which facilitates subsequent etching of the third insulating layer 13 without affecting the fourth insulating layer 14. When the fourth insulating layer is SiO2, a high-temperature atomic layer deposition method can be used, with temperatures such as 700℃ to 800℃, resulting in a larger etching selectivity compared to SiO2 formed by low-temperature atomic layer deposition.

[0149] The fourth insulating layer 14 and the third insulating layer 13 in the second hole K2 are removed by etching, exposing the semiconductor structure layer 23' on the sidewall of the second hole K2;

[0150] Based on the second hole K2, the semiconductor structure layer 23' is etched laterally to form a second lateral groove A2; the etched length of the semiconductor structure layer 23' is less than the etched length of the sacrificial layer 10, and after the lateral etching of the semiconductor structure layer 23', a semiconductor structure layer 23' still exists between adjacent second holes K2 along the second direction Y, that is, a small length of the lateral etching of the semiconductor structure layer 23' is retained here, and the semiconductor structure layer 23' is subsequently connected to the bit line 30; as Figure 3A , Figure 3B , Figure 3C As shown. Among them, Figures 3A-3C These are cross-sectional views along the AA', B1B1', and CC' directions after the formation of the second hole K2, as provided in some embodiments. The B1B1' direction is perpendicular to the substrate 1.

[0151] 3) Thinning of the bit line region;

[0152] A fifth insulating film is deposited to form a fifth insulating layer 15 covering the inner wall of the second transverse groove A2 and the second hole K2;

[0153] Based on the second hole K2, the second insulating layer 12 and the fifth insulating layer 15 are wet etched to expose the sidewall of the first dummy layer 91;

[0154] Based on the second hole K2, the first dummy layer 91 is wet-etched to reduce the length of the first dummy layer 91 along the second direction Y; the first dummy layer 91 is etched from the two second holes K2 adjacent to the first hole K1, such as... Figure 4A , Figure 4B , Figure 4C As shown. Among them, Figures 4A-4C The figures show cross-sectional views along the AA', B1B1', and CC' directions after thinning the bit line region according to some embodiments. The region where the first dummy layer 91 is located is the bit line region. Bit lines will subsequently be formed in the region where the first dummy layer 91 is located and in the region surrounding the first dummy layer 91. As the first dummy layer 91 is thinned, the subsequently formed bit lines 30 are correspondingly thinned. In the solution provided in this embodiment, by thinning the first dummy layer 91, the distance of the subsequently formed bit lines 30 along the second direction Y can be increased, thereby reducing the coupling between bit lines and enhancing device performance. When thinning the first dummy layer 91, it can be thinned until the size of the first dummy layer 91 along the second direction Y is smaller than the size of the end face of the semiconductor layer structure layer 23' that contacts the second insulating layer 12 along the second direction Y, thereby maximizing the spacing of the subsequently formed bit lines along the second direction Y.

[0155] 4) Form the first trench T1;

[0156] A sixth insulating film is deposited and smoothed to form a sixth insulating layer 16, which fills the etched areas in the second hole K2, the second transverse groove A2 and the first hole K1 (i.e., the etched areas of the second insulating layer 12 and the first dummy layer 91).

[0157] The stacked structure is etched along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a first trench T1 that penetrates the stacked structure. The first trench T1 extends along a second direction Y. A set of memory cells is defined between two first trenches T1 that are spaced apart along a first direction X. The set of memory cells includes two columns of memory cells.

[0158] Based on the first trench T1, the sacrificial layer 10 is removed by lateral etching to form a third lateral groove A3;

[0159] A seventh insulating film is deposited, and the seventh insulating film in the first trench T1 is etched away to form a seventh insulating layer 17 filling the third lateral groove A3; at this time, the semiconductor structure layer 23' is exposed in the first trench T1, as... Figure 5A , Figure 5B , Figure 5C , Figure 5D As shown. Among them, Figures 5A-5C The figures provided are cross-sectional views along the AA', B1B1', CC', and DD' directions after the formation of the first trench T1, as provided in some embodiments. Before depositing the seventh insulating film, the third insulating layer 13 exposed in the third transverse groove A3 can be etched away, that is, the third insulating layer 13 on the bottom wall of the first transverse groove A1 can be etched away. However, the embodiments of this disclosure are not limited to this, and the third insulating layer 13 may not be etched.

[0160] 5) Formation of the third hole K3;

[0161] A first isolation layer film is deposited and smoothed to form a first isolation layer 81 that fills the first trench T1; the first isolation layer film may be, for example, SiN.

[0162] In the capacitor region, the stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of third holes K3 spaced apart along the second direction Y; the third holes K3 and the first holes K1 can be spaced apart along the first direction X; wherein, the aperture of the third hole K3 is larger than the aperture of the first hole K1.

[0163] Based on the third hole K3, the semiconductor structure layer 23' is etched laterally to form a fourth lateral groove A4. The fourth lateral groove A4 provides space for manufacturing a capacitor, that is, provides space for the first capacitor electrode 41. When the semiconductor structure layer 23' is etched laterally, the semiconductor structure layer 23' between the first trench T1 and the third hole K3 is not etched through. That is, after the semiconductor structure layer 23' is etched laterally, the first trench T1 and the third hole K3 are not connected.

[0164] After depositing the eighth insulating film and the second dummy layer film in sequence, the layers are ground flat to form the eighth insulating layer 18 covering the inner wall of the fourth transverse groove A4 and the third hole K3, and the second dummy layer 92 filling the fourth transverse groove A4 and the third hole K3; at this time, the second dummy layer 92 and the first isolation layer 81 are flush.

[0165] The first dummy layer 91 and the second dummy layer 92 are etched such that the distance between the surfaces of the first dummy layer 91 and the substrate 1 facing away from the substrate 1 is less than the distance between the surface of the first isolation layer 81 facing away from the substrate 1. That is, a portion of the top of the first dummy layer 91 and the second dummy layer 92 is etched away, forming a recess relative to the first isolation layer 81; as... Figure 6A , Figure 6B , Figure 6C , Figure 6D As shown. Among them, Figures 6A-6D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the third hole K3, provided in some embodiments.

[0166] 6) Formation of a second isolation layer 82;

[0167] A ninth insulating film is deposited and smoothed to form a ninth insulating layer 19, which covers the top of the first dummy layer 91 and the second dummy layer 92 and serves as a protective structure. The ninth insulating layer 19 is flush with the first insulating layer 81.

[0168] Etching removes the first isolation layer 81 in the first trench T1;

[0169] Based on the first trench T1, the semiconductor structure layer 23' is etched laterally to the area between the third hole K3 and the second hole K2, and closer to the third hole K3, to form a fifth lateral groove A5; the third insulating layer 13 exposed in the fifth lateral groove A5 is etched away; to avoid the formation of voids in the fifth lateral groove A5 when etching the third insulating layer 13 in the subsequent step 8).

[0170] A second isolation layer film is deposited, filling the area where the fifth lateral groove A5 and the third insulating layer 13 are etched away. The second isolation layer film is laterally etched to the side of the third hole K3 facing the first hole K1, forming a second isolation layer 82. The second isolation layer 82 is distributed in a portion of the outer wall of the eighth insulating layer 18 in the third hole K3 facing the first hole K1 (i.e., the area not in contact with the semiconductor structure layer 23'). The portion of the outer wall of the eighth insulating layer 18 facing the first hole K1 is in contact with the semiconductor structure layer 23'. Along the second direction Y, the second isolation layer 82 is distributed on both sides of the area where the eighth insulating layer 18 contacts the semiconductor structure layer 23'. Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E As shown. Among them, Figures 7A-7E These are cross-sectional views along the AA', BB', B1B1', CC', and DD' directions after the formation of the second isolation layer 82, as provided in some embodiments.

[0171] In some embodiments, the second insulating layer film may be SiN.

[0172] 7) Form the first letter hole K41 and the second letter hole K42;

[0173] A third dummy layer film is deposited, which fills the first trench T1 and the fifth transverse groove A5 where the second isolation layer 82 is formed, to form a third dummy layer 93;

[0174] The third dummy layer 93 is etched such that the distance between the surface of the third dummy layer 93 facing away from the substrate 1 and the substrate 1 is less than the distance between the surface of the second dummy layer 92 facing away from the substrate 1 and the substrate 1.

[0175] A tenth insulating film is deposited to form a tenth insulating layer 70; the tenth insulating layer 70 covers the aforementioned structure.

[0176] In the transistor region, the stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of first word line vias K41 spaced apart along the second direction Y and a plurality of second word line vias K42 spaced apart along the second direction Y. The first word line vias K41 and second word line vias K42 are spaced apart along the first direction X. A first word line via K41 is disposed between adjacent third vias K3, and two second word line vias K42 are disposed in the region where each second via K2 is located. Part of the sidewall of the first word line via K41 exposes the second isolation layer 82, and part of the sidewall exposes the semiconductor structure layer 23'. Part of the sidewall of the second word line via K42 exposes the sixth insulating layer 16 filling the second via K2, and part of the sidewall exposes the semiconductor structure layer 23'. Figure 8A , Figure 8B , Figure 8C , Figure 8D As shown. Among them, Figures 8A-8D These are cross-sectional views along the AA', BB', DD', and EE' directions respectively, provided in some embodiments after the formation of the first word line hole K41 and the second word line hole K42. The EE' direction is perpendicular to the substrate 1.

[0177] The solution provided in this embodiment forms the first word line hole K41 in the transistor region, instead of forming the first word line hole K41 between the adjacent third holes K3 along the second direction Y. This can shorten the distance between adjacent capacitors along the second direction Y and reduce the area occupied by the device.

[0178] 8) Forming semiconductor layer 23;

[0179] Based on the first word line hole K41 and the second word line hole K42, the semiconductor structure layer 23' is etched laterally to form a channel that connects the first word line hole K41 and the second word line hole K42 adjacent along the first direction X, thereby dividing the semiconductor structure layer 23' into multiple independent parts distributed along the second direction Y, that is, multiple semiconductor layers 23 forming multiple transistors;

[0180] The third insulating layer 13 is wet-etched to make the semiconductor layer 23 have a suspended structure; that is, the third insulating layer 13 located on the side of the semiconductor layer 23 facing the substrate 1 and the side away from the substrate 1 is etched away; at this time, the side surfaces of the semiconductor layer 23 (including the surface facing the substrate 1, the surface away from the substrate 1, and the surface disposed opposite to each other along the second direction Y) are exposed.

[0181] The thickness of the semiconductor layer 23 is reduced along the direction perpendicular to the substrate 1; and the semiconductor layer 23 can be thinned simultaneously from the side facing the substrate 1 and the side away from the substrate 1; the semiconductor layer 23 can be thinned by wet etching to meet the channel layer thickness requirements of the transistor; since the capacitor structure is formed in the layer where the initially formed semiconductor structure layer 23' is located, the thickness of the semiconductor structure layer 23' cannot be too small when it is initially grown and formed, as this thickness is greater than the channel layer thickness requirement of the transistor. Therefore, the semiconductor layer 23 is thinned here. In addition, the semiconductor layer 23 is thinned to leave space for the subsequent formation of the word line 40.

[0182] Etching removes the second isolation layer 82, such as Figure 9A , Figure 9B , Figure 9C , Figure 9D As shown. Among them, Figures 9A-9D These are cross-sectional views along the AA', BB', DD', and EE' directions after the semiconductor layer 23 is formed, provided in some embodiments.

[0183] 9) Forming a character line 40;

[0184] The semiconductor layer 23 is subjected to high-temperature thermal oxidation treatment, so that a semiconductor oxide is formed on the exposed surface of the semiconductor layer 23, which serves as the gate insulating layer 24; for example, the semiconductor oxide is SiO2; before the high-temperature thermal oxidation treatment, the channel region of the semiconductor layer 23 can be doped according to the doping requirements of the channel region of the transistor.

[0185] A first conductive thin film is deposited to form word lines 40 extending along the second direction Y, surrounding a plurality of semiconductor layers 23 of a column of transistors; as shown Figure 10A , Figure 10B , Figure 10C , Figure 10D As shown. Among them, Figures 10A-10D These are cross-sectional views along the AA', BB', DD', and EE' directions after forming the word line 40, as provided in some embodiments.

[0186] In some embodiments, the deposition of the first conductive film may include the sequential deposition of a first sub-conductive film and a second sub-conductive film. In this case, the word line 40 may include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 may be a conductive film with good adhesion, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten.

[0187] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0188] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0189] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0190] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0191] The materials of the subsequent second to fifth conductive films are similar to those of the first conductive film, and will not be described in detail again.

[0192] 10) Disconnect word lines from different layers by 40;

[0193] The first conductive film on the sidewalls of the first word line hole K41 and the second word line hole K42 is etched away, while the first conductive film in the channel is retained; at this time, the word lines 40 of different layers are disconnected;

[0194] An eleventh insulating film is deposited and smoothed to form an eleventh insulating layer 71. The eleventh insulating layer 71 fills the first letter hole K41 and the second letter hole K42. The surface of the eleventh insulating layer 71 facing away from the substrate 1 is flush with the second dummy layer 92. Figure 11A , Figure 11B , Figure 11C , Figure 11D As shown. Among them, Figures 11A-11D The figures shown are cross-sectional views along the AA', BB', DD', and FF' directions after disconnecting the word lines 40 of different layers, as provided in some embodiments. The transistor structure of the subsequent FF' cross-section remains basically unchanged and is omitted.

[0195] 11) Expose the first hole K1 and the third hole K3;

[0196] The first dummy layer 91 and the second dummy layer 92 are removed by etching; that is, the dummy layers in the first hole K1 and the third hole K3 are removed by etching.

[0197] The eighth insulating layer 18 is etched away from the inner wall of the fourth lateral groove A4 and the third hole K3 to expose the semiconductor layer 23 and the word line 40 on the sidewall of the third hole K3. The second insulating layer 12 is also etched away from the inner wall of the first hole K1 to expose the semiconductor layer 23 and the word line 40 on the sidewall of the first hole K1. This facilitates the subsequent connection of the first capacitor electrode 41 and bit line 30 to the semiconductor layer 23. Figure 12A , Figure 12B , Figure 12C As shown. Among them, Figures 12A-12C The figures show cross-sectional views along the AA', BB', and DD' directions after the first hole K1 and the third hole K3 have been exposed according to some embodiments. At this time, a portion of the sixth insulating layer 16, which is in contact with the first dummy layer 91, has been etched away. The currently exposed first hole K1 is only a part of the initial first hole K1, referred to as the bit line hole K1'. When the second insulating layer 12 is etched, the area where the sixth insulating layer 16 contacts the first dummy layer 91 is etched away, exposing the end face of the semiconductor layer 23 facing the first hole K1 into the first hole K1, thereby maximizing the contact area between the semiconductor layer 23 and the subsequently formed bit line 30.

[0198] 12) Etch away the letter lines in the non-groove area 40;

[0199] The word lines 40 are laterally etched based on the bit line holes K1' and the third hole K3, retaining the word lines 40 surrounding the channel region of the semiconductor layer 23, and removing the word lines 40 located outside the channel region of the semiconductor layer 23. The channel region can be located between adjacent first word line holes K41 and second word line holes K42 in the same transistor region, that is, in the middle of the transistor region.

[0200] A twelfth insulating film is deposited, and the twelfth insulating film in the sidewalls of bit line hole K1', the third hole K3, and the fourth lateral groove A4 is etched away to form a twelfth insulating layer 72 filling the area where the word line 40 was etched away. At this time, the semiconductor layer 23 is exposed in the fourth lateral groove A4 and the semiconductor layer 23 is exposed in the bit line hole K1'. Figure 13A , Figure 13B , Figure 13C As shown. Among them, Figures 13A-13C These are cross-sectional views along the AA', BB', and DD' directions after etching away the word lines 40 in the non-channel regions, as provided in some embodiments.

[0201] 13) Form a connecting layer 25;

[0202] The surface of the semiconductor layer 23 exposed in the first hole K1 and the fourth lateral groove A4 is subjected to metallization treatment to form a connection layer 25, such as... Figure 14A , Figure 14B ,Figure 14C As shown. Among them, Figures 14A-14C Cross-sectional views along the AA', BB', and DD' directions are provided in some embodiments after the interconnect layer 25 is formed. Additionally, when the third dummy layer 93 exposed in the fourth lateral groove A4 is polysilicon, metal silicide is also formed on the surface of the third dummy layer 93 exposed in the fourth lateral groove A4. The interconnect layer 25 comprises three parts: a first interconnect sub-layer 251 and a second interconnect sub-layer 252 formed from the semiconductor layer 23, and a third interconnect sub-layer 253 formed from the third dummy layer 93. The semiconductor layer 23 includes a channel region surrounded by word lines 40 and source and drain regions located at opposite ends of the channel region. Before metal silicide processing, the source and drain regions of the semiconductor layer 23 can be doped according to the doping requirements of the source and drain regions of the semiconductor layer. The solution provided in this embodiment can simultaneously achieve doping of the source and drain regions, simplifying the process. The connecting layer 25 can be a metal silicide, such as a silicide of titanium (Ti), cobalt (Co), nickel (Ni), or nickel-platinum (NiPt), i.e., titanium silicide (TiSi). x ), cobalt silicide (CoSi) x The materials used include nickel-platinum silicide (NiPtSix) and others. The connecting layer 25 can reduce the contact resistance between the subsequently formed electrode and the semiconductor layer 23. The first connecting sublayer 251 is connected to the subsequently formed bit line 30, and the second connecting sublayer 252 is connected to the first capacitor electrode 41.

[0203] In some embodiments, the semiconductor layer 23 may be silicon, and the interconnect layer 25 may be TiSi. x The metal silicide treatment may include:

[0204] Deposited titanium thin film;

[0205] High-temperature heat treatment is performed to allow the titanium thin film to react with the semiconductor layer 23, forming TiSi. x ;

[0206] Etching removes the titanium film.

[0207] The solution provided in this embodiment can simultaneously form the interconnect layer 25 at both ends of the semiconductor layer 23. Compared with the solution of forming the interconnect layer 25 at each end of the semiconductor layer 23, this simplifies the process and reduces the cost.

[0208] 14) Forming a first conductive sublayer 301 for the first capacitor electrode 41 and bit line 30;

[0209] A second conductive film is deposited, which covers the inner wall of the first hole K1, the inner wall of the third hole K3 and the inner wall of the fourth transverse groove A4. The second conductive film covering the inner wall of the first hole K1 forms the first conductive sublayer 301.

[0210] A fourth dummy layer film is deposited to form a fourth dummy layer 94. Since the aperture of the third hole K3 is larger than the aperture of the first hole K1, the fourth dummy layer 94 can fill the bit line hole K1', but does not completely fill the third hole K3, that is, the third hole K3 is hollow.

[0211] The fourth dummy layer 94 on the sidewall of the third hole K3 is etched away, exposing the second conductive film on the sidewall of the third hole K3; at this time, only a portion of the fourth dummy layer 94 at the top of the bit line hole K1' is etched away.

[0212] The second conductive film on the sidewall of the third hole K3 is etched away, while the second conductive film in the fourth transverse groove A4 is retained. At this time, the second conductive films of different layers are disconnected, and the second conductive film in the fourth transverse groove A4 becomes the first capacitor electrode 41; Figure 15A , Figure 15B , Figure 15C As shown. Among them, Figures 15A-15C These are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first capacitor electrode 41 and the first conductive layer 301.

[0213] 15) Form the first dielectric layer 431 and the first sub-electrode 421;

[0214] Etching removes the fourth dummy layer 94 in the third hole K3;

[0215] The seventh insulating layer 17 is etched to expose the first capacitor electrode 41 on the side facing the substrate 1 and the side away from the substrate 1, forming a sixth lateral groove A6.

[0216] A first dielectric film and a third conductive film are deposited sequentially to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41 and the inner wall of the sixth lateral groove A6 (including the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall of the first capacitor electrode 41 away from the substrate 1); the first sub-electrode 421 fills the third hole K3, the fourth lateral groove A4, and the sixth lateral groove A6; as Figure 16A , Figure 16B , Figure 16C As shown. Among them, Figures 16A-16CThese are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first dielectric layer 431 and the first sub-electrode 421.

[0217] In some embodiments, the first sub-electrode 421 may include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 may be, for example, TiN, and the fourth sub-layer 34 may be, for example, tungsten. The third sub-layer 33 is distributed on the bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1. The fourth sub-layer 34 fills the third hole K3, the fourth lateral groove A4, and the sixth lateral groove A6.

[0218] In some embodiments, the first dielectric film may be a high-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent second dielectric film is similar to the first dielectric film and will not be described further.

[0219] 16) Forming the thirteenth insulating layer 73;

[0220] The first sub-electrode 421 is etched away, so that the first sub-electrode 421 at the top of the third hole K3 is etched away;

[0221] A thirteenth insulating film is deposited to form a thirteenth insulating layer 73, which is disposed within and fills the third hole K3; the thirteenth insulating layer 73 serves as a protective structure for the first sub-electrode 421. Figure 17A , Figure 17B As shown. Among them, Figure 17A and Figure 17B These are cross-sectional views along the BB' and DD' directions after the formation of the thirteenth insulating layer 73, as provided in some embodiments.

[0222] 17) Forming the second conductive sublayer 302 of bit line 30;

[0223] The fourth dummy layer 94 inside the first hole K1 is removed by etching;

[0224] A fourth conductive film is deposited to fill the first hole K1 and then smoothed to form the second conductive sublayer 302 of the bit line 30; as shown. Figure 18A , Figure 18B As shown. Among them, Figure 18A and Figure 18BThese are cross-sectional views along the AA' and BB' directions after the formation of the second conductive layer 302, as provided in some embodiments.

[0225] The solution provided in this embodiment eliminates the need for photolithography when forming bit line 30, simplifying the process and saving costs.

[0226] 18) Form the fourteenth insulating layer 74;

[0227] The bit line 30 is etched away so that the bit line 30 at the top of the bit line hole K1' is etched away;

[0228] A fourteenth insulating film is deposited and smoothed to form a fourteenth insulating layer 74. The fourteenth insulating layer 74 is disposed within the bit line hole K1', filling the bit line hole K1'. The fourteenth insulating layer 74 serves as a protective structure for the top of the bit line 30, and is flush with the third dummy layer 93 in the first trench T1. Figure 19 As shown. Among them, Figure 19 This is a cross-sectional view along the BB' direction after the formation of the fourteenth insulating layer 74, provided for some embodiments. During grinding, a portion of the thirteenth insulating layer 73 is etched away, flush with the third dummy layer 93.

[0229] 19) Formation of the second dielectric layer 432;

[0230] The third dummy layer 93 is removed by etching;

[0231] Etching removes the connecting layer 25 (i.e., the third connecting sub-layer 253) distributed on the outer bottom wall of the first capacitor electrode 41 in the fifth transverse groove A5 to expose the first capacitor electrode 41.

[0232] A second dielectric film is deposited to form a second dielectric layer 432; the second dielectric layer 432 covers the inner wall of the first trench T1 and the inner wall of the fifth transverse groove A5; as shown Figure 20A , Figure 20B , Figure 20C As shown. Among them, Figures 20A-20C These are cross-sectional views along the AA', BB', and DD' directions after the formation of the second dielectric layer 432, as provided in some embodiments.

[0233] 20) Form the second sub-electrode 422;

[0234] A fifth conductive film is deposited and smoothed. The fifth conductive film fills the first trench T1 and the fifth lateral groove A5 to form a second sub-electrode 422. The second sub-electrode 422, the bit line 30, and the first sub-electrode 421 are exposed on the side facing away from the substrate 1. Figure 1A , Figure 1B , Figure 1Cand Figure 1D As shown.

[0235] In some embodiments, the second sub-electrode 422 may include a fifth sub-layer 35 and a sixth sub-layer 36. The fifth sub-layer 35 may be a conductive film with good adhesion, such as TiN, and the sixth sub-layer 36 may be a conductive material with low resistivity, such as tungsten. The fifth sub-layer 35 is distributed on the inner walls of the first trench T1 and the fifth transverse groove A5, and the sixth sub-layer 36 fills the first trench T1 and the fifth transverse groove A5.

[0236] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0237] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a plurality of memory cell arrays stacked in a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed in a second direction parallel to the substrate; a plurality of bit lines extending in the direction perpendicular to the substrate through the memory cells of the plurality of layers; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed in a first direction parallel to the substrate, the word lines extending in the second direction, the first direction and the second direction intersecting; the memory cells comprising transistors, the transistors comprising semiconductor layers extending in the first direction; the word lines surrounding a part of side surfaces of a plurality of the semiconductor layers of the memory cells in the column; a dimension of the semiconductor layer in the second direction toward an end surface of the bit line being smaller than a minimum dimension of an area of the semiconductor layer surrounded by the word line in the second direction, and a dimension of the semiconductor layer in the second direction away from the end surface of the bit line being smaller than the minimum dimension of the area of the semiconductor layer surrounded by the word line in the second direction.

2. The semiconductor device according to claim 1, wherein of the semiconductor layer, each of the side surfaces comprises a first surface, a second surface and a third surface distributed in the first direction in sequence, a part of the first surface and the second surface being surrounded by the word line, the third surface being located between the area of the semiconductor layer surrounded by the word line and the end surface of the semiconductor layer toward the bit line, and a connection of the first surface and the second surface being protruded toward a semiconductor layer adjacent in the second direction.

3. The semiconductor device of claim 2, wherein, a connection of the second surface and the third surface being protruded toward a semiconductor layer adjacent in the second direction.

4. The semiconductor device of claim 1, wherein two side surfaces of the word line located between semiconductor layers adjacent in the second direction and opposite in the first direction form an arc-shaped recess.

5. The semiconductor device of claim 1, wherein a cross section of the bit line parallel to the substrate has a dimension in the second direction smaller than a dimension in the first direction.

6. The semiconductor device of claim 2, wherein a gate insulating layer is provided between the semiconductor layer and the word line, the gate insulating layer surrounds the semiconductor layer, and on two side surfaces of the semiconductor layer opposite in the second direction, the gate insulating layer is distributed on the first surface and the second surface and not distributed on the third surface.

7. The semiconductor device of claim 6, wherein, the gate insulating layer continuously extends on a surface of the semiconductor layer away from the substrate and a surface of the semiconductor layer toward the substrate.

8. The semiconductor device of claim 6, wherein, the semiconductor layer comprises single crystal silicon, and the gate insulating layer is silicon oxide formed by oxidizing the single crystal silicon.

9. The semiconductor device of claim 8, wherein, the semiconductor device further comprises a first connection sub-layer connected to an end surface of the semiconductor layer toward the bit line, and a second connection sub-layer connected to an end surface of the semiconductor layer away from the bit line, the first connection sub-layer and the second connection sub-layer are metal silicides formed by metal silicidizing single crystal silicon, and the first connection sub-layer is connected to the bit line.

10. The semiconductor device of claim 9, wherein, The memory cell further comprises a capacitor, the capacitor comprises a first capacitor electrode and a second capacitor electrode, the second capacitor electrode comprises a first sub-electrode, the semiconductor device further comprises a capacitor hole penetrating through the memory cell in multiple layers, a plurality of first capacitor electrodes of a plurality of memory cells in the same position of different layers are arranged on the sidewall of the capacitor hole and are spaced apart in a direction perpendicular to the substrate, and the first sub-electrode fills the capacitor hole, and a plurality of the first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

11. The semiconductor device of claim 10, wherein, The capacitor hole exposes a plurality of second connection sub-layers respectively connected to a plurality of semiconductor layers of a plurality of memory cells stacked in a direction perpendicular to the substrate, and the first capacitor electrode is connected to the exposed second connection sub-layers.

12. The semiconductor device of claim 10, wherein, The first capacitor electrode comprises a first part extending in a direction perpendicular to the substrate and a second part extending from both ends of the first part towards the first sub-electrode, respectively; the first part is connected to the second connection sub-layer.

13. The semiconductor device of claim 12, wherein, The second capacitor electrode further comprises a second sub-electrode, and the second sub-electrode surrounds the first part through a second dielectric layer.

14. The semiconductor device of claim 10, wherein, The distance between the surface away from the substrate and the surface towards the substrate of the word line is equal to the length of the first capacitor electrode extending in a direction perpendicular to the substrate.

15. The semiconductor device according to any one of claims 10 to 14, wherein The semiconductor device further comprises a first isolation hole penetrating through the memory cell array between a plurality of semiconductor layers arranged in a second direction and between a plurality of capacitors arranged in the second direction and the word line, and an insulating film layer filling the first isolation hole; and a second isolation hole penetrating through the memory cell array between a plurality of bit lines arranged in the second direction and between a plurality of word lines arranged in the first direction, and an insulating film layer filling the second isolation hole.

16. A method of manufacturing a semiconductor device, characterized by Comprising: forming a stack structure comprising a plurality of semiconductor structure layers and a plurality of sacrificial layers arranged alternately on a substrate; forming a plurality of first holes spaced apart in a second direction penetrating through the stack structure in a direction perpendicular to the substrate; forming a second hole penetrating through the stack structure in a direction perpendicular to the substrate between adjacent first holes, and the aperture of the second hole in a first direction is larger than the aperture of the first hole in the first direction; the first direction and the second direction are parallel to the substrate and intersect; lateral etching the semiconductor structure layer based on the second hole, so that the second hole intersects the first hole, and the semiconductor structure layer is reserved between second holes adjacent in the second direction; forming a first trench extending through the stack structure in the second direction; forming a plurality of third holes penetrating through the stack structure in a direction perpendicular to the substrate and spaced apart in the second direction between the first trench and the first hole, and a plurality of transistor regions are defined between a plurality of the third holes and a plurality of the first holes; etching the semiconductor structure layer based on the first trench in a direction parallel to the substrate to remove the semiconductor structure layer outside the transistor region and part of the semiconductor structure layer in the transistor region, and the semiconductor structure layer reserved in the transistor region is connected to part of the sidewall of the third hole towards the first hole side, forming a fifth lateral recess. forming, in the transistor region, a plurality of first word line holes spaced apart along the second direction and penetrating the stack structure along a direction perpendicular to the substrate direction, and a plurality of second word line holes spaced apart along the second direction and penetrating the stack structure along a direction perpendicular to the substrate direction, side walls of the first word line holes and the second word line holes exposing each of the semiconductor structure layers; the first word line holes and the second word line holes being spaced apart along the first direction, the second word line holes being located in the region where the second holes are located; based on the first word line holes and the second word line holes, etching the semiconductor structure layers along a direction parallel to the substrate direction, forming a channel that connects the first word line hole and the second word line hole adjacent along the first direction in communication, to divide the semiconductor structure layers to form a plurality of semiconductor layers corresponding to a plurality of transistors spaced apart along the second direction and extending along the first direction; sequentially forming a gate insulating layer surrounding the semiconductor layers, and a word line surrounding part of the side surfaces of the plurality of semiconductor layers of a column of transistors distributed along the second direction; forming a bit line extending along a direction perpendicular to the substrate direction in the first hole.

17. The method of manufacturing a semiconductor device according to Claim 16, wherein Before forming the first word line hole and the second word line hole, further comprising: depositing an isolation layer film filling the fifth lateral groove, and etching the isolation layer film to the side of the third hole facing the first hole outside the transistor region, to form an isolation layer extending along the second direction and distributed in the region of the semiconductor layer not in contact with the third hole facing the first hole; wherein the side wall of the first word line hole exposes the isolation layer.

18. The semiconductor device manufacturing method of claim 17, wherein, Before laterally etching the semiconductor structure layer based on the second hole, further comprising: based on the second hole, etching the sacrificial layer of a predetermined length along a direction parallel to the substrate direction, and sequentially forming a first barrier layer covering the inner wall of the region where the etched sacrificial layer is located and an insulating layer filling the region where the etched sacrificial layer is located; After forming the plurality of semiconductor layers corresponding to a plurality of transistors spaced apart along the second direction and extending along the first direction, and before sequentially forming a gate insulating layer surrounding the semiconductor layers, further comprising: etching and removing the first barrier layer, so that the semiconductor layer forms a suspended structure with exposed side surfaces, and thinning the semiconductor layer along a direction perpendicular to the substrate direction; the sequentially forming a gate insulating layer surrounding the semiconductor layers, and a word line surrounding part of the side surfaces of the plurality of semiconductor layers of a column of transistors distributed along the second direction comprises: performing an oxidation treatment on the exposed side surfaces of the semiconductor layer to form the gate insulating layer; forming a word line filling the channel and the gap left after the semiconductor layer is thinned; based on the first hole and the third hole, etching the word line to retain the word line surrounding the channel region of the semiconductor layer.

19. The method of manufacturing a semiconductor device according to Claim 18, wherein After based on the first hole and the third hole, etching the word line to retain the word line surrounding the channel region of the semiconductor layer, further comprising, forming a first connection sub-layer disposed on a side of the semiconductor layer close to the first hole and a second connection sub-layer disposed on a side of the semiconductor layer close to the third hole.

20. The method of manufacturing a semiconductor device according to Claim 19, wherein Before forming the first trench extending through the stack structure and along the second direction, further comprising: forming a second blocking layer covering sidewalls of the first hole and a first dummy layer filling the first hole; etching the second blocking layer towards two sidewalls of a second hole adjacent along the second direction to expose sidewalls of the first dummy layer and thinning the first dummy layer along the second direction; the forming the bit line extending along a direction perpendicular to the substrate direction in the first hole comprises: etching and removing the first dummy layer and the second blocking layer to form a bit line hole and forming a bit line filling the bit line hole.

21. The method of manufacturing a semiconductor device according to Claim 20, wherein Before etching the word line based on the first hole and the third hole, further comprising: etching the semiconductor structure layer along a direction parallel to the substrate direction based on the third hole to form a second lateral recess; forming a third blocking layer covering inner walls of the second lateral recess and the third hole and a second dummy layer filling the third hole and the second lateral recess; etching and removing the second dummy layer while etching and removing the first dummy layer and etching and removing the third blocking layer while etching and removing the second blocking layer; after forming the first connection sub-layer disposed on a side of the semiconductor layer close to the first hole and the second connection sub-layer disposed on a side of the semiconductor layer close to the third hole, further comprising: depositing a first conductive thin film covering inner walls of the third hole and the second lateral recess, etching and removing the first conductive thin film on sidewalls of the third hole and retaining the conductive thin film on the inner walls of the second lateral recess to form a first capacitor electrode; the forming the bit line filling the bit line hole comprises: depositing a first conductive thin film covering inner walls of the third hole and the second lateral recess at the same time as depositing a first conductive thin film covering inner walls of the bit line hole to form a first conductive sub-layer of the bit line; depositing a second conductive thin film filling the bit line hole in the bit line hole with the first conductive thin film to form a second conductive sub-layer of the bit line.

22. An electronic device, comprising: The semiconductor device as claimed in any one of claims 1 to 15, or a semiconductor device formed according to the manufacturing method of the semiconductor device as claimed in any one of claims 16 to 21.

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