Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed in a second direction parallel to the substrate; the bit lines penetrate through the storage units of different layers and extend in the direction perpendicular to the substrate; the plurality of storage units in the same layer and the same column are respectively connected to a plurality of bit lines which are distributed at intervals along a second direction; the word lines extend in the second direction, the word lines and the bit lines are distributed in the first direction, and the first direction and the second direction are parallel to the substrate, intersect with each other and are not perpendicular to each other; the semiconductor layers of the transistors of the storage units surround the word lines, and the semiconductor layers of the storage units in the same column are distributed at intervals in the second direction and surround the same word line. According to the scheme provided by the embodiment, the distribution direction of the bit lines is not perpendicular to the arrangement direction of the bit lines and the word lines, the distance between the bit lines can be increased, and coupling capacitance is reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which reduces coupling capacitance.

[0006] This application provides a semiconductor device, including:

[0007] A multilayer array of memory cells stacked perpendicular to the substrate, the array comprising at least one column of multiple memory cells distributed along a second direction parallel to the substrate;

[0008] Multiple bit lines extend through memory cells in different layers along a direction perpendicular to the substrate; multiple memory cells in the same layer and column are respectively connected to multiple bit lines spaced apart along a second direction;

[0009] Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction, and the word lines extend along a second direction. Both the first and second directions are parallel to the substrate, intersect each other, and are not perpendicular.

[0010] The memory cell includes a transistor, the transistor including a semiconductor layer connected to the bit line, the semiconductor layer surrounding the word line, and the semiconductor layers of memory cells in the same column are spaced apart along a second direction and surround the same word line.

[0011] In some embodiments, every two adjacent memory cells along a first direction are connected to the same bit line;

[0012] A first isolation hole penetrating the multilayer memory cell is provided between adjacent bit lines along the second direction and between adjacent word lines along the first direction. The first isolation hole is filled with a first isolation layer of an integral structure. The first isolation hole exposes the side surface of the adjacent word line and the side surface of the adjacent bit line.

[0013] In some embodiments, the memory cell further includes a capacitor connected to the semiconductor layer, the capacitor being disposed on the side of the semiconductor layer away from the bit line, the capacitor and the word line being distributed along the first direction, and multiple capacitors connected to multiple memory cells in the same column being distributed along the second direction.

[0014] In some embodiments, the capacitor includes a first capacitor electrode and a second capacitor electrode, the second capacitor electrode includes a first sub-electrode, and the semiconductor device further includes a capacitor hole penetrating through multiple layers of the memory cells, a plurality of first capacitor electrodes of a plurality of memory cells at the same position in different layers are disposed on the sidewall of the capacitor hole and spaced apart along a direction perpendicular to the substrate, the first sub-electrode fills the capacitor hole, and a plurality of first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

[0015] A second isolation hole penetrating the multilayer memory cell is provided between adjacent capacitor holes along the second direction. The second isolation hole is filled with a second isolation layer of an integral structure. The second isolation hole exposes the first capacitor electrode in the adjacent capacitor hole, as well as the side surface of the word line adjacent to the capacitor hole.

[0016] In some embodiments, the first isolation hole extends along a second direction, and a plurality of first isolation holes distributed between a column of bit lines are sequentially staggered along a first direction.

[0017] In some embodiments, the second isolation hole extends along a second direction, and a plurality of second isolation holes distributed between a row of capacitor holes are sequentially staggered along a first direction.

[0018] In some embodiments, the first capacitor electrode includes a first portion extending in a direction perpendicular to the substrate and a second portion extending from both ends of the first portion toward the first sub-electrode; the first portion is connected to the semiconductor layer and two second isolation layers adjacent to the capacitor aperture.

[0019] In some embodiments, the second capacitor electrode further includes a second sub-electrode, which surrounds a first portion of the first capacitor electrode via a second dielectric layer portion.

[0020] In some embodiments, the transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line surrounding the word line; the gate insulating layers of the plurality of transistors in the same layer and column are disconnected at the contact region between the first isolation layer and the word line surrounded by the plurality of gate insulating layers, and are disconnected at the contact region between the second isolation layer and the word line surrounded by the plurality of gate insulating layers.

[0021] In some embodiments, the first isolation hole also exposes the side surface of the adjacent gate insulating layer and the end face of the adjacent semiconductor layer.

[0022] In some embodiments, the second isolation hole also exposes the side surface of the adjacent gate insulating layer and the end face of the adjacent semiconductor layer.

[0023] In some embodiments, the contact surfaces of the semiconductor layer and the first capacitor electrode, and the contact surfaces of the semiconductor layer and the bit line, are misaligned in the first direction.

[0024] This disclosure provides a method for manufacturing a semiconductor device, including:

[0025] A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate;

[0026] A plurality of bit line holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate and are spaced apart along a second direction;

[0027] A bit line is formed within the bit line hole, extending in a direction perpendicular to the substrate to fill the bit line hole;

[0028] A plurality of capacitor holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate and are spaced apart along a second direction, and the bit line holes are spaced apart from the capacitor holes along a first direction. The sacrificial layer is etched along a direction parallel to the substrate based on the capacitor holes to form a first lateral groove. A first capacitor electrode is formed distributed on the inner wall of the first lateral groove. The first direction and the second direction intersect but are not perpendicular.

[0029] A first isolation hole is formed between adjacent bit line holes along a second direction, penetrating the stacked structure, the first isolation hole exposing the side surface of the adjacent bit line; and a second isolation hole is formed between adjacent capacitor holes along a second direction, penetrating the stacked structure, the second isolation hole exposing the adjacent first capacitor electrode; the first isolation hole and the second isolation hole are spaced apart along a first direction;

[0030] Etching removes the sacrificial layer distributed between the first and second isolation holes, forming a channel extending in the second direction between adjacent insulating layers, between a row of first isolation holes distributed in the second direction, and between second isolation holes distributed in the second direction;

[0031] A word line extending in a second direction is formed in the channel, and a plurality of semiconductor layers are spaced apart in the second direction around the word line.

[0032] In some embodiments, the word lines formed in the channel extending in a second direction, and the plurality of semiconductor layers spaced apart in the second direction around the word lines, include:

[0033] A semiconductor thin film, a gate insulating film, and a conductive thin film are deposited sequentially. The semiconductor thin film and the gate insulating film sequentially cover the first isolation hole, the second isolation hole, and the inner wall of the channel. The conductive thin film fills the channel but does not completely fill the first isolation hole and the second isolation hole.

[0034] The semiconductor thin film, gate insulating film, and conductive thin film in the first isolation hole and the second isolation hole are etched away. The semiconductor thin film is etched along a direction parallel to the substrate based on the first isolation hole and the second isolation hole, such that the semiconductor thin film forms a plurality of semiconductor layers spaced apart along a second direction, the conductive thin film forms word lines extending along the second direction, and the gate insulating film forms a gate insulating layer.

[0035] In some embodiments, the method further includes sequentially forming a first dielectric layer covering the inner wall of a capacitor hole on which the first capacitor electrode is formed and a first sub-electrode filling the capacitor hole.

[0036] In some embodiments, the method further includes,

[0037] A trench is formed between two adjacent columns of capacitor holes on the side of the capacitor holes facing away from the second isolation hole, the trench exposing each of the sacrificial layers;

[0038] Based on the trench etching, the sacrificial layer between the trench and the second isolation hole is removed to form a second lateral groove. The trench and the second lateral groove expose the surface of the first capacitor electrode located on the side of the second isolation hole away from the bit line.

[0039] A second dielectric layer covering the inner walls of the trench and the second lateral groove, and a second sub-electrode filling the trench and the second lateral groove are sequentially formed within the trench and the second lateral groove.

[0040] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed according to the manufacturing method of any of the above-described semiconductor devices.

[0041] This application includes a semiconductor device comprising: a multilayer array of memory cells stacked perpendicular to a substrate direction, the memory cell array including at least one column of multiple memory cells distributed along a second direction parallel to the substrate; multiple bit lines extending through the memory cells in different layers along a direction perpendicular to the substrate; multiple memory cells in the same layer and column respectively connected to the multiple bit lines spaced apart along the second direction; multiple word lines distributed in different layers, the word lines and the bit lines distributed along a first direction, and the word lines extending along the second direction; both the first and second directions are parallel to the substrate, intersecting each other but not perpendicular; each memory cell includes a transistor, the transistor including a semiconductor layer connected to the bit line, the semiconductor layer surrounding the word line, and the semiconductor layers of memory cells in the same column spaced apart along the second direction and surrounding the same word line. The solution provided in this embodiment, where the bit line distribution direction is not perpendicular to the arrangement direction of the bit lines and word lines, can increase the distance between bit lines and reduce coupling capacitance.

[0042] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0043] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0044] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0045] FIG. 1A , FIG. 1B , FIG. 1C , FIG. 1D Cross-sectional views of a semiconductor device along the AA', BB', CC', and DD' directions provided in some embodiments are shown respectively.

[0046] FIG. 2A , FIG. 2B , FIG. 2C , FIG. 2D These are cross-sectional views along the AA', BB', CC', and EE' directions after the bit lines are formed, provided in some embodiments.

[0047] FIG. 3A ,FIG. 3B , FIG. 3C , FIG. 3D Cross-sectional views along the AA', BB', CC', and EE' directions after the formation of the first capacitor electrode are provided in some embodiments;

[0048] FIG. 4A , FIG. 4B , FIG. 4C , FIG. 4D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the second dummy layer are provided in some embodiments;

[0049] FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the third and fourth holes, respectively, provided in some embodiments.

[0050] FIG. 6A , FIG. 6B , FIG. 6C , FIG. 6D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first trench are provided in some embodiments;

[0051] FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D Cross-sectional views along the AA', BB', CC', and DD' directions respectively, provided in some embodiments after the formation of the second dielectric layer and the second sub-electrode;

[0052] FIG. 8 A cross-sectional view along the CC' direction after the protective structure for forming the second sub-electrode is provided in some embodiments;

[0053] FIG. 9A , FIG. 9B , FIG. 9C , FIG. 9D Cross-sectional views along the AA', BB', CC', and DD' directions after etching to remove the sacrificial layer, provided in some embodiments;

[0054] FIG. 10A , FIG. 10B , FIG. 10C , FIG. 10D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the semiconductor layer, gate insulating layer, and word line are provided in some embodiments;

[0055] FIG. 11A , FIG. 11B, FIG. 11C , FIG. 11D Cross-sectional views along the AA', BB', CC', and DD' directions after disconnecting multiple semiconductor layers and multiple word lines, as provided in some embodiments;

[0056] FIG. 12A , FIG. 12B , FIG. 12C , FIG. 12D These are cross-sectional views along the AA', BB', CC', and DD' directions after exposing the second initial hole, as provided in some embodiments. Detailed Implementation

[0057] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0059] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0060] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0061] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0062] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0063] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0064] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0065] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0066] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0067] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0068] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0069] FIG. 1A A cross-sectional view of a semiconductor device provided for some embodiments along the AA' direction parallel to substrate 1. FIG. 1B A cross-sectional view of a semiconductor device provided for some embodiments along the BB' direction parallel to substrate 1.FIG. 1C For along FIG. 1A A cross-sectional view perpendicular to the CC' direction of substrate 1. FIG. 1D For along FIG. 1A A cross-sectional view of the section perpendicular to the DD' direction of substrate 1. (See figure) FIG. 1A to FIG. 1D As shown, this disclosure provides a semiconductor device including a multilayer memory cell array and multiple bit lines 30 vertically stacked on a substrate 1. The memory cell array may include at least one column of multiple memory cells distributed along a second direction Y parallel to the substrate 1, and multiple word lines 40. The multiple word lines 40 may be distributed in different layers.

[0070] In some embodiments, each layer of the memory cell array may include a plurality of memory cells distributed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect but are not perpendicular.

[0071] In some embodiments, the angle between the first direction X and the second direction Y is, for example, 30° to 60°.

[0072] The bit line 30 can extend through the memory cells in different layers along a direction perpendicular to the substrate 1. Multiple memory cells stacked at the same position in different layers along the direction perpendicular to the substrate 1 are connected to the same bit line 30. Multiple memory cells in the same layer and column are respectively connected to multiple bit lines 30 spaced apart along the second direction Y. In the solution provided in this embodiment, the bit lines 30 are arranged along the second direction Y which is not perpendicular to the first direction X, so that the bit lines 30 are misaligned in the direction perpendicular to the first direction X, thereby increasing the distance between adjacent bit lines and reducing the parasitic capacitance between bit lines.

[0073] In some embodiments, two adjacent memory cells along the first direction X are connected to the same bit line 30. Each pair of memory cells can be grouped together, and adjacent memory cells along the first direction X within the same group are connected to the same bit line 30.

[0074] The word line 40 can extend along the second direction Y. The word line 40 may include two end faces disposed opposite each other along the second direction Y and a side surface located between the two end faces (i.e., a surface along the extension direction of the word line 40). The multiple word lines 40 of the same memory cell array can be distributed at intervals along the first direction X. The word lines 40 of memory cell arrays of different layers can be stacked in a direction perpendicular to the substrate 1.

[0075] The storage unit can be a 1T1C storage unit, or it can be a storage unit with other structures.

[0076] Taking a 1T1C memory cell as an example, the memory cell may include a transistor and a capacitor connected to the transistor. The transistor and capacitor of the same memory cell may be distributed along a first direction X. The capacitor, the word line 40, and the bit line 30 are distributed along the first direction X. Multiple capacitors connected to multiple memory cells in the same column are distributed along a second direction Y.

[0077] The transistor may include a semiconductor layer 23 surrounding a side surface of the word line 40 and connected to the bit line 30. Semiconductor layers 23 of memory cells in the same column are spaced apart along a second direction Y and surround the same word line 40. Semiconductor layer 23 may include two side surfaces (i.e., a surface facing the word line 40 and a surface facing away from the word line) and two end faces connecting the two side surfaces.

[0078] A gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40. The gate insulating layer 24 surrounds the side surface of the word line 40. The gate insulating layer 24 may include a side surface facing the word line 40 and a side surface away from the word line 40.

[0079] In some embodiments, the gate insulating layers 24 of the memory cells in the same column are spaced apart along the second direction Y and surround the same word line 40.

[0080] The bit line 30 can be disposed in a bit line via (i.e., the first via K1 in the subsequent embodiment) that penetrates the multilayer memory cell along a direction perpendicular to the substrate 1. The bit line vias are spaced apart along the second direction Y.

[0081] In some embodiments, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode. The first capacitor electrode 41 is connected to the side of the semiconductor layer 23 opposite to the bit line 30.

[0082] In some embodiments, the contact surfaces of the semiconductor layer 23 and the first capacitor electrode 41, and the contact surfaces of the semiconductor layer 23 and the bit line 30, are misaligned in the first direction X. Taking any memory cell as an example, referred to as the target memory cell, and the two memory cells adjacent to the target memory cell along the second direction, referred to as the first memory cell and the second memory cell, respectively, one of the contact surfaces of the semiconductor layer 23 and the first capacitor electrode 41, and the other of the contact surfaces of the semiconductor layer 23 and the bit line 30, is closer to the first memory cell, and the other is closer to the second memory cell. That is, compared to the scheme where the bit lines are distributed in a direction perpendicular to the first direction X, in this embodiment, the semiconductor layer 23 is tilted around the word line 40, and the surrounding direction of the semiconductor layer 23 is not perpendicular to the extension direction of the word line 40.

[0083] The second capacitor electrode may include a first sub-electrode 421 and a second sub-electrode 422. The first capacitor electrode 41 may be surrounded by a first dielectric layer 431, and the second capacitor electrode 422 may be partially surrounded by a second dielectric layer 432.

[0084] In some embodiments, the first capacitor electrode 41 may include a first portion extending in a direction perpendicular to the substrate 1 and a second portion extending from both ends of the first portion toward the first sub-electrode 421; the first portion is connected to the semiconductor layer 23.

[0085] In some embodiments, the semiconductor device may further include a capacitor via (i.e., a second via in subsequent embodiments) penetrating multiple layers of the memory cells. A first capacitor electrode 41 may be disposed on the sidewall of the capacitor via. Multiple first capacitor electrodes 41 of multiple memory cells at the same location in different layers are disposed on the sidewall of the capacitor via and spaced apart along a direction perpendicular to the substrate 1. A first sub-electrode 421 and a first dielectric layer 431 are distributed within the capacitor via. The first dielectric layer 431 covers the inner wall of the capacitor via where the first capacitor electrode 41 is formed, and the first sub-electrode 421 fills the capacitor via. A second sub-electrode 422 and a second dielectric layer 432 are distributed outside the capacitor via.

[0086] In some embodiments, a first isolation hole penetrating a multilayer memory cell is provided between adjacent bit lines 30 along the second direction Y and between adjacent word lines 40 along the first direction X. The first isolation hole is filled with a first isolation layer 151 of an integral structure. The first isolation hole exposes the side surface of the adjacent word line 40 and the side surface of the adjacent bit line 30 (i.e. the surface of the bit line 30 extending in the direction perpendicular to the substrate 1).

[0087] In some embodiments, the first isolation hole also exposes the side surface of the gate insulating layer 24 (which may include a gate insulating layer 24 for four memory cells, i.e., four memory cells adjacent along the first direction X and the second direction Y) facing the word line 40, and exposes the end face of the semiconductor layer 23 (which may include a semiconductor layer 23 for four memory cells) adjacent to the first isolation hole. The first isolation layer 151 contacts the exposed side surface of the gate insulating layer 24 and the end face of the exposed semiconductor layer 23.

[0088] In some embodiments, a second isolation via penetrating the multilayer memory cell is provided between adjacent capacitor vias along the second direction Y. The second isolation via is filled with a second isolation layer 152 of an integral structure. The second isolation via exposes the first capacitor electrode 41 in the adjacent capacitor vias (including two capacitor vias adjacent along the second direction Y), as well as the side surface of the word line 40 adjacent to the capacitor vias. The second isolation layer 152 can contact a first portion of the exposed first capacitor electrode 41 (can contact the first portions of the two first capacitor electrodes 41 adjacent along the second direction Y), and contact the side surface of the exposed word line 40. The second isolation via also exposes a second dielectric layer 432, that is, the second isolation layer 152 contacts the second dielectric layer 432.

[0089] In some embodiments, the second isolation via may also expose the side surface of the adjacent gate insulating layer 24 (which may include the gate insulating layers 24 of two adjacent memory cells along the second direction Y) and the end face of the adjacent semiconductor layer 23 (which may include the semiconductor layers 23 of two adjacent memory cells along the second direction Y). The second isolation layer 152 contacts the exposed side surface of the gate insulating layer 24 and the exposed end face of the semiconductor layer 23.

[0090] In some embodiments, the contact surface between the word line 40 and the first isolation layer 151 may form a recess away from the first isolation layer 151, and the contact surface between the word line 40 and the second isolation layer 152 may form a recess away from the second isolation layer 152. The solution provided in this embodiment can maximize the distance between the word line 40 and the electrodes of adjacent word lines or capacitors, thereby reducing the coupling capacitance.

[0091] In some embodiments, the first isolation hole may extend along the second direction Y, and a plurality of first isolation holes distributed between a row of bit lines 30 are sequentially staggered along the first direction X. (See reference...) FIG. 11A and FIG. 11B The first isolation hole K3' in the middle, and the multiple first isolation holes K3' between a row of bit lines 30 are misaligned along the first direction X, and are in the same direction as the misalignment of the bit line holes.

[0092] In some embodiments, the second isolation hole may extend along a second direction Y, and a plurality of second isolation holes distributed among a row of capacitor holes are sequentially staggered along a first direction X. (Reference) FIG. 11A and FIG. 11B The second isolation hole K4' in the middle, the multiple second isolation holes K4' between a row of capacitor holes are staggered in sequence along the first direction X, and the staggered direction is the same as that of the capacitor holes.

[0093] In some embodiments, the first insulating layer 151 and the second insulating layer 152 may be manufactured simultaneously. For example, the first insulating layer 151 and the second insulating layer 152 may be the fifth insulating layer 15 described in subsequent embodiments.

[0094] In some embodiments, the second sub-electrodes 422 of multiple memory cells arranged in the same column along the second direction Y can be connected to form an integral structure. The second sub-electrode 422 may include a first sub-part extending through the multiple memory cells in a direction perpendicular to the substrate 1 and a plurality of second sub-parts extending from the first sub-part in a direction parallel to the substrate 1. The first sub-part fills the region between adjacent first capacitor electrodes 41 along the first direction X; the second sub-parts extend to the side of the second isolation hole away from the word line 40, partially surround the first capacitor electrode 41, and fill the region between adjacent first capacitor electrodes 41 along the second direction Y.

[0095] In some embodiments, the first sub-part may include: a plurality of main body portions 4221 extending along a second direction Y, and a plurality of connecting portions 4222 connecting adjacent main body portions 4221, the connecting portions 4222 being located between adjacent capacitor holes along a first direction X. The plurality of main body portions 4221 of the first sub-part may be misaligned along the first direction X, and the misalignment direction is the same as the misalignment direction of a row of capacitor holes.

[0096] In some embodiments, the second sub-electrodes 422 of a plurality of memory cells distributed along the second direction Y in each of two adjacent columns can be connected to form an integral structure.

[0097] In some embodiments, the second dielectric layer 432 of multiple memory cells distributed in the same column along the second direction Y can be connected to form an integral structure.

[0098] In some embodiments, the second dielectric layer 432 of a plurality of memory cells distributed along the second direction Y in each of two adjacent columns can be connected to form an integral structure.

[0099] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0100] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0101] 1) Form bit line 30;

[0102] A substrate 1 is provided, and a first insulating film and a sacrificial layer film are alternately deposited on the substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and sacrificial layers 10;

[0103] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form multiple rows of first holes K1, each row including multiple first holes K1 spaced apart along the second direction Y, the second direction Y intersecting the first direction X but not perpendicular to it;

[0104] After depositing the first conductive film, it is smoothed to form a bit line 30 that fills the first hole K1; as shown FIG. 2A , FIG. 2B , FIG. 2C and FIG. 2D As shown. Among them, FIG. 2A , FIG. 2B , FIG. 2C , FIG. 2D These are cross-sectional views along the AA', BB', CC', and EE' directions after the bit line 30 is formed, provided in some embodiments. FIG. 2A to FIG. 2D Only the first hole K1 in the column is shown.

[0105] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0106] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0107] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0108] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0109] The materials of the subsequent second to fifth conductive films are similar to those of the first conductive film, and will not be described in detail again.

[0110] In some embodiments, the bit line 30 may include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 may be a conductive material with good adhesion to other film layers, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten. The first sub-layer 31 covers the bottom and sidewalls of the first hole K1, and the second sub-layer 32 fills the first hole K1. However, the embodiments disclosed herein are not limited to this, and the bit line 30 may be other single-layer or multi-layer structures.

[0111] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0112] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to fifth insulating films are similar and will not be described in detail.

[0113] In some embodiments, the sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0114] In some embodiments, the first hole K1 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0115] 2) Form the first capacitor electrode 41;

[0116] A second insulating film is deposited to form a second insulating layer 12, which covers the bit line 30 and the topmost sacrificial layer 10.

[0117] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of second initial holes K2 spaced apart along the second direction Y; the second initial holes K2 and the first holes K1 are spaced apart along the first direction X;

[0118] Based on the second initial hole K2, the sacrificial layer 10 is etched laterally to form a first lateral groove V1. The second initial hole K2 and the first lateral groove V1 constitute a second hole. The orthographic projection of the sub-hole of the first insulating layer 11 on the substrate 1 falls into the orthographic projection of the sub-hole of the sacrificial layer 10 on the substrate 1.

[0119] A second conductive film and a first dummy layer film are deposited sequentially to form a first capacitor electrode 41 and a first dummy layer 91. The second conductive film covers the inner wall of the second initial hole K2 and the inner wall of the first transverse groove V1, and the first dummy layer film fills the second initial hole K2 and the first transverse groove V1.

[0120] The first dummy layer 91 in the second initial hole K2 is removed by etching, while the first dummy layer 91 in the first transverse groove V1 is retained. FIG. 3A , FIG. 3B , FIG. 3C and FIG. 3D As shown. Among them, FIG. 3A , FIG. 3B , FIG. 3C , FIG. 3D These are cross-sectional views along the AA', BB', CC', and EE' directions respectively, provided in some embodiments after the formation of the first capacitor electrode 41.

[0121] In some embodiments, the first dummy layer film may be a film layer such as polycrystalline silicon that has an etching selectivity ratio with the first insulating film and the sacrificial layer film. The materials of the subsequent second and third dummy layer films are similar and will not be described again.

[0122] In some embodiments, the second initial hole K2 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0123] 3) Forming a second virtual layer 92;

[0124] The first capacitor electrode 41 in the second initial hole K2 is removed by etching, while the first capacitor electrode 41 in the first transverse groove V1 is retained. At this time, the first capacitor electrodes 41 in different layers are disconnected.

[0125] A second dummy layer film is deposited and smoothed to form a second dummy layer 92 filling the second initial hole K2; the second dummy layer 92 and the second insulating layer 12 are flush, as shown. FIG. 4A , FIG. 4B , FIG. 4C and FIG. 4D As shown. Among them, FIG. 4A , FIG. 4B , FIG. 4C , FIG. 4D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the second dummy layer 92, as provided in some embodiments.

[0126] 4) Formation of the third hole K3 and the fourth hole K4;

[0127] A first hard mask thin film is deposited to form a first hard mask layer 71 covering the aforementioned structure; the first hard mask thin film may be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO2.

[0128] A first isolation trench extending in the second direction Y is formed in the first hard mask layer 71 to fully expose a row of bit lines 30 on the side away from the substrate 1, and a second isolation trench extending in the second direction Y is formed in the first hard mask layer 71 to expose a row of second initial holes K2 near the bit lines 30.

[0129] Based on the first isolation groove, a third hole K3 extending in the second direction Y is formed between adjacent first holes K1 along the second direction Y; and based on the second isolation groove, a fourth hole K4 extending in the second direction Y is formed between adjacent second initial holes K2 along the second direction Y, and the fourth hole K4 is close to the second initial hole K2 facing the bit line 30; adjacent third holes K3 and fourth holes K4 are spaced apart along the first direction X; the sidewall of the third hole K3 exposes two bit lines 30 adjacent along the second direction Y; the sidewall of the fourth hole K4 exposes two first capacitor electrodes 41 adjacent along the second direction Y.

[0130] A third insulating film and a third dummy layer film are sequentially deposited and smoothed to form a third insulating layer 13 covering the inner walls of the first isolation trench, the second isolation trench, the third hole K3, and the fourth hole K4, and a third dummy layer 93 filling the first isolation trench, the second isolation trench, the third hole K3, and the fourth hole K4; as shown. FIG. 5A , FIG. 5B , FIG. 5C and FIG. 5D As shown. Among them, FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5DThe images show cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the third hole K3 and the fourth hole K4, respectively, provided in some embodiments. The distance between the surface of the third dummy layer 93 away from the substrate 1 and the substrate 1 is greater than the distance between the surface of the second dummy layer 92 away from the substrate 1 and the substrate 1.

[0131] 5) Form the first trench T1;

[0132] A second hard mask film is deposited to form a second hard mask layer 72 covering the structure formed above; the second hard mask film may be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO2.

[0133] The stacked structure is etched along a direction perpendicular to the substrate 1 on the side of the second initial hole K2 away from the bit line 30 to form a plurality of first trenches T1 penetrating the stacked structure; the first trenches T1 extend along the second direction Y, and adjacent first trenches T1 define a group of memory cells, each group of memory cells including two columns of memory cells; the first trenches T1 are located between two adjacent columns of second initial holes K2 along the first direction X, and the first trenches T1 extend substantially along the second direction Y, and may include a plurality of first sub-trenches located between two adjacent second initial holes K2 along the first direction X and a plurality of second sub-trenches connected by the plurality of first sub-trenches, the second sub-trenches extend along the second direction Y, and there is a misalignment between different second sub-trenches along the first direction X, and the misalignment direction is the same as the misalignment direction of the second initial hole K2.

[0134] Based on the first trench T1, the sacrificial layer 10 is laterally etched to the fourth hole K4 (i.e., etched to the side of the third insulating layer 13 away from the bit line 30 in the fourth hole K4), forming a second lateral groove V2, such as... FIG. 6A , FIG. 6B , FIG. 6C and FIG. 6D As shown. Among them, FIG. 6A , FIG. 6B , FIG. 6C , FIG. 6D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first groove T1, provided in some embodiments.

[0135] 6) Form the second dielectric layer 432 and the second sub-electrode 422;

[0136] A second dielectric film and a third conductive film are deposited sequentially to form a second dielectric layer 432 and a second sub-electrode 422. The second dielectric layer 432 covers the inner walls of the first trench T1 and the second lateral groove V2, and the second sub-electrode 422 fills the first trench T1 and the second lateral groove V2.

[0137] In some embodiments, the second sub-electrode 422 may include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 may be a conductive material with good adhesion to other film layers, such as TiN, and the fourth sub-layer 34 may be a conductive material with low resistivity, such as tungsten. FIG. 7A , FIG. 7B , FIG. 7C and FIG. 7D As shown. Among them, FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D These are cross-sectional views along the AA', BB', CC', and DD' directions respectively, provided in some embodiments after the formation of the second dielectric layer 432 and the second sub-electrode 422.

[0138] In some embodiments, the second dielectric film may be a high-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent description of the first dielectric film is similar to that of the second dielectric film and will not be repeated.

[0139] 7) Forming a protective structure for the second sub-electrode 422;

[0140] The second sub-electrode 422 at the top of the first trench T1 is removed by wet etching; the distance between the surface of the second sub-electrode 422 away from the substrate 1 and the substrate 1 is less than the distance between the surface of the second dummy layer 92 away from the substrate 1 and the substrate 1.

[0141] A fourth insulating film is deposited and smoothed to form a fourth insulating layer 14 covering the side of the second sub-electrode 422 facing away from the substrate 1. The fourth insulating layer 14 is flush with the third dummy layer 93 and serves as a protective structure for the top of the second sub-electrode 422. FIG. 8 As shown. Among them, FIG. 8 A cross-sectional view along the CC' direction after the protective structure for forming the second sub-electrode 422 is provided for some embodiments.

[0142] 8) Etch to remove the sacrificial layer 10;

[0143] Wet etching removes the third dummy layer 93;

[0144] The third insulating layer 13 is wet-etched to expose the sacrificial layer 10;

[0145] Based on the third hole K3 and the fourth hole K4, the sacrificial layer 10 is removed by wet etching to form channel B1, providing space for the subsequent fabrication of semiconductor layer 23 and word line 40; as FIG. 9A , FIG. 9B , FIG. 9C and FIG. 9D As shown. Among them, FIG. 9A , FIG. 9B , FIG. 9C , FIG. 9D These are cross-sectional views along the AA', BB', CC', and DD' directions after etching away the sacrificial layer 10, as provided in some embodiments.

[0146] 9) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0147] A semiconductor thin film, a gate insulating thin film, and a fourth conductive thin film are sequentially deposited to form a semiconductor layer 23, a gate insulating layer 24, and a word line 40. The fourth conductive thin film fills the space between adjacent first insulating layers 11, but does not completely fill the third hole K3 and the fourth hole K4, facilitating subsequent etching of the semiconductor layer 23 and the word line 40 through the third hole K3 and the fourth hole K4. FIG. 10A , FIG. 10B , FIG. 10C and FIG. 10D As shown. Among them, FIG. 10A , FIG. 10B , FIG. 10C , FIG. 10D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40, respectively, according to some embodiments.

[0148] In some embodiments, the material of the semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0149] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0150] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0151] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0152] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0153] In some embodiments, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0154] 10) Disconnect multiple semiconductor layers 23 on the same layer, and disconnect multiple word lines 40;

[0155] The semiconductor film, gate insulating film, and fourth conductive film in the third hole K3 and the fourth hole K4 are removed by etching. Furthermore, the gate insulating film and semiconductor film are etched along a direction parallel to the substrate 1 based on the third hole K3 and the fourth hole K4, thereby disconnecting different word lines 40, disconnecting multiple semiconductor layers 23 in the same layer and column, and disconnecting multiple gate insulating layers 24 in the same layer and column. At this time, the etched areas of the semiconductor film and gate insulating film around the third hole K3 form a first isolation hole K3', and the etched areas of the semiconductor film and gate insulating film around the fourth hole K4 form a second isolation hole K4'; as... FIG. 11A , FIG. 11B , FIG. 11C and FIG. 11D As shown. Among them, FIG. 11A , FIG. 11B , FIG. 11C , FIG. 11D These are cross-sectional views along the AA', BB', CC', and DD' directions after disconnecting multiple semiconductor layers 23 and multiple word lines 40, as provided in some embodiments.

[0156] 11) Expose the second initial hole K2;

[0157] A fifth insulating film is deposited to form a fifth insulating layer 15, which fills the first isolation hole K3' and the second isolation hole K4'.

[0158] The fifth insulating layer 15 is ground flat to expose the surface of the second dummy layer 92 on the side opposite to the substrate 1.

[0159] The second dummy layer 92 and the first dummy layer 91 are etched away to expose the second initial hole K2;

[0160] Based on the second initial hole K2, the first insulating layer 11 is laterally etched to form a third lateral groove V3, thereby exposing the surface of the first capacitor electrode 41 facing the substrate 1 and the surface facing away from the substrate 1. That is, the surfaces of the first capacitor electrode 41 parallel to the substrate 1 are exposed, thereby increasing the area between the electrodes of the capacitor. FIG. 12A , FIG. 12B , FIG. 12C and FIG. 12D As shown. Among them, FIG. 12A , FIG. 12B , FIG. 12C , FIG. 12D These are cross-sectional views along the AA', BB', CC', and DD' directions after exposing the second initial hole K2, as provided in some embodiments.

[0161] 12) Form the first dielectric layer 431 and the first sub-electrode 421;

[0162] A first dielectric film and a fifth conductive film are deposited sequentially to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the second initial hole K2, the inner wall of the first capacitor electrode 41, and the inner wall of the third lateral groove V3; the first sub-electrode 421 fills the second initial hole K2, the first lateral groove V1, and the third lateral groove V3; as shown FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D FIG. 1A As shown.

[0163] In some embodiments, the first sub-electrode 421 may include a fifth sub-layer 35 and a sixth sub-layer 36. The fifth sub-layer 35 may be, for example, TiN, and the sixth sub-layer 36 may be, for example, tungsten. The fifth sub-layer 35 is distributed on the bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall of the first capacitor electrode 41 facing the substrate 1 and on the outer sidewall facing away from the substrate 1. The sixth sub-layer 36 fills the second initial hole K2, the first lateral groove V1, and the third lateral groove V3.

[0164] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0165] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed along a second direction parallel to the substrate; a plurality of bit lines extending along the direction perpendicular to the substrate through the memory cells of different layers; a plurality of memory cells in the same column and layer are connected to a plurality of bit lines spaced along the second direction; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction, the word lines extending along the second direction; the first direction and the second direction are both parallel to the substrate, intersecting each other and not perpendicular; the memory cells comprise transistors, the transistors comprise a semiconductor layer connected to the bit lines, the semiconductor layer surrounds the word lines, the semiconductor layers of the memory cells in the same column are spaced along the second direction and surround the same word line.

2. The semiconductor device according to claim 1, wherein Every two adjacent memory cells along the first direction are connected to the same bit line; a first isolation hole penetrating the memory cells of multiple layers is arranged between adjacent bit lines along the second direction and between adjacent word lines along the first direction, the first isolation hole is filled with a first isolation layer of an integral structure, the first isolation hole exposes the side surfaces of the adjacent word lines and the side surfaces of the adjacent bit lines.

3. The semiconductor device of claim 2, wherein, The memory cells further comprise a capacitor connected to the semiconductor layer, the capacitor is arranged on the side of the semiconductor layer away from the bit line, the capacitor and the word line are distributed along the first direction, and a plurality of capacitors connected to the memory cells in the same column are distributed along the second direction.

4. The semiconductor device according to claim 3, wherein The capacitor comprises a first capacitor electrode connected to the semiconductor layer and a second capacitor electrode comprising a first sub-electrode, the semiconductor device further comprises a capacitor hole penetrating the memory cells of multiple layers, a plurality of first capacitor electrodes of the memory cells in the same position of different layers are arranged on the sidewall of the capacitor hole and spaced along the direction perpendicular to the substrate, the first sub-electrode fills the capacitor hole, and the plurality of first capacitor electrodes surround the first sub-electrode through a first dielectric layer; a second isolation hole penetrating the memory cells of multiple layers is arranged between adjacent capacitor holes along the second direction, the second isolation hole is filled with a second isolation layer of an integral structure, the second isolation hole exposes the first capacitor electrodes in the adjacent capacitor holes and the side surfaces of the word lines adjacent to the capacitor holes.

5. The semiconductor device of claim 4, wherein, The contact surface of the semiconductor layer and the first capacitor electrode and the contact surface of the semiconductor layer and the bit line are misaligned in the first direction.

6. The semiconductor device of claim 2, wherein The first isolation hole extends along the second direction, and a plurality of first isolation holes distributed between a column of bit lines are misaligned in the first direction in sequence.

7. The semiconductor device of claim 4, wherein The second isolation hole extends along the second direction, and a plurality of second isolation holes distributed between a column of capacitor holes are misaligned in the first direction in sequence.

8. The semiconductor device of claim 4, wherein, The first capacitor electrode comprises a first part extending along the direction perpendicular to the substrate and a second part extending from both ends of the first part towards the first sub-electrode respectively; the first part is connected to the semiconductor layer and the two second isolation layers adjacent to the capacitor hole.

9. The semiconductor device of claim 8, wherein, The second capacitor electrode further comprises a second sub-electrode, the second sub-electrode partially surrounds a first portion of the first capacitor electrode through a second dielectric layer.

10. The semiconductor device of claim 4, wherein The transistor further comprises a gate insulating layer disposed between the semiconductor layer and the word line and surrounding the word line; the gate insulating layers of the plurality of transistors in the same layer and the same column are disconnected at the contact area of the first isolation layer and the word line surrounded by the plurality of gate insulating layers, and at the contact area of the second isolation layer and the word line surrounded by the plurality of gate insulating layers.

11. The semiconductor device of claim 10, wherein, The first isolation hole further exposes the side surface of the adjacent gate insulating layer, and exposes the end surface of the adjacent semiconductor layer.

12. The semiconductor device of claim 10, wherein, The second isolation hole further exposes the side surface of the adjacent gate insulating layer, and exposes the end surface of the adjacent semiconductor layer.

13. A method of manufacturing a semiconductor device, characterized by Comprising: forming a stack structure comprising a plurality of first insulating layers and sacrificial layers arranged alternately on a substrate; forming a plurality of bit line holes penetrating the stack structure along a direction perpendicular to the substrate and spaced along a second direction; forming a bit line extending along a direction perpendicular to the substrate direction within the bit line hole and filling the bit line hole; forming a plurality of capacitor holes penetrating the stack structure along a direction perpendicular to the substrate and spaced along a second direction, and the bit line hole and the capacitor hole are spaced along a first direction, based on etching the sacrificial layer along a direction parallel to the substrate, a first lateral groove is formed; forming a first capacitor electrode distributed on the inner wall of the first lateral groove; the first direction and the second direction intersect and are not perpendicular; forming a first isolation hole penetrating the stack structure between the bit line holes adjacent along the second direction, the first isolation hole exposes the side surface of the adjacent bit line; and forming a second isolation hole penetrating the stack structure between the capacitor holes adjacent along the second direction, the second isolation hole exposes the adjacent first capacitor electrode; the first isolation hole and the second isolation hole are spaced along the first direction; etching and removing the sacrificial layer distributed between the first isolation hole and the second isolation hole, forming a channel extending along the second direction between a column of first isolation holes distributed along the second direction and between the second isolation holes distributed along the second direction between the adjacent insulating layers; forming a word line extending along the second direction in the channel, a plurality of semiconductor layers surrounding the word line and spaced along the second direction.

14. The method of manufacturing a semiconductor device according to Claim 13, wherein The forming a word line extending along the second direction in the channel, a plurality of semiconductor layers surrounding the word line and spaced along the second direction comprises: sequentially depositing a semiconductor thin film, a gate insulating thin film and a conductive thin film, the semiconductor thin film and the gate insulating thin film sequentially cover the inner wall of the first isolation hole, the second isolation hole and the channel, the conductive thin film fills the channel and does not completely fill the first isolation hole and the second isolation hole; The semiconductor thin film, the gate insulating thin film, and the conductive thin film in the first isolation hole and the second isolation hole are etched, and the semiconductor thin film is etched along a direction parallel to the substrate based on the first isolation hole and the second isolation hole, so that the semiconductor thin film forms a plurality of semiconductor layers spaced apart along a second direction, the conductive thin film forms a word line extending along a second direction, and the gate insulating thin film forms a gate insulating layer.

15. The method of manufacturing a semiconductor device according to Claim 13, wherein The method further includes sequentially forming a first dielectric layer covering inner walls of capacitor holes in which the first capacitor electrode is formed and a first sub-electrode filling the capacitor holes.

16. The method of manufacturing a semiconductor device according to Claim 13, wherein The method further includes, A trench is formed through the stack structure between two adjacent rows of capacitor holes on a side of the capacitor holes facing away from the second isolation hole, and the trench exposes the sacrificial layer of each layer; Based on the trench, the sacrificial layer between the trench and the second isolation hole is etched to form a second lateral recess, and the trench and the second lateral recess expose a surface of the first capacitor electrode on a side of the second isolation hole facing away from the bit line; A second dielectric layer covering inner walls of the trench and the second lateral recess and a second sub-electrode filling the trench and the second lateral recess are sequentially formed in the trench and the second lateral recess.

17. An electronic device, comprising: The semiconductor device includes the semiconductor device as claimed in any one of claims 1 to 12, or the semiconductor device formed by the manufacturing method of the semiconductor device as claimed in any one of claims 13 to 16.

Images