Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are provided, the method including providing a substrate, an array region of the substrate having a central region and a boundary region surrounding the central region, and the substrate including a first active region and a second active region separated by an isolation structure. The method includes sequentially forming a bit line contact and a bit line structure over a first active region of a substrate, conformally forming a dielectric liner on the substrate to cover sidewalls of the bit line contact and the bit line structure and a top surface of the bit line structure, and performing an etching process on the substrate to form a trench and expose a second active region. The method also includes performing an ion implantation process on the trench in the boundary region of the substrate to form an insulating layer at a bottom of the trench and covering the second active region, and forming a capacitive contact structure over the second active region. According to the memory device and the manufacturing method thereof provided by the invention, the capacitor contact formed on the memory device can be ensured to be electrically isolated from the second active region.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor technology, and more particularly, to a method of fabricating a memory device and a memory device. BACKGROUND

[0002] In current memory device fabrication processes, as device dimensions continue to shrink, process margins also continue to shrink. For example, after formation of a buried word line and bit line structure, a subsequent formation of a capacitor contact structure can cause active regions in a dummy region to short through the capacitor contact structure to a subsequently formed conductive layer due to process variations, which can result in leakage current and reduced memory device reliability. Therefore, there is a need in the industry to improve the method of fabricating a memory device to maintain memory device yield. SUMMARY

[0003] A method of fabricating a memory device is provided, including: providing a substrate, wherein the substrate has an array region and a peripheral region surrounding the array region, and wherein the substrate includes a first active region and a second active region separated by an isolation structure; sequentially forming a bit line contact and a bit line structure over the first active region of the substrate; conformally forming a dielectric liner on the substrate to cover sidewalls of the bit line contact and the bit line structure and a top surface of the bit line structure; performing an etch process on the substrate to form a trench and expose the second active region; performing an ion implantation process on the trench in the peripheral region of the substrate to form an insulating layer at a bottom of the trench and cover the second active region; and forming a capacitor contact structure over the second active region.

[0004] A memory device is provided, including: a substrate, wherein the substrate has an array region and a peripheral region surrounding the array region, and wherein the substrate includes a first active region and a second active region separated by an isolation structure; a bit line structure over the first active region of the substrate; a trench over the second active region of the substrate; an insulating layer at a bottom of the trench and covering the second active region; and a capacitor contact structure over the second active region and filling in the trench. BRIEF DESCRIPTION OF DRAWINGS

[0005] Embodiments of the present application will be best understood by reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that various features are not drawn to scale and are only intended to illustrate the features. In fact, the dimensions of the various features can be arbitrarily increased or decreased, to clearly show the features of the embodiments of the present application.

[0006] Figure 1 is a top view schematic diagram of a substrate of a memory device according to embodiments of the present application.

[0007] Figures 2 to 5is a cross-sectional schematic view illustrating an intermediate stage of fabricating a memory device according to an embodiment of the present invention.

[0008] BRIEF DESCRIPTION OF DRAWINGS

[0009] 10: memory device

[0010] 100: substrate

[0011] 101: center region

[0012] 102: border region

[0013] 103: peripheral region

[0014] 105A: first active region

[0015] 105B: second active region

[0016] 107: isolation structure

[0017] 130: bit line contact

[0018] 140: bit line structure

[0019] 1401: conductive layer

[0020] 1403: conductive layer

[0021] 1405: conductive layer

[0022] 1407: dielectric layer

[0023] 1409: cap layer

[0024] 150: spacer structure

[0025] 1501: spacer material layer

[0026] 1503: spacer material layer

[0027] 1505: spacer material layer

[0028] 1507: spacer material layer

[0029] 160: etch process

[0030] 170: trench

[0031] 180: ion implantation process

[0032] 190: insulating layer

[0033] 200: capacitor contact structure

[0034] A-A: cross-section

[0035] X: direction

[0036] Y: direction

[0037] Z: direction DETAILED DESCRIPTION

[0038] Figure 1 is a top view schematic diagram (e.g., a plan view in the direction X-direction Y) of a substrate 100 of a memory device 10 according to an embodiment of the present application. Figures 2 to 5 is a cross-sectional view schematic diagram (e.g., a plan view in the direction X-direction Z) of the memory device 10 during a formation process according to an embodiment of the present application. In this embodiment, Figures 2 to 5 corresponds to Figure 1 the cross-section A-A.

[0039] First, referring to Figure 1 , a substrate 100 is provided, which has an array region and a peripheral region 103 surrounding the array region. The array region further includes a central region 101 and a border region 102 surrounding the central region 101. Generally, the border region 102 is a dummy region. In one embodiment, the substrate 100 can be an elemental semiconductor substrate, such as a silicon substrate, or a germanium substrate; a compound semiconductor substrate, such as a silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP) substrate; or an alloy semiconductor substrate, such as SiGe, SiGeC, GaAsP, or GaInP. In other embodiments, the substrate 100 can be a semiconductor-on-insulator substrate. The semiconductor-on-insulator substrate can include a handle substrate, a buried oxide layer disposed on the handle substrate, and a semiconductor layer disposed on the buried oxide layer.

[0040] The substrate 100 has a first active region 105A and a second active region 105B, and the first active region 105A and the second active region 105B are separated from each other by an isolation structure 107. In one embodiment, the substrate 100 has a buried word line structure (not shown), which can serve as a gate of the memory device 10, and can include a gate liner and a gate electrode. The gate liner is formed of tungsten nitride, titanium nitride, or tantalum nitride. The gate electrode is formed of a conductive material, such as doped polysilicon, metal, or metal nitride. In one embodiment, the substrate 100 has a protective layer (not shown) formed on the buried word line structure, which serves as a dielectric layer to control a channel of the memory device 10.

[0041] Referring to Figure 2The bit line structure 140 is formed on the substrate 100, and the bit line contact 130 can be formed to extend into the substrate 100. The bit line contact 130 is in direct contact with a corresponding active region (e.g., the first active region 105A located underneath the bit line contact 130). In one embodiment, the bit line structure 140 can include, from bottom to top, a conductive layer 1401, a conductive layer 1403, a conductive layer 1405, a dielectric layer 1407, and a cap layer 1409. The dielectric layer 1407 and the cap layer 1409 can protect the underlying film layers (such as the conductive layer 1401, the conductive layer 1403, or the conductive layer 1405) from damage during subsequent processes. In one embodiment, when the aforementioned stack structure is formed, the bit line contact 130 and the substrate 100 on both sides of the bit line contact 130 are also partially removed to form recesses on both sides of the bit line contact 130. The aforementioned recesses expose part of the active region (e.g., the first active region 105A) and part of the isolation structure 107. Subsequently, a spacer structure 150 is formed on the sidewalls of the bit line structure 140 and in the recesses. The spacer structure 150 includes a combination of different dielectric materials. In one embodiment, a spacer material layer 1501 can be conformally formed on the sidewalls of the bit line structure 140 and in the recesses, followed by forming a spacer material layer 1503 to fill the remaining recesses, and sequentially forming spacer material layers 1505 and 1507 over the sidewalls of the bit line structure 140, thereby isolating the bit line contact 130 and the bit line structure 140 from a subsequently formed capacitor contact structure 200.

[0042] In one embodiment, the conductor material (the bit line contact 130) can include doped polysilicon, metal, or metal nitride.

[0043] In one embodiment, the conductive layer 1401, the conductive layer 1403, and the conductive layer 1405 can include doped polysilicon, metal, or metal nitride, such as tungsten (W), titanium (Ti), and titanium nitride (TiN). In one embodiment, the conductive layer 1405 on top has a lower resistance than the conductive layer 1401. In one embodiment, the dielectric layer 1407 and the cap layer 1409 can include silicon oxide, silicon nitride, or a combination thereof.

[0044] In one embodiment, the material of the spacer structure 150 (e.g., the spacer material layers 1501, 1503, 1505, and 1507) can include nitride material, oxide material, or a combination thereof. In one embodiment, the spacer structure 150 can be formed by a deposition process and an etching process. The deposition process can include a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. The etching process can include a non-isotropic etching process (or a directional etching process), such as a reactive ion etching process, a plasma etching, an inductively coupled plasma etching, or a dry etching process of a combination thereof.

[0045] Next, referring to FIG. 1C, a capacitor contact structure 200 is formed on the substrate 100. The capacitor contact structure 200 can include a conductive layer 2001, a dielectric layer 2003, and a conductive layer 2005. The capacitor contact structure 200 is in direct contact with the spacer structure 150. In one embodiment, the capacitor contact structure 200 can be formed by a deposition process and an etching process. The deposition process can include a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. The etching process can include a non-isotropic etching process (or a directional etching process), such as a reactive ion etching process, a plasma etching, an inductively coupled plasma etching, or a dry etching process of a combination thereof. Figure 3An etching process 160 is performed on the substrate 100 to form trenches 170 and expose the second active region 105B. In one embodiment, the etching process 160 may include anisotropic etching processes (or directional etching processes), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or a combination of the above dry etching processes.

[0046] Next, please see Figure 4 An ion implantation process 180 is performed on the trench 170 located in the boundary region 102 of the array region of the substrate 100 to form an insulating layer 190 at the bottom of the trench 170 and covering the second active region 105B. More specifically, in one embodiment, the step of performing the ion implantation process 180 further includes forming a patterned mask (not shown) to cover the central region 101 and the peripheral region 103 of the substrate 100. Figure 1 The boundary region 102 of the exposed substrate 100 is then subjected to an ion implantation process 180, and the aforementioned patterned mask is removed. In one embodiment, the element used in the ion implantation process 180 includes Xe, Kr, Fe, Ar, or N. In this embodiment of the invention, by performing an additional ion implantation process 180 and implanting selected element ions into the second active region 105B of the boundary region 102, an insulating layer 190 with insulating properties can be formed on the surface of the second active region 105B of the boundary region 102.

[0047] Next, please see Figure 5 A capacitor contact structure 200 is formed on the second active region 105B. As shown, the second active region 105B located in the boundary region 102 is electrically isolated from the capacitor contact structure 200 by an insulating layer 190. In one embodiment, the capacitor contact structure 200 may include, from bottom to top, a conductive layer, a silicide layer, and another conductive layer. In one embodiment, the material of the conductive layer may include doped polysilicon, a metal, or a metal nitride. In one embodiment, the material of the silicide layer may include a metal silicide, such as tungsten silicide (CoW) or cobalt silicide (CoSi).

[0048] In summary, embodiments of the present invention employ an additional ion implantation process to implant selected elemental ions into the second active region of the boundary region, thereby forming an insulating layer on the surface of the second active region. This ensures that the capacitor contacts formed thereon are electrically isolated from the second active region. Therefore, even if subsequent processes deviate and leakage paths occur in the capacitor contacts of the boundary region, the present invention can prevent leakage current from occurring through the insulating layer formed on the surface of the second active region of the boundary region, further maintaining the electrical performance of the memory device.

[0049] The above-described features of the embodiments are presented as a summary so that those skilled in the art can better understand the inventive concept of the embodiments. Those skilled in the art will readily understand that other processes and structures can be readily devised or modified to achieve the same objectives and / or advantages as those described herein, based on the embodiments of the present application. It should also be understood that such equivalent constructions are intended to fall within the spirit and scope of the present application, and that various changes, substitutions, and alterations can be made to the embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the present application is defined by the following claims.

Claims

1. A method of manufacturing a memory device, characterized by, comprising: providing a substrate, wherein an array region of the substrate has a center region and a border region surrounding the center region, and wherein the substrate includes a first active region and a second active region separated by an isolation structure; sequentially forming a bit line contact and a bit line structure over the first active region of the substrate; conformally forming a dielectric liner on the substrate to cover sidewalls of the bit line contact and the bit line structure and a top surface of the bit line structure; performing an etching process on the substrate to form a trench and expose the second active region; performing an ion implantation process on the trench located in the border region of the substrate to form an insulating layer at a bottom of the trench and covering the second active region; and forming a capacitor contact structure over the second active region. The ion implantation process uses an element including Xe, Kr, Fe, Ar, or N.

2. The method of manufacturing a memory device according to claim 1, wherein, The second active region located in the border region is electrically isolated from the capacitor contact structure by the insulating layer.

3. The method of manufacturing a memory device according to Claim 1, wherein, The insulating layer is formed at the bottom of the trench and buried in the substrate.

4. The method of fabricating a memory device of claim 1, wherein, A bottommost surface of the insulating layer is higher than a level of a top surface of the first active region.

5. The method of fabricating a memory device of claim 1, wherein, The step of performing the ion implantation process further includes:

6. The method of fabricating a memory device of claim 1, wherein, forming a patterned mask to cover the center region of the array region of the substrate and expose the border region of the array region of the substrate; performing the ion implantation process; and removing the patterned mask. comprising:

7. A memory device, comprising: a substrate, wherein an array region of the substrate has a center region and a border region surrounding the center region, and wherein the substrate includes a first active region and a second active region separated by an isolation structure; a bit line structure over the first active region of the substrate; a trench over the second active region of the substrate; an insulating layer at a bottom of the trench and covering the second active region; and a capacitor contact structure over the second active region and filled in the trench. The insulating layer has an element implanted therein including Xe, Kr, Fe, Ar, or N. The second active region located in the border region is electrically isolated from the capacitor contact structure by the insulating layer.

8. The memory device of claim 7, wherein, A bottommost surface of the insulating layer is higher than a level of a top surface of the first active region.

9. The memory device of claim 7, wherein, The insulating layer is formed at the bottom of the trench and buried in the substrate.

10. The memory device of claim 7, wherein, The insulating layer is formed at the bottom of the trench and buried in the substrate.

11. The memory device of claim 7, wherein, ​

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