Semiconductor memory device

Abstract

According to one embodiment of the invention, a semiconductor memory device is provided, and the manufacturing cost can be reduced. According to one embodiment, a semiconductor memory device includes: a stacked body in which a plurality of wiring layers (34) and a plurality of insulating layers (35) are alternately stacked layer by layer; a memory pillar that passes through the stacked body; and a first member that blocks the stacked body. The plurality of insulating layers includes a first insulating layer. The plurality of wiring layers includes a first wiring layer and a second wiring layer provided on the first insulating layer. The memory pillar includes a first sub-pillar that passes through the first wiring layer and has an upper end positioned between the first wiring layer and the second wiring layer, and a second sub-pillar that is provided on the first sub-pillar and passes through the second wiring layer. The first member includes a first portion passing through the first wiring layer and the second wiring layer and having an upper end positioned above the second wiring layer, and a second portion provided above the first portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0002] As a semiconductor storage device, three-dimensional stacked NAND flash memory is known. Summary of the Invention

[0003] In one embodiment of the present invention, a semiconductor memory device is provided that can reduce manufacturing costs.

[0004] The semiconductor memory device of the embodiment includes: a stacked body formed by alternately stacking a plurality of wiring layers and a plurality of insulating layers in a first direction; a memory pillar extending along the first direction and passing through the stacked body; and a first component extending along the first direction and a second direction intersecting the first direction, and the stacked body being truncated in a third direction intersecting the first and second directions. The plurality of insulating layers includes a first insulating layer. The plurality of wiring layers include: a first wiring layer on which the first insulating layer is disposed; and a second wiring layer disposed on the first insulating layer. The memory pillar includes: a first sub-pillar extending along the first direction and passing through the first wiring layer, with its upper end located between the first wiring layer and the second wiring layer; and a second sub-pillar disposed on the first sub-pillar, extending along the first direction and passing through the second wiring layer. The first component includes: a first portion extending along a first direction and a second direction respectively, and passing through a first wiring layer and a second wiring layer, with its upper end located above the second wiring layer; and a second portion disposed above the first portion and extending within the laminate along the first direction and the second direction respectively. Attached Figure Description

[0005] Figure 1 This is a block diagram showing the overall configuration of the semiconductor memory device according to the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the memory cell array included in the semiconductor memory device of the first embodiment.

[0007] Figure 3 This is a top view showing an example of the memory cell array included in the semiconductor memory device of the first embodiment.

[0008] Figure 4 This is a top view showing an example of the planar layout of the connection area of ​​the memory cell array included in the semiconductor memory device of the first embodiment.

[0009] Figure 5 It is along Figure 4 A cross-sectional view of the storage cell area along lines A1-A2.

[0010] Figure 6It is along Figure 5 A cross-sectional view of the memory cylinders along the C1-C2 lines in the XY plane.

[0011] Figure 7 It is along Figure 4 A sectional view of the area connecting lines B1-B2.

[0012] Figure 8 This is a conceptual diagram showing the junction of the memory pillar, component SLT, and support pillar in the semiconductor memory device of the first embodiment and the comparative example.

[0013] Figure 9 This is a flowchart illustrating an example of the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0014] Figure 10 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0015] Figure 11 It is along Figure 10 A sectional view of lines A1-A2 and B1-B2.

[0016] Figure 12 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0017] Figure 13 It is along Figure 12 A sectional view of lines A1-A2 and B1-B2.

[0018] Figure 14 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0019] Figure 15 It is along Figure 14 A sectional view of lines A1-A2 and B1-B2.

[0020] Figure 16 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0021] Figure 17 It is along Figure 16 A sectional view of lines A1-A2 and B1-B2.

[0022] Figure 18This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0023] Figure 19 It is along Figure 18 A sectional view of lines A1-A2 and B1-B2.

[0024] Figure 20 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0025] Figure 21 It is along Figure 20 A sectional view of lines A1-A2 and B1-B2.

[0026] Figure 22 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0027] Figure 23 It is along Figure 22 A sectional view of lines A1-A2 and B1-B2.

[0028] Figure 24 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0029] Figure 25 It is along Figure 24 A sectional view of lines A1-A2 and B1-B2.

[0030] Figure 26 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0031] Figure 27 It is along Figure 26 A sectional view of lines A1-A2 and B1-B2.

[0032] Figure 28 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0033] Figure 29 It is along Figure 28 A sectional view of lines A1-A2 and B1-B2.

[0034] Figure 30This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0035] Figure 31 It is along Figure 30 A sectional view of lines A1-A2 and B1-B2.

[0036] Figure 32 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0037] Figure 33 It is along Figure 32 A sectional view of lines A1-A2 and B1-B2.

[0038] Figure 34 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0039] Figure 35 It is along Figure 34 A sectional view of lines A1-A2 and B1-B2.

[0040] Figure 36 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the first embodiment.

[0041] Figure 37 It is along Figure 36 A sectional view of lines A1-A2 and B1-B2.

[0042] Figure 38 This is a cross-sectional view showing an example of the cross-sectional configuration of the memory cell region in the memory cell array of the semiconductor memory device of the second embodiment.

[0043] Figure 39 This is a cross-sectional view showing an example of the cross-sectional configuration of the connection region in the memory cell array of the semiconductor memory device of the second embodiment.

[0044] Figure 40 This is a conceptual diagram showing the intersection of the memory pillar, component SLT, and support pillar in the semiconductor memory device of the second embodiment and the comparative example.

[0045] Figure 41 This is a flowchart illustrating an example of the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0046] Figure 42This is a flowchart illustrating an example of the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0047] Figure 43 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0048] Figure 44 It is along Figure 43 A sectional view of lines A1-A2 and B1-B2.

[0049] Figure 45 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0050] Figure 46 It is along Figure 45 A sectional view of lines A1-A2 and B1-B2.

[0051] Figure 47 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0052] Figure 48 It is along Figure 47 A sectional view of lines A1-A2 and B1-B2.

[0053] Figure 49 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0054] Figure 50 It is along Figure 49 A sectional view of lines A1-A2 and B1-B2.

[0055] Figure 51 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0056] Figure 52 It is along Figure 51 A sectional view of lines A1-A2 and B1-B2.

[0057] Figure 53 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0058] Figure 54 It is along Figure 53 A sectional view of lines A1-A2 and B1-B2.

[0059] Figure 55 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0060] Figure 56 It is along Figure 55 A sectional view of lines A1-A2 and B1-B2.

[0061] Figure 57 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0062] Figure 58 It is along Figure 57 A sectional view of lines A1-A2 and B1-B2.

[0063] Figure 59 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0064] Figure 60 It is along Figure 59 A sectional view of lines A1-A2 and B1-B2.

[0065] Figure 61 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0066] Figure 62 It is along Figure 61 A sectional view of lines A1-A2 and B1-B2.

[0067] Figure 63 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0068] Figure 64 It is along Figure 63 A sectional view of lines A1-A2 and B1-B2.

[0069] Figure 65 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0070] Figure 66 It is along Figure 65A sectional view of lines A1-A2 and B1-B2.

[0071] Figure 67 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0072] Figure 68 It is along Figure 67 A sectional view of lines A1-A2 and B1-B2.

[0073] Figure 69 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0074] Figure 70 It is along Figure 69 A sectional view of lines A1-A2 and B1-B2.

[0075] Figure 71 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0076] Figure 72 It is along Figure 71 A sectional view of lines A1-A2 and B1-B2.

[0077] Figure 73 This is a diagram illustrating an example of the planar layout of the memory cell array during the manufacturing process of the memory cell array included in the semiconductor memory device of the second embodiment.

[0078] Figure 74 It is along Figure 73 A sectional view of lines A1-A2 and B1-B2.

[0079] Figure 75 This is a top view showing an example of the planar layout of the connection area of ​​the memory cell array included in the semiconductor memory device of the third embodiment.

[0080] Figure 76 It is along Figure 75 A sectional view of the area connecting lines B1-B2.

[0081] Figure 77 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the third embodiment.

[0082] Figure 78This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the third embodiment.

[0083] Figure 79 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the third embodiment.

[0084] Figure 80 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the third embodiment.

[0085] Figure 81 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the third embodiment.

[0086] Figure 82 This is a diagram showing an example of the cross-sectional configuration of the memory cell region of the memory cell array included in the first variation of the third embodiment of the semiconductor memory device.

[0087] Figure 83 This is a diagram showing an example of the cross-sectional configuration of the connection region of the memory cell array in the first variation of the third embodiment of the semiconductor memory device.

[0088] Figure 84 This is a diagram illustrating an example of the cross-sectional configuration of the memory cell region of the memory cell array included in the second variation of the third embodiment of the semiconductor memory device.

[0089] Figure 85 This is a diagram showing an example of the cross-sectional configuration of the connection region of the memory cell array in the second variation of the third embodiment of the semiconductor memory device.

[0090] Figure 86 This is a top view showing an example of the planar layout of the connection area of ​​the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0091] Figure 87 It is along Figure 86 A sectional view of the area connecting lines B1-B2.

[0092] Figure 88 This is a conceptual diagram showing the junction of the support pillar and the contact plug in the semiconductor memory device of the fourth embodiment and the comparative example.

[0093] Figure 89 This is a flowchart illustrating an example of the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0094] Figure 90 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0095] Figure 91 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0096] Figure 92 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0097] Figure 93 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0098] Figure 94 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0099] Figure 95 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0100] Figure 96 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0101] Figure 97 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0102] Figure 98 This is a diagram illustrating an example of the cross-sectional configuration of the connection region in the manufacturing process of the memory cell array included in the semiconductor memory device of the fourth embodiment.

[0103] Figure 99 This is a cross-sectional view of the memory cell array of a modified semiconductor memory device. Detailed Implementation

[0104] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and structure will be marked with common reference symbols. Additionally, when multiple constituent elements sharing a common reference symbol are distinguished, an additional mark will be added to the common reference symbol for differentiation. Furthermore, when it is not necessary to specifically distinguish multiple constituent elements, only the common reference symbol will be used to mark the multiple constituent elements, without adding an additional mark. Here, the additional mark is not limited to subscripts or superscripts, but also includes, for example, lowercase letters added to the end of the reference symbol, and indices indicating sequences.

[0105] 1. First Implementation Method

[0106] First, the semiconductor memory device of the first embodiment will be described. Hereinafter, as a semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate will be described as an example.

[0107] 1.1 Composition

[0108] 1.1.1 Overall Structure of Semiconductor Memory Devices

[0109] First, refer to Figure 1 An example of the overall configuration of semiconductor memory device 1 will be described. Figure 1 This is a block diagram showing the overall configuration of semiconductor memory device 1. Furthermore, in Figure 1 The arrows in the diagram indicate partial connections between the constituent elements, but the connections between the constituent elements are not limited to these.

[0110] like Figure 1 As shown, the semiconductor memory device 1 includes a memory core 10 and a peripheral circuit 20.

[0111] The memory core 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.

[0112] The memory cell array 11 is a region in three dimensions in which non-volatile memory cell transistors (hereinafter also referred to as "memory cells") are arranged. The memory cell array 11 contains multiple blocks (BLKs). Figure 1 In the example shown, the memory cell array 11 includes blocks BLK0 to BLK3. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased together. A block BLK contains multiple memory cell transistors that correspond to rows and columns. Each block BLK contains one or more string components SU. Figure 1In the example shown, block BLK contains six string components SU0, SU1, SU2, SU3, SU4, and SU5. A string component SU may be a set of multiple NAND strings NS selected together during a write or read operation. A NAND string NS contains a set of multiple memory cell transistors connected in series. Furthermore, the number of blocks BLK within memory cell array 11 and the number of string components SU within a block BLK are arbitrary. The details of memory cell array 11 will be described below.

[0113] The row decoder 12 is a circuit that decodes the row address. The row decoder 12 receives row address-related information from an external controller (not shown). Based on the decoding result of the row address-related information, the row decoder 12 selects the row-direction wiring (word lines and select gate lines) of the memory cell array 11. The row decoder 12 supplies voltage to the selected row-direction wiring.

[0114] The sense amplifier 13 is a circuit that performs data writing and reading. When reading data, the sense amplifier 13 reads data from any string component SU of any block BLK. In addition, when writing data, the sense amplifier 13 supplies a voltage based on the data being written to the memory cell array 11.

[0115] The peripheral circuit section 20 includes a sequencer 21 and a voltage generation circuit 22.

[0116] The sequencer 21 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generation circuit 22, the line decoder 12, and the sense amplifier 13 during write, read, and erase operations.

[0117] The voltage generation circuit 22 generates voltages for write, read, and erase operations and supplies them to the line decoder 12 and the sense amplifier 13, etc.

[0118] 1.1.2 Circuit configuration of memory cell array

[0119] Next, refer to Figure 2 An example of the circuit configuration of the memory cell array 11 will be described. Figure 2 This is a circuit diagram of memory cell array 11. Furthermore, Figure 2 The example shown illustrates the circuit configuration of a single block BLK.

[0120] like Figure 2 As shown, the string component SU contains multiple NAND strings NS.

[0121] The NAND string NS contains multiple memory cell transistors MC and select transistors ST1 and ST2. Figure 2In the example shown, the NAND string NS contains 10 memory cell transistors MC0 to MC9. Furthermore, the number of memory cell transistors MC in the NAND string NS is arbitrary.

[0122] A memory cell transistor (MC) is a non-volatile memory element that stores data. The MC includes a control gate and a charge storage film. MCs can be either MONOS (Metal-Oxide-Nitride-Oxide-Silicon) or FG (Floating Gate) type. MONOS type uses an insulating film for the charge storage film. FG type uses a conductor for the charge storage film. The following explanation focuses on the MONOS type MC.

[0123] Selector transistors ST1 and ST2 are switching elements. ST1 and ST2 are used to select the string component SU during various operations. The number of selector transistors ST1 and ST2 in the NAND string NS is arbitrary. It is sufficient that the NAND string NS contains at least one ST1 and one ST2.

[0124] The current paths of select transistor ST2, memory cell transistors MC0-MC9, and select transistor ST1 within the NAND string NS are connected in series. The drain of select transistor ST1 is connected to bit line BL. The source of select transistor ST2 is connected to source line SL.

[0125] Within the same block BLK, the control gates of memory cell transistors MC0 to MC9 are connected to word lines WL0 to WL9, respectively. More specifically, for example, block BLK contains six string components SU0 to SU5. Moreover, each string component SU contains multiple memory cell transistors MC0. The control gates of the multiple memory cell transistors MC0 within block BLK are shared by one word line WL0. The same applies to memory cell transistors MC1 to MC9.

[0126] The gates of multiple select transistors ST1 within the string assembly SU are connected to a single select gate line SGD. More specifically, the gates of multiple select transistors ST1 within the string assembly SU0 are connected to select gate line SGD0. The gates of multiple select transistors ST1 within the string assembly SU1 are connected to select gate line SGD1. The gates of multiple select transistors ST1 within the string assembly SU2 are connected to select gate line SGD2. The gates of multiple select transistors ST1 within the string assembly SU3 are connected to select gate line SGD3. The gates of multiple select transistors ST1 within the string assembly SU4 are connected to select gate line SGD4. The gates of multiple select transistors ST1 within the string assembly SU5 are connected to select gate line SGD5.

[0127] The gates of multiple select transistors ST2 within block BLK are connected to the select gate line SGS. Alternatively, similar to the select gate line SGD, a different select gate line SGS can be set for each string assembly SU.

[0128] Word lines WL0 to WL9, select gate lines SGD0 to SGD5, and select gate line SGS are respectively connected to the line decoder 12.

[0129] The bit line BL is connected to a single NAND string NS within each string component SU of each block BLK. Figure 2 In the example shown, there are m+1 bit lines (m is an integer greater than or equal to 0) BL0 to BLm. Each string component SU has m+1 NAND strings NS connected to bit lines BL0 to BLm. Multiple NAND strings NS connected to a single bit line BL are assigned the same column address. Each bit line BL is connected to the sense amplifier 13.

[0130] Source lines (SLs) can be shared, for example, across multiple block BLKs.

[0131] A collection of multiple memory cell transistors MC connected to a common word line WL within a single string component SU is, for example, described as a "cell component CU". For example, write and read operations are performed on a unit of cell component CU.

[0132] 1.1.3 Planar Layout of Storage Cell Array

[0133] Next, refer to Figure 3 An example of the planar layout of the storage cell array 11 will be described. Figure 3 This is a top view showing an example of a storage cell array 11. Figure 3 The example shown represents the region corresponding to the four blocks BLK0 to BLK3. Furthermore, in Figure 3In the example shown, a portion of the interlayer insulating film is omitted. In the following top view, shading lines have been appropriately added for easier observation. The shading lines added in the top view are not necessarily related to the material or characteristics of the elements in which they are attached.

[0134] In the following description, the direction parallel to the substrate and extending from the word line WL is defined as the X direction. The direction parallel to the substrate and intersecting the X direction is defined as the Y direction. The direction intersecting both the X and Y directions and perpendicular to the substrate is defined as the Z direction. Furthermore, the direction from the source lines SL stacked in the Z direction to the word line WL is described as "above", and the direction from the word line WL to the source lines SL is described as "below".

[0135] like Figure 3 As shown, the planar layout of the memory cell array 11 is, for example, divided in the X direction into a memory cell region MA (also referred to as a "memory region") and connection regions CA1 and CA2. The memory cell array 11 includes multiple wiring layers that function as word lines WL and select gate lines SGD and SGS, as well as multiple components SLT and SHE. The multiple wiring layers are stacked and spaced apart in the Z direction. Hereinafter, the multiple wiring layers stacked and spaced apart in the Z direction, corresponding to the word lines WL and select gate lines SGD and SGS respectively, will also be referred to as "stacked wiring".

[0136] The memory cell region MA is a region that contains multiple NAND strings NS (multiple memory cell transistors MC).

[0137] The connection area CA is used for connections between the various multilayer wirings and the line decoder 12. Within the connection area CA, each multilayer wiring is connected to its corresponding contact plug. Figure 3 In the example shown, there are 12 wiring layers. For example, the 12 wiring layers function as select gate line SGS, word lines WL0 to WL9, and select gate line SGD from the bottom layer (the side closest to the substrate) to the top layer.

[0138] exist Figure 3In the example shown, connection regions CA1 and CA2 are provided at both ends of the storage cell region MA in the X direction. Alternatively, a connection region CA can be provided between two storage cell regions MA. For example, in connection regions CA1 and CA2, a connection portion (hereinafter referred to as "plug connection portion") to a contact plug is provided in each wiring layer. In this embodiment, the two ends of each stacked wiring extending in the X direction are led out in a stepped manner. Furthermore, the stepped portion (stepped area) of the stacked wiring corresponds to the plug connection portion of each wiring layer. In this case, no other wiring layer is provided above the plug connection portion. Hereinafter, when the plug connection portion is arranged in a stepped manner and no other wiring layer is provided above it, the plug connection portion will also be described as a "step". Furthermore, the stacked wiring may not be led out in a stepped manner. That is, other wiring layers may be provided above the plug connection portion. In this case, a contact plug can be formed that is electrically connected to the target wiring layer but not electrically connected to other wiring layers.

[0139] Multiple component SLTs (also referred to as "component 1") extend along the X direction and are arranged along the Y direction. Each component SLT traverses (passes through) the memory cell region MA and the connection regions CA1 and CA2 in the X direction at the boundary region between adjacent blocks BLK. In other words, the component SLT is positioned across the memory cell region MA and the connection regions CA1 and CA2. Each component SLT may, for example, have a structure with insulators or plate-like contacts embedded within it. Each component SLT punctures the adjacent multilayer wiring that separates it.

[0140] Multiple components SHE extend along the X direction and are arranged along the Y direction. Figure 3 In the example shown, five components SHE are arranged between adjacent components SLT. Each component SHE traverses the memory cell region MA in the X direction. The two ends of each component SHE are contained within connection regions CA1 and CA2, respectively. Each component SHE has, for example, a structure filled with an insulator. Each component SHE truncates the adjacent select gate line SGD that is separated from it. Therefore, the select gate line SGD is truncated to each string assembly SU by components SLT and SHE.

[0141] Each region separated by component SLT corresponds to one block BLK. Additionally, each region separated by components SLT and SHE corresponds to one string component SU. Figure 3 In the example shown, one block BLK contains six string components SU0 to SU5.

[0142] Furthermore, the planar layout of the storage cell array 11 is not limited to the layout described above. For example, the number of components SHEs arranged between adjacent components SLTs can be designed to be arbitrary. The number of string components SUs formed between adjacent components SLTs can be varied based on the number of components SHEs arranged between adjacent components SLTs.

[0143] 1.1.4 Planar Layout of the Connecting Area

[0144] Next, refer to Figure 4 An example of the planar layout of the connecting region CA1 is illustrated. Figure 4 This is a top view showing an example of the planar layout of the connecting area CA1. Figure 4 This represents a portion of the connection region CA1 corresponding to one block BLK, and the nearby storage cell region MA. Furthermore, in Figure 4 In the example shown, for simplicity, one component SHE is set within the block BLK. That is, the block BLK contains two string components SU. Additionally, in Figure 4 In the example shown, a portion of the interlayer insulating film is omitted.

[0145] like Figure 4 As shown, in the connection area CA1, from the memory cell area MA to the X direction (right side of the paper), there are steps (plug connection parts) that correspond to the select gate line SGD, word lines WL9 to WL0, and select gate line SGS respectively.

[0146] Components SLT are provided on two sides of a block BLK facing the Y direction. Components SLT extend along the X and Z directions. Components SLT truncate the Z-direction-spaced, stacked select gate lines SGS, word lines WL0-WL9, and select gate line SGD to each block BLK. For example, each component SLT includes a conductor LI and a spacer SP. The conductor LI is a conductive component extending in the XZ plane and disposed within the component SLT. The spacer SP is an insulator disposed on the side of the conductor LI. Viewed from the Z direction, the conductor LI is surrounded by the spacer SP. The conductor LI is electrically connected to the source line SL disposed below the stacked wiring. Alternatively, the conductor LI can be removed. In this case, the component SLT is filled with an insulator.

[0147] The component SHE extends along the X direction. Within block BLK, the select gate line SGD is truncated by component SHE in the Y direction. Each region separated by components SLT and SHE corresponds to one string assembly SU.

[0148] Multiple memory pillars (MPs) are disposed in the memory cell region MA. Each memory pillar (MP) corresponds to a NAND string (NS). The detailed construction of the memory pillars (MPs) will be described below. For example, the memory pillars (MPs) have a generally cylindrical shape extending along the Z-direction. The memory pillars (MPs) pass through the select gate lines (SGS), word lines (WL0-WL9), and select gate line (SGD), which are stacked and spaced apart in the Z-direction. Figure 4 In the example shown, the multiple memory columns MP of the memory cell region MA are interleaved. Furthermore, the arrangement of the memory columns MP can be arbitrarily designed.

[0149] Multiple contact plugs CC and multiple support columns HR are provided in the connection areas CA1 and CA2.

[0150] The contact plug CC extends along the Z-direction. For example, the contact plug CC has a generally cylindrical shape formed of a conductor. The contact plug CC is electrically connected to any one of the wiring layers in the multilayer wiring, but not to the other wiring layers. In other words, the contact plug CC is electrically connected to the step of any one of the select gate line SGS, word lines WL0-WL9, and select gate line SGD. For example, the contact plug CC connected to the step of the select gate line SGD is not electrically connected to the select gate line SGS or the word lines WL0-WL9. The upper end of the contact plug CC is electrically connected to the line decoder 12. Figure 4 The diagram shows 24 contact plugs (CC). Each contact plug (CC) connecting to each wiring layer (step) requires at least one contact plug (CC).

[0151] As a method for forming word lines (WL) and select gate lines (SGD and SGS), one method is to form a structure equivalent to each wiring layer by forming a sacrificial film, and then replacing (replace) the sacrificial film with a conductive material to form the wiring layer (hereinafter referred to as "WL replacement"). In WL replacement, after removing the sacrificial film to form a void, the void is filled with a conductive material.

[0152] The support pillars HR function as pillars supporting the stacked structure with gaps during WL replacement. The support pillars HR are not electrically connected to the source line SL, word line WL, or select gate lines SGD and SGS. The support pillars HR extend along the Z-direction. For example, the support pillars HR have a generally cylindrical structure formed of an insulator. The support pillars HR penetrate (pass through) the select gate lines SGS, word lines WL0 to WL9, and select gate line SGD stacked in the Z-direction within the connection region CA1. Furthermore, the number and arrangement of the support pillars HR are arbitrary.

[0153] 1.1.5 Cross-sectional structure of the storage cell area

[0154] Reference Figure 5 and Figure 6An example of the cross-sectional structure of the memory cell region MA will be explained. Figure 5 It is along Figure 4 A cross-sectional view of the storage cell region MA along lines A1-A2. Figure 6 It is along Figure 5 A cross-sectional view of the memory cylinder MP along the C1-C2 lines in the XY plane. More specifically, Figure 6 This shows the cross-sectional structure of the memory cylinder MP in a layer parallel to the XY plane and containing the wiring layer. Furthermore, in the following sectional views, the structural details may be omitted for ease of observation.

[0155] like Figure 5 As shown, the memory cell array 11 includes a substrate 30, insulating layers 31, 33, 35, and 36, a semiconductor layer 32, a wiring layer 34, memory pillars MP, and components SLT and SHE.

[0156] The substrate 30 is, for example, a silicon substrate. An insulating layer 31 is disposed on the substrate 30. The insulating layer 31 includes, for example, silicon oxide. In the area where the insulating layer 31 is disposed, that is, between the substrate 30 and the semiconductor layer 32, circuits such as the line decoder 12 or the sense amplifier 13 may also be disposed. Furthermore, for example, if the semiconductor memory device 1 is a structure in which a chip having a memory cell array 11 is bonded to a chip having circuits other than the memory cell array 11, the substrate 30 disposed under the insulating layer 31 may be removed.

[0157] A semiconductor layer 32 is disposed on an insulating layer 31. The semiconductor layer 32 functions as a source line SL. The semiconductor layer 32 extends along the X and Y directions. The semiconductor layer 32 includes, for example, three semiconductor layers 32a, 32b, and 32c. Semiconductor layer 32a is disposed on the insulating layer 31. Semiconductor layer 32b is disposed on the semiconductor layer 32a. Semiconductor layer 32c is disposed on the semiconductor layer 32b. For example, semiconductor layer 32b is disposed in the memory cell region MA, but not in the connection region CA. Alternatively, semiconductor layer 32b may be disposed in the connection region CA. Semiconductor layer 32b is formed, for example, by replacing (replacing) the insulating layer disposed between semiconductor layers 32a and 32c. In the following description, the replacement of semiconductor layer 32 will also be described as "SL replacement". Semiconductor layers 32a to 32c include, for example, silicon. In addition, semiconductor layers 32a to 32c include, for example, phosphorus (P) as an impurity of an n-type semiconductor.

[0158] An insulating layer 33 is disposed on the semiconductor layer 32. The insulating layer 33 may contain, for example, silicon oxide.

[0159] Twelve wiring layers 34 (layered wiring) and twelve insulating layers 35 are alternately stacked on top of insulating layer 33. Hereinafter, the stacked structure of the twelve wiring layers 34 and twelve insulating layers 35 will also be described as a "stacked body". When the lower four wiring layers 34 of a specific set of twelve wiring layers 34 are used, they are referred to as "wiring layers 34a". The four wiring layers 34a function as the select gate line SGS and word lines WL0 to WL2 respectively, from bottom to top. When the two wiring layers 34 above a specific wiring layer 34a are used, they are referred to as "wiring layers 34b". The two wiring layers 34b function as word lines WL3 and WL4 respectively, from bottom to top. When the two wiring layers 34 above a specific wiring layer 34b are used, they are referred to as "wiring layers 34c". Two wiring layers 34c function as word lines WL5 and WL6 from bottom to top. When there are four wiring layers 34 above a specific wiring layer 34c, it is referred to as "wiring layer 34d". The four wiring layers 34d function as word lines WL7 to WL9 and select gate line SGD from bottom to top. In addition, multiple wiring layers 34 can be provided to function as select gate line SGS and SGD.

[0160] For example, a titanium nitride (TiN) / tungsten (W) multilayer structure is used as the conductive material for the wiring layer 34. In this case, titanium nitride is formed to cover tungsten. Titanium nitride functions as a barrier layer or a bonding layer when tungsten is deposited, for example, by CVD (Chemical Vapor Deposition). The barrier layer is used to suppress the oxidation of tungsten, and the bonding layer is used to improve the adhesion of tungsten. Alternatively, the wiring layer 34 may contain a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed to cover the conductive material. For example, in each wiring layer 34, the high dielectric constant material is provided in contact with the insulating layers 33 or 35 provided above and below the wiring layer 34 and the sides of the memory pillar MP. Moreover, titanium nitride is provided in contact with the high dielectric constant material. Furthermore, tungsten is provided in contact with the titanium nitride and to fill the interior of the wiring layer 34. For example, when aluminum oxide is used as a high dielectric constant material, the memory cell transistor MC is also described as MANOS (Metal-Aluminum-Nitride-Oxide-Silicon).

[0161] Next, the structure of the memory column MP will be explained.

[0162] The memory pillar MP extends along the Z-direction and passes through insulating layer 33, 12 wiring layers 34, and 12 insulating layers 35. The lower end of the memory pillar MP reaches semiconductor layer 32a. The upper end of the memory pillar MP is electrically connected to bit line BL via a contact plug (not shown).

[0163] A memory column (MP) can contain more than one sub-pillar stacked in the Z direction. Figure 5 In the example shown, memory column MP comprises lower memory column LMP, middle memory column MMP, and upper memory column UMP. Lower memory column LMP, middle memory column MMP, and upper memory column UMP are sub-columns of memory column MP. In other words, memory column MP has a structure formed by dividing it into three levels. That is, memory column MP is processed in three stages. Hereinafter, the level corresponding to lower memory column LMP will be described as "lower level T". LMP The hierarchy corresponding to the median memory column MMP is described as "median hierarchy T". MMP The hierarchy corresponding to the upper-level memory cylinder UMP is described as "upper-level T". UMP Furthermore, memory columns (MPs) can also have a structure with two or more layers. That is, memory columns (MPs) can be processed in two or four or more steps.

[0164] The lower memory column (LMP) passes through the insulating layer 33, the four wiring layers 34a, and the four insulating layers 35 disposed on the four wiring layers 34a. That is, the lower memory column (LMP) passes through the four wiring layers 34a, which function as the select gate line (SGS) and word lines WL0 to WL2, respectively. The lower surface of the lower memory column (LMP) reaches the semiconductor layer 32a. Therefore, the lower level T... LMP It includes four wiring layers 34a. Hereinafter, the stacked structure of the four wiring layers 34a and the four insulating layers 35 through which the lower memory cylinder LMP passes will also be described as the "lower stacked body".

[0165] The median memory column MMP passes through two wiring layers 34b, two wiring layers 34c, and four insulating layers 35 respectively disposed above wiring layers 34b and 34c. That is, the median memory column MMP passes through two wiring layers 34b, which function as word lines WL3 and WL4 respectively, and two wiring layers 34c, which function as word lines WL5 and WL6 respectively. Therefore, the median level T... MMP It includes two wiring layers 34b and two wiring layers 34c. The lower surface of the intermediate memory cylinder MMP is connected to the upper surface of the lower memory cylinder LMP. The boundary BDm1 where the upper surface of the lower memory cylinder LMP connects to the lower surface of the intermediate memory cylinder MMP is located between wiring layer 34a, which functions as word line WL2, and wiring layer 34b, which functions as word line WL3. In other words, the lower level T LMP With median level T MMPThe boundary BDm1 is located between the wiring layer 34a, which functions as word line WL2, and the wiring layer 34b, which functions as word line WL3. Hereinafter, the stacked structure of the two wiring layers 34b, two wiring layers 34c, and four insulating layers 35 through which the intermediate memory column MMP passes will be described as the "intermediate stacked structure". Furthermore, the layer in the intermediate stacked structure containing the two wiring layers 34b and the two insulating layers 35 will be described as the "lower layer of the intermediate stacked structure". The layer in the intermediate stacked structure containing the two wiring layers 34c and the two insulating layers 35 will be described as the "upper layer of the intermediate stacked structure".

[0166] The upper memory column UMP passes through four wiring layers 34d and four insulating layers 35 disposed above the four wiring layers 34d. That is, the upper memory column UMP passes through the four wiring layers 34d, which function as word lines WL7 to WL9 and the select gate line SGD, respectively. Therefore, the upper level T... UMP It contains four wiring layers 34d. The lower surface of the upper memory cylinder UMP is connected to the upper surface of the middle memory cylinder MMP. That is, the boundary BDm2 where the upper surface of the middle memory cylinder MMP is connected to the lower surface of the upper memory cylinder UMP is located between wiring layer 34c, which functions as word line WL6, and wiring layer 34d, which functions as word line WL7. In other words, the middle layer T... MMP With the higher level T UMP The boundary BDm2 is located between the wiring layer 34c, which functions as word line WL6, and the wiring layer 34d, which functions as word line WL7. Hereinafter, the stacked structure of the four wiring layers 34d and the four insulating layers 35 through which the upper memory cylinder UMP passes will also be described as the "upper stack".

[0167] The lower memory column LMP, the middle memory column MMP, and the upper memory column UMP each have a conical shape (also described as a "positive cone shape"), for example, where the diameter of the upper end is larger than the diameter of the lower end. In other words, the lower memory column LMP, the middle memory column MMP, and the upper memory column UMP each have a frustum-shaped shape, for example, where the lower surface is smaller than the upper surface. Therefore, the boundary BDm1 between the lower memory column LMP and the middle memory column MMP, and the boundary BDm2 between the middle memory column MMP and the upper memory column UMP, can be identified by observing the shape of the cross-section.

[0168] Memory pillars MP include, for example, a core film 40, a semiconductor film 41, and a stacked film 42. Each of the core film 40, semiconductor film 41, and stacked film 42 is formed as a continuous film, for example, within a lower memory pillar LMP, a middle memory pillar MMP, and a upper memory pillar UMP. The core film 40 has a generally cylindrical shape extending along the Z-direction. For example, the upper end of the core film 40 is located above the wiring layer 34, and the lower end of the core film 40 is located in the same layer as the semiconductor layer 32. The semiconductor film 41 extends along the Z-direction and covers the periphery of the core film 40. The side surface of the semiconductor film 41 is in contact with the semiconductor layer 32b. The stacked film 42 covers the side surface and bottom surface of the semiconductor film 41, except for the portion where the semiconductor film 41 contacts the semiconductor layer 32b. The core film 40 contains an insulator, such as silicon oxide. The semiconductor film 41 contains, for example, silicon.

[0169] like Figure 6 As shown, the laminated film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a barrier insulating film 45.

[0170] In the cross-section including the wiring layer 34, the core film 40 is disposed, for example, at the center of the memory pillar MP. A semiconductor film 41 surrounds the sides of the core film 40. A tunnel insulating film 43 surrounds the sides of the semiconductor film 41. A charge storage film 44 surrounds the sides of the tunnel insulating film 43. A barrier insulating film 45 surrounds the sides of the charge storage film 44. The wiring layer 34 surrounds the sides of the barrier insulating film 45. Each of the tunnel insulating film 43 and the barrier insulating film 45 comprises, for example, silicon oxide. The charge storage film 44 has the function of storing charge and, for example, comprises silicon nitride.

[0171] like Figure 5 As shown, memory cell transistors MC0 to MC9 are formed by combining memory pillars MP with wiring layers 34 that function as word lines WL0 to WL9. Similarly, select transistor ST1 is formed by combining memory pillars MP with wiring layers 34 that function as select gate line SGD. Select transistor ST2 is formed by combining memory pillars MP with wiring layers 34 that function as select gate line SGS. Semiconductor film 41 serves as a channel (current path) for memory cell transistors MC0 to MC9 and select transistors ST1 and ST2. Thus, each memory pillar MP can function as a NAND string NS.

[0172] Next, the structure of component SLT will be explained.

[0173] In this embodiment, the structure formed by dividing the component SLT, the support post HR, and the contact plug CC into two layers will be described. That is, the case where the interface between the component SLT, the support post HR, and the contact plug CC is located in the same wiring layer 34 will be described. Hereinafter, the layer corresponding to the lower component LSLT, the lower support post LHR, and the lower contact plug LCC will be referred to as "lower layer T". LCA Additionally, the hierarchy corresponding to the upper-level component USLT, upper-level support column UHR, and upper-level contact plug UCC is described as "upper-level T". UCA ".

[0174] The component SLT extends along the X and Z directions. The component SLT penetrates (passes through) insulating layer 33, 12 wiring layers 34, and 12 insulating layers 35. The component SLT truncates the stack in the Y direction. The lower end of the component SLT, for example, reaches semiconductor layer 32b.

[0175] A component SLT can contain more than one sub-part of a stacked layer in the Z direction. Figure 5 In the example shown, component SLT includes a lower-level component LSLT (also referred to as "part 1 of component SLT") and a higher-level component USLT (also referred to as "part 2 of component SLT") positioned above the lower-level component LSLT. Both the lower-level component LSLT and the higher-level component USLT are parts of component SLT. In other words, component SLT has a hierarchy divided into lower-level levels T. LCA and the higher level T UCA The resulting structure is such that the component SLT is processed in two steps. Furthermore, the component SLT can also have a structure with three or more layers. That is, the component SLT can also be processed in three or more steps. The number of layers (segments) of the component SLT in this embodiment differs from the number of layers (segments) of the memory column MP.

[0176] The lower-level component LSLT passes through the insulating layer 33, the six wiring layers 34 (four wiring layers 34a and two wiring layers 34b), and the six insulating layers 35 disposed on the six wiring layers 34. That is, the lower-level component LSLT passes through the six wiring layers 34 (four wiring layers 34a and two wiring layers 34b) that function as the select gate line SGS and word lines WL0 to WL4, respectively. Therefore, the lower-level T... LCA It includes four wiring layers 34a and two wiring layers 34b. The lower end of the lower component LSLT reaches the semiconductor layer 32b.

[0177] The upper-level component USLT passes through six wiring layers 34 (two wiring layers 34c and four wiring layers 34d) and six insulating layers 35 disposed above the six wiring layers 34. That is, the upper-level component USLT passes through the six wiring layers 34 (two wiring layers 34c and four wiring layers 34d) that function as word lines WL5 to WL9 and the select gate line SGD, respectively. Therefore, the upper-level T... UCA It includes two wiring layers 34c and four wiring layers 34d. The lower surface of the upper component USLT is in contact with the upper surface of the lower component LSLT. That is, the boundary BDc1 where the upper surface of the lower component LSLT and the lower surface of the upper component USLT are in contact is located between wiring layer 34b, which functions as word line WL4, and wiring layer 34c, which functions as word line WL5. In other words, the lower level T LCA With the higher level T UCA The boundary BDc1 is located between wiring layer 34b, which functions as word line WL4, and wiring layer 34c, which functions as word line WL5. The wiring layers 34 at the boundary between the memory cylinder MP and the component SLT are different from each other.

[0178] The lower component LSLT and the upper component USLT each have a conical shape, for example, the width of the upper end in the Y direction is greater than the width of the lower end in the Y direction. Therefore, the junction BDc1 between the lower component LSLT and the upper component USLT can be confirmed by observing the shape of the cross-section.

[0179] The component SLT includes a conductor LI and a spacer SP. Each of the conductor LI and the spacer SP is formed as a continuous film, for example, within a lower component LSLT and an upper component USLT. In other words, the conductor LI is a conductive component that extends in the XZ plane and is disposed within the component SLT. The spacer SP is an insulator disposed on the side of the conductor LI. The lower end of the conductor LI is electrically connected to the semiconductor layer 32 (source line SL). The conductor LI may contain, for example, tungsten and titanium nitride, or silicon. The spacer SP may contain, for example, silicon oxide.

[0180] The component SHE separates the wiring layer 34, which functions as the select gate line (SGD), in the Y direction. In other words, the component SHE separates at least the uppermost wiring layer 34, which is located furthest from the semiconductor layer 32. The upper end of the component SHE is located above the uppermost wiring layer 34. The lower end of the component SHE is located between the wiring layer 34, which functions as the select gate line (SGD), and the wiring layer 34, which functions as the word line (WL). The lower end of the component SHE may be deeper depending on the number of wiring layers 34 that function as the select gate line (SGD). The component SHE contains an insulator, such as silicon oxide.

[0181] An insulating layer 36 is disposed on the insulating layer 35. The insulating layer 36 may contain, for example, silicon oxide.

[0182] 1.1.6 Cross-sectional composition of the connecting region

[0183] Reference Figure 7 An example of the cross-sectional structure of the connecting region CA will be explained. Figure 7 It is along Figure 4 A cross-sectional view of the connection area CA1 of lines B1-B2. Furthermore, in Figure 7 In the example shown, two support pillars HR passing through the step of the select gate line SGD are shown to match the cross-section along line B1-B2. In contrast, at each step of word lines WL0-WL9 and select gate line SGS, a portion of the support pillars HR is omitted for simplicity, and only one support pillar HR passing through each step is shown. Although a portion of the support pillars HR is omitted at each step of word lines WL0-WL9 and select gate line SGS, the support pillars HR are configured in the same way as those at the step of select gate line SGD.

[0184] like Figure 7 As shown, the storage cell array 11 also includes insulating layers 37 and 50, support pillars HR, and contact plugs CC in the connection area CA.

[0185] The insulating layer 37 is formed by filling the stepped portion (stepped region) of the laminate formed in the connecting region CA. The insulating layer 37 flattens the stepped portion. The insulating layer 37 may contain, for example, silicon oxide.

[0186] An insulating layer 50 is disposed between semiconductor layers 32a and 32c in the connection region CA. The insulating layer 50 in the connection region CA is a layer that remains after being not removed during the replacement (SL replacement) of semiconductor layer 32. The insulating layer 50 may contain, for example, silicon oxide.

[0187] Next, we will explain the support column HR.

[0188] The support pillars HR are provided extending along the Z-direction and passing through the steps of any wiring layer 34 and the wiring layer 34 below that step. Therefore, the number of wiring layers 34 traversed by the support pillars HR varies depending on the corresponding step. For example, a support pillar HR located on the step of the select gate line SGD passes through 12 wiring layers 34. Alternatively, for example, a support pillar HR located on the step of the select gate line SGS passes through 1 wiring layer 34. The multiple support pillars HR have approximately the same shape regardless of the corresponding step. For example, the lower end of the support pillar HR reaches the semiconductor layer 32a. The support pillars HR are buried by an insulator 38. The insulator 38 comprises, for example, silicon oxide.

[0189] The supporting column HR can contain more than one sub-column stacked in the Z direction. Figure 7 In the example shown, the support column HR includes a lower support column LHR and an upper support column UHR positioned above the lower support column LHR. The lower support column LHR and the upper support column UHR are sub-columns of the support column HR. In other words, the support column HR has lower-level T... LCA and the higher level T UCA The resulting structure is as follows: the support column HR is processed in two stages. Furthermore, the support column HR can also have a structure with three or more layers. That is, the support column HR can also be processed in three or more stages. The number of layers (segments) of the support column HR in this embodiment differs from the number of layers (segments) of the memory column MP.

[0190] The lower support post LHR passing through each step of the select gate line SGS and word lines WL0 to WL4 passes through the corresponding step and the wiring layer 34 located below the step. For example, the lower support post LHR passing through the step of the select gate line SGS passes through the wiring layer 34a that functions as the select gate line SGS and the insulating layer 35 disposed on the wiring layer 34a. The lower support post LHR passing through the step of the word line WL0 passes through two wiring layers 34a and two insulating layers 35 that function as the select gate line SGS and the word line WL0, respectively. The lower support post LHR passing through the step of the word line WL4 passes through six wiring layers 34 (four wiring layers 34a and two wiring layers 34b) that function as the select gate line SGS and the word lines WL0 to WL4, respectively, and six insulating layers 35. Furthermore, the lower support pillars LHR passing through each step of the select gate line SGS and word lines WL0 to WL3 pass through the insulating layer 37 used for planarization (burying) of the stepped portion. Additionally, the lower support pillars LHR located below each step of word lines WL5 to WL9 and the select gate line SGD do not pass through the steps. These lower support pillars LHR pass below the corresponding steps through a 6-layer wiring layer 34 (4-layer wiring layer 34a and 2-layer wiring layer 34b) and a 6-layer insulating layer 35, respectively serving as the select gate line SGS and word lines WL0 to WL4. The lower end of each lower support pillar LHR, for example, reaches the semiconductor layer 32a.

[0191] The upper support post UHR, located above each step of the select gate line SGS and word lines WL0 to WL4, passes through the insulating layer 37 instead of the wiring layer 34. Additionally, the upper support post UHR passing through each step of word lines WL5 to WL9 and the select gate line SGD passes through the corresponding step and the upper layer T located below the step. UCAThe wiring layer 34. For example, the upper support post UHR of the step provided for word line WL5 passes through the wiring layer 34c that functions as word line WL5 and the insulating layer 35 provided on the wiring layer 34c. For example, the upper support post UHR of the step provided for the select gate line SGD passes through the 6 wiring layers 34 (2 wiring layers 34c and 4 wiring layers 34d) that function as word lines WL5 to WL9 and the select gate line SGD, respectively, and the 6 insulating layers 35. Furthermore, the upper support post UHR of each step provided for word lines WL5 to WL9 passes through the insulating layer 37. The lower surface of each upper support post UHR is in contact with the upper surface of the corresponding lower support post LHR. That is, the boundary BDc1 where the upper surface of the lower support post LHR and the lower surface of the upper support post UHR are in contact is located between the wiring layer 34b that functions as word line WL4 and the wiring layer 34c that functions as word line WL5. The wiring layers 34 at the junction of the memory column MP and the support column HR are different from each other.

[0192] The lower support column LHR and the upper support column UHR each have a conical shape, for example, with the diameter of the upper end being larger than the diameter of the lower end. In other words, the lower support column LHR and the upper support column UHR each have a frustum-shaped shape, for example, with the lower surface being smaller than the upper surface. Therefore, the junction BDc1 between the lower support column LHR and the upper support column UHR can be identified by observing the shape of the cross-section.

[0193] Next, the contact plug CC will be explained.

[0194] In the connection area CA, contact plugs CC are provided on each step. The lower end of the contact plug CC is in contact with the step of the corresponding wiring layer 34. The contact plug CC extends along the Z direction. In this embodiment, the contact plug CC does not pass through the wiring layer 34 located below the step. Therefore, the shape (height in the Z direction) of the contact plug CC varies depending on the connected step. The upper end of the contact plug CC is located above the uppermost wiring layer 34, which functions as the select gate line SGD. The contact plug CC contains, for example, tungsten or copper as a conductor.

[0195] A contact plug CC can contain one or more sub-plugs stacked in the Z direction. Figure 7 In the example shown, the contact plug CC includes a lower contact plug LCC and a higher contact plug UCC. The lower contact plug LCC and the higher contact plug UCC are sub-plugs of the contact plug CC. A portion of each higher contact plug UCC is disposed above a corresponding lower contact plug LCC. In other words, the contact plug CC has a hierarchy T. LCA and the higher level T UCAThe resulting structure is as follows: the contact plug CC is processed in two stages. Furthermore, the contact plug CC can have a single-layer structure or a structure with three or more layers. That is, the contact plug CC can be processed in one go without division, or it can be processed in three or more stages. The number of layers (segments) of the contact plug CC in this embodiment differs from the number of layers (segments) of the memory cylinder MP.

[0196] The lower-level contact plug (LCC) is positioned on each step of the select gate line SGS and word lines WL0 to WL4. For example, the upper end of the lower-level contact plug (LCC) is located between wiring layer 34b, which functions as word line WL4, and wiring layer 34c, which functions as word line WL5. In other words, the upper end of the lower-level contact plug (LCC) is located at the lower-level layer T. LCA With the higher level T UCA The boundary BDc1.

[0197] The upper contact plug UCC is disposed above the lower contact plug LCC disposed above each step of the select gate line SGS and word lines WL0 to WL4. Additionally, the upper contact plug UCC is disposed above each step of word lines WL5 to WL9 and the select gate line SGD. The lower surface of the upper contact plug UCC corresponding to the select gate line SGS and word lines WL0 to WL4 is in contact with the upper surface of the lower contact plug LCC. That is, the boundary BDc1 where the upper surface of the lower contact plug LCC and the lower surface of the upper contact plug UCC are in contact is located between the wiring layer 34b, which functions as word line WL4, and the wiring layer 34c, which functions as word line WL5. The upper end of the upper contact plug UCC is located above the uppermost wiring layer 34d, which functions as the select gate line SGD.

[0198] The lower contact plug LCC and the upper contact plug UCC each have a conical shape, for example, with the diameter of the upper end being larger than the diameter of the lower end. In other words, the lower contact plug LCC and the upper contact plug UCC each have a frustum-shaped shape, for example, with the lower surface being smaller than the upper surface. Therefore, the junction BDc1 between the lower contact plug LCC and the upper contact plug UCC can be identified by observing the shape of the cross-section.

[0199] 1.2 The junction of memory pillars, component SLTs, and support pillars

[0200] Next, refer to Figure 8 The boundaries of the memory column (MP), component (SLT), and support column (HR) are explained. Figure 8 This is a conceptual diagram representing the intersection of memory pillars (MP), component segments (SLT), and support pillars (HR). Figure 8In the comparative example, the memory column MP, component SLT, and support column HR are shown to have the same number of intersections. Furthermore, in both the comparative example and the embodiment, the shape and number of intersections of the memory column MP are the same.

[0201] First, let's explain the comparative examples.

[0202] like Figure 8 As shown in (a), for example in the comparative example, the number of layers (intersections) of the memory column MP, component SLT, and support column HR is the same. In this case, the layer intersections of the memory column MP, component SLT, and support column HR are located between the same wiring layers 34.

[0203] For example, a memory column (MP) includes a lower memory column (LMP), a middle memory column (MMP), and a higher memory column (UMP). A component (SLT) includes a lower component (LSLT), a middle component (MSLT), and a higher component (USLT). A support column (HR) includes a lower support column (LHR), a middle support column (MHR), and a higher support column (UHR). For example, the boundary BDm1 between the lower memory column (LMP) and the middle memory column (MMP), the boundary between the lower component (LSLT) and the middle component (MSLT), and the boundary between the lower support column (LHR) and the middle support column (MHR) are the same.

[0204] For example, let L0 be the distance between the top of an adjacent memory column MP (upper memory column UMP) and the top of a component SLT (upper component USLT). Let L1a be the distance between the middle memory column MMP near the boundary BDm1 and the middle component MSLT. Let L2a be the distance between the upper memory column UMP near the boundary BDm2 and the upper component USLT. Each of the memory column MP, component SLT, and support column HR has a conical shape in its respective division. Therefore, distance L0 and distance L1a are related by L0 < L1a. Similarly, distance L0 and distance L2a are related by L0 < L2a.

[0205] Next, the embodiments will be described.

[0206] like Figure 8 As shown in (b) of the diagram, in this embodiment, the memory column MP has 3 levels. The component SLT and support column HR have 2 levels. In other words, the memory column MP has 2 boundaries BDm1 and BDm2. The component SLT and support column HR have 1 boundary BDc1. That is, the number of levels (boundaries) of the memory column MP and the component SLT and support column HR are different.

[0207] In this case, the interlayer positions of the wiring layer 34 where the junctions BDm1 and BDm2 of the memory pillar MP and the junction BDc1 of the component SLT and the support pillar HR are located are different. More specifically, when using Figure 5 and Figure 7 In the description, the boundary BDm1 is located between the wiring layer 34a, which functions as word line WL2, and the wiring layer 34b, which functions as word line WL3. The boundary BDm2 is located between the wiring layer 34c, which functions as word line WL6, and the wiring layer 34d, which functions as word line WL7. In contrast, the boundary BDc1 is located between the wiring layer 34b, which functions as word line WL4, and the wiring layer 34c, which functions as word line WL5.

[0208] The memory column MP, component SLT, and support column HR each have a conical shape in their respective divisions (levels).

[0209] More specifically, the diameter D of the lower end of the lower memory cylinder (LMP) LMP1 With the diameter D at the top LMP2 D exists LMP1 <D LMP2 The relationship. The diameter D of the lower end of the median memory cylinder MMP. MMP1 With the diameter D at the top MMP2 D exists MMP1 <D MMP2 The relationship. The diameter D of the lower end of the upper memory cylinder UMP. UMP1 With the diameter D at the top UMP2 D exists UMP1 <D UMP2 The relationship. Furthermore, the diameter D at the top of the lower memory cylinder LMP... LMP2 The diameter D of the lower end of the median memory column MMP MMP1 D exists LMP2 >D MMP1 The relationship. The diameter D of the upper end of the median memory column MMP. MMP2 The diameter D of the lower end of the upper memory cylinder UMP UMP1 D exists MMP2 >D UMP1 The relationship.

[0210] Additionally, the width W in the Y direction of the lower end of the lower component LSLT LSLT1 Width W in the Y direction at the top LSLT2 There exists W LSLT1 <W LSLT2 The relationship. The width W in the Y direction of the lower end of the upper component USLT. USLT1 Width W in the Y direction at the top USLT2 There exists W USLT1 <W USLT2 The relationship. Furthermore, the width W in the Y direction of the upper end of the lower component LSLT. LSLT2 The width W in the Y direction of the lower end of the upper component USLT USLT1There exists W LSLT2 >W USLT1 The same relationship exists regarding the support column HR.

[0211] For example, the distance between the top of an adjacent memory column MP (upper memory column UMP) and the top of a component SLT (upper component USLT) is set to L0, the same as in the comparative example (a). The distance between the memory column MP at the boundary BDm1 and the component SLT is set to L1b. The distance between the memory column MP at the boundary BDm2 and the component SLT is set to L2b. The distances L0 and L1b are related by L0 < L1b. Similarly, the distances L0 and L2b are related by L0 < L2b.

[0212] In the comparative example of (a), for example, the width of the middle component MSLT is narrowest at the boundary BDm1. In contrast, in the embodiment of (b), the boundary BDm1 is located in the middle of the lower component LSLT. Therefore, when comparing distance L1a and distance L1b, L1a > L1b. Similarly, in the comparative example of (a), the width of the upper component USLT is narrowest at the boundary BDm2. In contrast, in the embodiment of (b), the boundary BDm2 is located in the middle of the upper component USLT. Therefore, when comparing distance L2a and distance L2b, L2a > L2b. The relationship between the memory column MP and the support column HR is similar.

[0213] Therefore, with the configuration of this embodiment, the increased distance between the memory pillar MP and the component SLT can be suppressed by the conical shape. In other words, by placing the boundary between the memory pillar MP and the component SLT in the interlayer of different wiring layers 34, the increased distance between the memory pillar MP and the component SLT can be suppressed. The same applies to the support pillar HR. By placing the boundary between the memory pillar MP and the support pillar HR in the interlayer of different wiring layers 34, the increased distance between the memory pillar MP and the support pillar HR can be suppressed. As a result, for example, the deflection of the laminate caused by WL replacement can be suppressed.

[0214] 1.3 Manufacturing method of memory cell array

[0215] Next, refer to Figures 9 to 37 An example of a method for manufacturing the memory cell array 11 will be described. Figure 9 This is a flowchart illustrating an example of the manufacturing process of the memory cell array 11. Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 ,and Figure 36 This is a diagram illustrating an example of the planar layout of the memory cell array 11 during the manufacturing process of the memory cell array 11. Figure 11 It is along Figure 10 A sectional view of lines A1-A2 and B1-B2. Figure 13 It is along Figure 12 A sectional view of lines A1-A2 and B1-B2.

[0216] Figure 15 It is along Figure 14 A sectional view of lines A1-A2 and B1-B2. Figure 17 It is along Figure 16 A sectional view of lines A1-A2 and B1-B2. Figure 19 It is along Figure 18 A sectional view of lines A1-A2 and B1-B2. Figure 21 It is along Figure 20 A sectional view of lines A1-A2 and B1-B2. Figure 23 It is along Figure 22 A sectional view of lines A1-A2 and B1-B2. Figure 25 It is along Figure 24 A sectional view of lines A1-A2 and B1-B2. Figure 27 It is along Figure 26 A sectional view of lines A1-A2 and B1-B2. Figure 29 It is along Figure 28 A sectional view of lines A1-A2 and B1-B2. Figure 31 It is along Figure 30 A sectional view of lines A1-A2 and B1-B2. Figure 33 It is along Figure 32 A sectional view of lines A1-A2 and B1-B2. Figure 35 It is along Figure 34 A sectional view of lines A1-A2 and B1-B2. Figure 37 It is along Figure 36 The cross-sectional views are along lines A1-A2 and B1-B2. Furthermore, the dimensions of the memory pillar MP, component SLT, support pillar HR, and contact plug CC in each cross-sectional view are arbitrary. Additionally, in the cross-sectional views of the manufacturing process shown below, a portion of the support pillar HR passing through each step is omitted for simplicity.

[0217] like Figure 9 As shown, the lower-level stacked body is first formed into a film (S101).

[0218] like Figure 10 and Figure 11 As shown, more specifically, an insulating layer 31 is first formed on a semiconductor substrate 30. A semiconductor layer 32a is formed on the insulating layer 31. An insulating layer 50 is formed on the semiconductor layer 32a. The insulating layer 50 includes, for example, three insulating layers 50a, 50b, and 50c. For example, insulating layers 50a and 50c contain silicon oxide. Insulating layer 50b contains silicon nitride. Furthermore, insulating layer 50b is formed in the memory cell region MA where the replacement (SL replacement) of insulating layer 50 will be performed in the following process, and is not formed in the connection region CA where the replacement is not performed. A semiconductor layer 32c is formed on the insulating layer 50. An insulating layer 33 is formed on the semiconductor layer 32c. On the insulating layer 33, four sacrificial films 60a and four insulating layers 35 are alternately deposited layer by layer as the lower-level stack before SL replacement. The four sacrificial films 60a correspond to the lower-level layer T. LMP In the WL replacement, four wiring layers 34a are replaced to function as the select gate line SGS and word lines WL0 to WL2, respectively. For example, silicon nitride is used for the sacrificial film 60a.

[0219] like Figure 9 As shown, after performing step S101, a memory hole LMH corresponding to the lower memory column LMP is processed (formed), and the memory hole LMH is filled with a sacrificial film 61 (S102).

[0220] like Figure 12 and Figure 13 As shown, a memory hole LMH corresponding to the lower memory column LMP is formed in the memory cell region MA. The memory hole LMH has a tapered shape and its lower end reaches the semiconductor layer 32a.

[0221] like Figure 14 and Figure 15 As shown, the memory hole LMH is then filled using a sacrificial film 61. The sacrificial film 61 may contain carbon, silicon, or a metallic material.

[0222] like Figure 9 As shown, after performing step S102, the lower layer of the intermediate stack is formed into a film (S103).

[0223] like Figure 16 and Figure 17 As shown, two sacrificial films 60b and two insulating layers 35 are alternately deposited on the lower stack as the lower layer of the intermediate stack before WL replacement. During WL replacement, the two sacrificial films 60b are replaced by two wiring layers 34b that function as word lines WL3 and WL4, respectively. For example, silicon nitride is used for the sacrificial films 60b.

[0224] like Figure 9As shown, after executing step S103, a lower-level T is formed that is connected to the region CA. LCA The corresponding stepped section (S104).

[0225] like Figure 18 and Figure 19 As shown, the lower layers of the lower and middle stacked bodies are processed in a stepped manner to form steps corresponding to the multiple sacrificial films 60a and 60b, respectively. Figure 19 In the example shown, steps corresponding to the select gate line SGS and word lines WL0 to WL3 are fabricated.

[0226] like Figure 9 As shown, after step S104, the processing of the lower support column LHR and the filling of the sacrificial membrane 62, the processing of the lower component LSLT and the filling of the sacrificial membrane 63, and the processing of the lower contact plug LCC and the filling of the sacrificial membrane 64 are performed sequentially (S105). Furthermore, the order in which the processing of the lower support column LHR, the lower component LSLT, and the lower contact plug LCC, and the filling of the sacrificial membranes 62 to 64 are performed is arbitrary.

[0227] like Figure 20 and Figure 21 As shown, the stepped portion is buried in the insulating layer 37, and planarized, for example, by CMP (Chemical Mechanical Polishing). Then, in the connection region CA, a hole corresponding to the lower support pillar LHR is formed, and the hole is filled with a sacrificial film 62. For example, the lower end of the hole corresponding to the lower support pillar LHR reaches the semiconductor layer 32a. Then, a slit corresponding to the lower component LSLT is formed, and the slit is filled with a sacrificial film 63. The lower end of the slit corresponding to the lower component LSLT reaches the insulating layer 50. Then, in the connection region CA, a hole corresponding to the lower contact plug LCC is formed, and the hole is filled with a sacrificial film 64. The lower end of the lower contact plug LCC is connected to the step of the corresponding sacrificial film 60 (wiring layer 34). Furthermore, the lower contact plug LCC is provided on the steps of the select gate line SGS and word lines WL0 to WL4, but not on the steps of word lines WL5 to WL9 and select gate line SGD. For example, the sacrificial films 62-64 may contain carbon, silicon, or metallic materials. Furthermore, the materials of the sacrificial films 62-64 may be the same or different.

[0228] like Figure 9 As shown, after performing step S105, the upper layer of the intermediate stack is formed into a film (S106).

[0229] like Figure 22 and Figure 23As shown, two sacrificial films 60c and two insulating layers 35 are alternately deposited on the lower layer of the intermediate stack as the upper layer of the intermediate stack before WL replacement. During WL replacement, the two sacrificial films 60c are replaced by two wiring layers 34c that function as word lines WL5 and WL6, respectively. For example, silicon nitride is used for the sacrificial films 60c.

[0230] like Figure 9 As shown, after performing step S106, a memory hole corresponding to the center memory column MMP is processed (formed), and the memory hole is filled with a sacrificial film 61 (S107).

[0231] like Figure 24 and Figure 25 As shown, a memory hole corresponding to the middle memory column MMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the middle memory column MMP reaches the lower memory column LMP. Then, a sacrificial film 61 is used to fill the memory hole corresponding to the middle memory column MMP. In other words, a stacked structure of the lower memory column LMP and the middle memory column MMP filled by the sacrificial film 61 is formed.

[0232] like Figure 9 As shown, after performing step S107, the upper stacked body is formed into a film (S108).

[0233] like Figure 26 and Figure 27 As shown, four sacrificial films 60d and four insulating layers 35 are alternately deposited on the upper layer of the intermediate stack as the upper stack before WL replacement. During WL replacement, the four sacrificial films 60d are replaced with four wiring layers 34d, which function as word lines WL7 to WL9 and the select gate line SGD, respectively. For example, silicon nitride is used for the sacrificial films 60d.

[0234] like Figure 9 As shown, after executing step S108, a higher-level T is formed that is connected to the region CA. UCA The corresponding stepped section (S109).

[0235] like Figure 28 and Figure 29 As shown, the upper layer and the upper stack of the intermediate stack are processed into steps to form steps corresponding to the multiple sacrificial films 60c and 60d, respectively. Figure 29 In the example shown, steps corresponding to the letter lines WL4 to WL9 are machined.

[0236] like Figure 9As shown, after step S109, the processing of the upper support column UHR and the filling of the sacrificial membrane 62, the processing of the upper component USLT and the filling of the sacrificial membrane 63, and the processing of the upper contact plug UCC and the filling of the sacrificial membrane 64 are performed sequentially (S110). Furthermore, the order of processing the upper support column UHR, the upper component USLT, and the upper contact plug UCC, and the filling of the sacrificial membranes 62 to 64 is arbitrary.

[0237] like Figure 30 and Figure 31 As shown, the stepped portion is filled with insulating layer 37, and planarized, for example, by CMP. Then, in the connection region CA, a hole corresponding to the upper support post UHR is formed, and the hole is filled with sacrificial membrane 62. Thus, the support post HR filled with sacrificial membrane 62 is formed. Then, a slit corresponding to the upper component USLT is formed, and the slit is filled with sacrificial membrane 63. Thus, the component SLT filled with sacrificial membrane 63 is formed. Then, in the connection region CA, a hole corresponding to the upper contact plug UCC is formed, and the hole is filled with sacrificial membrane 64. Thus, the contact plug CC filled with sacrificial membrane 64 is formed.

[0238] like Figure 9 As shown, after performing step S110, a memory hole corresponding to the upper memory column UMP is processed (formed) to form the memory column MP (S111).

[0239] like Figure 32 and Figure 33 As shown, a memory hole corresponding to the upper memory column UMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the upper memory column UMP reaches the middle memory column MMP. Then, the sacrificial film 61 inside the memory hole is removed. Then, the stacked film 42, the semiconductor film 41, and the core film 40 are formed to fill the memory hole, forming the memory column MP.

[0240] like Figure 9 As shown, after performing step S111, the sacrificial membrane 62 inside the support column HR is removed, and the hole is filled with insulator 38 (S112).

[0241] After performing step S112, the sacrificial film 63 in the component SLT is removed (S113).

[0242] like Figure 34 and Figure 35 As shown, the sacrificial film 62 inside the support column HR is removed, and the interior is filled with insulator 38. After the insulating layer 36 is formed, an opening is made in the component SLT, and the internal sacrificial film 63 is removed.

[0243] like Figure 9As shown, after executing step S113, SL substitution and WL substitution are executed sequentially (S114).

[0244] After performing step S114, the spacer SP and conductor LI are used to fill the component SLT (S115).

[0245] like Figure 36 and Figure 37 As shown, for example, after forming an insulating film on the side of the slit corresponding to the component SLT, SL replacement is performed to replace the insulating layer 50 (50a, 50b, 50c) of the memory cell region MA with the semiconductor layer 32b. At this time, the laminated film 42, which is the same layer as the semiconductor layer 32b, is removed in the memory column MP. More specifically, the insulating layer 50b is removed from the side of the slit corresponding to the component SLT by wet etching. Then, the insulating layers 50a and 50c are removed from the side of the slit corresponding to the component SLT by wet etching. Thus, the insulating layers 50 (50a, 50b, and 50c) are removed in the memory cell region MA where the insulating layer 50b is formed. At this time, the laminated film 42, which is the same layer as the insulating layer 50, is also removed simultaneously. Then, the semiconductor layer 32b is formed to fill the area where the insulating layer 50 has been removed. Then, a semiconductor layer 32b is formed between semiconductor layers 32a and 32c by removing excess semiconductor layer 32b on the side of the slit corresponding to component SLT and on the insulating layer 36.

[0246] Then, WL replacement is performed. More specifically, the insulating layer on the side of the slit corresponding to the component SLT is first removed. Then, the sacrificial film 60 (60a to 60d) is removed from the side of the slit corresponding to the component SLT by wet etching. Then, the wiring layer 34 (34a to 34d) is formed.

[0247] Then, spacers SP and conductors LI are formed within component SLT.

[0248] like Figure 9 As shown, after performing step S115, the sacrificial film 64 inside the contact plug CC is removed, and the hole is filled with the conductor 39 (S116). Thus, a device is formed for use. Figure 5 , Figure 7 ,and Figure 8 The construction of the storage cell array 11 will be described.

[0249] 1.4 Effects of this implementation method

[0250] If the configuration of this embodiment is adopted, the semiconductor memory device 1 can reduce manufacturing costs. This effect will be described in detail.

[0251] For example, in 3D stacked NAND flash memory, as the number of word lines (WL) increases, the processing difficulty of memory cylinders (MP), component levels (SLT), support pillars (HR), and contact plugs (CC) increases. Therefore, memory cylinders (MP), component levels (SLT), support pillars (HR), and contact plugs (CC) are sometimes processed in multiple layers. In this case, the number of layers for memory cylinders (MP), component levels (SLT), support pillars (HR), and contact plugs (CC) is set to the same number. However, the processing difficulty of memory cylinders (MP), component levels (SLT), support pillars (HR), and contact plugs (CC) varies. The ideal number of layers varies depending on the processing difficulty. For example, if the number of layers is set to be consistent with the number of memory cylinders (MP), the number of layers (processing times) for component levels (SLT), support pillars (HR), and contact plugs (CC) may differ from the ideal number of layers. For example, if the set number of layers is greater than the ideal number of layers, the number of process steps and manufacturing cost of the memory cell array increase.

[0252] In contrast, with the configuration of this embodiment, the number of layers of the memory cylinder MP can be set to be different from the number of layers of the component SLT, support pillar HR, and contact plug CC. Furthermore, the interlayer of the wiring layers 34 can be set to be different at the boundary positions corresponding to the layers of the memory cylinder MP and the boundary positions corresponding to the layers of the component SLT, support pillar HR, and contact plug CC. For example, if using... Figure 5 As explained, the boundary BDm1 where the upper surface of the lower memory column LMP meets the lower surface of the middle memory column MMP is located between wiring layer 34a, which functions as word line WL2, and wiring layer 34b, which functions as word line WL3. Furthermore, the boundary BDc1 where the upper surface of the lower support column LHR meets the lower surface of the upper support column UHR is located between wiring layer 34b, which functions as word line WL4, and wiring layer 34c, which functions as word line WL5. By adapting the number of layers in the memory column MP to the number of layers in the component SLT, support column HR, and contact plug CC, the number of process steps and manufacturing cost of the memory cell array can be reduced.

[0253] Furthermore, in the configuration of this embodiment, the boundary position corresponding to the memory column MP and the boundary position corresponding to the component SLT, support column HR, and contact plug CC can be set as different wiring layers 34. Therefore, if using... Figure 8 This can, for example, suppress the increase in the distance between the memory pillar MP and the component SLT or support pillar HR. Therefore, for example, it can suppress the deflection of the laminate.

[0254] 2. Second Implementation Method

[0255] Next, the second embodiment will be described. In the second embodiment, the case where the number of layers of the component SLT, the support post HR, and the contact plug CC is greater than the number of layers of the memory post MP will be described. Hereinafter, the description will focus on the differences from the first embodiment.

[0256] 2.1 Cross-sectional structure of the storage cell area

[0257] Reference Figure 38 An example of the cross-sectional structure of the memory cell region MA will be explained. Figure 38 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell region MA.

[0258] like Figure 38 As shown, the shape of the memory column MP in this embodiment is different from that in the first embodiment. Figure 5 They are the same. A memory column MP includes a lower memory column LMP, a middle memory column MMP, and a higher memory column UMP.

[0259] Next, the structure of component SLT will be explained.

[0260] In this embodiment, the component SLT, the support post HR, and the contact plug CC have a structure formed in four layers. Hereinafter, the layers corresponding to the mid-position component MSLT, the mid-position support post MHR, and the mid-position contact plug MCC will be described as "mid-position layer T". MCA Additionally, the hierarchy corresponding to the topmost component TSLT, the topmost support post THR, and the topmost contact plug TCC is described as "topmost hierarchy T". TCA ".

[0261] The component SLT in this embodiment includes a lower-level component LSLT, a middle-level component MSLT, a higher-level component USLT, and a top-level component TSLT. The middle-level component MSLT is disposed above the lower-level component LSLT. The higher-level component USLT is disposed above the middle-level component MSLT. The top-level component TSLT is disposed above the higher-level component USLT. In other words, the component SLT in this embodiment has a lower-level hierarchy T LCA Median level T MCA Upper-level T UCA and the highest level T TCA The resulting structure is that the SLT component is processed in four stages.

[0262] The lower-level component LSLT passes through three wiring layers 34a, which function as the select gate line SGS and word lines WL0 and WL1, respectively. Therefore, the lower-level T... LCA It includes three wiring layers 34a. The lower end of the lower component LSLT reaches the semiconductor layer 32b.

[0263] The middle layer component MSLT passes through three wiring layers 34 (wiring layer 34a and wiring layer 34b), which function as word lines WL2 to WL4 respectively. Therefore, the middle layer T MCA It includes three wiring layers 34 (one wiring layer 34a and two wiring layers 34b). The lower surface of the intermediate component MSLT is in contact with the upper surface of the lower component LSLT. That is, the boundary BDc1 where the upper surface of the lower component LSLT and the lower surface of the intermediate component MSLT are in contact is located between wiring layer 34a, which functions as word line WL1, and wiring layer 34a, which functions as word line WL2. In other words, the lower layer T LCA With median level T MCA The boundary BDc1 is located between the wiring layer 34a, which functions as word line WL1, and the wiring layer 34a, which functions as word line WL2.

[0264] The upper-level component USLT passes through three wiring layers 34 (two wiring layers 34c and one wiring layer 34d) that function as word lines WL5 to WL7 respectively. Therefore, the upper-level T UCA It includes three wiring layers 34 (two wiring layers 34c and one wiring layer 34d). The lower surface of the upper component USLT is in contact with the upper surface of the middle component MSLT. That is, the boundary BDc2 where the upper surface of the middle component MSLT and the lower surface of the upper component USLT are in contact is located between wiring layer 34b, which functions as word line WL4, and wiring layer 34c, which functions as word line WL5. In other words, the middle layer T... MCA With the higher level T UCA The boundary BDc2 is located between the wiring layer 34b, which functions as word line WL4, and the wiring layer 34c, which functions as word line WL5.

[0265] The topmost component TSLT passes through three wiring layers 34d, which function as word lines WL8 and WL9 and the select gate line SGD, respectively. Therefore, the topmost level T TCA It contains three wiring layers 34d. The lower surface of the uppermost component TSLT is in contact with the upper surface of the uppermost component USLT. That is, the boundary BDc3 where the upper surface of the uppermost component USLT is in contact with the lower surface of the uppermost component TSLT is located between wiring layer 34d, which functions as word line WL7, and wiring layer 34d, which functions as word line WL8. In other words, the upper level T... UCA With the highest level T TCA The boundary BDc3 is located between wiring layer 34d, which functions as word line WL7, and wiring layer 34d, which functions as word line WL8. In this embodiment, the wiring layers 34 at the respective level boundaries of memory cylinder MP and component SLT are also different from each other.

[0266] The lower component LSLT, the middle component MSLT, the upper component USLT, and the uppermost component TSLT each have a conical shape, for example, with the width in the upper Y direction greater than the width in the lower Y direction. Therefore, each junction can be identified by observing the shape of its cross-section.

[0267] 2.2 Cross-sectional composition of the connection area

[0268] Reference Figure 39 An example of the cross-sectional structure of the connecting region CA will be explained. Figure 39 This is a sectional view showing an example of the cross-sectional structure of the connecting region CA1. Furthermore, in Figure 39 In the example shown, with Figure 7 Similarly, two support pillars HR passing through the step of the select gate line SGD are shown to correspond to the cross-section along line B1-B2. In contrast, for simplicity, a portion of the support pillars HR are omitted at each step of word lines WL0-WL9 and select gate line SGS; only one support pillar HR passing through each step is shown. Although a portion of the support pillars HR is omitted at each step of word lines WL0-WL9 and select gate line SGS, the support pillars HR are configured in the same way as those at the step of select gate line SGD.

[0269] like Figure 39 As shown, the support column HR in this embodiment includes a lower support column LHR, a middle support column MHR, an upper support column UHR, and a topmost support column THR. The middle support column MHR is positioned above the lower support column LHR. The upper support column UHR is positioned above the middle support column MHR. The topmost support column THR is positioned above the upper support column UHR. The support column HR in this embodiment, like component SLT, has a lower hierarchy T. LCA Median level T MCA Upper-level T UCA and the highest level T TCA That is, the support column HR is processed in four stages.

[0270] The lower support post LHR passing through each step of the select gate line SGS and word lines WL0 and WL1 passes through the corresponding step and the wiring layer 34 located below the step. For example, the lower support post LHR passing through the step of the select gate line SGS passes through the wiring layer 34a that functions as the select gate line SGS and the insulating layer 35 disposed on the wiring layer 34a. For example, the lower support post LHR passing through the step of the word line WL1 passes through the three wiring layers 34a and the three insulating layers 35 that function as the select gate line SGS and word lines WL0 and WL1, respectively. Furthermore, the lower support post LHR passing through each step of the select gate line SGS and word line WL0 passes through the insulating layer 37 disposed above the corresponding step. The lower support post LHR disposed below each step of word lines WL2 to WL9 and the select gate line SGD does not pass through the step. These lower support pillars (LHRs) pass beneath the corresponding steps through three wiring layers 34a and three insulating layers 35, which function as the select gate line (SGS) and word lines WL0 and WL1, respectively. The lower end of the lower support pillar (LHR) reaches, for example, the semiconductor layer 32a.

[0271] The center support post MHR, positioned above each step of the select gate line SGS and word lines WL0 and WL1, passes through the insulating layer 37. The center support post MHR, passing through each step of word lines WL2 to WL4, passes through the corresponding step and the center level T located below the step. MCA The wiring layer 34. For example, the center support post MHR passing through the step of word line WL2 passes through the wiring layer 34a that functions as word line WL2, and the insulating layer 35 disposed on the wiring layer 34a. For example, the center support post MHR passing through the step of word line WL4 passes through three wiring layers 34 (the uppermost wiring layer 34a and the second wiring layer 34b) that function as word lines WL2 to WL4, and the three insulating layers 35. Furthermore, the center support post MHR passing through each step of word lines WL2 and WL3 passes through the insulating layer 37 disposed above the step. In addition, the center support post MHR disposed below each step of word lines WL5 to WL9 and the select gate line SGD does not pass through the step. These intermediate support posts (MHRs) pass beneath their corresponding steps through three wiring layers 34 (the uppermost wiring layer 34a and two wiring layers 34b) and three insulation layers 35, which function as word lines WL2 to WL4, respectively. The lower surface of each intermediate support post (MHR) is in contact with the upper surface of its corresponding lower support post (LHR). Specifically, the junction BDc1 between the upper surface of the lower support post (LHR) and the lower surface of the intermediate support post (MHR) is located between wiring layer 34a, which functions as word line WL1, and the uppermost wiring layer 34a, which functions as word line WL2.

[0272] The upper support post UHR, positioned above each step of the select gate line SGS and word lines WL0 to WL4, passes through the insulating layer 37. The upper support post UHR, passing through each step of word lines WL5 to WL7, passes through the corresponding step and the upper level T located below the step. UCA The wiring layer 34. For example, the upper support post UHR passing through the step of word line WL5 passes through the wiring layer 34c that functions as word line WL5 and the insulating layer 35 disposed on the wiring layer 34c. For example, the upper support post UHR passing through the step of word line WL7 passes through the three wiring layers 34 (two wiring layers 34c and the bottom wiring layer 34d) and the three insulating layers 35 that function as word lines WL5 to WL7 respectively. Furthermore, the upper support post UHR passing through each step of word lines WL5 and WL6 passes through the insulating layer 37 disposed above the step. In addition, the upper support post UHR disposed below each step of word lines WL8 and WL9 and the select gate line SGD does not pass through the step. These upper support columns (UHRs) pass beneath their respective steps through three wiring layers 34 (two wiring layers 34c and the bottom wiring layer 34d) and three insulation layers 35, which function as word lines WL5 to WL7. The lower surface of each upper support column (UHR) is in contact with the upper surface of its corresponding middle support column (MHR). Specifically, the junction BDc2 where the upper surface of the middle support column (MHR) meets the lower surface of the upper support column (UHR) is located between the top wiring layer 34b (functioning as word line WL4) and the bottom wiring layer 34c (functioning as word line WL5).

[0273] The uppermost support post THR, positioned above each step of the select gate line SGS and word lines WL0 to WL7, passes through the insulating layer 37. The uppermost support post THR, passing through each step of word lines WL8 and WL9 and the select gate line SGD, passes through the corresponding step and the uppermost layer T located below the step. TCA The wiring layer 34. For example, the uppermost support post THR passing through the step of word line WL8 passes through the wiring layer 34d that functions as word line WL8 and the insulating layer 35 disposed on the wiring layer 34d. For example, the uppermost support post THR passing through the step of select gate line SGD passes through the three wiring layers 34 (three wiring layers 34d) and the three insulating layers 35 that function as word lines WL8 and WL9 and select gate line SGD, respectively. Furthermore, the uppermost support post THR of each step passing through word lines WL8 and WL9 passes through the insulating layer 37 disposed above the step. The lower surface of each uppermost support post THR is in contact with the upper surface of the corresponding upper support post UHR. That is, the junction BDc3 where the upper surface of the upper support post UHR and the lower surface of the uppermost support post THR are in contact is located between the wiring layer 34d that functions as word line WL7 and the wiring layer 34d that functions as word line WL8.

[0274] In this embodiment, the wiring layers 34 at the junction of the memory column MP and the support column HR are also different from each other.

[0275] The lower support column LHR, the middle support column MHR, the upper support column UHR, and the uppermost support column THR each have a conical shape, for example, with the diameter at the upper end larger than the diameter at the lower end. In other words, the lower support column LHR, the middle support column MHR, the upper support column UHR, and the uppermost support column THR each have a frustum-shaped shape, for example, with the lower surface smaller than the upper surface. Therefore, the boundaries of each of the lower support column LHR, the middle support column MHR, the upper support column UHR, and the uppermost support column THR can be identified by observing the shape of their cross-sections.

[0276] Next, the contact plug CC will be explained.

[0277] The contact plug CC includes a lower contact plug LCC, a middle contact plug MCC, a higher contact plug UCC, and a topmost contact plug TCC. A portion of each of the middle contact plug MCCs is disposed above its corresponding lower contact plug LCC. A portion of each of the higher contact plug UCCs is disposed above its corresponding middle contact plug MCC. A portion of each of the topmost contact plug TCCs is disposed above its corresponding higher contact plug UCC. Therefore, the contact plug CC of this embodiment, like the component SLT and the support column HR, has a lower-level TCC. LCA Median level T MCA Upper-level T UCA and the highest level T TCA The resulting structure is that the contact plug CC is processed in four stages.

[0278] The lower-level contact plug (LCC) is positioned on each step of the select gate line SGS and word lines WL0 and WL1. For example, the upper end of the lower-level contact plug (LCC) is located between wiring layer 34a, which functions as word line WL1, and wiring layer 34a, which functions as word line WL2. In other words, the upper end of the lower-level contact plug (LCC) is located at the lower-level layer T. LCA With median level T MCA The boundary BDc1.

[0279] The middle contact plug MCC is disposed above the lower contact plugs LCC corresponding to the select gate line SGS and word lines WL0 and WL1, respectively. Furthermore, the middle contact plug MCC is disposed above each step of word lines WL2 to WL4. The lower surface of the middle contact plug MCC corresponding to the select gate line SGS and word lines WL0 and WL1 is in contact with the upper surface of the lower contact plug LCC. That is, the boundary BDc1 where the upper surface of the lower contact plug LCC and the lower surface of the middle contact plug MCC are in contact is located between the wiring layer 34a functioning as word line WL1 and the wiring layer 34a functioning as word line WL2.

[0280] The upper contact plug UCC is disposed above the middle contact plug MCC corresponding to the select gate line SGS and word lines WL0 to WL4 respectively. Additionally, the upper contact plug UCC is disposed above each step of word lines WL5 to WL7. The lower surface of the upper contact plug UCC corresponding to the select gate line SGS and word lines WL0 to WL4 is in contact with the upper surface of the middle contact plug MCC. That is, the boundary BDc2 where the upper surface of the middle contact plug MCC and the lower surface of the upper contact plug UCC are in contact is located between the wiring layer 34b, which functions as word line WL4, and the wiring layer 34c, which functions as word line WL5.

[0281] The topmost contact plug TCC is positioned above the uppermost contact plugs UCC corresponding to the select gate line SGS and word lines WL0 to WL7, respectively. Furthermore, the topmost contact plug TCC is positioned above each step of word lines WL8 and WL9 and the select gate line SGD. The lower surface of the topmost contact plug TCC corresponding to the select gate line SGS and word lines WL0 to WL7 is in contact with the upper surface of the uppermost contact plug UCC. That is, the boundary BDc3 where the upper surface of the uppermost contact plug UCC and the lower surface of the topmost contact plug TCC meet is located between the wiring layer 34d, which functions as word line WL7, and the wiring layer 34d, which functions as word line WL8. The upper end of the topmost contact plug TCC is located above the uppermost wiring layer 34d, which functions as the select gate line SGD.

[0282] The lower contact plug (LCC), middle contact plug (MCC), upper contact plug (UCC), and uppermost contact plug (TCC) each have a conical shape, for example, with the diameter at the upper end larger than the diameter at the lower end. In other words, the lower contact plug (LCC), middle contact plug (MCC), upper contact plug (UCC), and uppermost contact plug (TCC) each have a frustum-shaped shape, for example, with the lower surface smaller than the upper surface. Therefore, the boundaries of each of the lower contact plug (LCC), middle contact plug (MCC), upper contact plug (UCC), and uppermost contact plug (TCC) can be identified by observing the shape of their cross-sections.

[0283] 2.3 The junction of memory pillars, component SLTs, and support pillars

[0284] Next, refer to Figure 40 The boundaries of the memory column (MP), component (SLT), and support column (HR) are explained. Figure 40 This is a conceptual diagram representing the intersection of memory pillars (MP), components (SLT), and support pillars (HR).

[0285] Figure 40 The comparative example shown in (a) is different from the one using the first embodiment. Figure 8 The comparative examples used for explanation are the same. Hereinafter, explanations will focus on the embodiments.

[0286] like Figure 40 As shown in (b) of the diagram, in this embodiment, the memory column MP has 3 levels. The component SLT and support column HR have 4 levels. In other words, the memory column MP has 2 boundaries BDm1 and BDm2. The component SLT and support column HR have 3 boundaries BDc1, BDc2, and BDc3. That is, the component SLT and support column HR have more levels than the memory column MP.

[0287] In this case, the interlayer positions of the wiring layers 34 containing the junctions BDm1 and BDm2 of the memory pillars MP and the junctions BDc1, BDc2, and BDc3 of the components SLT and support pillars HR are different. More specifically, when using Figure 38 and Figure 39 In the provided description, boundary BDm1 is located between wiring layer 34a, which functions as word line WL2, and wiring layer 34b, which functions as word line WL3. Boundary BDm2 is located between wiring layer 34c, which functions as word line WL6, and wiring layer 34d, which functions as word line WL7. Conversely, boundary BDc1 is located between wiring layer 34a, which functions as word line WL1, and wiring layer 34a, which functions as word line WL2. Boundary BDc2 is located between wiring layer 34b, which functions as word line WL4, and wiring layer 34c, which functions as word line WL5. Boundary BDc3 is located between wiring layer 34d, which functions as word line WL7, and wiring layer 34d, which functions as word line WL8.

[0288] For example, the distance between the top of an adjacent memory column MP (upper memory column UMP) and the top of component SLT (highest component TSLT) is set to L0, the same as in the comparative example (a). The distance between memory column MP at boundary BDm1 and component SLT is set to L1b. The distance between memory column MP at boundary BDm2 and component SLT is set to L2b. Distance L0 and distance L1b are related by L0 < L1b. Similarly, distance L0 and distance L2b are related by L0 < L2b.

[0289] When comparing distance L1a and distance L1b, compared with the method using the first embodiment... Figure 8 The same explanation applies, indicating a relationship of L1a > L1b. Furthermore, when comparing distances L2a and L2b, a relationship of L2a > L2b also exists.

[0290] 2.4 Manufacturing Method of Memory Cell Array

[0291] Next, refer to Figures 41 to 74 An example of a method for manufacturing the memory cell array 11 will be described. Figure 41 and Figure 42 This is a flowchart illustrating an example of the manufacturing process of the memory cell array 11. Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 , Figure 53 , Figure 55 , Figure 57 , Figure 59 , Figure 61 , Figure 63 , Figure 65 , Figure 67 , Figure 69 , Figure 71 ,and Figure 73 This is a diagram illustrating an example of the planar layout of the memory cell array 11 during the manufacturing process of the memory cell array 11. Figure 44 It is along Figure 43 A sectional view of lines A1-A2 and B1-B2. Figure 46 It is along Figure 45 A sectional view of lines A1-A2 and B1-B2. Figure 48 It is along Figure 47 A sectional view of lines A1-A2 and B1-B2. Figure 50 It is along Figure 49 A sectional view of lines A1-A2 and B1-B2. Figure 52 It is along Figure 51 A sectional view of lines A1-A2 and B1-B2. Figure 54 It is along Figure 53 A sectional view of lines A1-A2 and B1-B2. Figure 56 It is along Figure 55 A sectional view of lines A1-A2 and B1-B2. Figure 58 It is along Figure 57 A sectional view of lines A1-A2 and B1-B2. Figure 60 It is along Figure 59 A sectional view of lines A1-A2 and B1-B2. Figure 62 It is along Figure 61A sectional view of lines A1-A2 and B1-B2. Figure 64 It is along Figure 63 A sectional view of lines A1-A2 and B1-B2. Figure 66 It is along Figure 65 A sectional view of lines A1-A2 and B1-B2. Figure 68 It is along Figure 67 A sectional view of lines A1-A2 and B1-B2. Figure 70 It is along Figure 69 A sectional view of lines A1-A2 and B1-B2. Figure 72 It is along Figure 71 A sectional view of lines A1-A2 and B1-B2. Figure 74 It is along Figure 73 The sectional views along lines A1-A2 and B1-B2 are shown below. Furthermore, in the sectional views of the manufacturing process shown below, a portion of the support column HR passing through each step is omitted for simplicity.

[0292] Furthermore, in the following description, the structure consisting of the lower 3 wiring layers 34a and the 3 insulating layers 35 disposed on each of the 12 wiring layers 34 and 12 insulating layers 35 in the laminate is described as the "first laminate". The structure consisting of the uppermost wiring layer 34a and the insulating layer 35 disposed thereon is described as the "second laminate". The structure consisting of 2 wiring layers 34b and the 2 insulating layers 35 disposed on each of them is described as the "third laminate". The structure consisting of 2 wiring layers 34c and the 2 insulating layers 35 disposed on each of them is described as the "fourth laminate". The structure consisting of the lowermost wiring layer 34d and the insulating layer 35 disposed thereon is described as the "fifth laminate". The structure consisting of the uppermost 3 wiring layers 34d and the 3 insulating layers 35 disposed on each of them is described as the "sixth laminate".

[0293] like Figure 41 As shown, the first layer is first formed into a film (S201).

[0294] like Figure 43 and Figure 44 As shown, three sacrificial films 60a and three insulating layers 35 are alternately deposited on top of insulating layer 33, forming the first stacked layer before WL replacement. The three sacrificial films 60a correspond to the lower layer T. LCA In the WL replacement, it is replaced by a 3-layer wiring layer 34a that functions as the select gate line SGS and the word lines WL0 and WL1, respectively.

[0295] like Figure 41 As shown, after executing step S201, a lower-level T is formed that is connected to the region CA. LCAThe corresponding stepped section (S202).

[0296] like Figure 45 and Figure 46 As shown, the first stacked layer is processed with a stepped structure to form a step corresponding to the three sacrificial films 60a. That is, a step corresponding to the select gate line SGS and the word line WL0 is formed.

[0297] like Figure 41 As shown, after step S202, the processing of the lower support column LHR and the filling of the sacrificial membrane 62, the processing of the lower component LSLT and the filling of the sacrificial membrane 63, and the processing of the lower contact plug LCC and the filling of the sacrificial membrane 64 are performed sequentially (S203). Furthermore, the order of processing the lower support column LHR, the lower component LSLT, and the lower contact plug LCC, and the filling of the sacrificial membranes 62 to 64 is arbitrary.

[0298] like Figure 47 and Figure 48 As shown, the stepped portion is filled with insulating layer 37, and planarized, for example, by CMP. Then, in the connection region CA, a hole corresponding to the lower support pillar LHR is formed, and the hole is filled with sacrificial film 62. For example, the lower end of the hole corresponding to the lower support pillar LHR reaches semiconductor layer 32a. Then, a slit corresponding to the lower component LSLT is formed, and the slit is filled with sacrificial film 63. The lower end of the slit corresponding to the lower component LSLT reaches insulating layer 50. Then, in the connection region CA, a hole corresponding to the lower contact plug LCC is formed, and the hole is filled with sacrificial film 64. The lower end of the lower contact plug LCC reaches the step of the corresponding sacrificial film 60a (wiring layer 34a). Furthermore, the lower contact plug LCC is provided in the stepped portions of select gate line SGS and word lines WL0 and WL1, but not in the stepped portions of word lines WL2 to WL9 and select gate line SGD.

[0299] like Figure 41 As shown, after performing step S203, the second laminate is formed (S204). A sacrificial film 60a and an insulating layer 35 are laminated together as the second laminate before WL replacement. The sacrificial film 60a is replaced in the WL replacement as a wiring layer 34a that functions as the word line WL2.

[0300] After performing step S204, compared with the method using the first embodiment... Figure 9 Similarly, in step S102, a memory hole corresponding to the lower memory column LMP is processed (formed), and the memory hole is filled with a sacrificial film 61 (S205).

[0301] like Figure 49 and Figure 50As shown, a memory hole corresponding to the lower memory column LMP is formed in the memory cell region MA. Then, a sacrificial film 61 is used to fill the memory hole.

[0302] like Figure 41 As shown, after performing step S205, the third laminate is formed into a film (S206).

[0303] like Figure 51 and Figure 52 As shown, two sacrificial films 60b and two insulating layers 35 are stacked alternately layer by layer to form the third stack before WL replacement. In WL replacement, the two sacrificial films 60b are replaced by two wiring layers 34b that function as word lines WL3 and WL4, respectively.

[0304] like Figure 41 As shown, after executing step S206, a median level T is formed with respect to the connected region CA. MCA The corresponding stepped section (S207).

[0305] like Figure 53 and Figure 54 As shown, the second and third laminates are processed in a stepped manner to form steps corresponding to the sacrificial film 60a and the two sacrificial films 60b. That is, steps corresponding to the word lines WL1 and WL3 are processed.

[0306] like Figure 41 As shown, after step S207, the processing of the center support column MHR and the embedding of the sacrificial membrane 62, the processing of the center component MSLT and the embedding of the sacrificial membrane 63, and the processing of the center contact plug MCC and the embedding of the sacrificial membrane 64 are performed sequentially (S208). Furthermore, the order in which the center support column MHR, the center component MSLT, and the center contact plug MCC are processed and the sacrificial membranes 62 to 64 are embedded is arbitrary.

[0307] like Figure 55 and Figure 56 As shown, the stepped portion is filled with insulating layer 37, and planarized, for example, by CMP. Then, in the connection region CA, a hole corresponding to the center support post MHR is formed, and the hole is filled with sacrificial membrane 62. Then, a slit corresponding to the center component MSLT is formed, and the slit is filled with sacrificial membrane 63. Then, in the connection region CA, a hole corresponding to the center contact plug MCC is formed, and the hole is filled with sacrificial membrane 64.

[0308] like Figure 41 As shown, after performing step S208, the fourth stacked body is formed into a film (S209).

[0309] like Figure 57 and Figure 58As shown, two sacrificial films 60c and two insulating layers 35 are stacked alternately layer by layer, forming the fourth stack before WL replacement. In WL replacement, the two sacrificial films 60c are replaced by two wiring layers 34c that function as word lines WL5 and WL6, respectively.

[0310] like Figure 41 As shown, after performing step S209, compared with the method using the first embodiment... Figure 9 Similarly, in step S107, a memory hole corresponding to the center memory column MMP is machined (formed), and the memory hole is filled with a sacrificial film 61 (S210).

[0311] like Figure 59 and Figure 60 As shown, a memory hole corresponding to the middle memory column MMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the middle memory column MMP reaches the lower memory column LMP. Then, a sacrificial film 61 is used to fill the memory hole corresponding to the middle memory column MMP. In other words, a stacked structure of the lower memory column LMP and the middle memory column MMP filled by the sacrificial film 61 is formed.

[0312] like Figure 41 As shown, after performing step S210, the fifth laminate is formed into a film (S211).

[0313] like Figure 61 and Figure 62 As shown, a sacrificial film 60d and an insulating layer 35 are stacked together as the fifth stack before WL replacement. In WL replacement, the sacrificial film 60d is replaced by a wiring layer 34d that functions as the word line WL7.

[0314] like Figure 42 As shown, after executing step S211, a higher-level T is formed that is connected to the region CA. UCA The corresponding stepped section (S212).

[0315] like Figure 63 and Figure 64 As shown, the fourth and fifth laminates are processed in a stepped manner to form steps corresponding to the two sacrificial films 60c and the one sacrificial film 60d. That is, steps corresponding to the word lines WL4 and WL6 are processed.

[0316] like Figure 42As shown, after step S212, the processing of the upper support column UHR and the filling of the sacrificial membrane 62, the processing of the upper component USLT and the filling of the sacrificial membrane 63, and the processing of the upper contact plug UCC and the filling of the sacrificial membrane 64 are performed sequentially (S213). Furthermore, the order of processing the upper support column UHR, the upper component USLT, and the upper contact plug UCC, and the filling of the sacrificial membranes 62 to 64, is arbitrary.

[0317] like Figure 65 and Figure 66 As shown, the stepped portion is filled with insulating layer 37, and planarized, for example, by CMP. Then, in the connection region CA, a hole corresponding to the upper support post UHR is formed, and the hole is filled with sacrificial film 62. Then, a slit corresponding to the upper component USLT is formed, and the slit is filled with sacrificial film 63. Then, in the connection region CA, a hole corresponding to the upper contact plug UCC is formed, and the hole is filled with sacrificial film 64.

[0318] like Figure 42 As shown, after performing step S213, the sixth stacked body is formed into a film (S214).

[0319] like Figure 67 and Figure 68 As shown, three sacrificial films 60d and three insulating layers 35 are stacked alternately layer by layer to form the sixth stack before WL replacement. In WL replacement, the three sacrificial films 60d are replaced by three wiring layers 34d that function as word lines WL8 and WL9 and select gate line SGD, respectively.

[0320] like Figure 42 As shown, after executing step S214, the highest level T of the connection region CA is formed. TCA The corresponding stepped section (S215).

[0321] like Figure 69 and Figure 70 As shown, the sixth laminate is processed in a stepped manner to form a step corresponding to the three sacrificial films 60d. That is, a step corresponding to the word lines WL7 to WL9 is formed.

[0322] like Figure 42 As shown, after step S215, the processing of the uppermost support column THR and the filling of the sacrificial membrane 62, the processing of the uppermost component TSLT and the filling of the sacrificial membrane 63, and the processing of the uppermost contact plug TCC and the filling of the sacrificial membrane 64 are performed sequentially (S216). Furthermore, the order in which the processing of the uppermost support column THR, the uppermost component TSLT, and the uppermost contact plug TCC, and the filling of the sacrificial membranes 62 to 64 are arbitrary.

[0323] like Figure 71and Figure 72 As shown, the stepped portion is filled with insulating layer 37, and planarized, for example, by CMP. Then, in the connection region CA, a hole corresponding to the uppermost support post THR is formed, and the hole is filled with sacrificial membrane 62. Thus, the support post HR filled with sacrificial membrane 62 is formed. Then, a slit corresponding to the uppermost component TSLT is formed, and the slit is filled with sacrificial membrane 63. Thus, the component SLT filled with sacrificial membrane 63 is formed. Then, in the connection region CA, a hole corresponding to the uppermost contact plug TCC is formed, and the hole is filled with sacrificial membrane 64. Thus, the contact plug CC filled with sacrificial membrane 64 is formed.

[0324] like Figure 42 As shown, after performing step S216, compared with the first embodiment... Figure 9 Similarly, in step S111, a memory hole corresponding to the upper memory column UMP is machined (formed) to form the memory column MP (S217).

[0325] like Figure 73 and Figure 74 As shown, a memory hole corresponding to the upper memory column UMP is formed in the memory cell region MA. The lower end of the memory hole corresponding to the upper memory column UMP reaches the middle memory column MMP. Then, the sacrificial film 61 inside the memory hole is removed. Then, a multilayer film 42, a semiconductor film 41, and a core film 40 are formed and buried inside the memory hole to form the memory column MP.

[0326] like Figure 42 As shown, after performing step S217, compared with the first embodiment... Figure 9 Similarly, in step S112, the sacrificial membrane 62 inside the support column HR is removed, and the hole is filled with insulator 38 (S218).

[0327] Then, with the method using the first embodiment Figure 9 Similarly, in step S113, the sacrificial film 63 within the component SLT is removed (S219).

[0328] Then, with the method using the first embodiment Figure 9 Similarly, in step S114, the SL permutation and WL permutation are performed sequentially (S220).

[0329] Then, with the method using the first embodiment Figure 9 Similarly, in step S115, the spacer SP and conductor LI are used to fill the component SLT (S221).

[0330] Then, with the method using the first embodiment Figure 9Similarly, in step S116, the sacrificial film 64 inside the contact plug CC is removed, and the hole is filled with the conductor 39 (S222). Thus, a device is formed for use. Figure 38 and Figure 39 The structure of the storage cell array 11 described herein.

[0331] 2.5 Effects of this implementation method

[0332] If the configuration of this embodiment is used, then the same effect as the first embodiment can be obtained.

[0333] 3. Third Implementation Method

[0334] Next, the third embodiment will be described. In the third embodiment, the structure of the contact plug CC, which differs from that of the first embodiment, will be described. Hereinafter, the description will focus on the differences from the first embodiment.

[0335] 3.1 Plan layout of the connecting area

[0336] First, refer to Figure 75 An example of the planar layout of the connecting region CA1 is illustrated. Figure 75 This is a top view showing an example of the planar layout of the connecting area CA1. Figure 75 This represents a portion of the connection region CA1 corresponding to one block BLK, and the nearby storage cell region MA. Furthermore, in Figure 75 In the example shown, for simplicity, one component SHE is set within the block BLK. That is, the block BLK contains two string components SU. Additionally, in Figure 75 In the example shown, a portion of the interlayer insulating film is omitted.

[0337] like Figure 75 As shown, similar to the first embodiment, steps corresponding to the select gate line SGD, word lines WL9 to WL0, and select gate line SGS are sequentially provided at the end of the connection region CA1 from the memory cell region MA in the X direction (right side of the paper).

[0338] The memory column MP, components SLT and SHE of the memory cell region MA, and the support column HR of the connection region CA1 are configured and arranged in the same way as in the first embodiment.

[0339] In this embodiment, the contact plug CC extends along the Z direction and penetrates the corresponding step of the wiring layer 34 and the contact of the wiring layer 34 below it. For example, the contact plug CC has a protrusion that protrudes concentrically in the XY plane at the connection portion with the corresponding step. The contact plug CC is electrically connected to the corresponding step via the protrusion, but not electrically connected to the wiring layer 34 below. In addition, the lower end of each contact plug CC reaches the semiconductor layer 32, but is not electrically connected to the semiconductor layer 32. That is, the contact plug CC is electrically connected to the step of the wiring layer 34 corresponding to any one of the select gate line SGS, word lines WL0 to WL9, and select gate line SGD.

[0340] 3.2 Cross-sectional composition of the connection area

[0341] Next, refer to Figure 76 An example of the cross-sectional structure of the connecting region CA will be explained. Figure 76 It is along Figure 75 A cross-sectional view of the connection area CA1 of lines B1-B2. Furthermore, in Figure 76 In the example shown, the support column HR is omitted for the sake of simplicity.

[0342] like Figure 76 As shown, a stepped portion consisting of multiple wiring layers 34 steps (plug connection portions) is formed in the connection area CA. In this embodiment, the steps of the wiring layers 34 are thickened. That is, the wiring layer 34 includes a first portion P1 extending in the central part along the X direction and a second portion P2 disposed at the end (step) of the first portion P1 in the X direction. The film thickness of the second portion P2 is thicker than that of the first portion P1. No other second portions P2 of the wiring layers 34 (thick film portions) are disposed above or below the second portion P2. The second portions P2 of the multiple wiring layers 34 are arranged side by side in the X direction. Two adjacent second portions P2 in the X direction are separated from each other by a distance LS in the X direction, so that they are not electrically connected. Furthermore, the distance LS is arbitrary.

[0343] The contact plug CC passes through the corresponding second part P2 (step) and the first part P1 of the other wiring layers 34 located below the second part P2. Hereinafter, this contact plug CC will also be referred to as a "through contact". The height of the contact plug CC corresponding to each step is approximately the same. The contact plug CC has a protrusion PR disposed on the same layer as the second part P2. The protrusion PR has a generally cylindrical shape. The side of the protrusion PR is in contact with the second part P2. Furthermore, the lower surface of the protrusion PR can also be electrically connected to the step. The film thickness (height) of the protrusion PR is approximately the same as that of the second part P2.

[0344] An insulator 71 is provided between the contact plug CC and the first portion P1 of the wiring layer 34 through which the contact plug CC passes. The insulator 71 has an annular shape surrounding the side of the contact plug CC. The contact plug CC is not electrically connected to the first portion P1 of the wiring layer 34 through the insulator 71.

[0345] The lower end of the contact plug CC reaches, for example, semiconductor layer 32a. An insulator 70 is disposed between semiconductor layers 32a and 32c of the contact plug CC. The insulator 70, disposed in the same layer as semiconductor layer 32c, surrounds the side surface of the contact plug CC. The insulator 70, disposed in the same layer as semiconductor layer 32a, surrounds the side surface and bottom surface of the contact plug CC. The contact plug CC is not electrically connected to semiconductor layer 32 through the insulator 70. For example, insulators 70 and 71 comprise silicon oxide.

[0346] The contact plug CC, like in the first embodiment, includes a lower contact plug LCC and an upper contact plug UCC.

[0347] 3.3 Manufacturing method of contact plug

[0348] Next, refer to Figures 77-81 The manufacturing method of the contact plug CC is explained. Figures 77-81 This is a diagram showing an example of the cross-sectional configuration of the connection region CA in the manufacturing process of the memory cell array 11. In the following description, the process up to the fabrication of the lower contact plug LCC and its filling by the sacrificial film 64 will be explained. Furthermore, in the cross-sectional view of the manufacturing process shown below, the support column HR is omitted for simplicity.

[0349] The overall process of manufacturing the memory cell array 11 according to the third embodiment is the same as that using the first embodiment. Figure 9 The flowcharts described are the same. The step processing in step S104, the processing method of the lower contact plug LCC in step S105, the step processing in step S109, and the processing method of the upper contact plug UCC in step S110 are different from those in the first embodiment.

[0350] like Figure 77 As shown, for example, in conjunction with the first embodiment. Figure 9 The steps S101 to S103 described herein are performed in the same manner to form the lower layer of the intermediate stack. Then, in step S104, the lower layer T connected to the CA is first processed. LCAThe corresponding stepped portion. More specifically, the lower layers of the lower and middle stacked bodies are stepped to form steps corresponding to the multiple sacrificial films 60a and 60b respectively. Then, the second part P2 composed of sacrificial films 60a and 60b is formed. More specifically, after exposing the steps of sacrificial films 60a and 60b, sacrificial film 60 is formed, covering the entire surface. Then, sacrificial film 60 is processed to form the second part P2.

[0351] like Figure 78 As shown, firstly, the stepped portion is filled with insulating layer 37, and planarized, for example, by CMP. Then, using the first embodiment... Figure 9 In the processing of the lower contact plug LCC and the filling process of the sacrificial film 64 described in step S105, holes corresponding to the lower contact plug LCC are formed. In this embodiment, holes corresponding to the lower contact plug LCC are formed at positions corresponding to each step of the select gate line SGS, word lines WL0 to WL9, and select gate line SGD. The lower end of each hole reaches the semiconductor layer 32a. Then, the semiconductor layers 32a and 32c exposed on the lower side of the holes corresponding to the lower contact plug LCC are oxidized to form an insulator 70.

[0352] like Figure 79 As shown, groove etching of sacrificial films 60a and 60b is performed from the side of the hole corresponding to the lower contact plug LCC.

[0353] like Figure 80 As shown, an insulator 71 is formed to fill the groove regions corresponding to the first portion P1 of the sacrificial films 60a and 60b. More specifically, for example, the insulator 71 is conformally formed with a film thickness of at least half the thickness of the first portion P1 and less than half the thickness of the second portion P2. Thus, the groove portion of the first portion P1 is filled with the insulator 71, while the groove portion of the second portion P2 is not filled with the insulator 71. In this state, wet etching of the insulator 71 is performed to remove the insulator 71 from the side of the hole corresponding to the lower contact plug LCC and the groove portion of the second portion P2.

[0354] like Figure 81 As shown, the sacrificial membrane 64 is used to fill the hole corresponding to the lower contact plug LCC.

[0355] Steps S106 to S108 are related to the use of the first embodiment. Figure 9 The explanations are the same.

[0356] In steps S109 and S110, the through contact plug CC, which is filled by the sacrificial membrane 64, is formed by performing the same process as in steps S104 and S105.

[0357] The processes following step S111 are the same as those using the first embodiment. Figure 9 The explanations are the same.

[0358] 3.4 Effects of this implementation method

[0359] If the effect is the same as that of this embodiment, then the same effect as that of the first embodiment can be obtained.

[0360] 3.5 Examples of variations in the third embodiment

[0361] Next, two variations of the third embodiment will be described. In these two variations, the film thicknesses of the insulating layers 35 formed on the plurality of wiring layers 34 are different. Hereinafter, the description will focus on the differences from the third embodiment.

[0362] 3.5.1 Example of the first variation

[0363] First, the first variation example will be explained. In the first variation example, for each level (lower level T) LMP Median level T MMP Upper-level T UMP Lower level T LCA and higher-level T UCA The case where the thickness of the uppermost insulating layer 35 is thicker than that of the other insulating layers 35 will be explained.

[0364] Reference Figure 82 and Figure 83 An example of the cross-sectional configuration of the memory cell array 11 will be described. Figure 82 This is a diagram illustrating an example of the cross-sectional structure of the memory cell region MA. Figure 83 This is a diagram illustrating an example of the cross-sectional structure of the connecting region CA1. Furthermore, in Figure 83 In the example shown, the support column HR is omitted for the sake of simplicity.

[0365] like Figure 82 and Figure 83 As shown, in this variation, when the laminate is formed into a film (corresponding to...) Figure 9In steps S101, S103, S106, and S108, the uppermost insulating layer 35 is made thicker than the lower insulating layer 35. Other manufacturing methods are the same as in the third embodiment. More specifically, for example, in step S101, when the lower layer is formed, the insulating layer 35 disposed above the sacrificial film 60a that is to be replaced as the wiring layer 34a functioning as word line WL2 is made thicker than the lower insulating layer 35. In step S103, when the lower layer of the middle layer is formed, the insulating layer 35 disposed above the sacrificial film 60b that is to be replaced as the wiring layer 34b functioning as word line WL4 is made thicker than the lower insulating layer 35. In step S106, when the upper layer of the middle layer is formed, the insulating layer 35 disposed above the sacrificial film 60c that is to be replaced as the wiring layer 34c functioning as word line WL6 is made thicker than the lower insulating layer 35. In step S108, when the upper stacked body is formed, the insulating layer 35 disposed above the sacrificial film 60d, which is to be replaced as the wiring layer 34d that functions as the select gate line SGD, is made thicker than the lower insulating layer 35.

[0366] For example, the thickness of each insulating layer 35 disposed on the wiring layer 34, which is to be replaced respectively as word lines WL2, WL4, and WL6, and as the select gate line SGD, is set to T1. Furthermore, the thickness of the other insulating layers 35 is set to T2. In this case, there is a relationship between film thickness T1 and film thickness T2: T1 > T2. Moreover, the insulating layers 35 to be thickened are not limited to these. For example, the uppermost insulating layer 35 in each step processing may be thicker than the lower insulating layer 35, corresponding to the number of step processing operations performed in the connection region CA.

[0367] 3.5.2 Second Variation Example

[0368] Next, the second variation will be explained. In the second variation, the lower level T corresponding to the connecting region CA... LCA and the higher level T UCA The case where the thickness of the uppermost insulating layer 35 is thicker than that of the other insulating layers 35 will be explained.

[0369] Reference Figure 84 and Figure 85 An example of the cross-sectional configuration of the memory cell array 11 will be described. Figure 84 This is a diagram illustrating an example of the cross-sectional structure of the memory cell region MA. Figure 85 This is a diagram illustrating an example of the cross-sectional structure of the connecting region CA1. Furthermore, in Figure 85 In the example shown, the support column HR is omitted for the sake of simplicity.

[0370] like Figure 84 and Figure 85As shown, in this variation, when the lower and upper layers of the intermediate laminate are formed into a film (corresponding to...) Figure 9 In steps S103 and S108), the uppermost insulating layer 35 is made thicker than the lower insulating layer 35. Other manufacturing methods are the same as in the third embodiment. More specifically, for example, in step S103, when the lower layer of the intermediate stack is formed, the insulating layer 35 disposed above the sacrificial film 60b, which is to be replaced as the wiring layer 34b functioning as the word line WL4, is made thicker than the lower insulating layer 35. Furthermore, in step S108, when the upper stack is formed, the insulating layer 35 disposed above the sacrificial film 60d, which is to be replaced as the wiring layer 34d functioning as the select gate line SGD, is made thicker than the lower insulating layer 35.

[0371] For example, the thickness of each insulating layer 35 disposed on the wiring layer 34, which is to be replaced respectively to function as word line WL4 and select gate line SGD, is set to T1. Furthermore, the thickness of the other insulating layers 35 is set to T2. In this case, there is a relationship between film thickness T1 and film thickness T2: T1 > T2.

[0372] 3.5.3 Effects of the first and second variations

[0373] If the configuration is the first variation and the second variation, then the same effect as the first embodiment can be obtained.

[0374] In the configuration of the first variation, by thickening a portion of the thickness of the plurality of insulating layers 35, it is possible to suppress the thinning of the insulating layers 35 caused by processes such as the processing of memory pillars MP, components SLT, support pillars HR, and contact plugs CC, or by planarization of the insulating layers 37 using CMP, etc. Furthermore, in the configuration of the first variation, by thickening the insulating layer 35 corresponding to the boundary between the two layers, for example, it is possible to ensure the formation of a connection portion between the lower memory pillar LMP and the middle memory pillar MMP.

[0375] If the configuration is the second variation, then the thinning of the insulating layer 35 can be suppressed, for example, due to the processing of the component SLT, support post HR, and contact plug CC, or due to the planarization of the insulating layer 37 using CMP, etc.

[0376] Furthermore, the first and second variations can be applied to either the first or second embodiment.

[0377] 4. Fourth Implementation Method

[0378] Next, the fourth embodiment will be described. In the fourth embodiment, the structure of the memory cell array 11, which differs from that of the first and third embodiments, will be described. Hereinafter, the description will focus on the differences from the first and third embodiments.

[0379] 4.1 Plan layout of the connecting area

[0380] First, refer to Figure 86 An example of the planar layout of the connecting region CA1 is illustrated. Figure 86 This is a top view showing an example of the planar layout of the connecting area CA1. Figure 86 This represents a portion of the connection region CA1 corresponding to one block BLK, and the nearby storage cell region MA. Furthermore, in Figure 86 In the example shown, for the sake of simplicity, one component SHE is set within the block BLK. That is, the block BLK contains two string components SU.

[0381] like Figure 86 As shown, in the connection region CA1, from the memory cell region MA in the X direction (right side of the paper), there are sequentially arranged plug connection portions corresponding to the select gate line SGD, word lines WL9 to WL0, and select gate line SGS, respectively. However, in this embodiment, a step formed by a stacked body is not formed in the connection region CA. That is, no step is provided. In this embodiment, other wiring layers 34 are provided above the plug connection portions corresponding to the select gate line SGS and word lines WL0 to WL9.

[0382] The planar layout of the memory column MP, components SLT and SHE, support column HR, and contact plug CC is the same as in the first embodiment.

[0383] In this embodiment, the contact plug CC extends along the Z direction and passes through the wiring layer 34 located above the plug connection portion of the corresponding wiring layer 34, with its lower end connected to the plug connection portion. Therefore, similar to the first embodiment, the height of the contact plug CC varies depending on the corresponding plug connection portion (wiring layer 34). A sidewall made of an insulator is provided on the side of the contact plug CC. The contact plug CC is not electrically connected to the wiring layer 34 located above the plug connection portion through the sidewall. That is, the contact plug CC is electrically connected to the plug connection portion of the wiring layer 34 corresponding to any one of the select gate line SGS, word lines WL0 to WL9, and select gate line SGD.

[0384] 4.2 Cross-sectional composition of the connection area

[0385] Next, refer to Figure 87 An example of the cross-sectional structure of the connecting region CA will be explained. Figure 87 It is along Figure 86 A cross-sectional view of the connection area CA1 of lines B1-B2. Furthermore, in Figure 87 In the example shown, with Figure 7 Similarly, two support posts HR passing through the plug connection portion of the select gate line SGD are shown to correspond to the cross-section along line B1-B2. In contrast, for simplicity, a portion of the support posts HR is omitted at each plug connection portion of word lines WL0-WL9 and select gate line SGS; only one support post HR passing through each plug connection portion is shown. Although a portion of the support posts HR is omitted at each plug connection portion of word lines WL0-WL9 and select gate line SGS, the support posts HR are configured in the same way as those at the plug connection portion of the select gate line SGD.

[0386] like Figure 87 As shown, in this embodiment, the connection region CA does not form a stepped structure composed of multiple wiring layers 34. In other words, the ends of the multiple wiring layers 34 in the X direction do not extend in a stepped manner. The lengths of each wiring layer 34 in the X direction are approximately the same. Therefore, in this embodiment, the insulation layer 37 is removed.

[0387] In this embodiment, the support column HR includes a lower support column LHR, a middle support column MHR, and an upper support column UHR. The middle support column MHR is disposed above the lower support column LHR. The upper support column UHR is disposed above the middle support column MHR. In this embodiment, the boundary positions of the hierarchical levels in the memory column MP and the support column HR are the same. That is, the support column HR and the memory column MP both have a lower level T. LMP Median level T MMP and higher-level T UMP The structure is three-tiered. The support pillars HR and memory pillars MP are similarly processed in three stages. Furthermore, in... Figure 87 In the example shown, the support pillar HR is filled with insulator 38, but it could also have the same structure as the memory pillar MP. That is, the support pillar HR could also be filled with core film 40, semiconductor film 41, and stacked film 42. In the connection region CA, SL replacement is not performed, that is, the insulating layer 50 is not replaced with semiconductor layer 32b. Therefore, even if the support pillar HR has the same structure as the memory pillar MP, the support pillar HR is not electrically connected to the semiconductor layer 32.

[0388] The lower support column LHR passes through the lower level T in the same way as the lower memory column LMP. LMP That is, the lower support post LHR passes through the four wiring layers 34a, which function as the select gate line SGS and word lines WL0 to WL2, respectively. The lower surface of the lower support post LHR reaches, for example, the semiconductor layer 32a.

[0389] The median support column MHR and the median memory column MMP both pass through the median level T. MMP That is, the middle support post MHR passes through two wiring layers 34b, which function as word lines WL3 and WL4 respectively, and two wiring layers 34c, which function as word lines WL5 and WL6 respectively. The lower surface of the middle support post MHR is in contact with the upper surface of the lower support post LHR at the junction BDm1.

[0390] The upper support column UHR and the upper memory column UMP both pass through the upper hierarchy T. UMP That is, the upper support post UHR passes through the four wiring layers 34d, which function as word lines WL7 to WL9 and select gate line SGD, respectively. The lower surface of the upper support post UHR is in contact with the upper surface of the middle support post MHR at the junction BDm2.

[0391] The lower support column LHR, the middle support column MHR, and the upper support column UHR each have a conical shape, for example, with the diameter at the upper end larger than the diameter at the lower end. In other words, the lower support column LHR, the middle support column MHR, and the upper support column UHR each have a frustum-shaped shape, for example, with the lower surface smaller than the upper surface. Therefore, the junctions BDm1 and BDm2 of the lower support column LHR, the middle support column MHR, and the upper support column UHR can be identified by observing the shape of their cross-sections.

[0392] Next, the contact plug CC will be described. In the connection area CA, a corresponding contact plug CC is provided above the plug connection portion of each wiring layer 34. In other words, the lower end of the contact plug CC is in contact with the plug connection portion of the corresponding wiring layer 34. The contact plug CC extends along the Z direction. The contact plug CC passes through the wiring layer 34 located above the corresponding plug connection portion. The shape (height) of the contact plug CC varies depending on the connected plug connection portion. The contact plug CC includes a conductor 39 and an insulator 72 covering the side surface of the conductor 39. The bottom surface of the conductor 39 is in contact with the corresponding plug connection portion. The side surface of the contact plug CC is not electrically connected to the wiring layer 34 through which it passes via the insulator 72. For example, the insulator 72 contains silicon oxide.

[0393] The contact plug CC, like in the first embodiment, includes a lower contact plug LCC and an upper contact plug UCC. Hereinafter, the case where the boundary position of the layers of the contact plug CC is the same as that of the component SLT, as in the first embodiment, will be described. Furthermore, the component SLT may have a boundary position that is the same as that of the memory cylinder MP and the support cylinder HR, or it may have a boundary position that is different from that of the memory cylinder MP, the support cylinder HR, and the contact plug CC.

[0394] 4.3 The junction of the support column and the contact plug

[0395] Next, refer to Figure 88 The interface between the support column HR and the contact plug CC is explained. Figure 88 This is a conceptual diagram showing the junction of the support column HR and the contact plug CC. Figure 88 In the comparative example, the case where the support post HR and the contact plug CC each have the same number of intersections is shown. Furthermore, in both the comparative example and the embodiment, the support post HR has the same shape and the same number of intersections.

[0396] First, let's explain the comparative examples.

[0397] like Figure 88 As shown in (a) above, for example in the comparative example, the number of layers (intersections) of the support post HR and the contact plug CC is the same. In this case, the layer intersections of the support post HR and the contact plug CC are located between the same wiring layers 34.

[0398] For example, the support column HR includes the lower support column LHR, the middle support column MHR, and the upper support column UHR. The contact plug CC includes the lower contact plug LCC, the middle contact plug MCC, and the upper contact plug UCC. For example, the boundary BDm1 between the lower support column LHR and the middle support column MHR is the same as the boundary between the lower contact plug LCC and the middle contact plug MCC. In addition, the boundary BDm2 between the middle support column MHR and the upper support column UHR is the same as the boundary between the middle contact plug MCC and the upper contact plug UCC.

[0399] For example, let L5 be the distance between the upper end of the adjacent support post HR (upper support post UHR) and the upper end of the contact plug CC (upper contact plug UCC). Let L6a be the distance between the middle support post MHR near the junction BDm1 and the middle contact plug MCC. Let L7a be the distance between the upper support post UHR near the junction BDm2 and the upper contact plug UCC. Each of the support posts HR and the contact plug CC has a conical shape in its respective division. Therefore, distance L5 < L6a. Similarly, distance L5 < L7a.

[0400] Next, the embodiments will be described.

[0401] like Figure 88 As shown in (b) of the diagram, in this embodiment, the support post HR has 3 levels. The contact plug CC has 2 levels. In other words, the support post HR has 2 junctions BDm1 and BDm2. The contact plug CC has 1 junction BDc1. That is, the support post HR and the contact plug CC have different numbers of levels (junctions).

[0402] In this case, if using Figure 87 As explained, the interlayer positions of the wiring layer 34 where the junctions BDm1 and BDm2 of the support column HR and the junction BDc1 of the contact plug CC are located are different.

[0403] The support column HR and the contact plug CC each have a conical shape in their respective sections (levels).

[0404] For example, the distance between the upper end of the adjacent support post HR (upper support post UHR) and the upper end of the contact plug CC (upper contact plug UCC) is set to L5, the same as in the comparative example (a). The distance between the support post HR and the contact plug CC at the junction BDm1 is set to L6b. The distance between the support post HR and the contact plug CC at the junction BDm2 is set to L7b. There is a relationship between distance L5 and distance L6b: L5 < L6b. Similarly, there is a relationship between distance L5 and distance L7b: L5 < L7b.

[0405] In the comparative example of (a), for example, at the junction BDm1, the diameter of the middle contact plug MCC is the smallest. In contrast, in the embodiment of (b), the junction BDm1 is located in the middle of the lower contact plug LCC. Therefore, when comparing distance L6a and distance L6b, L6a > L6b. Similarly, in the comparative example of (a), at the junction BDm2, the diameter of the upper contact plug UCC is the smallest. In contrast, in the embodiment of (b), the junction BDm2 is located in the middle of the upper contact plug UCC. Therefore, when comparing distance L7a and distance L7b, L7a > L7b.

[0406] Therefore, with the configuration of this embodiment, the increase in the distance between the support post HR and the contact plug CC can be suppressed by the conical shape. In other words, by setting the boundary between the support post HR and the contact plug CC in the interlayer of different wiring layers 34, the increase in the distance between the support post HR and the contact plug CC can be suppressed. In the configuration of this embodiment, the contact plug CC passes through the wiring layer 34 located above the plug connection portion. Therefore, the contact plug CC, like the support post HR, functions as a post supporting the lamination structure with gaps during WL replacement. By suppressing the increase in the distance between the support post HR and the contact plug CC, the deflection of the lamination body above the plug connection portion caused by WL replacement can be suppressed.

[0407] 4.4 Manufacturing Method of Memory Cell Array

[0408] Next, refer to Figures 89-98 The manufacturing method of the storage cell array 11 will be described. Figure 89 This is a flowchart illustrating an example of the manufacturing process of the memory cell array 11. Figures 90-98This is a diagram illustrating an example of the cross-sectional configuration of the connection region CA during the manufacturing process of the memory cell array 11. Furthermore, in Figures 90-98 In the example shown, the support post HR is omitted for simplicity. The following description focuses on the process of machining the contact plug CC.

[0409] like Figure 89 As shown, for example, with the use of the first embodiment Figure 9 The described step S101 is similarly formed into the lower-level stacked body.

[0410] After step S101, the processing of the lower support post LHR and the filling of the sacrificial film 62, and the processing of the lower memory post LMP and the filling of the sacrificial film 61 are performed sequentially (S301). Furthermore, the order in which the processing of the lower support post LHR and the lower memory post LMP, and the filling of the sacrificial films 61 and 62 are performed is arbitrary. Alternatively, the lower support post LHR and the lower memory post LMP can be processed together. In this case, the holes corresponding to the lower support post LHR and the lower memory post LMP can be filled with the same sacrificial material.

[0411] After performing step S301, compared with the method using the first embodiment... Figure 9 The same process is performed to form the lower layer of the mesostratum (S103).

[0412] After step S103, the processing of the lower component LSLT and the filling of the sacrificial film 63, and the processing of the lower contact plug LCC and the filling of the sacrificial film 64 are performed sequentially (S302). Furthermore, the order of processing the lower component LSLT and the lower contact plug LCC and the filling of the sacrificial films 63 and 64 is arbitrary. In this embodiment, when forming holes corresponding to the lower contact plug LCC and the upper contact plug UCC, the hole processing is performed multiple times. More specifically, while increasing the number of wiring layers 34 processed by one step by a power of 2, the selected holes are repeatedly etched, thereby forming multiple holes with different heights (depths).

[0413] Reference Figures 90-93 The processing method of the lower contact plug LCC is explained in detail.

[0414] like Figure 90 As shown, firstly, holes corresponding to the uppermost insulating layer 35 are machined in the plug connection portions of the select gate line SGS and word lines WL0 to WL4. Figure 90 (As shown in the 0L processing). At this stage, the sacrificial membrane 60 is not processed. Thus, the formation of the hole in the lower contact plug LCC corresponding to the plug connection portion of the word line WL4 is completed.

[0415] like Figure 91As shown, in the selected gate line SGS and word lines WL1 and WL3, the inner hole of the hole is processed with a sacrificial film 60 and an insulating layer 35. Figure 91 (As shown in the 1L processing). That is, for 2 0 =1 layer of sacrificial film 60 is processed. Thus, the hole of the lower contact plug LCC corresponding to the plug connection portion of word line WL3 is formed.

[0416] like Figure 92 As shown, the two sacrificial films 60 and two insulating layers 35 inside the holes are processed at the plug connection portions of word lines WL1 and WL2. Figure 92 The 2L process shown). That is, for 2 1 =2 layers of sacrificial film 60 are processed. Thus, the hole of the lower contact plug LCC corresponding to the plug connection part of each word line WL1 and WL2 is completed.

[0417] like Figure 93 As shown, the four sacrificial films 60 and four insulating layers 35 inside the holes are processed at the plug connection portions of the selected gate line SGS and word line WL0. Figure 93 (As shown in the 4L processing). That is, for 2 2 A 4-layer sacrificial film 60 is processed. This completes the formation of the holes for the lower contact plugs LCC corresponding to the plug connection portions of the select gate line SGS and word line WL0. After the 4L processing, the sacrificial film 64 is used to fill the holes corresponding to the lower contact plugs LCC.

[0418] After performing step S302, compared with the method using the first embodiment... Figure 9 The same procedure was performed to form a film in the upper layer of the median lamination (S106).

[0419] After step S106, the processing of the center support post MHR and the filling of the sacrificial film 62, and the processing of the center memory post MMP and the filling of the sacrificial film 61 are performed sequentially (S303). Furthermore, the order in which the center support post MHR and the center memory post MMP are processed and the sacrificial films 61 and 62 are filled is arbitrary. Alternatively, the center support post MHR and the center memory post MMP can be processed together. In this case, the holes corresponding to the center support post MHR and the center memory post MMP can be filled with the same sacrificial material.

[0420] After performing step S303, compared with the first embodiment... Figure 9 The same procedure was performed to form a film from the superstructure (S108).

[0421] After step S108, the processing of the upper component USLT and the filling of the sacrificial membrane 63, and the processing of the upper contact plug UCC and the filling of the sacrificial membrane 64 are performed sequentially (S304). In addition, the order of processing of the upper component USLT and the upper contact plug UCC and filling of the sacrificial membranes 63 and 64 is arbitrary.

[0422] Reference Figures 94-98 The processing method of the upper contact plug UCC is explained in detail.

[0423] like Figure 94 As shown, firstly, holes corresponding to insulating layer 36 and the uppermost insulating layer 35 are machined at the plug connection portions of select gate lines SGS and SGD and word lines WL0 to WL9. Figure 94 (As shown in the 0L processing). In this stage, the sacrificial film 60 is not processed. Thus, the formation of the hole of the upper contact plug UCC (contact plug CC) corresponding to the plug connection portion of the select gate line SGD is completed.

[0424] like Figure 95 As shown, the inner layers of the sacrificial film 60 and insulating layer 35 are processed at the plug connection portions of word lines WL5, WL7, and WL9. Figure 95 (As shown in the 1L processing). That is, for 2 0 =1 layer of sacrificial film 60 is processed. Thus, the hole of the upper contact plug UCC (contact plug CC) corresponding to the plug connection part of the word line WL9 is formed.

[0425] like Figure 96 As shown, the two sacrificial films 60 and two insulating layers 35 inside the holes are processed at the plug connection portions of the selected gate line SGS and word lines WL0~WL4, WL7 and WL8. Figure 96 The 2L process shown). That is, for 2 1 =2 layers of sacrificial film 60 are processed. Thus, the hole of the upper contact plug UCC (contact plug CC) corresponding to the plug connection part of each word line WL7 and WL8 is completed.

[0426] like Figure 97 As shown, the four sacrificial films 60 and four insulating layers 35 inside the holes are processed at the plug connection portions of the selected gate line SGS and word lines WL0 to WL6. Figure 97 (As shown in the 4L processing). That is, for 2 2A 4-layer sacrificial film 60 is processed. This completes the formation of the holes for the upper contact plugs UCC (contact plug CC) corresponding to the plug connection portions of word lines WL5 and WL6. Furthermore, at the plug connection portions of select gate line SGS and word lines WL0 to WL4, the formation of the holes for the upper contact plugs UCC, whose lower ends reach the lower contact plug LCC, is completed.

[0427] like Figure 98 As shown, the sacrificial membrane 64 is used to fill the hole corresponding to the upper contact plug UCC. Thus, the contact plug CC filled by the sacrificial membrane 64 is formed.

[0428] After performing step S304, the upper support column UHR is processed and the sacrificial membrane 62 is filled (S305).

[0429] After performing step S305, compared with the first embodiment... Figure 9 Similarly, a memory hole corresponding to the upper memory column UMP is machined (formed) to form the memory column MP (S111).

[0430] After performing step S111, compared with the first embodiment... Figure 9 Similarly, the sacrificial film 62 within the support pillar HR is removed, and the holes are filled using the insulator 38 (S112). Furthermore, if the support pillar HR and the memory pillar MP are formed together, steps S305 and S112 are omitted. Moreover, in step S111, the memory pillar MP and the support pillar HR are formed simultaneously. More specifically, holes corresponding to the upper support pillar UHR and the upper memory pillar UMP are formed together. Then, the sacrificial films 61 and 62 within each hole are removed. Then, the stacked film 42, the semiconductor film 41, and the core film 40 are deposited to fill the holes, thus forming the support pillar HR and the memory pillar MP together.

[0431] Steps S113 to S116 are the same as those using the first embodiment. Figure 9 The explanations are the same.

[0432] 4.5 Effects of this implementation method

[0433] If this embodiment is configured similarly to the first embodiment, by adapting the number of layers of the memory column MP, component SLT, support column HR, and contact plug CC respectively, the number of process steps and manufacturing cost of the memory cell array can be reduced.

[0434] Furthermore, in the configuration of this embodiment, the contact plug CC can be provided such that it passes through the wiring layer 34 located above the plug connection portion, and its lower end is connected to the plug connection portion. Additionally, in the configuration of this embodiment, the boundary position corresponding to the layer of the support column HR and the boundary position corresponding to the layer of the contact plug CC can be set to the interlayer of different wiring layers 34. Therefore, if using... Figure 88 As explained, for example, it can suppress the increase of the distance between the support post HR and the contact plug CC. Therefore, for example, it can suppress the deflection of the laminate above the plug connection portion.

[0435] 5. Examples of variations, etc.

[0436] The semiconductor memory device of the embodiment includes: a stack body formed by alternately stacking a plurality of wiring layers (34) and a plurality of insulating layers (35) in a first direction (Z direction); memory pillars (MP) extending along the first direction and passing through the stack body; and a first component (SLT) extending along the first direction and a second direction (X direction) intersecting the first direction, and truncating the stack body in a third direction (Y direction) intersecting the first and second directions. The plurality of insulating layers includes a first insulating layer. The plurality of wiring layers include: a first wiring layer (WL2) on which the first insulating layer is disposed; and a second wiring layer (WL3) disposed on the first insulating layer. The memory pillars include: a first sub-pillar (LMP) extending along the first direction and passing through the first wiring layer, with its upper end located between the first wiring layer and the second wiring layer; and a second sub-pillar (MMP) disposed on the first sub-pillar, extending along the first direction and passing through the second wiring layer. The first component includes: a first portion (LSLT) extending along a first direction and a second direction respectively, passing through the first wiring layer and the second wiring layer, with its upper end located above the second wiring layer; and a second portion (USLT) disposed on the first component and extending within the laminate along the first direction and the second direction respectively.

[0437] If the above-described embodiment is used, then manufacturing costs can be reduced.

[0438] Furthermore, various variations can be applied, not limited to the described implementation.

[0439] For example, in the described embodiment, the case where each of the lower memory column LMP, the middle memory column MMP, and the upper memory column UMP has a conical shape with the diameter of the upper end larger than the diameter of the lower end has been described, but the shape of each column is not limited to this. For example, the column can be a straight shape with a connecting portion provided at the layer boundary, or it can be a curved shape with the largest diameter in the middle portion in the Z direction. The same applies to the component SLT, the support column HR, and the contact plug CC.

[0440] Furthermore, in the described embodiment, for example, the diameter D of the upper end of the lower memory cylinder LMP... LMP2 The diameter D of the lower end of the median memory column MMP MMP1 D exists LMP2 >D MMP1 The relationship has been described, but it is not limited to this. Figure 99 This is a cross-sectional view of the storage cell array 11 in the variation example. Figure 99 This indicates the vicinity of the upper end of the lower memory cylinder (LMP) and the vicinity of the lower end of the middle memory cylinder (MMP). Figure 99 In the example shown, the diameter D at the top of the lower memory cylinder LMP is... LMP2 The diameter D of the lower end of the median memory column MMP MMP1 D exists LMP2 =D MMP1 The relationship. Moreover, at the lower level T... LMP The upper and middle levels T of the lower memory cylinder LMP included MMP The lower end of the included middle memory column MMP has a discontinuous shape on the side of the lower memory column LMP compared to the side of the middle memory column MMP (i.e., in the Z-direction cross-section, the side of the lower memory column LMP is offset from the side of the middle memory column MMP). Furthermore, the upper end of the lower memory column LMP has an inverted conical shape (the diameter of the upper side is smaller than the diameter of the lower side). In this case, the boundary BDm1 between the lower memory column LMP and the middle memory column MMP can also be confirmed by observing the shape of the cross-section. The relationship between the middle memory column MMP and the upper memory column UMP is similar. The same applies to components SLT, support column HR, and contact plug CC.

[0441] Furthermore, the "connection" in the above embodiments also includes a state in which the two are indirectly connected by other elements such as transistors or resistors.

[0442] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0443] [Symbol Explanation]

[0444] 1: Semiconductor memory devices

[0445] 10: Memory Core

[0446] 11: Memory Cell Array

[0447] 12: Line Decoder

[0448] 13: Sensing Amplifier

[0449] 20: Peripheral Circuit Section

[0450] 21: Sequencer

[0451] 22: Voltage generation circuit

[0452] 30: Substrate

[0453] 31, 33, 35, 36, 37, 50, 50a, 50b, 50c: Insulation layer

[0454] 32, 32a~32c: Semiconductor layers

[0455] 34, 34a, 34b, 34c, 34d: Wiring layers

[0456] 38, 70, 71, 72: Insulators

[0457] 39,LI: Conductor

[0458] 40: Core membrane

[0459] 41: Semiconductor film

[0460] 42: Stacked membrane

[0461] 43: Tunnel insulation film

[0462] 44: Charge storage membrane

[0463] 45: Barrier insulating film

[0464] 60, 60a, 60b, 60c, 60d, 61~64: Sacrificial membranes

[0465] BL, BL0~BLm: Bit lines

[0466] BLK, BLK0~BLK3: Blocks

[0467] CA1, CA2: Connecting regions

[0468] CC: Contact plug

[0469] HR: Support column

[0470] LCC: Lower Contact Plug

[0471] LHR: Lower Support Column

[0472] LMP: Lower Memory Pole

[0473] LSLT: Lower-level component

[0474] MA: Memory cell area

[0475] MC, MC0~MC9: Memory cell transistors

[0476] MCC: Mid-position contact plug

[0477] MHR: Mid-level support column

[0478] MMP: Mid-level memory column

[0479] MP: Memory column

[0480] MSLT: Mid-position component

[0481] SGD, SGD0~SGD5, SGS: Select gate line

[0482] SHE, SLT: Components

[0483] SP: Spacer

[0484] ST1, ST2: Select transistors

[0485] SU, SU0~SU5: Serial components

[0486] TCC: Topmost Contact Plug

[0487] THR: Uppermost support column

[0488] TSLT: Topmost component

[0489] UCC: Upper Contact Plug

[0490] UHR: Upper Support Column

[0491] UMP: Upper Memory Column

[0492] USLT: Upper-level component

[0493] WL, WL0~WL9: Word lines.

Claims

1. A semiconductor memory device comprising: a laminate body in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated layer by layer in a first direction; and a first member extending in the first direction and a second direction intersecting the first direction, respectively, and cutting the laminate body in a third direction intersecting the first direction and the second direction; and wherein the plurality of insulating layers include a first insulating layer, the plurality of wiring layers include: a first wiring layer on which the first insulating layer is provided; and a second wiring layer provided above the first insulating layer, the memory pillar includes: a first sub-pillar extending in the first direction and passing through the first wiring layer, an upper end of which is located between the first wiring layer and the second wiring layer; and a second sub-pillar provided above the first sub-pillar, extending in the first direction, and passing through the second wiring layer, the first member includes: a first portion extending in the first direction and the second direction, respectively, and passing through the first wiring layer and the second wiring layer, an upper end of which is located above the second wiring layer; and a second portion provided above the first portion and extending in the first direction and the second direction, respectively, within the laminate body.

2. The semiconductor memory device according to claim 1, wherein the laminate body includes: a memory region including the memory pillar; and a staircase region disposed side by side with the memory region in the second direction and provided with a portion of each of the plurality of wiring layers in a staircase shape. A memory pillar extends in the first direction and penetrates the laminate body.

3. The semiconductor memory device according to claim 1, further comprising a semiconductor layer provided below the laminate body, wherein a lower end of the first sub-pillar and a lower end of the first portion of the first member in the first member reach the semiconductor layer, respectively, and the first sub-pillar is electrically connected to the semiconductor layer.

4. The semiconductor memory device according to claim 1, further comprising a support pillar extending in the first direction and passing through the laminate body without being electrically connected to the plurality of wiring layers, wherein the laminate body includes: a memory region including the memory pillar; and a staircase region disposed side by side with the memory region in the second direction, including the support pillar, and provided with a portion of each of the plurality of wiring layers in a staircase shape.

5. The semiconductor memory device according to claim 4, further comprising a semiconductor layer provided below the laminate body, wherein a lower end of the third sub-pillar reaches the semiconductor layer, and the third sub-pillar is not electrically connected to the semiconductor layer.

6. The semiconductor memory device according to claim 1, further comprising a first contact plug extending in the first direction and electrically connected to the first wiring layer, wherein the first contact plug includes: a first contact pillar extending in the first direction and passing through the first wiring layer, an upper end of which is located between the first wiring layer and the second wiring layer; and a second contact pillar provided above the first contact pillar and extending in the first direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a first sub-plug electrically connected to the first wiring layer and extending in the first direction with an upper end positioned above the second wiring layer, 2 a sub-plug disposed above the first sub-plug and extending in the first direction.

7. The semiconductor memory device according to claim 6, wherein a second contact plug extending in the first direction and electrically connected to the second wiring layer is further provided, a lower end of the first contact plug is connected to a first plug connecting portion provided in the first wiring layer and not overlapping with a wiring layer of the plurality of wiring layers positioned above the first wiring layer in the first direction, a lower end of the second contact plug is connected to a second plug connecting portion provided in the second wiring layer and not overlapping with a wiring layer of the plurality of wiring layers positioned above the second wiring layer in the first direction, a height of the first contact plug is different from a height of the second contact plug.

8. The semiconductor memory device according to claim 7, wherein the first plug connecting portion and the second plug connecting portion are arranged in a stepped manner in the second direction.

9. The semiconductor memory device according to claim 1, wherein the plurality of insulating layers further include a second insulating layer, the plurality of wiring layers further include: a third wiring layer provided above the second wiring layer and having the second insulating layer provided thereon; and a fourth wiring layer provided above the second insulating layer; the second sub-column passes through the third wiring layer with an upper end positioned between the third wiring layer and the fourth wiring layer, the memory column further includes a fifth sub-column provided above the second sub-column, extending in the first direction, and passing through the fourth wiring layer, the second portion of the first component passes through the third wiring layer and the fourth wiring layer with an upper end positioned above the plurality of wiring layers.

10. The semiconductor memory device according to claim 6, wherein the plurality of wiring layers further include a fifth wiring layer provided below the first wiring layer, the first sub-plug passes through the fifth wiring layer and is not electrically connected to the fifth wiring layer.

11. The semiconductor memory device according to claim 10, wherein the first sub-plug includes a protrusion protruding in a concentric circular shape, the protrusion is connected to a first plug connecting portion provided in the first wiring layer and not overlapping with a wiring layer of the plurality of wiring layers positioned above the first wiring layer in the first direction.

12. The semiconductor memory device according to claim 10, wherein a second contact plug extending in the first direction and electrically connected to the second wiring layer is further provided, a height of the first contact plug is substantially the same as a height of the second contact plug.

13. A semiconductor memory device comprising: a laminate body in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated one on top of another in a first direction; a memory column extending in the first direction and passing through the laminate body; and a support pillar extending in the first direction and penetrating the laminate without being electrically connected to the plurality of wiring layers; and the laminate includes: a memory region including the memory pillar; and a staircase region arranged side by side with the memory region in a second direction intersecting the first direction, including the support pillar, and provided with a portion of each of the plurality of wiring layers in a staircase shape; the plurality of insulating layers include a first insulating layer, the plurality of wiring layers include: a first wiring layer on which the first insulating layer is provided; and a second wiring layer provided above the first insulating layer; the memory pillar includes: a first sub-pillar extending in the first direction and penetrating the first wiring layer, an upper end of which is located between the first wiring layer and the second wiring layer; and a second sub-pillar provided above the first sub-pillar, extending in the first direction, and penetrating the second wiring layer; the support pillar includes: a third sub-pillar extending in the first direction and penetrating the first wiring layer and the second wiring layer, an upper end of which is located above the second wiring layer; and a fourth sub-pillar provided above the third sub-pillar and extending in the first direction.

14. The semiconductor memory device according to claim 13, further comprising: a semiconductor layer provided below the laminate, lower ends of the first sub-pillar and the third sub-pillar each reach the semiconductor layer, the first sub-pillar is electrically connected to the semiconductor layer, the third sub-pillar is not electrically connected to the semiconductor layer.

15. The semiconductor memory device according to claim 13, wherein the plurality of insulating layers further include a second insulating layer, the plurality of wiring layers further include: a third wiring layer provided above the second wiring layer and on which the second insulating layer is provided; and a fourth wiring layer provided above the second insulating layer; the second sub-pillar penetrates the third wiring layer, an upper end of which is located between the third wiring layer and the fourth wiring layer, the memory pillar further includes a fifth sub-pillar provided above the second sub-pillar, extending in the first direction, and penetrating the fourth wiring layer, the fourth sub-pillar penetrates the third wiring layer and the fourth wiring layer, an upper end of which is located above the plurality of wiring layers.

16. A semiconductor memory device comprising: a laminate in which a plurality of wiring layers and a plurality of insulating layers are alternately layered one on top of another in a first direction; a memory pillar extending in the first direction and penetrating the laminate; a support pillar extending in the first direction and penetrating the laminate without being electrically connected to the plurality of wiring layers; and a first contact plug extending in the first direction and being electrically connected to any one of the plurality of wiring layers; and the plurality of insulating layers include a first insulating layer, the plurality of wiring layers include: a first wiring layer on which the first insulating layer is provided; and a second wiring layer provided above the first insulating layer; the support pillar includes: a first sub-pillar extending in the first direction and penetrating the first wiring layer, an upper end of which is located between the first wiring layer and the second wiring layer; and ​ a second sub-column disposed above the first sub-column, extending in the first direction, and penetrating the second wiring layer; the first contact plug includes: a first sub-plug extending in the first direction, penetrating the second wiring layer, not electrically connected to the second wiring layer, having a lower end electrically connected to the first wiring layer, and having an upper end above the second wiring layer; and a second sub-plug disposed above the first sub-plug and extending in the first direction.

17. The semiconductor storage device according to claim 16, wherein the plurality of wiring layers further includes a third wiring layer disposed above the second wiring layer, the second sub-plug penetrates the third wiring layer and is not electrically connected to the third wiring layer.

18. The semiconductor storage device according to claim 16, wherein the first contact plug includes an electrically conductive body extending in the first direction and having a lower end in contact with the first wiring layer, and an insulator covering a side surface of the electrically conductive body.

19. The semiconductor storage device according to claim 17, further comprising: a second contact plug extending in the first direction and electrically connected to the second wiring layer, the second contact plug includes: a third sub-plug extending in the first direction and having a lower end electrically connected to the second wiring layer; and a fourth sub-plug disposed above the third sub-plug, extending in the first direction, and penetrating the third wiring layer, not electrically connected to the third wiring layer; a height of the first sub-plug is different from a height of the third sub-plug, a height of the second sub-plug is substantially the same as a height of the fourth sub-plug.

20. The semiconductor storage device according to claim 16, wherein the plurality of insulating layers further includes a second insulating layer, the plurality of wiring layers further includes: a third wiring layer disposed above the second wiring layer and having the second insulating layer disposed thereon; and a fourth wiring layer disposed above the second insulating layer; the second sub-column penetrates the third wiring layer and has an upper end between the third wiring layer and the fourth wiring layer, the support column further includes a third sub-column disposed above the second sub-column, extending in the first direction, and penetrating the fourth wiring layer, the second sub-plug penetrates the third wiring layer and the fourth wiring layer, is not electrically connected to the third wiring layer and the fourth wiring layer, and has an upper end above the plurality of wiring layers.

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