Semiconductor memory device

Abstract

A semiconductor memory device having improved driving speed includes: a first wiring layer provided across first and second regions arranged in an X direction; a second wiring layer arranged apart from the first wiring layer in the Z direction; a plurality of third wiring layers provided on the opposite side from the first wiring layer with respect to the second wiring layer so as to be separated from each other in the Z direction; first and second members arranged in the Y direction, each extending in the X direction, and dividing the first and third wiring layers in the Y direction; a third member provided between the first and second members and dividing the second wiring layer in the Y direction; first and second storage posts extending in the Z-direction between the first and third members and between the second and third members, respectively, in the second region; and first and second contacts extending in the Z direction in the first region, and the second wiring layer has first and second land portions which are in contact with the first and second members, respectively, and which do not overlap the plurality of third wiring layers when viewed in the Z direction.

Description

Technical Field

[0001] The implementation method relates to a semiconductor memory device. Background Technology

[0002] NAND flash memory is a known semiconductor memory device capable of storing data non-volatilely. In NAND flash memory, a three-dimensional memory structure is sometimes employed for high integration and large capacity. Summary of the Invention

[0003] The implementation provides a semiconductor memory device with improved drive speed.

[0004] One embodiment of a semiconductor memory device includes: a first wiring layer, which, when viewed from a first direction, spans a first region and a second region arranged in a second direction intersecting the first direction; a second wiring layer, which is arranged separately from the first wiring layer in the first direction; a plurality of third wiring layers, which are arranged separately from each other in the first direction on a side opposite to the first wiring layer relative to the second wiring layer; a first insulating member and a second insulating member, which are arranged in a third direction intersecting the first and second directions and each extends along the second direction, dividing the second wiring layer and the plurality of third wiring layers in the third direction; a third insulating member, which is disposed between the first insulating member and the second insulating member and between the first wiring layer and the plurality of third wiring layers, dividing the second wiring layer into a first portion and a second portion in the third direction; and a first memory pillar, which extends along the first direction between the first insulating member and the third insulating member in the second region, and is connected to the first wiring layer. The second wiring layer comprises: a first platform portion, which is connected to a first portion of a second wiring layer and intersects with a plurality of third wiring layers, and the portions therein function as a plurality of first storage cells; a second storage column, which extends along a first direction between a second insulating member and a third insulating member in a second region, and is connected to the first wiring layer, intersects with a second portion of the second wiring layer, and the portions therein intersect with a plurality of third wiring layers, and functions as a plurality of second storage cells; and a first contact and a second contact, which extend along a first direction in a first region. The second wiring layer has: a first platform portion, which is connected to a first insulating member in a first portion of a first region and does not overlap with a plurality of third wiring layers when viewed in the first direction; and a second platform portion, which is connected to a second insulating member in a second portion of a first region and does not overlap with a plurality of third wiring layers when viewed in the first direction. The first contact is electrically connected to the first platform portion of the second wiring layer, and the second contact is electrically connected to the second platform portion of the second wiring layer. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of the storage system according to the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device according to the first embodiment.

[0007] Figure 3 This is a perspective view showing an example of the appearance of the semiconductor memory device according to the first embodiment.

[0008] Figure 4 This is a perspective view showing an outline of the bonding structure of the semiconductor memory device according to the first embodiment.

[0009] Figure 5 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device according to the first embodiment.

[0010] Figure 6 This is a top view showing an example of the planar layout of the memory area of ​​the memory cell array included in the semiconductor memory device according to the first embodiment.

[0011] Figure 7 This is an example of a cross-sectional structure along the memory region of the memory cell array included in the semiconductor memory device according to the first embodiment. Figure 6 A cross-sectional view of line VII-VII.

[0012] Figure 8 This is an example of the cross-sectional structure of the memory pillars in the semiconductor memory device according to the first embodiment, along... Figure 7 A cross-sectional view of line VIII-VIII.

[0013] Figure 9 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory cell array included in the semiconductor memory device according to the first embodiment.

[0014] Figure 10 This is a top view showing an example of the planar layout of the select gate line SGSa in the lead-out region of the memory cell array of the semiconductor memory device according to the first embodiment.

[0015] Figure 11 This illustrates the lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment, along... Figure 9 and Figure 10 A cross-sectional view of the XI-XI line.

[0016] Figure 12 This is a cross-sectional view showing an example of the first manufacturing process of the SGS partition structure in the memory cell array of the semiconductor memory device according to the first embodiment.

[0017] Figure 13 This is a cross-sectional view showing an example of the first manufacturing process of the SGS partition structure in the memory cell array of the semiconductor memory device according to the first embodiment.

[0018] Figure 14 This is a cross-sectional view showing an example of a second manufacturing process of the SGS partitioning structure in the memory cell array of the semiconductor memory device according to the first embodiment.

[0019] Figure 15 This is a cross-sectional view showing an example of a second manufacturing process of the SGS partitioning structure in the memory cell array of the semiconductor memory device according to the first embodiment.

[0020] Figure 16 This is a top view showing an example of the planar layout of the select gate line SGSa in the lead-out region of the memory cell array of the semiconductor memory device according to the first variation of the first embodiment.

[0021] Figure 17 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory cell array in the semiconductor memory device according to the second embodiment.

[0022] Figure 18 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory cell array in the semiconductor memory device according to the first variation of the second embodiment. Detailed Implementation

[0023] The embodiments will now be described with reference to the accompanying drawings. The drawings are schematic, and their dimensions and scale may not be identical to actual figures. In the following description, constituent elements having substantially the same function and configuration are given the same reference numerals. Where elements having the same configuration are intentionally distinguished, sometimes different text or numbers are appended to the end of the same reference numeral.

[0024] In the following description, a first element being “connected” to another second element includes cases where the first element is always or selectively connected to the second element indirectly or directly without the intermediate element via a conductive intermediate element.

[0025] 1. First Implementation Method

[0026] 1.1 Composition

[0027] 1.1.1 Storage System

[0028] The semiconductor memory device according to the first embodiment will be described. Figure 1This is a block diagram illustrating an example of the configuration of a storage system according to the first embodiment. Storage system 1 is a storage device configured to be connected to an external host device (not shown). Storage system 1 is, for example, an SD card. TM Memory cards, such as UFS (Universal Flash Storage), or SSDs (Solid State Drives). Storage system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0029] The memory controller 2 is, for example, an integrated circuit such as a System-on-a-Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 according to requests from an external host device. Specifically, the memory controller 2 writes data requested to be written from the external host device to the semiconductor memory device 3. Additionally, the memory controller 2 reads data requested to be read from the external host device from the semiconductor memory device 3 and outputs it to the external host device.

[0030] Semiconductor storage device 3 is, for example, a NAND flash memory capable of non-volatile data storage.

[0031] Communication between the memory controller 2 and the semiconductor memory device 3 is based on, for example, an SDR (Single Data Rate) interface, a Toggle DDR (Double Data Rate) interface, or ONFI (Open NAND Flash Interface).

[0032] 1.1.2 Semiconductor memory devices

[0033] Next, refer to Figure 1 The block diagram shown illustrates the internal configuration of the semiconductor memory device 3 according to the first embodiment. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a line decoder module 16, and a sense amplifier module 17.

[0034] The memory cell array 10 is a group of memory cell transistors and a collection of constituent elements connected to the memory cell transistors. The memory cell array 10 includes multiple blocks BLK1 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of non-volatilely storing data. The block BLK is used, for example, as an erase unit when erasing data stored in the memory cell transistors. Furthermore, the memory cell array 10 includes multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0035] Input / output circuit 11 is an interface circuit responsible for transmitting and receiving input / output signals with memory controller 2. Input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. Input / output circuit 11 transmits and outputs data DAT between sense amplifier module 17 and memory controller 2. Input / output circuit 11 outputs command CMD and address information ADD transmitted from memory controller 2 to register 13 respectively. Input / output circuit 11 outputs status information STA transmitted from register 13 to memory controller 2.

[0036] The logic control circuit 12 receives control signals from the memory controller 2. Based on these control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command (CMD), address information (ADD), etc. The logic control circuit 12 commands the input / output circuit 11 to input or output input / output signals. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. Additionally, the logic control circuit 12 outputs a signal to the memory controller 2 indicating whether the semiconductor memory device 3 is in a ready or busy state.

[0037] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, commands that instruct sequencer 14 to perform read, write, or erase operations. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used to select block BLK, word line, and bit line, respectively. Status information STA is updated according to the control of sequencer 14 and transmitted to input / output circuit 11.

[0038] The sequencer 14 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 14 controls the driver module 15, the line decoder module 16, and the sense amplifier module 17, etc., according to the command CMD stored in the register 13, to perform read operations, write operations, erase operations, etc.

[0039] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the line decoder module 16 and the sense amplifier module 17, among others. Additionally, the driver module 15 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PA stored in register 13.

[0040] The line decoder module 16 selects a corresponding block BLK within the memory cell array 10, for example, based on the block address BA stored in register 13. The line decoder module 16 then transmits the voltage of the signal line applied by the driver module 15 to the selected word line within the selected block BLK.

[0041] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit lines, a latch circuit for temporarily storing data, and the like. During a write operation, the sense amplifier module 17 applies the desired voltage to each bit line based on the write data DAT received from the input / output circuit 11. Conversely, during a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Then, the sense amplifier module 17 reads the determination result and transmits it as data DAT to the input / output circuit 11.

[0042] 1.1.3 Circuit configuration of memory cell array

[0043] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device according to the first embodiment. Figure 2 Block BLK0 is shown. Block BLK0 contains, for example, four string units SU0 to SU3.

[0044] Each string cell SU contains multiple NAND strings NS associated with each bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS, for example, contains eight memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge storage film, which stores data non-volatilely based on the amount of charge in the charge storage film. Select transistors ST1 and ST2 are used to select the string cell SU for various operations.

[0045] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selector transistor ST1 is connected to the associated bit line BL, and the source of selector transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selector transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selector transistor ST2 is connected to the source line SL.

[0046] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 within serial cells SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gate of select transistor ST2 within serial cells SU0 to SU1 is connected to select gate line SGS0. The gate of select transistor ST2 within serial cells SU2 to SU3 is connected to select gate line SGS1.

[0047] Bit lines BL0 to BLm are each assigned a different column address CA. Each bit line BL is shared by the NAND string NS, which is assigned the same column address CA, across multiple blocks BLK. Word lines WL0 to WL7 are configured for each block BLK. Source lines SL are shared, for example, across multiple blocks BLK.

[0048] Within a single string cell SU, an assembly of multiple memory cell transistors MT connected to a common word line WL is called a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, a cell unit CU can have a storage capacity of more than 2 pages of data.

[0049] Furthermore, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment is not limited to the description above. For example, the number of string cells SU included in each block BLK can be designed to be any number. However, the number of string cells SU included in each block BLK is preferably an even number. The number of memory cell transistors MT, and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to be any number.

[0050] 1.1.4 Appearance of Semiconductor Memory Devices

[0051] The semiconductor memory device 3 according to the first embodiment is formed by bonding two semiconductor circuit substrates on which semiconductor circuits are respectively formed, and then separating the bonded semiconductor circuit substrates for each chip. That is, the semiconductor memory device 3 according to the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Semiconductor substrates W1 and W2 are, for example, silicon substrates. Hereinafter, the case of removing semiconductor substrate W2 during the manufacturing process of semiconductor memory device 3 will be described. In addition, according to the structure of memory cell array 10, a portion of semiconductor substrate W2 may remain after bonding.

[0052] Figure 3 This is a perspective view showing an example of the appearance of the semiconductor memory device according to the first embodiment. Figure 3 The shading lines are added to improve the visibility of the accompanying drawings, but they are not necessarily related to the material or properties of the constituent elements for which the shading lines are added. For example... Figure 3 As shown, the semiconductor memory device 3 has, for example, a structure in which a semiconductor substrate W1, a control circuit layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300 are stacked in sequence.

[0053] In the following description, the plane extending from the semiconductor substrate W1 is designated as the XY plane. In the stacking direction of the laminated structure, the direction from the semiconductor substrate W1 toward the wiring layer 300 is designated as the Z1 direction, and the direction from the wiring layer 300 toward the semiconductor substrate W1 is designated as the Z2 direction. The Z1 and Z2 directions are approximately perpendicular to the semiconductor substrate W1. Furthermore, without distinguishing between the Z1 and Z2 directions, they are simply referred to as the Z direction.

[0054] The control circuit layer 100 includes control circuitry formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., corresponding to the design of the control circuitry. The control circuit layer 100 includes, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a line decoder module 16, and a sense amplifier module 17.

[0055] The bonding layer B1 is formed using the semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the control circuit disposed on the control circuit layer 100 to form part of the semiconductor circuit.

[0056] The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 disposed on the memory layer 200 to form part of a semiconductor circuit.

[0057] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2 (not shown).

[0058] The wiring layer 300 is formed after the semiconductor substrates W1 and W2 are bonded together. The wiring layer 300 includes wiring connected to the semiconductor circuitry disposed on the memory layer 200, and a plurality of pads PD. The plurality of pads PD are exposed on the surface of the semiconductor memory device 3. The plurality of pads PD are used for connection between the semiconductor memory device 3 and the memory controller 2, etc.

[0059] Figure 4 This is a perspective view showing a schematic of the bonding structure of the semiconductor memory device according to the first embodiment. (Using...) Figure 4 The bonding of semiconductor substrates W1 and W2 is explained.

[0060] like Figure 4 As shown, the plurality of bonding pads BP1 in bonding layer B1 and the plurality of bonding pads BP2 in bonding layer B2 are interconnected. Thus, the control circuit disposed in the control circuit layer 100 and the memory cell array 10 disposed in the memory layer 200 are electrically connected to each other via bonding pads BP1 and BP2. The boundary between bonding layers B1 and B2 corresponds to the boundary between the layer formed using semiconductor substrate W1 and the layer formed using semiconductor substrate W2 (not shown).

[0061] 1.1.5 Construction of Storage Cell Array

[0062] Hereinafter, an example of the structure of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment will be described. In the following description, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The planes extending in the X and Z directions are designated as the XZ plane. The planes extending in the Y and Z directions are designated as the YZ plane. In the top view, shading lines are appropriately added to improve the visibility of the drawings. The shading lines added in the top view are not necessarily related to the material or characteristics of the constituent elements to which the shading lines are added. In the cross-sectional view, the configuration illustrations are appropriately omitted to improve the visibility of the drawings.

[0063] 1.1.5.1 Summary

[0064] Figure 5 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device according to the first embodiment. Figure 5 The image shows the areas corresponding to the six blocks BLK0 to BLK5. The serial numbers used to distinguish the end of the blocks BLK are appended in ascending order from the top of the page. In the storage cell array 10, for example, these are repeatedly arranged along the Y direction. Figure 5 The layout shown. (As indicated) Figure 5As shown, the memory cell array 10 includes multiple components SLT and multiple components SHE. The planar layout of the memory cell array 10 is, for example, divided in the X direction into memory regions MA1 and MA2, and an outgoing region HA. The outgoing region HA is located between memory regions MA1 and MA2.

[0065] Storage areas MA1 and MA2 are areas containing multiple NAND strings NS for data storage. Lead-out area HA is the area used for connecting the stacked wiring, which consists of multiple wiring layers (e.g., word lines WL0 to WL7, and select gate lines SGS0, SGS1, and SGD) stacked separately along the Z direction, to the line decoder module 16.

[0066] Multiple component SLTs extend along the X direction and are arranged along the Y direction. In the boundary region between adjacent blocks BLK, each component SLT transversely cuts storage regions MA1 and MA2 along the X direction. In other words, each region divided by the component SLT corresponds to one block BLK in the storage cell array 10. Each component SLT has, for example, a structure with embedded insulators and plate-shaped contacts. Each component SLT divides the stacked wiring adjacent to it.

[0067] like Figure 5 As shown, in this embodiment, the odd-numbered SLT arranged from the top of the paper among the multiple SLTs arranged along the Y direction is called "SLTo", and the even-numbered SLT is called "SLTe". In the storage cell array 10, multiple sets of SLTs SLTo and SLTe are arranged in the Y direction.

[0068] Multiple component SHEs are configured in memory regions MA1 and MA2 respectively. The component SHEs corresponding to memory region MA1 are arranged transversely to memory region MA1 along the X direction and arranged along the Y direction. The component SHEs corresponding to memory region MA2 are arranged transversely to memory region MA2 along the X direction and arranged along the Y direction. The right-hand end of each component SHE corresponding to memory region MA1 and the left-hand end of each component SHE corresponding to memory region MA2 are each contained in a lead-out region HA. For example, in each memory region MA1 and MA2, three component SHEs are configured between adjacent component SLTs in the Y direction. The combination of each region in memory region MA1 divided by component SLTs and SHEs and each region in memory region MA2 divided by component SLTs and SHEs corresponds to one string cell SU in memory cell array 10. Each component SHE has, for example, a structure with embedded insulators. Each component SHE divides the select gate line SGD adjacent to that component SHE.

[0069] Furthermore, the planar layout of the memory cell array 10 included in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of components SHE disposed between adjacent components SLT can be designed to be any number. The number of string cells SU formed between adjacent components SLT can be varied depending on the number of components SHE disposed between adjacent components SLT. In addition, the number of string cells SU formed between adjacent components SLT is preferably an even number. That is, the number of components SHE in one block BLK is preferably an odd number.

[0070] The lead-out area HA includes multiple leads HP1 and HP2. Each lead HP1 and HP2 has a connection portion for contacting a contact in each layer of the cabling. Each lead HP1 is arranged along the Y-direction and is configured for every two adjacent blocks BLK sandwiched by clamping members SLTo along the Y-direction. In other words, each lead HP1 is configured to be clamped by two members SLTe sandwiching two adjacent blocks BLK within the lead-out area HA. ​​Each lead HP2 is arranged along the Y-direction and is configured for every two adjacent blocks BLK sandwiched by clamping members SLTe along the Y-direction. In other words, each lead HP2 is configured to be clamped by two members SLTo sandwiching two adjacent blocks BLK within the lead-out area HA.

[0071] The lead-out area HA contains multiple bridging sections BRG. Each bridging section BRG is configured for each block BLK. In each bridging section BRG, the portions of each routing layer of the stacked routing in storage area MA1 and the portions in storage area MA2 are interconnected. Each bridging section BRG includes: a first portion BRGa, which is configured to be sandwiched between lead-out HP1 and component SLTe in the Y direction; a second portion BRGb, which is configured to be sandwiched between lead-out HP2 and component SLTo in the Y direction; and a third portion BRGc, which is configured to be sandwiched between lead-out HP1 and lead-out HP2 in the X direction, and connects the first portion BRGa and the second portion BRGb. Each bridging section BRG has, for example, an S-shaped design.

[0072] 1.1.5.2 Storage Area

[0073] (Floor plan layout)

[0074] Figure 6 This is a top view showing an example of the planar layout of the memory region of the memory cell array included in the semiconductor memory device according to the first embodiment. Additionally, in Figure 6 The diagram illustrates the construction of a single block (BLK) within storage region MA1, but the construction of storage region MA2 is similar to that of storage region MA1. Figure 6As shown, in storage regions MA1 and MA2, the storage cell array 10 includes multiple storage columns MP, multiple contacts CV, and multiple bit lines BL. Additionally, each component SLT includes contacts LI and spacers SP.

[0075] Each memory column (MP) functions as, for example, a NAND string (NS). Multiple memory columns (MPs) are arranged in an alternating pattern of 19 rows in the region between two adjacent SLTs, for example, in the Y direction. Figure 6 In the example shown, counting from the top of the paper, one component SHE is superimposed on the storage column MP in the 5th, 10th and 15th rows respectively.

[0076] Multiple bit lines BL extend along the Y direction and are arranged in the X direction. Each bit line BL is configured to overlap with at least one memory column MP in each string cell SU. Figure 6 In the example shown, two bit lines BL are configured to overlap with one memory cylinder MP. When there are multiple bit lines BL overlapping with the memory cylinder MP, one of the multiple bit lines BL is electrically connected to the corresponding memory cylinder MP via a contact CV. Alternatively, when there is only one bit line BL overlapping with the memory cylinder MP, that bit line BL is electrically connected to the corresponding memory cylinder MP via a contact CV.

[0077] For example, the contact CV between the memory pillar MP that contacts the component SHE and the corresponding bit line BL is omitted. In other words, the contact CV between the memory pillar MP that connects to two different select gate lines SGD and the bit line BL is omitted. The number and arrangement of memory pillars MP, components SHE, etc., between adjacent components SLT are not limited to... Figure 6 The configuration shown can be modified as appropriate. For example, the number of bit lines BL overlapping each memory cylinder MP can be designed to be arbitrary.

[0078] The contact LI is a conductor extending in the XZ plane. The lower surface of the contact LI is connected to the source line SL (not shown). The spacer SP is an insulator disposed on the side of the contact LI. In other words, the spacer SP is grounded to the contact LI in such a way that it clamps the contact LI in the Y direction.

[0079] (Cross-section construction)

[0080] Figure 7 This is an example of a cross-sectional structure along the memory region of the memory cell array included in the semiconductor memory device according to the first embodiment. Figure 6 A cross-sectional view of line VII-VII. (See diagram below.) Figure 7As shown, the memory cell array 10 also includes wiring layers 21-25 and insulating layers 40-46, as well as components SSE. In the following description, the Z2 direction is defined as upward and the Z1 direction as downward.

[0081] The stacked wiring included in the memory cell array 10 includes wiring layer 22 corresponding to the select gate lines SGS0 and SGS1, multiple wiring layers 23 corresponding to word lines WL0 to WL7, and wiring layer 24 corresponding to the select gate line SGD. Hereinafter, without distinguishing between the select gate lines SGS0 and SGS1, it will only be referred to as the select gate line SGS.

[0082] exist Figure 7 In the example shown, the wiring layer 22 corresponding to the select gate line SGS has two layers. In the following description, the select gate line SGS corresponding to the upper wiring layer 22 will be referred to as select gate line SGSa, and the select gate line SGS corresponding to the lower wiring layer 22 will be referred to as select gate line SGSb. Select gate lines SGSa and SGSb are connected to the gates of select transistors ST2a and ST2b, respectively. Select transistors ST2a and ST2b function as a single select transistor ST2. Furthermore, the wiring layer 22 corresponding to the select gate line SGS can be one layer or three or more layers. Additionally, if the wiring layer 22 corresponding to the select gate line SGS is formed by multiple layers, each select transistor ST2a and ST2b can also function independently.

[0083] An insulating layer 41 is stacked on top of a semiconductor substrate W2 (not shown), and further, multiple wiring layers 22 and multiple insulating layers 42 are alternately and sequentially stacked on top of it. Figure 7 In the example shown, two wiring layers 22 and two insulating layers 42 are alternately stacked. The multiple wiring layers 22 are, for example, formed as plates extending along the X direction in the XY plane. Each wiring layer 22 serves as a select gate line SGSa and SGSb. Each wiring layer 22 contains, for example, tungsten (W). The insulating layer 41 and the multiple insulating layers 42 each contain, for example, silicon oxide (SiO).

[0084] Above the topmost insulating layer 42, multiple wiring layers 23 and multiple insulating layers 43 are alternately stacked. Figure 7 In the example shown, 8 wiring layers 23 and 7 insulating layers 43 are stacked alternately. Each wiring layer 23 is, for example, formed as a plate extending in the X direction on the XY plane. Each wiring layer 23, starting from the wiring layer 22 side, serves as word lines WL0 to WL7 respectively. Each wiring layer 23 contains, for example, tungsten. Each insulating layer 43 contains, for example, silicon oxide.

[0085] Above the topmost wiring layer 23, an insulating layer 44, wiring layer 24, and insulating layer 45 are stacked sequentially. Wiring layer 24 is, for example, formed as a plate extending along the X direction in the XY plane. Wiring layer 24 serves as the select gate line (SGD). Wiring layer 24 contains, for example, tungsten. Insulating layers 44 and 45 contain, for example, silicon oxide.

[0086] A wiring layer 25 is stacked above the insulating layer 45. The wiring layer 25 is formed, for example, as a line extending along the Y direction. The wiring layer 25 serves as a bit line BL. In areas not shown, multiple wiring layers 25 are arranged along the X direction. The wiring layer 25 contains, for example, copper.

[0087] An insulating layer 46 is stacked above the wiring layer 25. The insulating layer 46 is a layer connected to the bonding layer B2 and contains multiple wirings (not shown).

[0088] After removing the semiconductor substrate W2, a wiring layer 21 and an insulating layer 40 are sequentially disposed below the insulating layer 41 in the Z1 direction. The wiring layer 21 is, for example, formed as a plate extending in the X direction on the XY plane. The wiring layer 21 serves as a source line SL. The wiring layer 21 contains, for example, phosphorus-doped silicon. Furthermore, a wiring layer 300 may also be disposed below the insulating layer 40. This wiring layer 300 contains a plurality of wirings (not shown).

[0089] Each storage pillar MP extends along the Z-direction. The storage pillar MP penetrates the wiring layers 22-24 and the insulating layers 41-44. For example, the cross-sectional area (XY cross-sectional area) of each storage pillar MP increases from bottom to top along the XY plane.

[0090] Each memory column MP includes, for example, a core film 30, a semiconductor film 31, and a laminated film 32. The core film 30 extends along the Z direction. For example, the upper end of the core film 30 is located within an insulating layer 45, and the lower end of the core film 30 is located within a wiring layer 21. The core film 30 includes, for example, an insulator such as silicon oxide. The semiconductor film 31 covers, for example, the periphery of the core film 30. At the lower end of the memory column MP, a portion of the semiconductor film 31 contacts the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The laminated film 32 covers the sides of the semiconductor film 31, except for the portion of the semiconductor film 31 that contacts the wiring layer 21.

[0091] exist Figure 7 In the structure of the memory pillar MP shown, the portion where the memory pillar MP intersects with wiring layer 22 functions as selection transistor ST2. The portions where the memory pillar MP intersects with each wiring layer 23 function as memory cell transistors MT0 to MT7, respectively. The portion where the memory pillar MP intersects with wiring layer 24 functions as selection transistor ST1.

[0092] A columnar contact CV is disposed on the upper surface of the semiconductor film 31 within the storage column MP. Figure 7 The area shown displays two contact CVs corresponding to two of the six storage columns MP. Within this area, other contact CVs (not shown) are connected to storage columns MP that do not overlap with the component SHE and are not connected to contact CVs.

[0093] The upper surface of each contact CV contacts one wiring layer 25, i.e., one bit line BL. One wiring layer 25 contacts one contact CV in each space defined by components SLT and SHE. That is, in each wiring layer 25, for example, one memory post MP in each region between adjacent components SLT and SHE is electrically connected to one memory post MP in each region between two adjacent components SHE.

[0094] The component SLT is formed, for example, to extend along the XZ plane. Each component SLT penetrates the wiring layers 22-24 and the insulating layers 41-44. For example, the width of each component SLT increases from bottom to top in the Y direction.

[0095] Within the component SLT, the contact LI is configured to extend along the XZ plane, and the spacer SP is disposed between the contact LI and the wiring layers 22-24 and the insulating layers 41-45. The upper end of the contact LI is located, for example, within the insulating layer 45. The lower end of the contact LI is connected, for example, to the wiring layer 21. Alternatively, the contact LI may be omitted depending on the configuration of the memory cell array 10.

[0096] The component SHE is formed, for example, as a plate extending along the XZ plane, dividing the wiring layer 24. The upper end of the component SHE is located within the insulating layer 45. The lower end of the component SHE is located, for example, within the uppermost insulating layer 43. The component SHE contains, for example, an insulator such as silicon oxide. Furthermore, the upper end of the component SHE may or may not be flush with the upper end of the component SLT. Additionally, the upper end of the component SHE may or may not be flush with the upper end of the storage column MP.

[0097] In storage regions MA1 and MA2, the component SSE is formed, for example, as a plate extending along the XZ plane, dividing multiple wiring layers 22. For example, the upper end of the component SSE may be located at the boundary between the uppermost insulating layer 42 and the lowermost wiring layer 23, or it may be located inside the uppermost insulating layer 42. For example, the lower end of the component SSE may be located at the boundary between the wiring layer 21 and the insulating layer 41, or it may be located inside the insulating layer 41. The component SSE is preferably disposed in storage regions MA1 and MA2 at a position overlapping with one component SHE in the Z direction. The component SSE contains, for example, an insulator such as silicon oxide. In addition, the upper end of the component SSE may or may not be flush with the lower end of the component SLT.

[0098] Figure 8This is an example of the cross-sectional structure of the memory pillars in the semiconductor memory device according to the first embodiment, along... Figure 7 A cross-sectional view of line VIII-VIII. More specifically, Figure 8 The cross-sectional structure of the memory pillar MP in a layer containing wiring layer 23, parallel to the surface of semiconductor substrate W2 (not shown), is illustrated. Figure 8 As shown, the laminated membrane 32 includes, for example, a tunnel insulating membrane 33, a charge storage membrane 34, and a barrier insulating membrane 35.

[0099] In the cross-section including the wiring layer 23, the core film 30 is disposed, for example, in the central portion of the storage pillar MP. A semiconductor film 31 surrounds the sides of the core film 30. A tunnel insulating film 33 surrounds the sides of the semiconductor film 31. A charge storage film 34 surrounds the sides of the tunnel insulating film 33. A barrier insulating film 35 surrounds the sides of the charge storage film 34. The wiring layer 23 surrounds the sides of the barrier insulating film 35.

[0100] Semiconductor film 31 serves as the channel (current path) for memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Tunnel insulating film 33 and barrier insulating film 35 each contain, for example, silicon oxide. Charge storage film 34 has the function of storing charge and may contain, for example, silicon nitride (SiN). With this configuration, each memory pillar MP can function as a NAND string NS.

[0101] 1.1.5.3 Lead-out region

[0102] (Floor plan layout)

[0103] Figure 9 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory cell array included in the semiconductor memory device according to the first embodiment. Figure 10 This is a top view showing an example of the planar layout of the select gate line SGSa in the lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment. Figure 9 and Figure 10 The image shows the outgoing region HA, and a portion of the nearby storage regions MA1 and MA2. Figure 9 and Figure 10 The area shown corresponds to blocks BLK0 to BLK2. Additionally, in Figure 9 and Figure 10 For the sake of simplicity, a portion of the insulating layer has been omitted.

[0104] like Figure 9 and Figure 10 As shown, in the lead-out area HA, the memory cell array 10 also includes multiple contacts CC.

[0105] like Figure 9As shown, the select gate line SGD includes a first portion SGDa connected to memory region MA1 and a second portion SGDb connected to memory region MA2. Furthermore, each of the first portion SGDa and the second portion SGDb includes select gate lines SGD0 to SGD3 formed by dividing three components SHE into four portions in the Y direction. The portions of select gate lines SGD0 to SGD3 formed by dividing the three components SHE in the Y direction are mutually insulated. That is, in one block BLK, the select gate line SGD is divided into eight portions. Additionally, the corresponding portions of the portions disposed in the first portion SGDa and the portions disposed in the second portion SGDb are electrically connected to each other via a contact CC (described later) and an upper wiring layer (not shown).

[0106] like Figure 10 As shown, component SSE divides the select gate line SGS in the Y direction within the lead-out region HA. Additionally, although not shown, component SSE also divides the select gate line SGS in the Y direction within memory regions MA1 and MA2. The portion of component SSE extending in the X direction is formed as a plate extending along the XZ plane, and the portion extending in the Y direction is formed as a plate extending along the YZ plane. The select gate line SGSa includes select gate lines SGS0a and SGS1a, divided by component SSE in the Y direction. Select gate lines SGS0a and SGS1a are insulated from each other. For example, select gate line SGS0a is connected to the memory pillars MP corresponding to string cells SU0 and SU1 in memory regions MA1 and MA2. Select gate line SGS0a electrically connects the portion in memory region MA1 to the portion in memory region MA2 via a portion provided in the bridging portion BRG within the lead-out region HA. Select gate line SGS1a is connected to the memory pillars MP corresponding to string cells SU2 and SU3. The select gate line SGS1a, via a portion located in the bridge section BRG within the lead-out region HA, electrically connects the portions located in memory region MA1 and memory region MA2. For example, select gate lines SGS0a and SGS1a have a shape that overlaps upon rotation along the Z-axis. The cross-sectional area of ​​select gate line SGS0a in the XY plane is approximately equal to that of select gate line SGS1a. Therefore, the capacitance of select gate line SGS0a is approximately equal to that of select gate line SGS1a.

[0107] Additionally, although not illustrated, the select gate line SGSb also includes select gate lines SGS0b and SGS1b, which are divided in the Y direction by the component SSE. Select gate lines SGS0b and SGS1b are insulated from each other. For example, select gate line SGS0b is connected to the memory pillars MP corresponding to the string cells SU0 and SU1 in memory regions MA1 and MA2. Select gate line SGS0b electrically connects the portion in memory region MA1 to the portion in memory region MA2 via the portion in the bridge section BRG within the lead-out region HA. Select gate line SGS1b is connected to the memory pillars MP corresponding to the string cells SU2 and SU3. Select gate line SGS1b electrically connects the portion in memory region MA1 to the portion in memory region MA2 via the portion in the bridge section BRG within the lead-out region HA. For example, select gate lines SGS0b and SGS1b have a shape that overlaps each other when rotated along the Z-axis. The cross-sectional area of ​​the select gate line SGS0b in the XY plane is approximately equal to that of the select gate line SGS1b in the XY plane. Therefore, the capacitance of the select gate line SGS0b is approximately equal to that of the select gate line SGS1b.

[0108] As described above, the structure in which the selected gate line SGS is divided into multiple parts by the component SSE within a block BLK is called the SGS partition structure.

[0109] In the lead-out region HA, component SSE is disposed in the bridging portion BRG in a manner that bypasses lead-out portions HP1 and HP2 and does not overlap with component SLT in the Z direction. Specifically, component SSE extends in the X direction in the first portion BRGa and the second portion BRGb of the bridging portion BRG, and extends in the Y direction in the third portion BRGc. Component SSE has an S-shape in the lead-out region HA, for example. For example, the shape of component SSE disposed in one block BLK is symmetrical in the Y direction about component SLT to the shape of component SSE disposed in the block BLK adjacent to it.

[0110] like Figure 9 As shown, in the lead-out area HA, each wiring layer 22-23 has a platform portion that does not overlap with the upper wiring layers 23 and 24. The shape of the platform portion in the lead-out area HA is similar to that of a step, terrace, or rimstone. A contact CC is connected at the platform portion of each wiring layer 22-23.

[0111] Specifically, such as Figure 9As shown, in the lead-out section HP1, a first stepped structure is provided where the platform portions of wiring layers 22 corresponding to the select gate lines SGS0a and SGS0b and wiring layers 23 corresponding to word lines WL4 to WL7 are arranged along the X direction. The first stepped structure is provided so as to span the member SLTo and has a symmetrical structure with respect to the member SLTo. In the lead-out section HP2, a second stepped structure is provided where the platform portions of wiring layers 22 corresponding to the select gate lines SGS1a and SGS1b and wiring layers 23 corresponding to word lines WL0 to WL3 are arranged along the X direction. The second stepped structure is provided so as to span the member SLTe and has a symmetrical structure with respect to the member SLTe.

[0112] Multiple wiring layers 23 include slanted portions IP1 in the lead-out portion HP1. The slanted portions IP1 are multiple (in) consecutively stacked layers that are rectangular in shape when viewed from above. Figure 9 In the example shown, there are four steps at the ends of the wiring layers 23. A portion of the inclined portion IP1 is configured to transversely cut the first step along the Y direction. In the inclined portion IP1, the ends of the multiple consecutively stacked wiring layers 23 are inclined at approximately the same angle in the diagonal directions in the XZ and YZ planes, forming a slope. The inclined portion IP1 is configured to surround the platform portion of the wiring layer 22 corresponding to the select gate lines SGS0a and SGS0b.

[0113] Multiple wiring layers 23 include slanted portions IP2 in the lead-out portion HP2. The slanted portions IP2 are multiple (in) consecutively stacked layers that are set to a rectangular shape in the top view. Figure 9 In the example shown, there are four steps at the ends of the wiring layers 23. The inclined portion is arranged to surround the second step structure. In the inclined portion IP2, the ends of the multiple consecutively stacked wiring layers 23 are inclined at approximately the same angle in the diagonal directions in the XZ plane and YZ plane, forming a slope.

[0114] Each of the multiple wiring layers 23 electrically connects the portion located in storage region MA1 and the portion located in storage region MA2 via the portion located in the bridging section BRG within the lead-out region HA. That is, the same wiring layer 23 has equipotential regardless of the portion.

[0115] Multiple contacts CC are respectively configured to correspond to the select gate lines SGS0a, SGS1a, SGS0b, SGS1b, SGD0~SGD3, and word lines WL0~WL7. For example... Figure 9As shown, each contact CC corresponding to the select gate lines SGD0 to SGD3 is provided in each of the first part SGDa and the second part SGDb, arranged along the Y direction in each region divided by multiple components SHE. That is, in one block BLK, eight contacts CC are provided for the select gate line SGD. Each contact CC corresponding to the word lines WL4 to WL7 is arranged along the X direction in the lead-out section HP1. Each contact CC corresponding to the word lines WL0 to WL3 is arranged along the X direction in the lead-out section HP2.

[0116] The location of the contacts CC corresponding to the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b varies depending on whether the block BLK containing the contact CC is an even-numbered or odd-numbered block counting from the top of the paper. In the even-numbered blocks BLK (BLK0, BLK2, ...), the contacts CC corresponding to the select gate lines SGS0a and SGS0b are located in lead-out portion HP1, and the contacts CC corresponding to the select gate lines SGS1a and SGS1b are located in lead-out portion HP2. Figure 9 In the example shown, in the even-numbered blocks BLK, for example, the contacts CC provided in the lead-out section HP1 correspond sequentially from the left side of the paper to the select gate lines SGS0b, SGS0a, word lines WL4, WL5, WL6, and WL7, respectively. The contacts CC provided in the lead-out section HP2 correspond sequentially from the left side of the paper to the word lines WL3, WL2, WL1, WL0, and select gate lines SGS1a and SGS1b, respectively. On the other hand, in the odd-numbered blocks BLK (BLK1, BLK3, ...), the contacts CC corresponding to the select gate lines SGS0a and SGS0b are provided in the lead-out section HP2, and the contacts CC corresponding to the select gate lines SGS1a and SGS1b are provided in the lead-out section HP1. Figure 9 In the example shown, in the odd-numbered block BLK, for example, each contact CC provided in the lead-out section HP1 corresponds sequentially from the left side of the paper to the select gate lines SGS1b, SGS1a, word lines WL4, WL5, WL6, and WL7, respectively. Each contact CC provided in the lead-out section HP2 corresponds sequentially from the left side of the paper to the word lines WL3, WL2, WL1, WL0, and select gate lines SGS0a and SGS0b, respectively.

[0117] (Cross-section construction)

[0118] Figure 11 This illustrates the lead-out region of the memory cell array included in the semiconductor memory device according to the first embodiment, along... Figure 9 and Figure 10 A cross-sectional view of the XI-XI line. Figure 11The XZ cross-sections of the lead-out area HA and contact CC of block BLK1 are shown. Figure 11 As shown, the memory cell array 10 also includes a wiring layer 26 in the lead-out region HA.

[0119] like Figure 11 As shown, in the lead-out section HP1, a first stepped structure is formed, having an ascending step in the X direction from the storage region MA1 side toward the storage region MA2 side. In the lead-out section HP2, a second stepped structure is formed, having a descending step in the X direction from the storage region MA1 side toward the storage region MA2 side. The insulating layer 45 is provided in a manner that buries the first and second stepped structures.

[0120] Multiple contacts CC extend along the Z-direction. Each contact CC, when viewed from above, is positioned such that the insulating layer 45 at that location extends through it along the Z-direction. The upper surface of each contact CC is in contact with the wiring layer 26. The lower surface of each contact CC is in contact with one of the wiring layers 22-24 corresponding to that contact CC.

[0121] Multiple wiring layers 26 are respectively disposed on multiple contacts CC. Each contact CC is electrically connected to the line decoder module 16 via the wiring layer 26.

[0122] 1.2 Manufacturing process of SGS segmented structure

[0123] Hereinafter, an example of the manufacturing process of the SGS partition structure in the memory cell array of the semiconductor memory device according to the first embodiment is shown. Furthermore, regarding the manufacturing process of the SGS partition structure in the memory cell array 10 of the semiconductor memory device 3 according to the first embodiment, both the first manufacturing process and the second manufacturing process are considered. In this embodiment, as a method for forming multiple wiring layers 22, 23, and 24 corresponding to the select gate line SGS and SGD, and word lines WL0 to WL7 respectively, the following method will be described: after forming structures corresponding to each wiring layer 22, 23, and 24 with sacrificial members, the sacrificial members are replaced with conductive materials to form each wiring layer 22, 23, and 24 (hereinafter referred to as "replacement").

[0124] 1.2.1 First Manufacturing Process

[0125] In the first manufacturing step of the SGS partition structure, the component SSE is formed before the wiring layer is replaced, and the sacrificial component corresponding to the selected gate line SGS is partitioned. Figure 12 and Figure 13 This is a cross-sectional view illustrating an example of the first manufacturing process of the SGS partitioning structure in the memory cell array of the semiconductor memory device according to the first embodiment. Additionally, Figure 12 and Figure 13 The cross section shown corresponds to the cross section of storage region MA1, but the manufacturing process of the SGS segmentation structure in storage region MA2 and lead-out region HA is the same.

[0126] First, an insulating layer 41 is stacked on a semiconductor substrate W2, and sacrificial members 51 and insulating layers 42 are alternately stacked on top of it. The sacrificial members 51 are disposed at positions corresponding to the wiring layer 22. The sacrificial members 51 may contain, for example, silicon nitride.

[0127] Then, as Figure 12 As shown, a slit SSH corresponding to the component SSE is provided. Specifically, a mask is first formed by photolithography or the like to create an opening in the portion corresponding to the component SSE. Then, insulating layers 41 and 42 and sacrificial component 51 are removed by anisotropic etching of the mask. At the bottom of the slit SSH, a portion of the semiconductor substrate W2 is exposed. Alternatively, the bottom of the slit SSH can be provided within the insulating layer 41. In this case, a portion of the insulating layer 41 is exposed at the bottom of the slit SSH. The slit SSH has a tapered shape that tapers at its tip along the Z1 direction.

[0128] Next, as Figure 13 As shown, the slit SSH is filled with insulator 47 to form component SSE. Insulator 47 comprises, for example, silicon oxide. For example, the surfaces of insulator layer 42 and component SSE are planarized by CMP (Chemical Mechanical Polishing).

[0129] Then, above the insulating layer 42 and the component SSE, the sacrificial component and the insulating layer corresponding to the wiring layers 23 and 24 are stacked in sequence to form a stepped structure.

[0130] The component SSE, manufactured through the first manufacturing process, has a tapered shape that tapers at the tip along the Z1 direction.

[0131] 1.2.2 Second Manufacturing Process

[0132] In the second manufacturing step of the SGS partitioned structure, after the wiring layer is replaced to form the component SSE, the gate line is selected for SGS partitioning. Figure 14 and Figure 15 This is a cross-sectional view illustrating an example of a second manufacturing process of the SGS partitioning structure in the memory cell array of the semiconductor memory device according to the first embodiment. Additionally, Figure 14 and Figure 15 The cross section shown corresponds to the cross section of storage region MA1, but the manufacturing process of the SGS segmentation structure in storage region MA2 and lead-out region HA is the same.

[0133] First, a memory cell array 10 is formed on a semiconductor substrate W2, without the wiring layer 21 and with the selected gate lines SGSa and SGSb not segmented. Specifically, an insulating layer 41 is formed on the semiconductor substrate W2. The lower end (above the paper) of the memory pillar MP is disposed within the semiconductor substrate W2. Furthermore, at this time, the semiconductor film 31 is not exposed at the lower end of the memory pillar MP, but is covered by a laminated film 32. The lower end (above the paper) of the component SLT is connected to the semiconductor substrate W2. Then, as... Figure 4 As shown, the control circuit disposed on the control circuit layer 100 and the memory cell array 10 disposed on the memory layer 200 are electrically connected to each other via bonding pads BP1 and BP2.

[0134] Next, remove the semiconductor substrate W2. Then, as... Figure 14 As shown, a slit SSH corresponding to component SSE is provided. Specifically, a mask is first formed by photolithography or the like to create an opening in the portion corresponding to component SSE. Then, anisotropic etching is performed on the mask to remove insulating layer 41, wiring layer 22, and a portion of insulating layer 42. At the bottom of the slit SSH, a portion of the uppermost insulating layer 42 (below the paper) or a portion of the lowermost wiring layer 23 (above the paper) is exposed. The slit SSH has a tapered shape that tapers towards the tip along the Z2 direction.

[0135] Next, the slit SSH is filled with insulator 47 to form component SSE. Insulator 47 may contain, for example, silicon oxide.

[0136] Then, a portion of the stacked film 32 of the memory pillar MP is removed, exposing a portion of the semiconductor film 31. Next, a wiring layer 21 is formed on the Z1 direction surface of the insulating layer 41 and the component SSE. Specifically, for example, a semiconductor layer containing polysilicon is formed on the Z1 direction surface of the insulating layer 41 and the component SSE. Then, by performing laser annealing on the semiconductor layer, impurities (e.g., phosphorus) are doped into the semiconductor layer to form a conductive wiring layer 21. At this time, the wiring layer 21 is electrically connected to the semiconductor film 31 of the memory pillar MP. In addition, an insulating layer 40 is formed on the Z1 direction surface of the wiring layer 21.

[0137] The component SSE, manufactured through the second manufacturing process, has a tapered shape that tapers at the tip along the Z2 direction.

[0138] 1.3 Effects of the first implementation method

[0139] According to the first embodiment, the driving speed of the semiconductor memory device can be improved. This effect will be explained in detail below.

[0140] In the semiconductor memory device 3 according to the first embodiment, the select gate lines SGSa and SGSb are divided into two in one block BLK. Therefore, when the memory cell array 10 is operated, the select gate lines SGSa and SGSb corresponding to the memory pillars MP that form the selected memory cell transistors MT can be selectively driven. Specifically, for example, when reading or writing data to the memory pillars MP provided in the string cell SU0, the select gate lines SGS0a and SGS0b are driven, but the select gate lines SGS1a and SGS1b are not driven. Therefore, compared to a structure where the select gate lines are not divided, the cross-sectional area of ​​the select gate lines SGS0a and SGS1a in the XY plane is approximately half, and their respective capacitances are also reduced. Therefore, the time for charging each select gate line SGS0a and SGS1a is shortened, and the driving speed is increased. Similarly, the cross-sectional area of ​​the select gate lines SGS0b and SGS1b in the XY plane is also approximately half, and their respective capacitances are also reduced. Therefore, the time required to charge each select gate line SGS0b and SGS1b separately is shortened, and the driving speed is increased.

[0141] Furthermore, in the semiconductor memory device 3 according to the first embodiment, each of the select gate lines SGS0a, SGS1a, SGS0b, and SGS1b connects the portion disposed in memory region MA1 and the portion disposed in memory region MA2 via a bridging portion BRG formed in the lead-out region HA. In other words, each select gate line SGS0a, SGS1a, SGS0b, and SGS1b is not divided into multiple portions and is not connected via upper layer wiring, etc. Therefore, compared to a structure in which the select gate lines are divided into multiple portions in the X direction and connected via upper layer wiring, the capacitance of each select gate line SGS0a, SGS1a, SGS0b, and SGS1b can be reduced. That is, the time for charging each select gate line SGS0a, SGS1a, SGS0b, and SGS1b is shortened, and the driving speed is increased.

[0142] Furthermore, in the semiconductor memory device 3 according to the first embodiment, the component SSE is not disposed at a position overlapping with the component SLT in the Z direction. Therefore, when performing the process of forming a slit corresponding to the component SLT, it is possible to prevent the portion where the component SSE is disposed from being deeper than other portions due to differences in etching selectivity. Therefore, it is possible to suppress short circuits between the select gate lines SGS0a and SGS1a, and between the select gate lines SGS0b and SGS1b, which are associated with the deep etching of the portion where the component SSE is disposed, thereby improving the yield of the semiconductor memory device 3.

[0143] 1.4 Variations

[0144] The semiconductor memory device 3 according to the first embodiment described above can be modified in various ways. Hereinafter, a first modification of the first embodiment will be described, showing the differences from the first embodiment.

[0145] Figure 16 This is a top view showing an example of the planar layout of the select gate line SGSa in the lead-out region of the memory cell array of a semiconductor memory device according to a first variation of the first embodiment. Figure 16 The image shows the outgoing region HA, and a portion of the nearby storage regions MA1 and MA2. Figure 16 The area shown corresponds to blocks BLK0 to BLK2. Additionally, in Figure 16 For the sake of simplicity, a portion of the insulating layer has been omitted. Additionally, in Figure 16 In the diagram, dashed lines indicate the positions of the wiring layers (word lines WL0 to WL7) located above the select gate line SGSa when viewed from above.

[0146] In the memory cell array 10 of the semiconductor memory device 3 according to the first variation of the first embodiment, the component SSE may also be provided in the lead-out portion HP1 or HP2. The component SSE is formed, for example, as a plate extending along the XZ plane. The component SSE is provided, for example, below the platform portion of the wiring layer provided above the select gate line SGSa. When the component SSE is provided in the lead-out portion HP1, in top view, the component SSE is provided on the component SLTe side, which is adjacent to the block BLK where the component SSE is provided, more so than the platform portion of the select gate lines SGSa and SGSb. When the component SSE is provided in the lead-out portion HP2, in top view, the component SSE is provided on the component SLTo side, which is adjacent to the block BLK where the component SSE is provided, more so than the platform portion of the select gate lines SGSa and SGSb. In addition, when there are three or more wiring layers 22 corresponding to the select gate line SGS, the component SSE is provided in such a way that the wiring layer 22 is not divided into the memory region MA1 side and the memory region MA2 side for all wiring layers 22.

[0147] 2. Second Implementation Method

[0148] Next, the semiconductor memory device according to the second embodiment will be described. The semiconductor memory device 3 according to the second embodiment differs from the semiconductor memory device 3 according to the first embodiment in that it also includes the component SLTp. In the following description, the description of the same configuration and manufacturing process as the first embodiment will be omitted, and the configuration that is different from the first embodiment will be mainly described.

[0149] 2.1 Construction of Storage Cell Array

[0150] Figure 17 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory cell array included in the semiconductor memory device according to the second embodiment. Figure 17 As shown, the memory cell array 10 of the semiconductor memory device 3 according to the second embodiment further includes a plurality of components SLTp. In addition, a portion of the lead-out region HA of the component SHE in the second embodiment is provided in the bridging portion BRG in such a way that it bypasses the lead-out portions HP1 and HP2 when viewed from above and does not overlap with the component SLT in the Z direction.

[0151] Each component SLTp has, for example, a plate-like shape extending in the YZ plane. Each component SLTp has, for example, a structure in which insulators and plate-like contacts are embedded. Each component SLTp passes through (through) the select gate lines SGSa and SGSb, word lines WL0 to WL7, and insulating layers 41, 42, 43, 44, and 45 along the Z direction. Each component SLTp is, for example, connected to wiring layer 21 at its lower end.

[0152] like Figure 17 As shown, each component SLTp is disposed in the lead-out portion HP1 or HP2 in such a way that the select gate lines SGSa and SGSb, and the word lines WL0 to WL7 are not divided in the X direction. Therefore, each component SLTp is configured not to contact component SHE. Each component SLTp can be disposed at any position in the lead-out region HA as long as it is included in the lead-out portion HP1 or HP2 and does not overlap in the Z direction with the portion of the stacked wiring platform that is connected to the corresponding contact CC. Each component SLTp is disposed, for example, in a manner that crosses the first step structure or the second step structure in the Y direction.

[0153] Furthermore, during the replacement process in the manufacturing process, the shape of the component SLTp is irrelevant as long as it has a sufficient size to allow the conductive material (e.g., tungsten) to flow into it. For example, the component SLTp can also be cylindrical.

[0154] 2.2 Effects of the Second Implementation Method

[0155] According to the second embodiment, similarly to the first embodiment, the driving speed of the semiconductor memory device can be improved.

[0156] Furthermore, according to the second embodiment, the yield of semiconductor memory devices can be improved. This effect will be explained in detail below.

[0157] When manufacturing the semiconductor memory device 3 according to the second embodiment, the wiring layer 22 corresponding to the select gate lines SGSa and SGSb is replaced starting from the slit provided in the portion corresponding to the components SLT and SLTp. At this time, when the SGS split structure is formed by the same process as the first manufacturing process in the first embodiment, the distance from the far end of the wiring layer 22 to the nearest slit is shortened by providing the slit corresponding to the component SLTp. Therefore, it is possible to suppress the situation where conductive material (e.g., tungsten) does not flow to the far end of the wiring layer 22 during replacement, thus preventing the formation of voids. Therefore, the yield of the semiconductor memory device 3 can be improved.

[0158] 2.3 Variations

[0159] The semiconductor memory device 3 according to the second embodiment described above can be modified in various ways. Hereinafter, a first modification of the second embodiment will be described to explain the differences from the second embodiment.

[0160] Figure 18 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory cell array in the semiconductor memory device according to the first variation of the second embodiment. Figure 18 As shown, in the memory cell array 10 of the semiconductor memory device 3 according to the first variation of the second embodiment, component SLTp is connected to component SLT in the Y direction, forming a single component. In other words, component SLTp can be considered as a portion of component SLT protruding into lead-out portion HP1 or HP2. Component SLTp provided at lead-out portion HP1 is connected to component SLTo, forming a single component. Component SLTp provided at lead-out portion HP2 is connected to component SLTe, forming a single component.

[0161] According to the first variation of the second embodiment, similarly to the second embodiment, the driving speed of the semiconductor memory device can be improved. Furthermore, similarly to the second embodiment, the yield of the semiconductor memory device can be improved.

[0162] 3. Other

[0163] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to the invention as described in the claims.

[0164] [Explanation of reference numerals in the attached figures]

[0165] 1: Storage System

[0166] 2: Memory controller

[0167] 3: Semiconductor memory devices

[0168] 10: Memory cell array

[0169] 11: Input / output circuit

[0170] 12: Logic control circuit

[0171] 13: Registers

[0172] 14: Sequencer

[0173] 15: Driver Module

[0174] 16: Line decoder module

[0175] 17: Sensing Amplifier Module

[0176] 21, 22, 23, 24, 25, 26: Wiring Layer

[0177] 30: Core membrane

[0178] 31: Semiconductor film

[0179] 32: Laminated film

[0180] 33: Tunnel insulation film

[0181] 34: Charge storage membrane

[0182] 35: Barrier insulating film

[0183] 40, 41, 42, 43, 44, 45, 46: Insulating layer

[0184] 47: Insulator

[0185] 51: Sacrificial component

[0186] 100: Control Circuit Layer

[0187] 200: Storage layer

[0188] 300: Wiring layer

[0189] B1, B2: Bonding layer

[0190] BL: Bitline

[0191] BLK: Block

[0192] BP1, BP2: Bonding pads

[0193] BRG: Bridging section

[0194] CC, CV, LI: Contacts

[0195] CU: Unit

[0196] HA: Lead-out region

[0197] HP1, HP2: Lead-out section

[0198] IP1, IP2: Inclined section

[0199] MA1, MA2: Storage areas

[0200] MP: Storage column

[0201] MT: Memory cell transistor

[0202] NS: NAND string

[0203] PD: solder pad

[0204] SGD, SGSa, SGSb: Select gate line

[0205] SHE, SSE, SLT, SLTe, SLTo, SLTp: Components

[0206] SSH: Slit

[0207] SL: Source Line

[0208] SP: Spacer

[0209] ST1, ST2: Select transistors

[0210] SU: Serial Unit

[0211] W1, W2: Semiconductor substrates

[0212] WL: Word Line

Claims

1. A semiconductor memory device comprising: a first wiring layer provided in a first region; a second wiring layer arranged separately from the first wiring layer in a first direction, provided across the first region and a second region arranged in a second direction intersecting the first direction; a plurality of third wiring layers provided separately from each other in the first direction on a side opposite to the first wiring layer with respect to the second wiring layer; a first insulating member and a second insulating member arranged in a third direction intersecting the first direction and the second direction, each extending along the second direction, dividing the second wiring layer and the plurality of third wiring layers in the third direction; a third insulating member provided between the first insulating member and the second insulating member and between the first wiring layer and the plurality of third wiring layers, dividing the second wiring layer in the third direction into a first portion and a second portion; a first storage pillar extending along the first direction between the first insulating member and the third insulating member in the second region, interfacing with the first wiring layer, intersecting the first portion of the second wiring layer, and portions respectively intersecting the plurality of third wiring layers functioning as a plurality of first storage cells; a second storage pillar extending along the first direction between the second insulating member and the third insulating member in the second region, interfacing with the first wiring layer, intersecting the second portion of the second wiring layer, and portions respectively intersecting the plurality of third wiring layers functioning as a plurality of second storage cells; and a first contact and a second contact extending along the first direction in the first region, the second wiring layer having: a first terrace portion in the first portion in the first region, interfacing with the first insulating member and not overlapping the plurality of third wiring layers when viewed in the first direction; and a second terrace portion in the second portion in the first region, interfacing with the second insulating member and not overlapping the plurality of third wiring layers when viewed in the first direction, the first contact being electrically connected to the first terrace portion of the second wiring layer, and the second contact being electrically connected to the second terrace portion of the second wiring layer.

2. The semiconductor memory device according to claim 1, wherein the plurality of third wiring layers each have, in the first region: a first bridge portion interfacing with the second insulating member and extending along the second direction between the first terrace portion of the second wiring layer and the second insulating member; a second bridge portion interfacing with the first insulating member and extending along the second direction between the second terrace portion of the second wiring layer and the first insulating member; and a third bridge portion extending along the third direction between the first insulating member and the second insulating member and interfacing with the first bridge portion and the second bridge portion.

3. The semiconductor memory device according to claim 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ Further provided are a third contact and a fourth contact that extend in the first direction within the first region, The plurality of third wiring layers includes a fourth wiring layer and a fifth wiring layer, The fourth wiring layer has a third land portion that is disposed so as to be in contact with the first insulating member within the first region and not to overlap the plurality of third wiring layers in the first direction as seen in the first direction with the upper layer, The fifth wiring layer has a fourth land portion that is disposed so as to be in contact with the second insulating member within the first region and not to overlap the plurality of third wiring layers in the first direction as seen in the first direction with the upper layer, The third contact is electrically connected to the third land portion of the fourth wiring layer, The fourth contact is electrically connected to the fourth land portion of the fifth wiring layer.

4. The semiconductor storage device according to claim 3, wherein The third insulating member is disposed within the first region at a position where the first bridge portion, the second bridge portion, and the third bridge portion of the plurality of third wiring layers overlap in the first direction, respectively.

5. The semiconductor storage device according to claim 4, wherein The third insulating member includes: a third portion that extends in the second direction within the first region at a position where the first bridge portion of the plurality of third wiring layers overlaps in the first direction; a fourth portion that extends in the second direction within the first region at a position where the second bridge portion of the plurality of third wiring layers overlaps in the first direction; and a fifth portion that extends in the third direction within the first region at a position where the third bridge portion of the plurality of third wiring layers overlaps in the first direction and is in contact with the third portion and the fourth portion.

6. The semiconductor storage device according to claim 1, wherein The capacitance of the first portion of the second wiring layer is substantially equal to the capacitance of the second portion.

7. The semiconductor storage device according to claim 3, wherein The third insulating member is disposed at a position where the third land portion of the fourth wiring layer or the fourth land portion of the fifth wiring layer overlaps in the first direction.

8. The semiconductor storage device according to claim 1, wherein Further provided is a control circuit that independently applies a voltage to the first portion and the second portion of the second wiring layer, respectively.

9. The semiconductor storage device according to claim 1, wherein Further provided are: a sixth wiring layer that is disposed so as to be separated from each other in the first direction on a side opposite to the second wiring layer with respect to the plurality of third wiring layers; and a fourth insulating member that divides the sixth wiring layer in the third direction between the first insulating member and the second insulating member, The first land portion and the second land portion of the second wiring layer are disposed so as not to overlap the sixth wiring layer as seen in the first direction, ​ The first storage pillar and the second storage pillar intersect with the sixth wiring layer, In the second region, the third insulating member and the fourth insulating member are disposed at positions overlapping in the first direction.

10. The semiconductor storage device according to claim 1, wherein The third insulating member has a tapered shape that interfaces with a wiring layer disposed on the most first-wiring-layer side among the plurality of third wiring layers in the first direction and tapers from the plurality of third-wiring-layer side toward the first-wiring-layer side.

11. The semiconductor storage device according to claim 1, wherein The third insulating member has a tapered shape that interfaces with the first wiring layer in the first direction and tapers from the first-wiring-layer side toward the plurality of third-wiring-layer side.

12. The semiconductor storage device according to claim 1, wherein Further comprising a third storage pillar and a fourth storage pillar, The first wiring layer, the second wiring layer, and the plurality of third wiring layers further comprise a third region disposed so as to sandwich the first region together with the second region in the second direction, The third storage pillar extends between the first insulating member and the third insulating member in the third region in the first direction, interfaces with the first wiring layer, intersects with the first portion of the second wiring layer, and portions that respectively intersect with the plurality of third wiring layers function as a plurality of third storage cells, The fourth storage pillar extends between the second insulating member and the third insulating member in the third region in the first direction, interfaces with the first wiring layer, intersects with the second portion of the second wiring layer, and portions that respectively intersect with the plurality of third wiring layers function as a plurality of fourth storage cells.

13. The semiconductor storage device according to claim 12, wherein Portions of the first portion of the second wiring layer disposed in the second region and portions disposed in the third region interface via portions disposed in the first region, Portions of the second portion of the second wiring layer disposed in the second region and portions disposed in the third region interface via portions disposed in the first region.

14. The semiconductor storage device according to claim 12, wherein Further comprising: a sixth wiring layer disposed separately from each other in the first direction on a side opposite the second wiring layer with respect to the plurality of third wiring layers; and a fourth insulating member that divides the sixth wiring layer in the third direction between the first insulating member and the second insulating member, The first land portion and the second land portion of the second wiring layer are disposed so as not to overlap the sixth wiring layer when viewed in the first direction, The third storage pillar and the fourth storage pillar intersect with the sixth wiring layer, In the third region, the third insulating member and the fourth insulating member are disposed at positions overlapping in the first direction.

15. The semiconductor storage device according to claim 1, wherein Further comprising: a fifth insulating member that, in the first region, passes through the first portion of the second wiring layer and the plurality of third wiring layers in the first direction without contacting the third insulating member between the first insulating member and the third insulating member; and a sixth insulating member that, in the first region, passes through the second portion of the second wiring layer and the plurality of third wiring layers in the first direction without contacting the third insulating member between the second insulating member and the third insulating member.

16. The semiconductor memory device according to claim 15, wherein the fifth insulating member is continuous with the first insulating member in the third direction, the sixth insulating member is continuous with the second insulating member in the third direction.

17. The semiconductor memory device according to claim 15, wherein the fifth insulating member and the sixth insulating member are provided at positions where the first contact and the second contact do not overlap in the first direction.

18. The semiconductor memory device according to claim 1, wherein Further comprising: a seventh wiring layer that is provided so as to be separated from each other in the first direction in a manner of being sandwiched between the first wiring layer and the second wiring layer; and a fifth contact and a sixth contact that extend in the first direction in the first region, the third insulating member divides the seventh wiring layer into a sixth portion and a seventh portion in the third direction, the seventh wiring layer has a fifth flat portion and a sixth flat portion, the fifth flat portion, in the sixth portion in the first region, is continuous with the first insulating member and does not overlap with any of the second wiring layer and the plurality of third wiring layers when viewed in the first direction, the sixth flat portion, in the seventh portion in the first region, is continuous with the second insulating member and does not overlap with any of the second wiring layer and the plurality of third wiring layers when viewed in the first direction, the first memory pillar intersects the sixth portion of the seventh wiring layer, the second memory pillar intersects the seventh portion of the seventh wiring layer, the fifth contact is electrically connected to the fifth flat portion of the seventh wiring layer, the sixth contact is electrically connected to the sixth flat portion of the seventh wiring layer.

19. The semiconductor memory device according to claim 18, wherein Further comprising a control circuit, the control circuit independently applies voltages to the first portion and the second portion of the second wiring layer respectively, the control circuit independently applies voltages to the sixth portion and the seventh portion of the seventh wiring layer respectively.

20. The semiconductor memory device according to claim 19, wherein the control circuit applies voltages of substantially the same magnitude to the first portion of the second wiring layer and the sixth portion of the seventh wiring layer, the control circuit applies voltages of substantially the same magnitude to the second portion of the second wiring layer and the seventh portion of the seventh wiring layer.

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