Semiconductor device

Abstract

A semiconductor device includes: a cell region including a plurality of memory cells connected to a plurality of word lines, a plurality of plate lines, and a plurality of bit lines; and a peripheral circuit region configured to control the cell region, and the peripheral circuit region inputs a first program voltage and a second program voltage having different polarities to at least one target cell among the plurality of memory cells once, and sensing degradation of the target cell by comparing a voltage of a target bit line connected to the target cell with a predetermined reference voltage, and when the voltage of the target bit line is lower than the reference voltage, the peripheral circuit region inputs a recovery voltage higher than the first program voltage and the second program voltage to the target cell.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0123416, filed on September 10, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Embodiments of the disclosure relate to a semiconductor device. BACKGROUND

[0003] A semiconductor device can provide the ability to write data to a memory cell and erase data from the memory cell, or read recorded data from the memory cell, and the memory cell can record data therein in various ways. Recently, a ferroelectric random access memory (FeRAM) including a ferroelectric layer has been proposed as a semiconductor device capable of recording data, and the FeRAM has the advantage of high-speed operation while having a nonvolatile characteristic of maintaining data even when power is cut off. The FeRAM can record data by changing a polarization state of the ferroelectric layer, and thus, a relationship between a voltage applied to the ferroelectric layer and the polarization state can greatly affect the performance of the FeRAM. SUMMARY

[0004] Some aspects of the disclosure provide a semiconductor device having improved reliability and performance by sensing a change in a polarization state of a ferroelectric layer according to a voltage applied to the ferroelectric layer and performing a recovery operation of the ferroelectric layer based on a sensing result.

[0005] A semiconductor device according to some embodiments of the disclosure includes a cell region in which memory cells connected to a plurality of word lines, a plurality of bit lines, and a plurality of plate lines are disposed, each of the memory cells including a switching element and a capacitor connected to the switching element and including a ferroelectric layer, and a peripheral circuit region configured to control the memory cells through the plurality of word lines, the plurality of bit lines, and the plurality of plate lines, and the peripheral circuit region turns on the switching element included in a target cell among the memory cells to activate the target cell, and when the target cell is activated, the peripheral circuit region inputs a first voltage to a target plate line connected to the target cell and a second voltage higher than the first voltage to a target bit line connected to the target cell, then inputs the second voltage to the target plate line and the first voltage to the target bit line, and when a voltage of the target bit line is lower than a predetermined reference voltage, the peripheral circuit region increases the voltage of the target bit line to a third voltage higher than the second voltage to perform a recovery operation of the target cell.

[0006] A semiconductor device according to some embodiments of the disclosure includes a cell region including a plurality of memory cells connected to a plurality of word lines, a plurality of plate lines, and a plurality of bit lines, and a peripheral circuit region configured to control the cell region, and the peripheral circuit region inputs a first programming voltage and a second programming voltage having different polarities to at least one target cell among the plurality of memory cells at a time, and senses a deterioration of the target cell by comparing a voltage of a target bit line connected to the target cell with a predetermined reference voltage, and when the voltage of the target bit line is lower than the reference voltage, the peripheral circuit region inputs a recovery voltage higher than the first programming voltage and the second programming voltage to the target cell.

[0007] A semiconductor device according to some embodiments of the disclosure includes a cell region including a plurality of memory cells connected to a plurality of word lines, a plurality of plate lines, and a plurality of bit lines, and a peripheral circuit region configured to change a degree of polarization of each of the plurality of memory cells to record first data or second data in each of the plurality of memory cells, and the peripheral circuit region inputs a predetermined reset voltage to at least one target cell among the plurality of memory cells to reset data of the target cell to the second data, performs a read operation on the target cell to sense a deterioration of the target cell, and inputs a recovery voltage higher than the reset voltage to the target cell in which the deterioration is sensed.

[0008] According to some embodiments of the disclosure, each of the memory cells can include a switching element and a capacitor, and the capacitor can include a ferroelectric layer. When the semiconductor device is started or at a certain time, for at least one target cell among the memory cells, a voltage applied to the ferroelectric layer and a polarization state according to the applied voltage can be sensed, and a recovery operation of the target cell can be performed based on the sensing result. Accordingly, reliability and performance of the semiconductor device that records data by changing the polarization state of the ferroelectric layer can be improved.

[0009] Advantages and effects of the present application are not limited to the foregoing, and can be understood based on the following disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram schematically illustrating an example of a semiconductor device;

[0012] Figures 2 to 4 is a schematic diagram illustrating an example of a memory cell array included in a semiconductor device;

[0013] Figure 5 is a polarization curve graph illustrating characteristics of an example of a memory cell included in a semiconductor device;

[0014] Figure 6A , Figure 6B , Figure 7A and Figure 7B These are circuit diagrams and polarization curves illustrating examples of programming operations on semiconductor devices;

[0015] Figure 8 This is a voltage curve illustrating an example of a read operation on a semiconductor device;

[0016] Figure 9 This is a flowchart illustrating an example of a recovery operation for a semiconductor device;

[0017] Figure 10 This is a voltage curve diagram illustrating an example of the recovery operation of a semiconductor device;

[0018] Figures 11 to 13 This is a diagram illustrating an example of a recovery operation of a semiconductor device;

[0019] Figure 14A and Figure 14B This is a polarization graph illustrating an example of the recovery operation of a semiconductor device;

[0020] Figure 15A and Figure 15B These are circuit diagrams and voltage curves illustrating an example of the operation of the semiconductor device.

[0021] Figure 16 This is a flowchart illustrating an example of a recovery operation for a semiconductor device;

[0022] Figure 17 This is a voltage curve illustrating an example of the recovery operation of a semiconductor device; and

[0023] Figures 18 to 20 This is a diagram illustrating an example of a recovery operation of a semiconductor device. Detailed Implementation

[0024] Figure 1 This is a block diagram schematically illustrating a semiconductor device according to some embodiments of the present disclosure.

[0025] refer to Figure 1Semiconductor device 10 can be a storage device based on semiconductor elements. Semiconductor device 10 can be a random access memory (RAM) device and can be used as main memory in electronic devices such as desktop computers, laptop computers, tablet PCs, and smartphones. Semiconductor device 10 can, in response to address signals and control command signals received from an external host (e.g., a central processing unit (CPU), application processor (AP), system-on-a-chip (SoC), etc.), store received data as a data signal DQ, or read stored data and output the data as a data signal DQ.

[0026] Semiconductor device 10 may include cell region 20 and peripheral circuit region 30. Cell region 20 may include multiple memory cells, and the multiple memory cells may be included in a memory cell array. Peripheral circuit region 30 may include word line driving circuit 31, board line driving circuit 32, sense amplifier circuit 33, data input / output circuit 34, and control logic 35, and may control unit region 20.

[0027] Multiple memory cells included in cell region 20 can be connected to word lines WL, bit lines BL, and board lines PL and can be included in a memory cell array. Multiple memory cells can be connected to word line driver circuit 31 via word line WL and to board line driver circuit 32 via board line PL. Simultaneously, multiple memory cells can be connected to sense amplifier circuit 33 via bit line BL, and sense amplifier circuit 33 can perform programming and reading operations via bit line BL. Each of the multiple memory cells can be located at the point where word line WL and bit line BL intersect.

[0028] Each of the plurality of memory cells (e.g., at least some) may include a switching element and a capacitor connected to the switching element, and the capacitor may include electrodes and a ferroelectric layer. A first electrode of the electrodes included in the capacitor may be connected to the switching element, and a second electrode may be connected to a board line PL. Meanwhile, the switching element may be implemented using a transistor, and the gate of the transistor may be connected to a word line WL, one of the source / drain regions of the transistor may be connected to the first electrode of the capacitor, and another of the source / drain regions of the transistor may be connected to a bit line BL. The peripheral circuit region 30 can record data by changing the polarization state and polarization degree of the ferroelectric layer in the capacitor included in the memory cell.

[0029] Control logic 35 can receive address signals and control command signals from an external host. The address signals may include row addresses indicating rows in the memory cell array of cell region 20 and column addresses indicating columns in the memory cell array. For example, word line driver circuit 31 can determine the selected word line among multiple word lines WL by referring to the row address, and board line driver circuit 32 and sense amplifier circuit 33 can determine the selected board line and selected bit line by referring to the column address.

[0030] The sense amplifier circuit 33 may include multiple sense amplifiers connected to the cell region 20 via multiple bit lines BL. For example, when performing a read operation, a sense amplifier connected to a selected bit line can read data from a selected memory cell connected to the selected bit line. The data input / output circuit 34 may also output the data read by the sense amplifier as a data signal DQ.

[0031] When a programming operation is performed, a predetermined programming voltage can be applied to a selected bit line and a selected board line connected to the selected memory cell while the switching element included in the selected memory cell is turned on. In some embodiments, the programming voltage is determined by the difference between the voltage applied to the selected board line and the voltage applied to the selected bit line, and the polarization of the ferroelectric layer in the capacitor included in the selected memory cell can be changed by the programming voltage. The polarization can include the polarization direction and / or polarization degree (e.g., the magnitude of polarization) of the ferroelectric layer.

[0032] In this way, the polarization of the ferroelectric layer included in the capacitor of the memory cell can be changed by the voltage applied to the memory cell. The polarization of the ferroelectric layer and the voltage applied to the memory cell can have a relationship defined by a hysteresis curve. When a specific voltage is continuously applied to the memory cell, the relationship between voltage and polarization expressed by the hysteresis curve can change, which may lead to the degradation of the characteristics of the memory cell and the performance of the semiconductor device 10.

[0033] In some embodiments according to this disclosure, changes in the characteristics of memory cells can be sensed, and recovery operations can be performed on the corresponding memory cells based on the sensing results. Therefore, performance degradation of the semiconductor device 10 can be minimized to improve reliability, and the lifespan of the semiconductor device 10 can also be extended.

[0034] Figures 2 to 4 This is a schematic diagram illustrating an array of memory cells included in a semiconductor device.

[0035] First, refer to Figure 2The memory cell array 40 may include multiple memory cells MC connected to multiple word lines WL1 to WLm (WL), multiple board lines PL1 to PLm (PL), and multiple bit lines BL1 to BLn (BL). The number of word lines WL, board lines PL, bit lines BL, and memory cells MC may vary in different embodiments. The multiple memory cells MC may be located at the points where the word lines WL, board lines PL, and bit lines BL intersect each other.

[0036] As referenced above Figure 1 The multiple word lines WL can be connected to a word line driver circuit, the multiple board lines PL can be connected to a board line driver circuit, and the multiple bit lines BL can be connected to a sense amplifier circuit. When a selected word line selected by the word line driver circuit and a selected board line selected by the board line driver circuit are determined, programming, reading, and restoring operations can be performed on selected memory cells connected to the selected word line and the selected board line. Each of the multiple bit lines BL can be connected to a different sense amplifier included in the sense amplifier circuit, allowing each of the selected memory cells to be controlled individually.

[0037] Figure 3 This is a circuit diagram of the memory cell MC. (Reference) Figure 3 A memory cell MC included in a semiconductor device may include a switching element SW and a capacitor CC connected to each other. The switching element SW may be implemented, for example, a transistor, and the gate of the transistor may be connected to a word line WL. Meanwhile, one of the source / drain regions of the switching element SW may be connected to a bit line BL, and the other may be connected to a capacitor CC. The capacitor CC may include a ferroelectric layer and may be connected to a plate line PL.

[0038] When the semiconductor device selects a memory cell MC via an address signal received from an external host, the switching element SW can be turned on by applying a voltage to the word line WL. Then, programming operations can be performed to change the polarization of capacitor CC by applying voltage to each of the bit line BL and board line PL, and reading operations can be performed to read data recorded in the memory cell MC by determining the polarization of capacitor CC. The programming and reading operations are explained below.

[0039] refer to Figure 4 The memory cell array 50 may include multiple memory cells connected to multiple word lines WL1 to WL2, multiple board lines PL1 to PL5, and multiple bit lines BL1 to BL2. In some embodiments, such as Figure 4 As shown, some of the multiple memory cells can share a single switching element SW. (Reference) Figure 4Multiple capacitors CC can be connected to the first switching element SW1, which is connected to the first bit line BL1 and the first word line WL1.

[0040] like Figure 4 As shown, multiple capacitors CC can be connected to different board lines PL1 to PL5. For example, multiple capacitors CC connected to the first switching element SW can be matched one-to-one with multiple board lines PL1 to PL5. Therefore, the polarization of each of the multiple capacitors CC sharing a single switching element can be controlled individually.

[0041] For example, in a state where the first switching element SW1 and the second switching element SW2 are turned on by applying a voltage to the first word line WL1, the polarization of the capacitor CC connected only to the first board line PL can be changed by applying a voltage to the first word line BL1 and the first board line PL1. In order to selectively change only the polarization of the capacitor CC connected to the first board line PL, the same voltage as the first word line BL1 can be applied to the second board lines PL2 to PL5, or the second board lines PL2 to PL5 can be floated.

[0042] For reference Figures 2 to 4 The memory cell of the semiconductor device includes a capacitor CC, and the capacitor CC may include a ferroelectric layer. The polarization of the ferroelectric layer may vary depending on the voltage applied to the memory cell, and, for example, the relationship between voltage and polarization may be expressed as a hysteresis curve. Reference will be made below to... Figure 5 To describe this in more detail.

[0043] Figure 5 This is a view illustrating the characteristics of a memory cell included in a semiconductor device. Figure 5 This is a graph illustrating the relationship between the voltage applied to a memory cell and the polarization of the ferroelectric layer included in the memory cell. For example... Figure 5 As illustrated in the figure, the relationship between the voltage applied to the memory cell and the polarization of the ferroelectric layer included in the memory cell can be expressed as a hysteresis curve.

[0044] Referring to the first pattern G1, under the condition that a positive voltage is applied to the memory cell, the polarization of the ferroelectric layer can increase in a specific direction along the first curve CV1. For example, the voltage of the plate line connected to the memory cell can be set to be higher than the voltage of the bit line connected to the memory cell, so that a positive voltage can be applied to the memory cell. The polarization of the ferroelectric layer can be changed by the positive voltage applied to the memory cell. Then, even if the voltage applied to the memory cell is cut off, the polarization of the ferroelectric layer can maintain the first positive polarization (P+).

[0045] On the other hand, when a negative voltage is applied to a memory cell, the polarization of the ferroelectric layer can be changed along the second curve CV2 in a direction different from the first positive polarization (P+). The voltage of the plate line connected to the memory cell can be set lower than the voltage of the bit line connected to the memory cell, allowing a negative voltage to be applied to the memory cell. The polarization of the ferroelectric layer included in the memory cell can be reduced to a first negative polarization (P1-) by the negative voltage, and this first negative polarization (P1-) can be maintained even if the voltage applied to the memory cell is cut off.

[0046] In this way, data can be recorded in a memory cell by changing the polarization of the ferroelectric layer to either the negative or positive direction. For example, the state in which the polarization of the ferroelectric layer is changed to the negative direction can be defined as the state in which the first data is recorded in the memory cell, and the state in which the polarization of the ferroelectric layer is changed to the positive direction can be defined as the state in which the second data is recorded in the memory cell. Assuming that 1 bit of data is recorded in the memory cell, one of the first and second data can correspond to "0", and the other can correspond to "1".

[0047] However, when a positive or negative voltage is repeatedly applied to a memory cell due to the operation of a semiconductor device, the hysteresis curve indicating the relationship between voltage and polarization may not remain as the first curve G1 and may shift in the horizontal direction. For example, when a positive voltage is repeatedly applied to a memory cell, as... Figure 5 The relationship between voltage and polarization represented by the first graph G1 shown can be shifted to the left as in the second graph G2 and the third graph G3.

[0048] A horizontal shift in the hysteresis curve can indicate a change in the characteristics of a memory cell. For example, referring to the third graph G3, the polarization of the ferroelectric layer under a programming operation where a positive voltage is applied to the memory cell is not significantly different from the first positive polarization (P+), while the polarization of the ferroelectric layer under a programming operation where a negative voltage is applied to the memory cell can change from the first negative polarization (P1-) to the second negative polarization (P2-). In some cases, such as... Figure 5 As shown, the absolute value of the second negative polarization (P2-) can be smaller than the absolute value of the first negative polarization (P1-).

[0049] In some implementations, a read operation for a memory cell is performed by applying a read voltage, which is a positive voltage, to the memory cell while the switching element included in the memory cell is turned on. For example, in the case of a memory cell in which first data is recorded, since the ferroelectric layer has positive polarization (P+), the polarization of the ferroelectric layer may not change much due to the read voltage, which is a positive voltage. Therefore, the voltage of the capacitor including the ferroelectric layer can be sensed as relatively small. On the other hand, in the case of a memory cell in which second data is recorded, since the ferroelectric layer has negative polarization (P1- or P2-), the polarization of the ferroelectric layer can be changed relatively large by the read voltage, which is a positive voltage, and the voltage of the capacitor can be sensed as relatively large during the read operation.

[0050] During a read operation, the voltage of a sense capacitor can be measured from bit lines connected to the memory cell, and the capacitor voltage can be determined based on the difference between the polarization of the ferroelectric layer of the memory cell before the read operation and the polarization of the ferroelectric layer due to the read voltage applied to the memory cell. Therefore, when the hysteresis curve indicating the characteristics of the memory cell shifts from the first pattern G1 to the third pattern G3, the voltage of the sense capacitor during the read operation of the memory cell in which second data is recorded can decrease, which can lead to a reduction in the performance and reliability of the semiconductor device. When the shift in the hysteresis curve becomes severe, it may be impossible to program the second data for the corresponding memory cell.

[0051] In some implementations, a recovery operation of the memory cell is performed by allocating time during the startup of the semiconductor device or during its operation. The recovery operation can be an operation that restores the relationship between voltage and polarization in the memory cell to a state close to that of the first curve G1 when the relationship changes as shown in the third curve G3. Therefore, the characteristics of the memory cell can be restored through the recovery operation, thereby improving the performance and reliability of the semiconductor device and extending its lifespan.

[0052] Figure 6A , Figure 6B , Figure 7A and Figure 7B The diagram illustrates the programming operations of a semiconductor device. Figure 6A and 6B The diagram illustrates the programming operations used to record the first data into the memory unit MC. (Reference) Figure 6AIn the programming operation of recording the first data, the switching element SW can be turned on by applying a voltage to the word line WL. With the switching element SW on, a first bias voltage VBIAS1 can be applied to the bit line BL, and a second bias voltage VBIAS2 can be applied to the board line PL. The second bias voltage VBIAS2 can be higher than the first bias voltage VBIAS1, and the first bias voltage VBIAS1 can be a reference voltage such as ground voltage.

[0053] The difference between the first bias voltage VBIAS1 and the second bias voltage VBIAS2 can be defined as the first programming voltage VPGM1, and the first programming voltage VPGM1 can be a positive voltage. Refer to the hysteresis curve of the memory cell MC in the figure. Figure 6B The polarization of the ferroelectric layer, including that in capacitor CC, can be changed to a positive polarization (P+) by a first programming voltage VPGM1. Even after the voltage supply to each of the plate lines PL and BL is cut off, the polarization of the ferroelectric layer can remain positive (P+), and the first data recorded in the memory cell MC can be retained. Depending on the degree of degradation of the memory cell MC, during the first programming operation, the polarization of the ferroelectric layer can be changed from a first negative polarization (P1-) to a positive polarization (P+), or from a second negative polarization (P2-) to a positive polarization (P+).

[0054] Figure 7A and 7B The diagram illustrates the programming operation of recording the second data into the memory unit MC. (Reference) Figure 7A In the programming operation of recording the second data, the switching element SW can be turned on by applying a voltage to the word line WL, and the first bias voltage VBIAS1 can be applied to the board line PL and the second bias voltage VBIAS2 can be applied to the bit line BL. Similar to the reference... Figure 6A As an example of the explanation, the second bias voltage VBIAS2 can be higher than the first bias voltage VBIAS1, and the first bias voltage VBIAS1 can be a reference voltage such as ground voltage.

[0055] The difference between the first bias voltage VBIAS1 and the second bias voltage VBIAS2 can be defined as the second programming voltage VPGM2, and the second programming voltage VPGM2 can be a negative voltage. For example, the first programming voltage VPGM1 and the second programming voltage VPGM2 can have the same amplitude, but their polarities can be opposite to each other.

[0056] Refer to the hysteresis curve of the memory cell MC shown in the figure. Figure 7BThe polarization of the ferroelectric layer, including in capacitor CC, can be changed from positive polarization (P+) to negative polarization (P1- or P2-) by a second programming voltage VPGM2. Even after the voltage supply to each of the plate line PL and bit line BL is cut off, the polarization of the ferroelectric layer can be maintained at negative polarization (P1- or P2-), and the second data recorded in the memory cell MC can be retained.

[0057] Depending on the degree of degradation of the memory cell MC, during the second programming operation, the polarization of the ferroelectric layer is sometimes changed from positive polarization (P+) to a first negative polarization (P1-) or a second negative polarization (P2-). When a specific voltage is repeatedly applied to the memory cell MC, for example, when a positive voltage is repeatedly applied to the memory cell MC, the hysteresis curve may shift further to the left. In this case, after terminating the input of the second programming voltage VPGM2, the polarization of the ferroelectric layer, which has been reduced to the first negative polarization (P1-) by the second programming voltage VPGM2, can be increased to a value greater than the second negative polarization (P2-).

[0058] Memory cell MC can degrade due to, for example, the repeated application of a specific voltage to the memory cell MC, and the degradation of the memory cell MC can be represented as a horizontal shift in the hysteresis curve. For example... Figure 7B As shown, when the hysteresis curve shifts to the left, the polarization of the ferroelectric layer, which decreased to the first negative polarization (P1-) during the application of the second programming voltage VPGM2, can increase after the input of the second programming voltage VPGM2 is terminated. In the case of severe degradation of the memory cell MC, the polarization of the ferroelectric layer can change to positive polarization after the input of the second programming voltage VPGM2 is terminated, in which case the second data may not be programmable.

[0059] Conversely, when the hysteresis curve shifts to the right, the polarization of the ferroelectric layer, which decreased to a first positive polarization (P1+) during the application of the first programming voltage VPGM1, can decrease after the input of the first programming voltage VPGM1 is terminated. In cases of severe degradation of the memory cell MC, the polarization of the ferroelectric layer can change to negative polarization after the input of the first programming voltage VPGM1 is terminated, in which case the first data may not be programmable.

[0060] In some implementations, a recovery operation for compensating for degradation of memory cells MC as described above can be performed in the semiconductor device. The recovery operation can be performed after an operation to sense the degradation of the memory cells MC, and in some implementations, the recovery operation can be performed only for memory cells MC in which degradation is sensed. For example, the degradation of the memory cells MC can be determined by sequentially inputting voltages of different signs to the memory cells MC and measuring the voltage of the capacitors included in the memory cells MC at the bit line BL or board line PL. For memory cells MC in which degradation is sensed, a recovery operation can be performed by inputting a voltage higher than the first programming voltage VPGM1 and the second programming voltage VPGM2.

[0061] Figure 8 This is a view illustrating the read operation of a semiconductor device. (Reference) Figure 8 The read operation can include an activation segment (ACT), a charge-sharing segment (CS), a sensing segment (RD), a write segment (RW), and a pre-charge segment (PRECH). First, in the activation segment (ACT), a turn-on voltage (VPP) can be input to the selected word line (WL) connected to the selected cell (e.g., a cell that has already been selected). Therefore, the switching element included in the selected cell can be turned on, and the selected cell can be activated.

[0062] Then, in the charge-sharing segment CS, a first voltage VSS can be input to a selected bit line BL connected to the selected cell, and a second voltage Vinta can be input to a selected plate line PL connected to the selected cell. In some embodiments, the first voltage VSS is a ground voltage, and / or the second voltage Vinta is higher than the first voltage VSS and lower than the turn-on voltage VPP. A positive voltage can be applied to the selected cell via the first voltage VSS and the second voltage Vinta, and the polarization of the capacitor included in the selected cell can be set to positive polarization.

[0063] In the sensing section RD, the voltage of the capacitor included in the selected cell, which is subject to a first voltage VSS and a second voltage VINTA, can be sensed from the selected bit line BL by a sensing amplifier. For example, assuming that the first data D0 has been recorded to the selected cell before the read operation begins, the voltage of the selected bit line BL may hardly change from the first voltage VSS, since the polarization of the capacitor included in the selected cell hardly changes in the charge-sharing section CS.

[0064] On the other hand, assuming that the second data D1 has been recorded in the selected cell before the read operation begins, the voltage of the selected bit line BL may increase relatively significantly because the polarization of the capacitor included in the selected cell in the charge-sharing segment CS changes from negative to positive. The sensing amplifier can amplify the voltage of the selected bit line BL in the sensing segment RD and compare the amplified voltage with a reference voltage.

[0065] In some implementations, such as Figure 8 As illustrated in the diagram, the reference voltage compared to the voltage of the selected bit line BL can be the intermediate voltage VMID. For example... Figure 8 As shown, when the voltage of the selected bit line BL is lower than the reference voltage, the data of the selected cell can be read as the first data D0, and when the voltage of the selected bit line BL is higher than the reference voltage, the data of the selected cell can be read as the second data D1.

[0066] When reading data from the selected cell (e.g., afterwards), the voltage of the selected board line PL can be reduced to a first voltage VSS. Then, a write operation to restore the data of the selected cell that was changed in the charge-sharing section CS can be performed during the write segment RW. By applying a positive voltage to the selected cell in the charge-sharing section CS, the data of the selected cell can be changed to the first data D0.

[0067] Therefore, as Figure 8 As shown, when the data of the selected cell is read as the first data D0, a separate write operation is not required. On the other hand, when the data of the selected cell is read as the second data D1, the voltage of the selected bit line BL can be maintained at the second voltage VINTA during the write segment RW, and the second data D1 can be recorded again in the selected cell, while the first data D0 has already been recorded in the selected cell during the charge-sharing segment CS. When the write segment RW terminates, an operation to reduce the voltage of the selected bit line BL to the first voltage VSS can be performed during the precharge segment PRECH.

[0068] For reference Figure 8 The selected cell can be subjected to a positive voltage during the charge-sharing segment CS of the read operation. When the data recorded in the selected cell is the second data D1, since the operation of recording the second data D1 again by applying a negative voltage to the selected cell during the write segment RW can, to some extent, prevent the degradation of the selected cell that might occur due to only a positive voltage being repeatedly applied to it.

[0069] On the other hand, when the data recorded in the selected cell is the first data D0, a positive voltage can also be applied to the selected cell to record the first data D0, and a positive voltage is also applied to the selected cell during the charge-sharing segment CS of the read operation. Since only the selected cell is repeatedly applied with a positive voltage, as described above... Figure 6B and Figure 7B As described, the hysteresis curve relating the indicator voltage to the polarization of the ferroelectric layer included in the selected cell can shift to the left. Therefore, it may become difficult or impossible to record second data in the selected cell, or the difference between the positive and negative polarization may decrease, thereby reducing the accuracy of the readout operation.

[0070] In some embodiments according to this disclosure, a recovery operation for resolving the above-described problems can be performed in a semiconductor device. In the semiconductor device, prior to the recovery operation for the memory cell, a sensing operation for determining the degradation of the memory cell can be performed first, and in the sensing operation, negative and positive voltages can be sequentially applied to the memory cell.

[0071] When the difference between the positive and negative polarization in the ferroelectric layer included in the capacitor decreases due to memory cell degradation, the voltage change of the capacitor may be small in memory cells where negative and positive voltages are applied sequentially. Conversely, when memory cell degradation is not severe, the difference between the positive and negative polarization in the ferroelectric layer included in the capacitor can be sufficiently ensured, allowing the voltage change of the capacitor to be relatively large in memory cells where negative and positive voltages are applied sequentially. Therefore, memory cell degradation can be sensed, and whether a recovery operation should be performed can be determined by sequentially applying negative and positive voltages to the memory cell and measuring the voltage of the capacitor included in the memory cell.

[0072] For example, operations such as sensing memory cell degradation and recovery operations can be performed by the peripheral circuitry of the semiconductor device. When the voltage of a capacitor sensed by a sensing amplifier from a memory cell where negative and positive voltages are sequentially applied, falls below a predetermined reference voltage, the peripheral circuitry can determine that the memory cell has degraded and can perform a recovery operation. The reference voltage compared to the voltage of the capacitor sensed by the sensing amplifier can be compared with a reference voltage. Figure 8 The reference voltage applied to the sensing section RD is described differently.

[0073] Figure 9 This is a flowchart illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure.

[0074] In some implementations, such as reference Figure 9As described, a recovery operation to compensate for the degradation of memory cells can be performed during startup. When the startup of the system including the semiconductor device begins (S100), the peripheral circuit region of the semiconductor device can activate a target word line (S110). The target word line can be one of a plurality of word lines, and can be the word line of the target cell to which the recovery operation is to be performed, connected in the memory cell. The word line driving circuit of the peripheral circuit region can input a conduction voltage to the target word line, so that the switching element of the target cell connected to the target word line can be turned on.

[0075] Next, a reset operation for the target cell can be performed (S120), during which a first programming voltage or a second programming voltage can be input to the target cell. First data can be recorded by inputting the first programming voltage to the target cell, and second data can be recorded by inputting the second programming voltage. The reset operation can reset the data recorded in the target cell to the first or second data. When the target cell is reset, the peripheral circuit area can perform a read operation on the target cell (S130).

[0076] During the read operation, a charge-sharing operation and a sensing operation can be performed for the target cell. In the charge-sharing operation, a voltage with the opposite polarity to the voltage input to the target cell during the reset operation in operation S120 can be input. For example, when a second programming voltage is input to the target cell during the reset operation, a first programming voltage can be input during the charge-sharing operation. The polarization of the capacitor included in the target cell can be set to a first polarization using the first programming voltage, and can be set to a second polarization different from the first polarization using the second programming voltage. In the sensing operation, a sensing amplifier can sense the voltage of the capacitor corresponding to the difference between the first and second polarizations via a target bit line connected to the target cell.

[0077] The peripheral circuit region can determine whether degradation of the target cell has occurred by referring to the voltage of the target bit line sensed by the sensing amplifier in operation S130 (S140). When degradation occurs in the target cell, the difference between the first polarization and the second polarization may appear relatively small, and the voltage sensed by the sensing amplifier in the target bit line may also decrease. Therefore, when the voltage of the target bit line is lower than a predetermined reference voltage, the peripheral circuit region can determine that degradation has occurred in the target cell. On the other hand, when the voltage of the target bit line is higher than the reference voltage, the peripheral circuit region can determine that no degradation has occurred in the target cell.

[0078] When degradation is sensed in operation S140, a recovery operation (S150) can be performed in the peripheral circuit region. The recovery operation can be an operation of applying a recovery voltage to the target cell in which degradation was sensed. The charge imbalance of the capacitors included in the target cell can be resolved by the recovery voltage.

[0079] The recovery voltage can vary depending on the cause and type of degradation occurring in the target cell. For example, degradation of the target cell can occur due to a decrease in the difference between the first and second polarizations, which can be due to a decrease in the first polarization or an increase in the second polarization. When the degradation of the target cell is caused by an increase in the second polarization, a recovery voltage can be applied to the target bit line by applying a higher voltage than that applied to the target board line. When the degradation of the target cell is caused by a decrease in the first polarization, a recovery voltage can be applied to the target board line by applying a higher voltage than that applied to the target bit line.

[0080] When the recovery voltage is input to the target cell, a pre-charge operation to initialize the voltage of the target bit line connected to the target cell can be performed, and the recovery operation can be terminated (S160). Conversely, if no degradation is detected in operation S140, the recovery voltage may not be input to the target cell, and a pre-charge operation to initialize the voltage of the target bit line can be performed, and the recovery operation can be terminated.

[0081] Figure 10 This is a view illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure.

[0082] refer to Figure 10 The recovery operation may include the activation section ACT, the reset section RST, the charge sharing section CS, the detection section DET, the recovery section REC, and the precharge section PRECH. In the activation section ACT, a turn-on voltage VPP can be input to the target word line WL connected to the target cell. This turn-on voltage turns on the switching elements included in the target cell, thus activating the target cell.

[0083] In the Reset Section (RST), the data of the target cell can be reset. In some implementations, such as... Figure 10 As illustrated, during the reset segment RST, a first voltage VSS can be input to the target board line PL connected to the target cell, and a second voltage Vinta, which is higher than the first voltage VSS, can be input to the target bit line BL. In some embodiments, the first voltage VSS can be the power supply voltage, and / or the second voltage Vinta can be higher than the first voltage VSS and lower than the turn-on voltage VPP.

[0084] In some implementations (e.g., at least when the target unit is similar to the reference),Figure 6A and Figure 7A When describing the structure of the memory cell MC, the data of the target cell can be reset to the second data through a reset operation. Furthermore, since a voltage higher than the target board line PL is applied to the target bit line BL, a negative voltage can be applied to the target cell, and the polarization of the ferroelectric layer included in the capacitor of the target cell can be set to negative polarization.

[0085] In the charge-sharing segment CS, a first voltage VSS can be input to the target bit line BL, and a second voltage VINTA can be input to the target plate line PL. A positive voltage can be applied to the target cell via the first voltage VSS and the second voltage VINTA, and the polarization of the ferroelectric layer included in the capacitor of the target cell can be changed from negative polarization to positive polarization.

[0086] During the detection segment DET following the charge-sharing segment CS, a sensing amplifier connected to the target bit line BL can include sensing the voltage change of a capacitor in the target cell. The voltage change sensed by the sensing amplifier from the capacitor in the target cell during the detection segment DET can vary depending on the degree of degradation of the target cell. When the target cell is severely degraded, the difference between the negative polarization set in the ferroelectric layer in the capacitor included in the target cell during the reset segment RST and the positive polarization set in the ferroelectric layer in the capacitor included in the target cell during the charge-sharing segment CS can be small. Therefore, the amplitude of the voltage sensed by the sensing amplifier from the target bit line BL during the detection segment DET can be lower. On the other hand, when the target cell is not severely degraded, the amplitude of the voltage sensed by the sensing amplifier from the target bit line BL during the detection segment DET can be relatively higher.

[0087] The sensing amplifier compares the voltage detected from the target bit line BL during the detection segment DET with a predetermined reference voltage. The reference voltage input to the sensing amplifier during the detection segment DET can be higher than the reference voltage input during the general read operation. For example, setting the reference voltage input to the sensing amplifier during the detection segment DET to be higher than the reference voltage input during the general read operation allows for more stringent sensing of target cell degradation. Thus, even minute degradation that has already occurred in the target cell can be detected during the detection segment DET.

[0088] During the recovery phase (REC), the peripheral circuitry can perform a recovery operation on the target cell based on the determination results in the detection phase (DET). For example, when the determination results in the detection phase (DET) indicate that degradation exists in the target cell, the sense amplifier can increase the voltage of the target bit line BL to a recovery voltage VBL_REC that is higher than the second voltage VINTA.

[0089] During the recovery phase (REC), the voltage of the target bit line PL can be reduced to a first voltage VSS, and therefore, the voltage of the target bit line BL can be increased to the recovery voltage VBL_REC, thus applying a significantly higher negative voltage to the target cell. This can compensate for the degradation that occurs in the target cell where a positive voltage is repeatedly applied. The degradation that occurs in the target cell where a positive voltage is repeatedly applied can include, for example, charge imbalances occurring in capacitors.

[0090] Simultaneously, when it is determined, as a result of the detection segment DET, that there is no degradation in the target cell, the sensing amplifier can maintain the voltage of the target bit line BL at a general bit line voltage VBL_NOR that is substantially the same as the second voltage VINTA. Then, if the recovery segment REC terminates, a pre-charge operation can be performed during the pre-charge segment PRECH to reduce the voltage of the target bit line BL to a first voltage VSS. For example, the pre-charge operation can be performed when a predetermined time has elapsed after sensing in the detection segment DET (e.g., a predetermined time after sensing that the voltage of the target bit line BL is lower than a predetermined reference voltage) or in response to this.

[0091] In some implementations, such as reference Figure 10 As described, the recovery operation may include applying voltages of different polarities to the target cell once while the target word line WL is activated, and then detecting the voltage change of the capacitor included in the target cell from the target bit line BL. (See reference...) Figure 5 As described by the hysteresis curve, the voltage change of the capacitor may appear relatively small as the target cell deteriorates more severely.

[0092] The first input terminal of the sense amplifier can be connected to the target bit line BL, and the second input terminal can receive a reference voltage. When the voltage change of the capacitor detected from the target cell through the target bit line BL is lower than the reference voltage, the control logic connected to the sense amplifier can determine that degradation exists in the target cell and perform a recovery operation. In the recovery operation, a negative voltage can be applied to the target cell, the absolute value of which is greater than the voltage applied to the target cell during normal read and normal program operations. Therefore, the causes of target cell degradation, such as capacitor charge imbalance, can be addressed, and the reliability and performance of the semiconductor device can be improved and its lifespan extended by compensating for the degradation of the target cell.

[0093] Figures 11 to 13 This is a view illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure.

[0094] refer to Figures 11 to 13The described semiconductor device 100 may include a plurality of memory cells MC1 to MC25, and the plurality of memory cells MC1 to MC25 may be connected to a plurality of word lines WL1 to WL5 (WL), a plurality of board lines PL1 to PL5 (PL), and a plurality of bit lines BL1 to BL5 (BL). The voltage of each of the plurality of word lines WL may be controlled by word line driving circuitry included in a peripheral circuitry region of the semiconductor device 100, and the voltage of each of the plurality of board lines PL may be controlled by board line driving circuitry included in a peripheral circuitry region of the semiconductor device 100. The plurality of bit lines BL may be connected to a sense amplifier included in a sense amplifier circuitry. The number of the plurality of memory cells MC1 to MC25 may vary depending on the implementation.

[0095] Each of the plurality of memory cells MC1 to MC25 may have a first programming state in which first data D0 is recorded or a second programming state in which second data D1 is recorded. The programming state of the plurality of memory cells MC1 to MC25 can be determined by voltages applied to a plurality of board lines PL and a plurality of bit lines BL. For example, in a state in which the first word line WL1 is selected, a first bias voltage can be applied to the fifth bit line BL5, and a second bias voltage higher than the first bias voltage can be applied to the fifth board line PL5, such that the first data D0 can be recorded in the fifth memory cell MC5. Simultaneously, in a state in which the first word line WL1 is selected, a second bias voltage can be applied to the first bit line BL1 and a first bias voltage can be applied to the first board line PL1, such that the second data D1 can be recorded in the first memory cell MC1.

[0096] Figure 11 This is a view illustrating the programming state of each of a plurality of memory cells MC1 to MC25 when the power supply to a system including semiconductor device 100 is cut off. Each of the plurality of memory cells MC1 to MC25 may include a switching element and a capacitor, and can record first data D0 or second data D1 by changing the polarization of the ferroelectric layer included in the capacitor. Since the polarization of the ferroelectric layer included in the capacitor is immutably maintained in the power-off state, the programming state of each of the plurality of memory cells MC1 to MC25 can be maintained even after the power supply to the system is cut off. Figure 11 The state shown.

[0097] After power is restored to the system and the semiconductor device 100 starts up, the semiconductor device 100 can perform a recovery operation to compensate for at least a portion of the degradation of the plurality of memory cells MC1 to MC25. In some embodiments, the semiconductor device 100 performs recovery operations sequentially on a plurality of word lines WL. Reference will be made below to... Figure 12 and Figure 13 TogetherFigure 10 Together, we describe the recovery operations for the first memory cell MC1 to the fifth memory cell MC5 connected to the first word line WL1.

[0098] To perform the recovery operation, the first word line WL1 can be activated first. The word line drive circuit can input the turn-on voltage VPP to the first word line WL1, and the switching elements included in each of the first memory cells MC1 to the fifth memory cells MC5 can be turned on by the turn-on voltage VPP.

[0099] With the on-state voltage VPP input to the first word line WL1, the board line driver circuit can input the first voltage VSS to multiple board lines PL1 to PL5, and the sense amplifier circuit can input the second voltage VINTA to multiple bit lines BL1 to BL5. Therefore, as Figure 12 As shown, the second data D1 can be recorded in the first memory cells MC1 to the fifth memory cells MC5, and the first memory cells MC1 to the fifth memory cells MC5 can be set to a second programming state. The polarization of the capacitor in each memory cell included in the first memory cells MC1 to the fifth memory cells MC5 can be set to a negative polarization.

[0100] Next, the board line drive circuit can input a second voltage VINTA to multiple board lines PL1 to PL5, and the sense amplifier circuit can input a first voltage VSS to multiple bit lines BL1 to BL5. For example, the polarity of the voltage applied to each of the first memory cells MC1 to the fifth memory cells MC5 can be reversed. Therefore, the first memory cells MC1 to the fifth memory cells MC5 can be set to a first programming state, and the polarization of the capacitors included in each of the first memory cells MC1 to the fifth memory cells MC5 can be changed to positive polarization.

[0101] The sensing amplifier circuit can sense the voltage of each of the multiple bit lines BL1 to BL5. The voltage sensed by the sensing amplifier circuit from each of the multiple bit lines BL1 to BL5 can be the voltage generated during the transition of the first memory cell MC1 to the fifth memory cell MC5 from a second programming state to a first programming state. For example, the polarization of the capacitor included in each of the first memory cell MC1 to the fifth memory cell MC5 can be changed from negative polarization to positive polarization, thereby changing the voltage of each bit line BL1 to BL5.

[0102] The control logic in the peripheral circuitry region can use the voltage sensed by the sense amplifier circuit in each of the bit lines BL1 to BL5 to determine whether each of the first memory cells MC1 to the fifth memory cells MC5 is degraded. The difference between the negative and positive polarizations in the capacitors of a severely degraded cell can be smaller than the difference between the negative and positive polarizations in the capacitors of a relatively less degraded cell. Therefore, a relatively low voltage can be sensed in the bit lines connected to severely degraded cells, and a relatively high voltage can be sensed in the bit lines connected to relatively less degraded cells. The sense amplifier circuit can compare the voltage sensed from each of the multiple bit lines BL1 to BL5 with a reference voltage and can output a sense signal. The control logic can then use the reference sense signal to determine whether each of the first memory cells MC1 to the fifth memory cells MC5 is degraded and whether a recovery operation should be performed. When the determination of whether each of the first memory cells MC1 to the fifth memory cells MC5 is degraded is complete, the control logic can reduce the voltage of the multiple board lines PL to a first voltage VSS.

[0103] exist Figure 13 In the example illustrated, the control logic can determine that only the first memory cell MC1 out of the first memory cell MC1 to the fifth memory cell MC5 requires a recovery operation. Figure 10 As illustrated, the control logic can apply a voltage higher than the second voltage VINTA to the first bit line BL1, while maintaining the voltage of the first board line PL1 connected to the first memory cell MC1 at the first voltage VSS. A recovery voltage higher than the second voltage VINTA can be applied to the first memory cell MC1, and the recovery voltage can be used to mitigate and / or remove charge imbalances in the capacitors included in the first memory cell MC1.

[0104] Figure 14A and Figure 14B This is a view illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure. Figure 14A The illustration is referenced above. Figures 11 to 13 A graph depicting the characteristics of the first memory cell MC1, which is selected as the target of the recovery operation in the described scenario. Figure 14B This is a graph illustrating the characteristics of the second memory cell MC2, which was not selected as the target for the recovery operation. Figure 14A and Figure 14B It is a hysteresis curve illustrating the relationship between the voltage applied to the capacitors included in each of the memory cells MC1 and MC2 and the polarization of the capacitors according to the voltage applied to the capacitors.

[0105] refer to Figure 14AIn the first memory cell MC1, the polarization of the capacitor can be set to a first positive polarization (P1+) by applying a positive voltage to the capacitor, and the polarization of the capacitor can be set to a first negative polarization (P1-) by applying a negative voltage to the capacitor. Meanwhile, reference... Figure 14B In the second memory cell MC2, the polarization of the capacitor can be set to a second positive polarization (P2+) by applying a positive voltage to the capacitor, and the polarization of the capacitor can be set to a second negative polarization (P2-) by applying a negative voltage to the capacitor.

[0106] Compare Figure 14A and Figure 14B The graph illustrating the characteristics of the first memory cell MC1, which exhibits relatively severe degradation, is a graph representing the characteristics of the second memory cell MC2, which exhibits relatively less degradation and is shifted to the left in the horizontal direction. Therefore, it can be seen that the difference between the first positive polarization (P1+) and the second positive polarization (P2+) is almost non-existent, while the difference between the first negative polarization (P1-) and the second negative polarization (P2-) can be large. The first negative polarization (P1-) can be greater than the second negative polarization (P2-) (or closer to zero, or with a smaller magnitude).

[0107] In the operation of selecting the target of the recovery operation, voltages of opposite polarities can be sequentially applied to each of the first memory cell MC1 and the second memory cell MC2. In the case of the first memory cell MC1, due to the sequential application of voltages of opposite polarities, a voltage corresponding to the difference between the first positive polarity (P1+) and the first negative polarity (P1-) can be output to the first bit line BL1. In the case of the second memory cell MC2, due to the sequential application of voltages of opposite polarities, a voltage corresponding to the difference between the second positive polarity (P2+) and the second negative polarity (P2-) can be output to the second bit line BL2. Therefore, the voltage of the first bit line BL1 can be lower than the voltage of the second bit line BL2.

[0108] The first bit line BL1 can be connected to a first sensing amplifier, and the first sensing amplifier can output a first sensing signal by comparing the voltage of the first bit line BL1 with a predetermined reference voltage. The second bit line BL2 can be connected to a second sensing amplifier, and the second sensing amplifier can output a second sensing signal by comparing the voltage of the second bit line BL2 with a predetermined reference voltage. The control logic of the peripheral circuit area can determine whether to apply a recovery voltage to the first memory cell MC1 based on the first sensing signal, and can determine whether to apply a recovery voltage to the second memory cell MC2 based on the second sensing signal. In the following text, reference will be used... Figure 15A and Figure 15BDescribe the operation of the sense amplifier and the operation of determining whether a memory cell is degraded based on the sense signal output by the sense amplifier.

[0109] Figure 15A and Figure 15B This is a view illustrating the operation of a semiconductor device according to some embodiments of the present disclosure. First, refer to... Figure 15A The memory cell MC can be connected to the word line WL, the board line PL, and the bit line BL, and can include a switching element SW and a capacitor CC, wherein the capacitor CC can include a ferroelectric layer. The gate of the switching element SW can be connected to the word line WL, and one of the source / drain regions of the switching element SW can be connected to the capacitor CC, and the other of the source / drain regions of the switching element SW can be connected to the bit line BL. The capacitor CC can be connected to the board line PL.

[0110] The word line WL can be connected to the first driver DRV1, and the board line PL can be connected to the second driver DRV2. The voltages of the word line WL and the board line PL can be controlled independently by the first driver DRV1 and the second driver DRV2. The bit line BL can be connected to the sense amplifier SA, and the sense amplifier SA can sense the voltage of the bit line BL. The voltage of the bit line BL can be controlled by a separate driver connected to the bit line BL or a separate sense amplifier SA.

[0111] Programming operations on the memory cell MC can be performed by applying voltages to each of the board line PL and bit line BL. For example, by applying a voltage higher than that applied to bit line BL to board line PL, first data can be recorded in the memory cell MC, and by applying a voltage lower than that applied to bit line BL to board line PL, second data can be recorded in the memory cell MC. In the state of recording the first data, the first polarization of capacitor CC can differ from the second polarization of capacitor CC in the state of recording the second data. As the difference between the first and second polarizations increases, the reliability of the memory cell MC can be improved, and sufficient margin can be ensured in read operations.

[0112] However, when repeatedly performing programming operations to record specific data, such as first data, into the memory cell MC, degradation may sometimes occur in the memory cell MC, such as a decrease in the difference between the first polarization and the second polarization. According to some embodiments of this disclosure, operations to sense and compensate for degradation can be performed on the memory cell MC.

[0113] With the switching element SW turned on by the first driver DRV1, degradation sensing can be performed by sequentially applying voltages of opposite polarities to the memory cell MC and sensing the voltage of the bit line BL by the sensing amplifier SA. When degradation of the memory cell MC is not severe or nonexistent, i.e., when the difference between the first polarization and the second polarization is sufficiently high, the voltage of the bit line BL can be higher than the reference voltage VREF. On the other hand, when degradation has occurred in the memory cell MC, i.e., when the difference between the first polarization and the second polarization is not sufficiently high, the voltage of the bit line BL can be lower than the reference voltage VREF. Therefore, the sensing signal SOUT can be determined differently depending on the degree of degradation of the memory cell MC, and the control logic of the peripheral circuit area can determine whether the memory cell MC is degraded by referring to the sensing signal SOUT.

[0114] Figure 15B This is a graph illustrating the relationship between the voltage input to the bit line BL of the read amplifier SA and the reference voltage VREF. In addition to sensing the degradation of the memory cell MC, the sense amplifier SA can also perform a read operation to read the data recorded in the memory cell MC, and the reference voltages VREF1 and VREF2 applied to each of the read operation and the degradation sensing operation can differ from each other by a predetermined voltage difference (ΔVREF).

[0115] As referenced above Figure 8 As described, during a read operation, a voltage higher than the voltage applied to bit line BL can be applied to board line PL, and the voltage of bit line BL can be sensed to read data from memory cell MC. For example, when the data recorded in memory cell MC is first data, a relatively low first data voltage VD0 can be sensed from bit line BL, and when the data recorded in memory cell MC is second data, a relatively high second data voltage VD1 can be sensed from bit line BL. During the read operation, the sense amplifier SA can read data from memory cell MC by comparing the voltage of bit line BL with a first reference voltage VREF1.

[0116] Simultaneously, in the degradation sensing operation, voltages of different polarities can be sequentially applied to the memory cell MC. Then, the sensing amplifier SA can sense the voltage of the bit line BL and compare the sensed voltage with a reference voltage VREF. For example, in the degradation sensing operation, a second programming voltage for recording second data and a first programming voltage for recording first data can be sequentially input to the memory cell MC. For example, whether the memory cell MC is degraded can be sensed by resetting the data in the memory cell MC to the second data and then performing a read operation.

[0117] Since the data in the memory cell MC is reset to the second data regardless of the previously recorded data, the second data voltage VD1 can be sensed on the bit line BL when there is no degradation or only slight degradation in the memory cell MC. On the other hand, when there is degradation in the memory cell MC, a degradation voltage VD1_DEG lower than the second data voltage VD1 can be sensed on the bit line BL.

[0118] However, since both the second data voltage VD1 and the degradation voltage VD1_DEG are higher than the first reference voltage VREF1, they can be indistinguishable from each other when the first reference voltage VREF1 is input to the sensing amplifier SA. In some embodiments, to distinguish between the second data voltage VD1 and the degradation voltage VD1_DEG, the reference voltage VREF input to the sensing amplifier SA is increased from the first reference voltage VREF1 to the second reference voltage VREF2. Therefore, in each case where the voltage of bit line BL is the second data voltage VD1 and the voltage of bit line BL is the degradation voltage VD1_DEG, a sensing signal SOUT can be output differently, and the control logic can determine whether the memory cell MC is degraded by referring to the sensing signal SOUT.

[0119] The magnitude of the degradation voltage VD1_DEG can vary depending on the degree of degradation present in the memory cell MC. (See above reference.) Figure 14A As described, as the degradation of the memory cell MC becomes more severe, the difference between the positive and negative polarities can decrease, and the amplitude of the degradation voltage VD1_DEG can also decrease. Therefore, the second reference voltage VREF2 can be set high, allowing for more effective sensing of the degradation of the memory cell MC. For example, when the second reference voltage VREF2 is made high, even small degradations present in the memory cell MC can be sensed. According to some embodiments, the control logic can perform the operation of sensing the degradation of the memory cell MC two or more times while changing the amplitude of the second reference voltage VREF2.

[0120] Figure 16 This is a flowchart illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure.

[0121] In some implementations, such as reference Figure 16As described, a recovery operation for compensating for the degradation of memory cells is performed during the operation of the semiconductor device. The semiconductor device may first determine the target word line to which the target cell, which is the target of the recovery operation, is connected, and may activate the target word line (S200). When the target word line is activated, a copy operation may be performed in the semiconductor device to copy the data of the target cell connected to the target word line to a copy cell connected to a word line different from the target word line (S210).

[0122] In the recovery operation, voltages with different polarities can be sequentially input to each of the target cells, and the voltages can include a first programming voltage for recording first data and a second programming voltage for recording second data. Therefore, since the data previously recorded in the target cells is lost during the recovery operation, in the recovery operation performed during the operation of the semiconductor device, the copying operation that sends the data from the target cells to the copying unit can be performed first.

[0123] When the copying operation is complete, a reset operation on the target cell can be performed (S220). During the reset operation, a first programming voltage or a second programming voltage can be input to the target cell. First data can be recorded by inputting the first programming voltage to the target cell, and second data can be recorded by inputting the second programming voltage. The reset operation can reset the data in the target cell to either the first or the second data. When the target cell is reset, the peripheral circuit area can perform a read operation on the target cell (S230).

[0124] In the read operation, a charge-sharing operation and a sensing operation for the target cell can be performed. In the charge-sharing operation, a voltage with the opposite polarity to the voltage input to the target cell in the reset operation of operation S220 can be input. For example, when a second programming voltage is input to the target cell in the reset operation, a first programming voltage can be input in the charge-sharing operation. The polarity of the capacitor included in the target cell can be set to a second polarity using the second programming voltage in the reset operation, and can be set to a first polarity using the first programming voltage in the read operation. In the sensing operation, a sensing amplifier can sense the voltage of the capacitor corresponding to the difference between the first and second polarities via a target bit line connected to the target cell.

[0125] The peripheral circuit area can determine whether the target cell has deteriorated by referring to the voltage sensed by the sensing amplifier during the read operation in operation S230 (S240). (Refer to the above...) Figure 15B The voltage of the target cell that has already deteriorated can be relatively lower than the voltage of the target cell that has not deteriorated. Therefore, the peripheral circuit region can determine that deterioration has occurred in the target cell that outputs a voltage lower than the reference voltage.

[0126] For a target cell that has been detected as degraded in operation S240, a recovery operation (S250) can be performed in the peripheral circuit area. The recovery operation can be the application of a recovery voltage to the detected degraded target cell. Charge imbalances in the capacitors included in the target cell can be resolved using the recovery voltage. (Refer to the above.) Figure 9 The recovery voltage can vary depending on the cause and type of degradation occurring in the target cell.

[0127] When the recovery voltage is input to the target cell, a pre-charge operation to initialize the voltage of the target bit line connected to the target cell can be performed, and the recovery operation can be terminated (S260). On the other hand, when no degradation is sensed in operation S140, the recovery voltage may not be input to the target cell, and a pre-charge operation to initialize the voltage of the target bit line can be performed, and the recovery operation can be terminated.

[0128] Figure 17 This is a view illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure.

[0129] It can be performed at startup and / or during the operation of the semiconductor device (e.g., after determination). Figure 17 The recovery operation is illustrated in the figure. In some implementations, such as... Figure 17 As shown, in the recovery operation, before sensing whether the target cell has deteriorated, a copy operation can be performed first to copy the data of the target cell to the copy unit. To perform the copy operation, the target cell and the copy unit can be connected to different word lines WL_S and WL_R, and board lines PL_S and PL_R. The bit line BL_S can be shared by the target cell and the copy unit, or the target cell and the copy unit can be connected to different bit lines.

[0130] refer to Figure 17 In the activation section ACT, a turn-on voltage VPP can be input to the target word line WL_S connected to the target cell, and the target cell can be activated by the turn-on voltage. Then, in the charge sharing section CS, while the voltage of the target bit line BL_S is maintained at the first voltage VSS, the voltage of the target plate line PL_S can be increased to the second voltage VINTA, and the polarization of the capacitor included in the target cell can be set to negative polarization.

[0131] In the subsequent sensing section RD, the sensing amplifier SA connected to the target bit line BL_S can read the data of the target cell. For example, when the voltage of the target bit line BL_S is lower than the reference voltage, the data of the target cell can be read as the first data, and when the voltage of the target bit line BL_S is higher than the reference voltage, the data of the target cell can be read as the second data. The reference voltage input to the sensing amplifier in the sensing section RD can be the above reference voltage. Figure 15B The first reference voltage VREF1 is described.

[0132] In the sensing section RD, the copy word line WL_R, which is different from the target word line WL_S, can be activated by the on-state voltage VPP. In some embodiments, the copy word line WL_R is also activated in the charge-sharing section CS. When the copy word line WL_R connected to the copy unit is activated, the voltage of the copy board line PL_R connected to the copy unit can be maintained at a first voltage VSS during the first copy time CP0, and then the voltage of the copy board line PL_R can be set to a second voltage Vinta during the second copy time CP1.

[0133] When the data sensed in the target cell in the sensing section RD is the first data, the voltage of the target bit line BL_S can be maintained at the first voltage VSS during the sensing section RD. Therefore, during the first replication time CP0 of applying the first voltage VSS to the replication board line PL_R, programming operations can be omitted in the replication cell, and during the second replication time CP1 of applying the second voltage VINTA to the replication board line PL_R, the first data can be recorded in the replication cell.

[0134] Simultaneously, when the data detected in the target cell in the sensing section RD is the second data, the voltage of the target bit line BL_S can be increased to the second voltage VINTA during the sensing section RD. Therefore, the second data can be recorded in the copy cell during the first copy time CP0 when the first voltage VSS is applied to the copy line PL_R, and programming operations can be avoided in the copy cell during the second copy time CP1 when the second voltage VINTA is applied to the copy line PL_R. Therefore, as Figure 17 As shown, the copying operation, which copies data recorded in the target cell to the copying cell, can be performed by controlling the voltage of the copying line PL_R.

[0135] When the copying and sensing operations terminate, a reset operation to reset the target cell's data can be performed during the Reset Section (RST). Then, through operations in each of the Charge Sharing Section (CS), Detection Section (DET), Recovery Section (REC), and Precharge Section (PRECH), the degradation of the target cell can be sensed, and a recovery operation can be performed accordingly. The operations during the Reset Section (RST), Charge Sharing Section (CS), Detection Section (DET), Recovery Section (REC), and Precharge Section (PRECH) can be referenced above. Figure 10 The operation described is similar. For example, the reference voltage input to the sensing amplifier in the detection segment DET can be a second reference voltage VREF2, which is higher than the first reference voltage VREF1, as described above. Figure 15B As stated above.

[0136] Figures 18 to 20 This is a view illustrating the recovery operation of a semiconductor device according to some embodiments of the present disclosure.

[0137] Figures 18 to 20 This is a view illustrating the copying operation of data from the target cell to the copying cell before the degradation sensing and recovery operations of the target cell. (Reference) Figures 18 to 20 The semiconductor device 200 described may include a plurality of memory cells MC1 to MC25, and the plurality of memory cells MC1 to MC25 may be connected to a plurality of word lines WL1 to WL5 (WL), a plurality of board lines PL1 to PL5 (PL) and a plurality of bit lines BL1 to BL5 (BL).

[0138] Each of the plurality of memory cells MC1 to MC25 may have a first programming state in which first data D0 is recorded or a second programming state in which second data D1 is recorded. The programming state of the plurality of memory cells MC1 to MC25 may be determined by voltages applied to a plurality of board lines PL and a plurality of bit lines BL.

[0139] Figure 18 This is a view illustrating the programming state of each of a plurality of memory cells MC1 to MC25 in the semiconductor device 200 immediately prior to the start of the recovery operation. For example, the semiconductor device 200 may perform the recovery operation when the semiconductor device 200 is not in use or when the system including the semiconductor device 200 enters a standby state, etc.

[0140] When the first word line WL1 is the target word line for the recovery operation, the semiconductor device 200 can first copy the data from the first memory cells MC1 to the fifth memory cell MC5 connected to the first word line WL1 to other memory cells MC6 to MC25. (Refer to the above...) Figure 17In order to read data from the first memory cell MC1 to the fifth memory cell MC5, the first word line WL1 can be activated, the first voltage VSS can be applied to the first bit line BL1, and the second voltage VINTA can be applied to the first board line PL1.

[0141] Therefore, as Figure 19 As shown, the first data D0 can be recorded in the first memory cell MC1 to the fifth memory cell MC5, and the voltage of each of the first bit line BL1 to the fifth bit line BL5 can depend on the voltage of the first bit line BL1 to the fifth bit line BL5. Figure 18 The data recorded at the indicated time varies in each of the first memory cells MC1 to the fifth memory cell MC5. For example, the voltages connected to the third bit line BL3 and the fourth bit line BL4 of the third memory cell MC3 and the fourth memory cell MC4, which have already recorded the first data D0, can be set to a first voltage VSS. On the other hand, the voltages connected to the first bit line BL1, the second bit line BL2, and the fifth bit line BL5 of the first memory cell MC1, the second memory cell MC2, and the fifth memory cell MC5, which have already recorded the second data D1, can be increased to a second voltage VINTA.

[0142] Next, as Figure 20 As shown, data from the first memory cell MC1 to the fifth memory cell MC5 can be copied to memory cells MC21 to MC25 connected to the fifth word line WL5, which is the copy word line. Data from the first memory cell MC1 can be copied to the twenty-first memory cell MC21, data from the second memory cell MC2 can be copied to the twenty-second memory cell MC22, and data from the third memory cell MC3 can be copied to the twenty-third memory cell MC23. Furthermore, data from the fourth memory cell MC4 can be copied to the twenty-fourth memory cell MC24, and data from the fifth memory cell MC5 can be copied to the twenty-fifth memory cell MC25. (See above reference.) Figure 17 The data of the first memory cell MC1, the second memory cell MC2, and the fifth memory cell MC5 can be copied during the first copy time CP0 when the voltage of the fifth board line PL5 is maintained at the first voltage VSS, and the data of the third memory cell MC3 and the fourth memory cell MC4 can be copied during the second copy time CP1 when the voltage of the fifth board line PL5 is set to the second voltage VINTA.

[0143] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in this disclosure in the context of individual implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0144] While various examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure.

Claims

1. A semiconductor device comprising: a cell region including a plurality of memory cells connected to a plurality of word lines, a plurality of bit lines, and a plurality of plate lines, wherein each of the plurality of memory cells includes a switching element and at least one capacitor connected to the switching element, wherein each of the at least one capacitor includes a ferroelectric layer; and a peripheral circuit region including a peripheral circuit configured to control the plurality of memory cells using the plurality of word lines, the plurality of bit lines, and the plurality of plate lines, wherein the peripheral circuit is configured to, in a recovery operation: turn on the switching element included in a target cell among the plurality of memory cells to activate the target cell, and when the target cell is activated: input a first voltage to a target plate line connected to the target cell and a second voltage higher than the first voltage to a target bit line connected to the target cell, after inputting the first voltage to the target plate line and the second voltage to the target bit line, input the second voltage to the target plate line and the first voltage to the target bit line, and based on the voltage of the target bit line being lower than a predetermined reference voltage, increase the voltage of the target bit line to a third voltage higher than the second voltage.

2. The semiconductor device of claim 1, wherein, the peripheral circuit includes: a word line driver circuit including a word line driver connected to the plurality of word lines; a sense amplifier circuit including a sense amplifier connected to the plurality of bit lines; and a plate line driver circuit including a plate line driver connected to the plurality of plate lines.

3. The semiconductor device of claim 1, wherein, the peripheral circuit is configured to, based on the voltage of the target bit line being higher than the predetermined reference voltage, maintain the voltage of the target bit line at the second voltage.

4. The semiconductor device of claim 1, wherein, the peripheral circuit is configured to, after sensing that the voltage of the target bit line is lower than the predetermined reference voltage, decrease the voltage of the target bit line to the first voltage at a predetermined time.

5. The semiconductor device of claim 1, wherein, the peripheral circuit is configured to turn on the switching element of the target cell by applying a turn-on voltage to the switching element of the target cell, and wherein the turn-on voltage is higher than the third voltage.

6. The semiconductor device of claim 1, wherein, the target cell is configured to reset stored data in response to receiving the first voltage from the target plate line and the second voltage from the target bit line.

7. The semiconductor device of claim 6, wherein, the peripheral circuit is configured to copy data of the target cell to a copy cell before inputting the first voltage to the target plate line and the second voltage to the target bit line.

8. The semiconductor device of claim 7, wherein, the target cell and the copy cell share the target bit line, and wherein the copy cell is connected to: a copy word line different from a target word line to which the target cell is connected, and a copy plate line different from the target plate line.

9. The semiconductor device of claim 8, wherein, the peripheral circuit is configured to copy the data of the target cell by: inputting the second voltage to the target plate line to read the data of the target cell, and when the voltage of the target plate line is equal to the second voltage: turning on a switching element included in the copy cell using the copy word line, and increasing the voltage of the copy plate line from the first voltage to the second voltage.

10. The semiconductor device of claim 9, wherein, the peripheral circuit is configured to read the data of the target cell by comparing the voltage of the target bit line to a first reference voltage lower than the predetermined reference voltage.

11. The semiconductor device of claim 1, wherein, each of the plurality of memory cells includes a switching element and a plurality of capacitors connected to the switching element, and wherein, in each of the plurality of memory cells, the plurality of capacitors of the memory cell are connected to different plate lines.

12. The semiconductor device of claim 11, wherein, In each of the plurality of memory cells, a switching element of the memory cell is connected to one of the plurality of word lines and one of the plurality of bit lines.

13. The semiconductor device of claim 1, wherein, In a programming operation on a selected memory cell among the plurality of memory cells, the peripheral circuit region is configured to input a first programming voltage to the selected memory cell to record first data, and input a second programming voltage having an opposite polarity to the first programming voltage to the selected memory cell to record second data, and wherein the third voltage is higher than the first programming voltage and the second programming voltage.

14. The semiconductor device of claim 13, wherein, A polarity of the third voltage matches a polarity of the second programming voltage.

15. A semiconductor device comprising: a cell region including a plurality of memory cells connected to a plurality of word lines, a plurality of plate lines, and a plurality of bit lines; and a peripheral circuit region including a peripheral circuit configured to control the plurality of memory cells, wherein the peripheral circuit is configured to, in a recovery operation: apply a first programming voltage and a second programming voltage having different polarities across a target cell among the plurality of memory cells, compare a voltage of a target bit line connected to the target cell with a predetermined reference voltage, and based on the comparison of the voltage of the target bit line with the predetermined reference voltage, input a recovery voltage higher than the first programming voltage and the second programming voltage to the target cell.

16. The semiconductor device of claim 15, wherein, The target cell includes a switching element and at least one capacitor connected to the switching element, wherein each of the at least one capacitor includes a ferroelectric layer.

17. The semiconductor device of claim 16, wherein, The ferroelectric layer in each of the at least one capacitor is configured to be set to a first polarization degree by the first programming voltage and to a second polarization degree different from the first polarization degree by the second programming voltage, and wherein the voltage of the target bit line is based on a difference between the first polarization degree and the second polarization degree.

18. The semiconductor device of claim 15, wherein, The peripheral circuit is configured to input the recovery voltage to the target bit line.

19. A semiconductor device comprising: a cell region including a plurality of memory cells connected to a plurality of word lines, a plurality of plate lines, and a plurality of bit lines; and a peripheral circuit region including a peripheral circuit configured to change a polarization degree of the plurality of memory cells to record first data or second data in the plurality of memory cells, and wherein the peripheral circuit is configured to, in a recovery operation: input a reset voltage to a target cell among the plurality of memory cells to reset data of the target cell to the second data, perform a read operation on the target cell to sense a degradation of the target cell, and based on the sensing of the degradation of the target cell, input a recovery voltage higher than the reset voltage to the target cell.

20. The semiconductor device of claim 19, wherein, The peripheral circuit is configured to perform the read operation by: changing the data of the target cell to the first data, and comparing a voltage of a target bit line connected to the target cell with a predetermined reference voltage.

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