Improved stack structure for maintaining high resistance state (HRS) and low resistance state (LRS) of oxide-based random access memory (OxRAM)

Abstract

An improved stack structure for maintaining a high resistance state (HRS) and a low resistance state (LRS) of an oxide-based random access memory (OxRAM). A resistive stack (Stck) for a resistive random access memory cell includes: a first electrode (El1); a second electrode (El2); a dielectric layer (Diel) interposed between the first electrode (El1) and the second electrode (El2), the dielectric layer including: a first dielectric layer (Diel 1) formed of a first transition metal oxide; a second dielectric layer (Diel2) formed of a second transition metal oxide different from the first transition metal oxide; and a diffusion barrier layer (DiffBar) interposed between the first dielectric layer (Diel1) and the second dielectric layer (Diel2) and formed of a material having barrier properties for oxygen vacancies that are higher than barrier properties for oxygen vacancies of the first transition metal oxide and the second transition metal oxide.

Description

TECHNICAL FIELD

[0001] The technical field of the present invention is resistive random access memory (ReRAM) or resistive RAM, each comprising an element whose resistance state defines an information bit. More specifically, the invention relates to the structure of a material stack forming an active part of an oxide-based ReRAM, also called OxRAM. BACKGROUND

[0002] Non-volatile memory (NVM) is a computer memory that is able to retain information even when its power supply is turned off. Examples of non-volatile memory include read-only memory (ROM), erasable ROM (EPROM), flash memory, ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM) and resistive random access memory (ReRAM).

[0003] The latter type of memory, i.e. ReRAM, is typically formed by an array of stacks Stck having a layer Diel of dielectric solid-state material interposed between two electrodes El1 and El2, as exemplified in Figure 1 Such a structure constitutes a memory bit element and typically functions by changing the resistance of the layer Diel. The dielectric solid-state material can be, for example, a chalcogenide, a perovskite or an oxide of a transition metal, such as hafnium oxide (HfOx). A memory is formed from an array of such memory bit elements, each forming the core of a bit cell. The present application focuses on ReRAM employing an oxide of a transition metal to form the dielectric solid-state material, i.e. forming an OxRAM.

[0004] Figure 1 The functioning of an OxRAM memory element is exemplified, which is made of a stack Stck comprising a pair of electrodes El1 and El2, between which a dielectric active layer Diel is interposed.

[0005] During a set operation Set, due to the formation and diffusion of pairs of oxygen ions Oxy and oxygen vacancies V Oxy Applying a set current and a set voltage Vset and the associated electric field in a first direction between the two electrodes El1 and El2 in the volume of the dielectric layer Diel can cause the formation of a conductive filament Fil in the otherwise resistive layer Diel. The bit element is then set to a low resistance state or LRS. The higher the set current, the larger the filament and the lower the resistance of the bit element.

[0006] Conversely, during the reset operation, the reset current flows between the two electrodes El1 and El2 in a second direction opposite to the first direction, and similarly, a current is applied between the two electrodes in a direction similar to V. set Opposite voltage V reset This dissolves the conductive filaments (Fil) generated during the Set operation, thereby increasing the resistance of the bit element. The bit element is then placed in a high-resistance state, or HRS.

[0007] Each of the LRS and HRS states can be associated with a bit value in the digital memory. During a read operation, a read voltage V is applied between the electrodes. read Furthermore, the read current is measured. The read current is lower than both the set and reset currents, and it flows between the two electrodes. Measuring the read current allows for the evaluation of the resistive state of the bit element, and thus the evaluation of the associated bit value.

[0008] Here, electrode El1 is inert, meaning it does not play an active role in the structure but passively carries electrons. On the other hand, electrode El2 is active, acting as an oxygen reservoir that can remove oxygen ions from the dielectric layer during the set operation and release oxygen ions into the dielectric layer during the reset operation.

[0009] The formation and dissolution of the filaments, and their final configuration (which determines the resistance of the memory element under LRS), are inherently random. In other words, the characteristics of the bit cells are distributed within a certain range. In this case, Figure 2 The resistance of a set of bit cells in the same array is illustrated.

[0010] Figure 2 (A) and Figure 2 (B) illustrates the probability Pr of each bit cell in the array taking a given resistance value R (Ω) in the ideal and more realistic scenarios, respectively. In the ideal case, only two values ​​are possible: a unique first value for the resistance of the low-resistance state LRS and a second unique value for the resistance of the high-resistance state HRS.

[0011] In the ideal model, a bit cell can only reach these two states, and each state has a unique, definite resistance value. However, in practice, the resistance values ​​are dispersed across ranges that can each be described as probability densities, which have a given value (for the two states LRS and HRS, R0 ... 0_LRS and R 0_HRS The peak is centered on the shape of the peak and exhibits a standard deviation σ (for simplicity, the distributions of LRS and HRS are similar in this example), as shown. Figure 2 exemplified by (B).

[0012] likeFigure 2 As illustrated in (B), the two states, LRS and HRS, can actually be very close to each other. The distributions of these two states may even overlap, which complicates the control of the state of memory cells. Specifically, a problem arises in the retention of information in memory: over time, the state (LRS or HRS) of any given positioning element may gradually deviate from the state initially written (set or reset), and may become difficult to determine during a read operation: does the measured resistance value correspond to the LRS state or the HRS state?

[0013] It is known that the retention problem is related to the migration of oxygen ions and oxygen vacancies within the dielectric layer, and also to the release of purged oxygen ions from the active electrode to the dielectric layer. In fact, the state of the bit element is determined by the presence and localization of oxygen vacancies in the dielectric layer: do these oxygen vacancies form conductive filaments? However, the oxygen vacancy V... Oxy The migration of oxygen ions (Oxy) dissolves the filaments formed by the set operation, leading to a problem in maintaining the low-resistance state. Conversely, the migration of oxygen ions (Oxy) can reconstruct the filaments dissolved by the reset operation, leading to a problem in maintaining the high-resistance state. Oxy ions can originate from electrode E1. These phenomena are exacerbated by temperature.

[0014] Therefore, it is necessary to improve the retention characteristics of OxRAM memory, especially for high-temperature applications.

[0015] Purpose of the invention

[0016] Against the backdrop described above, the inventors propose a structure for a memory element that limits the occurrence of unwanted filament reformation and thus provides better retention characteristics for the memory based on such a memory element, specifically HRS retention. Summary of the Invention

[0017] Therefore, a first aspect of the present invention relates to a resistive stack for a resistive random access memory cell, the resistive stack comprising: a first electrode; a second electrode; a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer comprising: a first dielectric layer formed of a first transition metal oxide formed from a first transition metal; a second dielectric layer formed of a second transition metal oxide formed from a second transition metal, the first transition metal being different from the second transition metal; and a diffusion barrier layer disposed between the first dielectric layer and the second dielectric layer, and formed of a material having a barrier property for oxygen vacancies, the barrier property being higher than the barrier properties of the first transition metal oxide and the second transition metal oxide for oxygen vacancies, the diffusion barrier layer being formed of alumina, SiO2, or Si.

[0018] The diffusion barrier inserted between the two dielectric layers prevents the reformation of dissolved filaments by hindering oxygen vacancies, which brings a first advantage in terms of the stability of the stack and therefore in terms of the retention capability of the memory using the stack as a memory element.

[0019] The second advantage is that the diffusion barrier increases the resistance difference between the LRS and the HRS, making it easier to distinguish the LRS and the HRS of the memory.

[0020] Additional non-limiting features of the first aspect of the invention, either alone or in any technically feasible combination:

[0021] - The first electrode may be an inert electrode, and the second electrode may be an active electrode capable of removing oxygen ions from the dielectric layer;

[0022] - The migration energy of the second dielectric layer can be higher than that of the first dielectric layer;

[0023] - The second dielectric layer may have a thickness between 20% and 60% of the combined thickness of the first dielectric layer, the diffusion barrier and the second dielectric layer;

[0024] -The first dielectric layer may be formed of hafnium oxide or tantalum pentoxide;

[0025] -The first dielectric layer may have a thickness between 1nm and 4nm, preferably between 2nm and 3nm;

[0026] -The second dielectric layer may be formed of zirconium oxide;

[0027] -The second dielectric layer may have a thickness between 1nm and 4nm, preferably between 2nm and 3nm;

[0028] - This diffusion barrier can be formed from aluminum oxide;

[0029] - The diffusion barrier can be formed from C, SiO2, Si, TaSiN, TaCN or TiSiN;

[0030] - The diffusion barrier may have a thickness between 0.2 nm and 2 nm, preferably between 0.4 nm and 1 nm;

[0031] - At least the first dielectric layer and the second dielectric layer may be doped with trivalent elements with an atomic concentration between 1% and 15%;

[0032] - The trivalent element can be selected from Ti, Al, and La;

[0033] - At least the first dielectric layer and the second dielectric layer may each be doped with silicon at an atomic concentration between 1% and 15%, preferably between 2% and 6%; and

[0034] - The dielectric layer may further include a second diffusion barrier layer, which is inserted between the second dielectric layer and the second electrode.

[0035] The invention extends to a memory device comprising an array of bit cells, each bit cell comprising the stacked body according to the first aspect of the invention as a variable resistor; and to an embedded system comprising the memory device in communication with a microprocessor. Attached Figure Description

[0036] Many other features and advantages of the invention will become apparent when considered in conjunction with the accompanying drawings, and upon reading the following detailed description, in which the drawings are shown:

[0037] [ Figure 1 ]- Figure 1 The operating principle of OxRAM is illustrated;

[0038] [ Figure 2 ]- Figure 2 The resistivity distribution of a bit cell in a resistive memory is illustrated.

[0039] [ Figure 3 ]- Figure 3 The mechanism that leads to insufficient retention of the high-resistivity state of OxRAM memory elements is illustrated;

[0040] [ Figure 4 ]- Figure 4 An example of solving Figure 3 The memory element of the problem illustrated;

[0041] [ Figure 5 ]- Figure 5 A comparison was shown. Figure 3 and Figure 4 The graph illustrates the retention performance of the memory elements;

[0042] [ Figure 6 ]- Figure 6 Indicates used for Figure 4 A diagram illustrating the manufacturing process of the illustrated memory element;

[0043] [ Figure 7 ]- Figure 7 Examples Figure 4 Variations of the illustrated memory element;

[0044] [ Figure 8 ]- Figure 8 Examples of combinations Figure 4The illustrated memory element is an OxRAM memory array; and

[0045] [ Figure 9 ]- Figure 9 Examples of combinations Figure 8 An embedded system with an illustrated OxRAM memory array. Detailed Implementation

[0046] The following will use... Figures 1 to 9 The embodiments of the present invention will be described below.

[0047] Figure 3 An example is illustrated of a stack of memory elements forming an OxRAM memory. The stack includes a first inert electrode El1 and a second active electrode El2 capable of removing oxygen ions, with a dielectric layer Diel interposed between the two electrodes. The dielectric layer Diel includes: a first dielectric layer Diel1 formed of a first transition metal oxide located on one side of the first electrode; and a second dielectric layer Diel2 formed of a second transition metal oxide located on the second electrode side and having a higher migration energy than the first transition metal oxide. The first electrode El1 may be an inert electrode made of titanium nitride (TiN), and the first layer Diel1 and the second layer Diel2 may be made of dielectric hafnium oxide (HfO2) and dielectric zirconium oxide (ZrO2), respectively. The second electrode El2 may be made of an oxygen-removing layer made of titanium (Ti).

[0048] The applicant of this application has studied OxRAM memory cells employing this type of structure. Results show that these memory cells exhibit insufficient retention, particularly in the high-resistivity state (HRS). The HRS state is dissolved by oxygen vacancies (V0). Oxy The filaments were obtained by fabricating a filament. It was then hypothesized that the dissolved filaments after the resetting operation could reform due to the mobility of oxygen vacancies within the HfO2 layer, while the ZrO2 layer sufficiently immobilized these oxygen vacancies due to its high migration energy. This situation is caused by… Figure 3 For example, the arrow symbolizes oxygen vacancy V. Oxy Due to migration, these oxygen vacancies tend to reform dissolved filaments DisFil in the second dielectric layer Diel2.

[0049] As a countermeasure, the applicant proposed an intercalation diffusion barrier that is intercalated between two dielectric layers, Diel1 and Diel2, with the aim of preventing oxygen vacancies from diffusing and reforming dissolved filaments, thereby enhancing the retention capability of memory elements.

[0050] Figure 4 An example of a general structure of an OxRAM stack according to the present invention is illustrated, which is consistent with... Figure 3The illustrated structure differs only in the presence of a diffusion barrier, DiffBar, inserted between the two dielectric layers, Diel1 and Diel2. Advantageously, the diffusion barrier prevents the reformation of dissolved filaments by hindering oxygen vacancies. Figure 3 The illustrated structure and Figure 4 The effectiveness of the illustrated structure has been confirmed by comparison of its retention properties (with a diffusion barrier made of alumina).

[0051] Figure 5 Two graphs are shown at (A) and (B), illustrating the measurement results of an OxRAM memory based on memory cells with the same structure as each other. The difference is that for the test graph at (B), there is a diffusion barrier DiffBar formed by aluminum oxide Al2O3 between the HfO2 and ZrO2 layers, while for the reference graph at (A), there is no such diffusion barrier layer.

[0052] These graphs represent the distribution of memory cells as a function of the corresponding resistances of the LRS and HRS states. These graphs share a common X-axis and Y-axis, with the X-axis representing the resistance R of the memory cell in ohms and the Y-axis representing the cumulative probability Cum.Pr with a given resistance. This arrangement is to facilitate visualization of the proximity of the HRS and LRS states, i.e., the proportion of LRS and HRS states that are close to each other and may lead to retention loss and errors during read operations.

[0053] The graphs at (A) and (B) each show two sets of results. The first set, indicated as Init, corresponds to the resistance of the memory cell immediately after a set or reset operation that writes its LRS and HRS states. The second set, indicated as Init+210℃ / 2h, shows the resistance of the same memory cell after a set or reset operation and an additional heat treatment at 210℃ over a 2-hour period. The heat treatment tests the memory cell's ability to retain information (i.e., the LRS and HRS states written into it).

[0054] As can be seen in the reference curve at (A), the memory cell based on the HfO2 / ZrO2 structure without the Al2O3 diffusion barrier exhibits a significant shift Sh of its HRS state toward the LRS state after heat treatment (as indicated by the arrow), thereby greatly reducing the cumulative probability of 10. -4 The resistance difference Δ between the time-separated HRS state and LRS state R ef.

[0055] In contrast, as can be seen in the graph at (B), memory cells based on the HfO2 / Al2O3 / ZrO2 structure and including an Al2O3 diffusion barrier exhibit a reduced shift from the HRS state to the LRS state, thus significantly limiting the cumulative probability of 10. -4 The resistance difference Δ between the time-separated HRS state and LRS state I The decrease in nv. It should also be noted that the resistance difference is initially larger (before heat treatment).

[0056] Introducing a diffusion barrier, DiffBar, between dielectric layers Diel1 and Diel2 appears to be advantageous in two respects.

[0057] Firstly, the HRS state appears more stable, which is beneficial for the retention of OxRAM memory.

[0058] Secondly, it makes it easier to distinguish between the LRS state and HRS state of the memory.

[0059] The following uses Figure 6 To explain according to the present invention and Figure 4 Additional properties of the illustrated stack Stck, Figure 6 A process 100 for manufacturing a stacked body Stck, including consecutive steps S110 to S160, is illustrated.

[0060] In this specification, it should be understood that when a layer is formed from a given material, the layer comprises that material with an atomic concentration of more than 50%.

[0061] In the first step S110, for example, a first electrode E1, preferably 5 nm thick or thicker, is formed above a base substrate (not shown) by cathode sputtering in a vacuum deposition chamber. Preferably, the first electrode is chemically inert in the stack and does not react with oxygen ions or oxygen vacancies moving in the dielectric layer. In this embodiment, the first electrode E1 may be formed from titanium nitride (TiN) by reactive sputtering. Alternatively, the first electrode may be formed by chemical vapor deposition.

[0062] In step S120, a first dielectric layer Diel1 is formed on the first electrode El1.

[0063] In this embodiment, the dielectric layer Diel1 is a dielectric hafnium oxide layer, such as HfO2, with a thickness between 1 nm and 4 nm, preferably between 2 nm and 3 nm, and typically 2 nm. Alternatively, the dielectric layer Diel1 may be, for example, a tantalum pentoxide layer. A layer that is too thin will result in a small read margin, while a layer that is too thick may degrade the switching between the LRS state and the HRS state and produce a resistance tail.

[0064] In step S130, a diffusion barrier layer is formed on the first dielectric layer Diel1.

[0065] In this embodiment, the diffusion barrier layer (DiffBar) is a dielectric alumina layer, such as Al₂O₃, with a thickness between 0.2 nm and 2 nm, preferably between 0.4 nm and 1 nm. An appropriate thickness is chosen such that the layer is thin enough not to introduce excessively high resistance into the stack, and thick enough to fully realize its intended function. The active material layer can be deposited, for example, by cathode sputtering, physical vapor deposition (PVD), or ion beam deposition (IBD).

[0066] This invention is not limited to alumina, as alternatives can be used to achieve the same function (i.e., hindering oxygen vacancies V). Oxy Other materials, such as C, SiO2, Si, TaSiN, TaCN, or TiSiN. In any case, the material chosen to form the DiffBar layer has a higher barrier property for oxygen vacancies than that of layers Diel1 and Diel2.

[0067] In step S140, a second dielectric layer Diel2 is formed on the diffusion barrier layer DiffBar.

[0068] In this embodiment, dielectric layer Diel2 is a dielectric zirconium oxide layer, such as ZrO2, with a thickness between 1 nm and 4 nm, preferably between 2 nm and 3 nm. Diel2 preferably has a thickness between 20% and 60% of the combined thickness of layers Diel1, DiffBar, and Diel2. Excessive thickness of Diel2 may degrade the switching between LRS and HRS states and produce resistance tailing. If Diel2 is too thin, the structure combining Diel2 and DiffBar will not provide a significant retention gain for ReRAM.

[0069] In this embodiment, layers Diel1, DiffBar, and Diel2 are preferably deposited in a manner that ensures these layers have a substantially constant thickness at all points. In this specification, "substantially constant thickness" means a thickness variation of no more than 20%, preferably no more than 10%, and even more preferably no more than 5%.

[0070] Regarding the formation method, in this embodiment, layers Diel1, DiffBar, and Diel2 are deposited using atomic layer deposition (ALD). Alternatively, these layers may be deposited independently, for example, by cathode sputtering, physical vapor deposition (PVD), or ion beam deposition (IBD).

[0071] Figure 7 (A) illustratesFigure 4 A variation of the structure. This structure is related to... Figure 4 The structures are the same, except that the dielectric layer Diel includes an additional diffusion barrier inserted between the second dielectric layer Diel2 and the second electrode El2.

[0072] The DiffBar' layer is formed of a semiconductor (preferably Si), a semiconductor oxide, or a metal oxide (preferably silicon oxide SiO2 or aluminum oxide Al2O3). The function of the DiffBar' layer is to provide an additional barrier between the electrode El2 and the other layers forming the Diel. Its function is to help set a balance in oxygen ion movement to allow for reset operation, while enhancing the maintenance of the LRS state.

[0073] In step S150, as a first alternative, the layers forming the dielectric layers Diel are doped with trivalent elements by ion implantation into at least the first dielectric layer Diel1 and the second dielectric layer Diel2 to control the migration energy of oxygen and oxygen vacancies. The trivalent dopant can be Ti, Al, La, etc. In a second alternative, silicon, argon, or nitrogen can be implanted into the dielectric layers to create defects. These defects are designed to facilitate oxygen vacancy movement and the switching between the LRS and HRS states. Excessive silicon concentration will reduce the resistivity margin.

[0074] For these two alternative approaches, direct implantation can be achieved with a doping energy, for example, between 1.5 keV and 3.5 keV, typically 3 keV, and with a doping energy between 1.10... 15 atoms / cm 2 Up to 5.10 15 atoms / cm 2 Between, preferably in 2.10 15 atoms / cm 2 Up to 3.10 15 atoms / cm 2 Between, usually 2.10 15 atoms / cm 2 The dosage of the dopant element is selected for implantation. The dopant element accounts for 1% to 15% of the atoms present in the Diel layer, preferably 2% to 7%. Excessive defect concentration may cause the LRS state of the ReRAM to remain degraded.

[0075] Other processes may be used without departing from the scope of the disclosed embodiments. For example, doping may be performed during layer formation.

[0076] In step S160, a second electrode El2 is formed on the second dielectric layer Diel2, for example, by cathode sputtering in a vacuum deposition chamber to form a second electrode approximately 5 nm thick. The second electrode may be a deoxygenation layer that participates in the formation and retention of the conductive filament made of oxygen vacancies during the placement operation by capturing and neutralizing oxygen substances, preventing them from recombinating with the oxygen vacancies of the filament, thereby preventing the dissolution of the filament. In this embodiment, the second electrode El2 is preferably formed of titanium (Ti), but may also be formed of another transition metal, and for example, TaN, Hf, or Ta. As an alternative to cathode sputtering, the first electrode may be formed by chemical vapor deposition or ion beam deposition.

[0077] Figure 7 (B) illustrates Figure 4 A variation of the second electrode El2. This structure Stck and... Figure 4 The structure is the same, except that the second electrode El2 has a composite structure, comprising a first electrode layer El2a on one side of the second dielectric layer Diel2 and a second electrode layer El2b on the opposite side. The first electrode layer El2a is preferably a deoxygenating layer in direct contact with the second dielectric layer and can be formed of Ti, Hf, or Ta, with a thickness, for example, between 3 nm and 20 nm. The second electrode layer El2b is formed of a conductive material including a transition metal and functions to prevent complete oxidation of the first electrode layer El2a and to allow electrical contact with the electrode El2. El2b can be formed of, for example, TiN, TaN, or W.

[0078] After the stack is completed, and before it is used as a bit element in the OxRAM memory, the stack undergoes a “forming” initialization step, which includes forming an initial filament. The voltage used to form this initial filament is higher than the set voltage Vset. The initialization phase occurs only once during the lifetime of each bit cell of the memory.

[0079] In this specification, unless otherwise stated, two directly adjacent layers are in direct physical contact with each other.

[0080] The stacked body Stck described above can form the active element of an OxRAM memory MEM. Set, reset, and read operations can be applied to the bit cells integrated in the array ARR, each of which includes the stacked body Stck. Figure 8 The basic conventional structure of a resistive memory (MEM) is illustrated. Such a memory is described, for example, in patent US11735260B2.

[0081] Usually, such as Figure 8 As illustrated in (C), each bit cell BC of the array ARR includes: (i) a stack body Stck that forms a variable resistor VarR (see Figure 8 (B) and implements the function of the memory bit element for each bit cell; and (ii) a selection transistor Sel Tr It has a source and a drain connected in series with a variable resistor.

[0082] An array of bit cells (ARR) typically includes rows and columns of bit cells, such as... Figure 8 As illustrated in (A). Each column includes: (i) a bit line BL, which passes through a variable resistor Var for each bit cell in the column. R Connected to transistor Sel Tr (i) the source and drain; and (ii) the source line SL, which passes through transistor Sel Tr The source and drain, and the variable resistor Var R Connected to bit line BL. Each row of bit cells includes a word line WL, which is connected to the select transistor Sel for each bit cell in that row. Tr The gate of the [unclear - likely a specific circuit or component]. The bit line BL and the source line SL are each connected to the column multiplexer circuit SL / BL-Mux and pass through this column multiplexer circuit.

[0083] The SL / BL-Mux circuit controls each word line WL. Each word line WL is connected to and controlled by the line driver circuit WL-Drv.

[0084] Figure 9 An example is the EmbSys embedded system, which integrates 0xRAM for communication with a microprocessor CPU. Such systems can be used in portable semiconductor devices configured to process numerical data. Generally, any embedded device that traditionally uses flash memory can alternatively use resistive memory. OxRAM benefits from the enhanced retention capabilities of the stack described above (Stck) and makes it particularly suitable for high-temperature applications, such as transportation applications.

[0085] By studying the accompanying drawings, the disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention.

Claims

1. Resistive stack (Stck) for a resistive random access memory, ReRAM, cell, the resistive stack comprising: - a first electrode (Ell); - a second electrode (El2); - a dielectric layer (Diel) interposed between the first electrode (Ell) and the second electrode (El2), the dielectric layer comprising: - a first dielectric layer (Diel1) formed from a first transition metal oxide formed from a first transition metal; - a second dielectric layer (Diel2) formed from a second transition metal oxide formed from a second transition metal, the first transition metal being different from the second transition metal; and - a diffusion barrier layer (DiffBar) interposed between the first dielectric layer (Diel1) and the second dielectric layer (Diel2) and formed from a material having a barrier property for oxygen vacancies, the barrier property being higher than the barrier property of the first and second transition metal oxides for oxygen vacancies, the diffusion barrier layer being formed from aluminum oxide, Si02 or Si.

2. The resistive stack of claim 1, wherein, the first electrode (Ell) is an inert electrode and the second electrode (El2) is an active electrode capable of scavenging oxygen ions from the dielectric layer (Diel).

3. The resistive stack of claim 1 or claim 2, wherein, the migration energy of the second dielectric layer (Diel2) is higher than the migration energy of the first dielectric layer (Diel1).

4. The resistive stack of any one of claims 1-3, wherein, the second dielectric layer (Diel2) has a thickness comprised between 20% and 60% of the combined thickness of the first dielectric layer (Diel1), the diffusion barrier (DiffBar) and the second dielectric layer (Diel2).

5. The resistive stack of any one of claims 1 to 4, wherein, the first dielectric layer (Diel1) is formed from hafnium oxide or tantalum pentoxide.

6. The resistive stack (Stck) of claim 5, wherein, the first dielectric layer (Diel1) has a thickness comprised between 1 nm and 4 nm, preferably between 2 nm and 3 nm.

7. The resistive stack of any one of claims 1 to 6, wherein, the second dielectric layer (Diel2) is formed from zirconium oxide.

8. The resistive stack (Stck) according to claim 7, wherein the second dielectric layer (Diel2) has a thickness comprised between 1 nm and 4 nm, preferably between 2 nm and 3 nm.

9. The resistive stack of any one of claims 1 to 8, wherein, the diffusion barrier (DiffBar) is formed from aluminum oxide.

10. The resistive stack (Stck) according to any one of claims 1 to 9, wherein, the diffusion barrier (DiffBar) has a thickness comprised between 0.2 nm and 2 nm, preferably between 0.4 nm and 1 nm.

11. The resistive stack of any one of claims 1 to 10, wherein, at least the first dielectric layer (Diel1) and the second dielectric layer (Diel2) are doped with a trivalent element at an atomic concentration comprised between 1% and 15%.

12. The resistive stack (Stck) according to claim 11, wherein, the trivalent element is selected from Ti, Al and La.

13. The resistive stack of any one of claims 1 to 12, wherein, at least the first dielectric layer (Diel1) and the second dielectric layer (Diel2) are each doped with silicon at an atomic concentration comprised between 1% and 15%, preferably between 2% and 6%.

14. The resistive stack of any one of claims 1 to 13, wherein, the dielectric layer further comprises a second diffusion barrier layer (DiffBar') interposed between the second dielectric layer (Diel2) and the second electrode (El2).

15. A memory device (MEM) comprising an array (ARR) of bit cells (BC), each bit cell comprising a stack (Stck) according to any one of claims 1 to 14 as a variable resistor (Var R ).

16. An embedded system (EmbSys) comprising a memory device (MEM) according to claim 15 in communication with a microprocessor (CPU).

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