Capacitor, semiconductor device and manufacturing method thereof, and electronic apparatus

Abstract

The invention discloses a capacitor, a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the capacitor comprises a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode. The first capacitor electrode is in a hollow tube shape with one end closed and the other end provided with an opening, and the first capacitor electrode is provided with an outer side wall and an inner wall located in the hollow tube shape. The outer side wall is sequentially provided with the dielectric substance layer and the second capacitor electrode, and the inner wall is sequentially provided with the dielectric substance layer and the second capacitor electrode. According to the capacitor provided by the embodiment of the invention, the contact area between the first capacitor electrode and the dielectric substance layer is large, large capacitance can be realized, the preparation process is simple, and the cost is low.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a capacitor, a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a capacitor, a semiconductor device and its manufacturing method, and an electronic device. The capacitor has a large contact area between the first capacitor electrode and the dielectric layer, which can achieve a large capacitance. Moreover, the manufacturing process is simple and the cost is low.

[0006] This application provides a capacitor, which includes: a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode;

[0007] The first capacitor electrode is a hollow tube that is closed at one end and open at the other end. The first capacitor electrode has an outer wall and an inner wall located inside the hollow tube. The dielectric layer and the second capacitor electrode are sequentially disposed on the outer wall, and the dielectric layer and the second capacitor electrode are sequentially disposed on the inner wall.

[0008] In some embodiments of this application, the dielectric layer at least partially surrounds the outer wall of the first capacitor electrode; and / or, the second capacitor electrode at least partially surrounds the outer wall of the first capacitor electrode.

[0009] In some embodiments of this application, the dielectric layer completely surrounds the outer wall of the first capacitor electrode, and the second capacitor electrode completely surrounds the outer wall of the first capacitor electrode.

[0010] In some embodiments of this application, the dielectric layer and the second capacitor electrode cover the entire inner wall of the first capacitor electrode.

[0011] In some embodiments of this application, the opening of the first capacitor electrode has a support layer on both sides;

[0012] The support layer is located on the outer wall of the first capacitor electrode and is in contact with the dielectric layer on the outer wall of the first capacitor electrode.

[0013] In some embodiments of this application, the dielectric layer on the outer wall of the first capacitor electrode is spaced apart from the dielectric layer on the inner wall of the first capacitor electrode; and / or,

[0014] The second capacitor electrode on the outer wall of the first capacitor electrode is spaced apart from the second capacitor electrode on the inner wall of the first capacitor electrode.

[0015] In some embodiments of this application, the dielectric layer on the outer wall of the first capacitor electrode and the dielectric layer on the inner wall of the first capacitor electrode are formed in the same process; and / or,

[0016] The second capacitor electrode on the outer wall of the first capacitor electrode and the second capacitor electrode on the inner wall of the first capacitor electrode are formed by the same process.

[0017] This application also provides a semiconductor device, the semiconductor device comprising: a plurality of memory cells distributed in different layers and stacked along a direction perpendicular to the substrate; each layer comprising a plurality of memory cells spaced apart along a row direction and a column direction parallel to the substrate; the memory cells comprising capacitors as described above.

[0018] In some embodiments of this application, the first capacitor electrode extends along the row direction, and the first capacitor electrodes of the plurality of memory cells located on the same layer are spaced apart in the column direction.

[0019] In some embodiments of this application, the dielectric layer on the inner wall of the first capacitor electrode of the plurality of memory cells stacked along a direction perpendicular to the substrate is a single-piece structure; and / or,

[0020] The dielectric layer on the inner wall of the first capacitor electrode of the plurality of memory cells spaced apart along the column direction is an integral structure.

[0021] In some embodiments of this application, the second capacitor electrode on the inner wall of the first capacitor electrode of the plurality of memory cells stacked along a direction perpendicular to the substrate is an integral structure; and / or,

[0022] The second capacitor electrode on the inner wall of the first capacitor electrode of the plurality of memory cells distributed at intervals along the column direction is an integral structure.

[0023] In some embodiments of this application, the dielectric layer on the outer wall of the first capacitor electrode of the plurality of memory cells stacked along a direction perpendicular to the substrate is a monolithic structure; and / or,

[0024] The second capacitor electrode on the outer wall of the first capacitor electrode of the plurality of memory cells stacked along a direction perpendicular to the substrate is an integral structure.

[0025] In some embodiments of this application, the dielectric layers on the opposite outer sidewalls of the first capacitor electrodes of two adjacent memory cells along the column direction are a single, integral structure; and / or,

[0026] The second capacitor electrodes on the opposite outer walls of the first capacitor electrodes of two adjacent memory cells along the column direction are integral structures.

[0027] In some embodiments of this application, a capacitor hole extending toward the substrate is provided between a string of memory cells stacked along a direction perpendicular to the substrate and another string of memory cells adjacent along the column direction, and the dielectric layer and the second capacitor electrode are sequentially disposed on the inner wall of the capacitor hole.

[0028] In some embodiments of this application, the capacitor holes have support layers on both sides distributed along the row direction, and the support layers on both sides are in contact with the dielectric layer.

[0029] In some embodiments of this application, the dielectric layer on the outer sidewall of the first capacitor electrode of the plurality of memory cells spaced apart along the column direction is an integral structure;

[0030] The second capacitor electrode on the outer wall of the first capacitor electrode of the plurality of memory cells distributed at intervals along the column direction is an integral structure.

[0031] In some embodiments of this application, the storage cell further includes a transistor, the transistor including a transistor electrode connected to the capacitor, wherein the first capacitor electrode is shared as the transistor electrode.

[0032] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0033] Multiple insulating layers and multiple first sacrificial layers are sequentially and alternately deposited on a substrate to obtain a stacked structure;

[0034] In the stacked structure, a plurality of trenches are formed extending toward the substrate, the plurality of trenches being spaced apart in a column direction parallel to the substrate; both sides of the trenches distributed along the row direction expose the insulating layer and the first sacrificial layer; one side of the trenches distributed along the row direction is a transistor via, and the other side is a capacitor via;

[0035] A support layer is formed in the transistor hole and on the side of the capacitor hole away from the transistor hole;

[0036] A second sacrificial layer is filled into the capacitor hole;

[0037] Remove the first sacrificial layer from the outer wall of the capacitor hole;

[0038] A tubular first capacitor electrode is formed in the region of the first sacrificial layer between two adjacent capacitor holes along the column direction, and the end of the first capacitor electrode that contacts the first sacrificial layer is closed.

[0039] Remove the second sacrificial layer;

[0040] A dielectric layer and a second capacitor electrode are sequentially formed on the inner wall of the first capacitor electrode and on the inner and outer walls of the capacitor hole.

[0041] In some embodiments of this application, the manufacturing method further includes: after forming a support layer in the transistor hole and on the side of the capacitor hole away from the transistor hole, and before filling the capacitor hole with a second sacrificial layer.

[0042] Remove the insulating layer exposed between two adjacent capacitor holes along the column direction, and form a connecting hole extending along the column direction in the insulating layer. The connecting hole connects a plurality of capacitor holes spaced apart along the column direction in the insulating layer, and the connected capacitor holes expose the circumferential sidewall of the first sacrificial layer between two adjacent capacitor holes along the column direction.

[0043] In some embodiments of this application, filling the capacitor orifice with a second sacrificial layer includes:

[0044] A second sacrificial layer is filled into the capacitor hole and the connecting hole;

[0045] Removing the first sacrificial layer from the outer wall of the capacitor hole includes:

[0046] Remove the first sacrificial layer on the outer wall of the capacitor hole, and form a capacitor groove between the second sacrificial layer in two adjacent capacitor holes along the column direction and between the second sacrificial layers in two adjacent connecting holes.

[0047] In some embodiments of this application, forming a tubular first capacitor electrode in the region of the first sacrificial layer between two adjacent capacitor holes along the column direction, wherein the end of the first capacitor electrode in contact with the first sacrificial layer is closed, includes:

[0048] A first electrode layer is formed on the inner wall of each capacitor slot, on the exposed outer wall of the capacitor hole, and on the side of each insulating layer distributed along the row direction and away from the first sacrificial layer; the first sacrificial layers on the inner walls of multiple capacitor slots located in the same layer are connected together through the first electrode layer on the exposed outer wall of the capacitor hole, and the first electrode layers on the inner walls of multiple capacitor slots located in different layers are connected together through the first electrode layer on one side of the insulating layer;

[0049] Remove the first electrode layer on the exposed outer wall of the capacitor hole, disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in the same layer; and remove the first electrode layer on one side of each insulating layer, disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in different layers.

[0050] The remaining first electrode layer located on the inner wall of the capacitor tank is the first capacitor electrode; the first capacitor electrode is a hollow tube with one end closed and the other end open, and the closed end of the first capacitor electrode is in contact with the first sacrificial layer.

[0051] In some embodiments of this application, removing the first electrode layer on the exposed outer wall of the capacitor hole disconnects the first electrode layer on the inner wall of the plurality of capacitor slots located on the same layer; and removing the first electrode layer on one side of each insulating layer disconnects the first electrode layer on the inner wall of the plurality of capacitor slots located on different layers, includes:

[0052] After the first electrode layer is formed, a fourth sacrificial layer is filled into each of the capacitor slots, and the fourth sacrificial layer covers the first electrode layer located on the outer wall of the capacitor hole and the first electrode layer located on one side of each of the insulating layers.

[0053] Remove the fourth sacrificial layer covering the first electrode layer located on one side of each of the insulating layers and the fourth sacrificial layer of the first electrode layer located on the outer wall of the capacitor hole, exposing the first electrode layer located on one side of each of the insulating layers and the first electrode layer located on the outer wall of the capacitor hole;

[0054] Remove the first electrode layer located on one side of each of the insulating layers and the first electrode layer located on the outer wall of the capacitor hole; disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in different layers on one side of the insulating layer; and disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in the same layer on the outer wall of the capacitor hole between the plurality of capacitor slots.

[0055] Remove the fourth sacrificial layer.

[0056] In some embodiments of this application, the step of sequentially forming a dielectric layer and a second capacitor electrode on the inner wall of the first capacitor electrode and on the inner and outer walls of the capacitor hole includes:

[0057] A dielectric layer and a second capacitor electrode are sequentially formed on the inner and outer walls of the capacitor hole, the inner walls of each capacitor slot, and the inner wall of the connecting hole.

[0058] In some embodiments of this application, forming a support layer in the transistor hole and on the side of the capacitor hole away from the transistor hole includes:

[0059] The trench is filled with a third sacrificial layer;

[0060] Remove the third sacrificial layer in the transistor hole and the third sacrificial layer on the side of the capacitor hole away from the transistor hole;

[0061] The support layer is formed in the transistor hole and on the side of the capacitor hole away from the transistor hole;

[0062] Remove the third sacrificial layer.

[0063] This application also provides an electronic device, which includes a capacitor as described above, or a semiconductor device as described above, or a semiconductor device obtained by the manufacturing method described above.

[0064] The first capacitor electrode of the capacitor in this embodiment adopts a hollow tubular structure. A dielectric layer is provided on both the outer and inner walls of the hollow tubular structure. Therefore, the contact area between the first capacitor electrode and the dielectric layer is large, which can achieve a large capacitance.

[0065] The semiconductor device in this application adopts a three-dimensional (3D) structure, which can integrate more memory cells in a limited area. Moreover, the capacitor has a large capacitance, which can achieve better storage performance in a limited area.

[0066] The semiconductor device manufacturing method of this application embodiment first forms a hollow tubular structure first capacitor electrode, and then a dielectric layer can be formed on the outer and inner walls of the first capacitor electrode in one process. This not only increases the contact area between the first capacitor electrode and the dielectric layer, but also simplifies the manufacturing process and reduces costs.

[0067] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0068] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0069] Figure 1A A schematic diagram of the cross-sectional structure of a capacitor, which is an exemplary embodiment of this application;

[0070] Figure 1B This is a schematic diagram of another cross-sectional structure of a capacitor, which is an exemplary embodiment of this application.

[0071] Figure 2A A schematic diagram of the cross-sectional structure of a semiconductor device in a section parallel to the substrate AA', which is an exemplary embodiment of this application;

[0072] Figure 2B for Figure 2A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB').

[0073] Figure 2C for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0074] Figure 2D for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0075] Figure 2E for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate, EE'.

[0076] Figure 3 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0077] Figure 4A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a stacked structure, on a section perpendicular to the substrate (CC').

[0078] Figure 5A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after trench formation, on a section parallel to the substrate AA'.

[0079] Figure 5B for Figure 5A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB').

[0080] Figure 5C for Figure 5A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0081] Figure 5D for Figure 5A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0082] Figure 6A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing the third sacrificial layers on both sides of the trench, on a section parallel to the substrate AA'.

[0083] Figure 6B for Figure 6A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB').

[0084] Figure 6C for Figure 6A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0085] Figure 6D for Figure 6A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0086] Figure 7A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method, after the formation of a support layer, in a section parallel to the substrate, according to an exemplary embodiment of this application;

[0087] Figure 7B for Figure 7A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB').

[0088] Figure 7C for Figure 7AThe diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0089] Figure 7D for Figure 7A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0090] Figure 8A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method, after the formation of a support layer, in a section parallel to the substrate BB', which is an exemplary embodiment of this application.

[0091] Figure 8B for Figure 8A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0092] Figure 9A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the second sacrificial layer 12, on a section parallel to the substrate AA'.

[0093] Figure 9B for Figure 9A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB').

[0094] Figure 9C for Figure 9A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0095] Figure 9D for Figure 9A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0096] Figure 10A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a capacitor trench, on a section parallel to the substrate AA'.

[0097] Figure 10B for Figure 10A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0098] Figure 10C for Figure 10A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0099] Figure 11AThis is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the first electrode layer on the inner wall of a plurality of capacitor trenches is disconnected within and between layers, on a section parallel to the substrate AA'.

[0100] Figure 11B for Figure 11A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0101] Figure 11C for Figure 11A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate;

[0102] Figure 12A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing the second sacrificial layer in a capacitor hole, on a section parallel to the substrate AA'.

[0103] Figure 12B for Figure 12A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB').

[0104] Figure 12C for Figure 12A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate;

[0105] Figure 12D for Figure 12A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate.

[0106] The meanings of the symbols in the attached diagram are as follows:

[0107] 10-Substrate; 11-First sacrificial layer; 12-Second sacrificial layer; 13-Third sacrificial layer; 14-Fourth sacrificial layer; 15-Support layer; 16-Insulating layer; 17-Mask; 21-First capacitor electrode; 22-Second capacitor electrode; 23-Dielectric layer; 31-Trench; 32-Capacitor hole; 33-Connecting hole; 34-Capacitor groove. Detailed Implementation

[0108] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0109] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0110] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the width-to-length ratio of the insulating layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0111] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0112] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0113] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0114] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0115] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0116] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0117] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0118] In this application, "film" and "layer" can be interchanged. For example, "sacrificial layer" can sometimes be replaced with "sacrificial film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0119] The phrase "A and B are arranged in the same layer" in this application refers to A and B being distributed on the same horizontal plane, or although not on the same horizontal plane, both being in different areas of the same supporting surface. One embodiment involves A and B being formed simultaneously on the same film layer using the same patterning process.

[0120] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0121] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0122] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0123] This application provides a capacitor. Figure 1A A schematic diagram of the cross-sectional structure of a capacitor, which is an exemplary embodiment of this application; Figure 1B This is a schematic diagram of another cross-sectional structure of a capacitor, which is an exemplary embodiment of this application. Figure 1A The cross section and Figure 1B The cross sections are perpendicular to each other.

[0124] like Figure 1A and Figure 1B As shown, the capacitor includes: a first capacitor electrode 21, a second capacitor electrode 22, and a dielectric layer 23; the dielectric layer 23 is located between the first capacitor electrode 21 and the second capacitor electrode 22.

[0125] The first capacitor electrode 21 is a hollow tube with one end closed and the other end open. The first capacitor electrode 21 has an outer wall and an inner wall located inside the hollow tube. A dielectric layer 23 and a second capacitor electrode 22 are sequentially disposed on the outer wall, and a dielectric layer 23 and a second capacitor electrode 22 are sequentially disposed on the inner wall.

[0126] The first capacitor electrode of the capacitor in this embodiment adopts a hollow tubular structure. A dielectric layer is provided on both the outer and inner walls of the hollow tubular structure. Therefore, the contact area between the first capacitor electrode and the dielectric layer is large, which can achieve a large capacitance.

[0127] In some embodiments of this application, such as Figure 1A and Figure 1B As shown, the dielectric layer 23 at least partially surrounds the outer wall of the first capacitor electrode 21; and / or, the second capacitor electrode 22 at least partially surrounds the outer wall of the first capacitor electrode 21.

[0128] In some embodiments of this application, such as Figure 1A and Figure 1B As shown, the dielectric layer 23 completely surrounds the outer wall of the first capacitor electrode 21.

[0129] The dielectric layer 23 completely surrounds the outer wall of the first capacitor electrode 21, and the second capacitor electrode 22 completely surrounds the outer wall of the first capacitor electrode 21. This can increase the contact area between the first capacitor electrode and the dielectric layer to a greater extent, thereby achieving a larger capacitance.

[0130] In some embodiments of this application, such as Figure 1A and Figure 1B As shown, the second capacitor electrode 22 completely surrounds the outer wall of the first capacitor electrode 21.

[0131] In some embodiments of this application, such as Figure 1A and Figure 1B As shown, the dielectric layer 23 and the second capacitor electrode 22 cover the entire inner wall of the first capacitor electrode 21.

[0132] In some embodiments of this application, such as Figure 1A and Figure 1B As shown, the opening of the first capacitor electrode 21 has a support layer 15 on both sides; the support layer 15 is located on the outer wall of the first capacitor electrode 21 and is in contact with the dielectric layer 23 on the outer wall of the first capacitor electrode 21.

[0133] In some embodiments of this application, the dielectric layer 23 on the outer side wall of the first capacitor electrode 21 is spaced apart from the dielectric layer 23 on the inner side wall of the first capacitor electrode 21.

[0134] In some embodiments of this application, the second capacitor electrode 22 on the outer side wall of the first capacitor electrode 21 is spaced apart from the second capacitor electrode 22 on the inner side wall of the first capacitor electrode 21.

[0135] In some embodiments of this application, the dielectric layer 23 on the outer side wall of the first capacitor electrode 21 and the dielectric layer 23 on the inner side wall of the first capacitor electrode 21 are formed by the same process.

[0136] In some embodiments of this application, the second capacitor electrode 22 on the outer side wall of the first capacitor electrode 21 and the second capacitor electrode 22 on the inner side wall of the first capacitor electrode 21 are formed by the same process.

[0137] This application also provides a semiconductor device. Figure 2A A schematic diagram of the cross-sectional structure of a semiconductor device in a section parallel to the substrate AA', which is an exemplary embodiment of this application; Figure 2B for Figure 2A The diagram shows a cross-sectional view of the semiconductor device on a section parallel to the substrate (BB'). Figure 2C for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the CC' section perpendicular to the substrate; Figure 2D for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the DD' section perpendicular to the substrate; Figure 2E for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section EE' perpendicular to the substrate.

[0138] in, Figure 2A The AA' section passes through the first capacitor electrode 21; Figure 2B The BB' section in the middle passes through the insulating layer 16 between two adjacent first capacitor electrodes 21; Figure 2C The CC' section extends along the row direction and passes through the capacitor hole 32; Figure 2D The DD' section extends along the column direction through the capacitor hole 32; Figure 2E The EE' section extends along the row direction and passes through the first capacitor electrode 21. The positions of the AA', BB', CC', DD', and EE' sections shown in other figures herein are... Figures 2A to 2E same.

[0139] like Figures 2A to 2E As shown, the semiconductor device includes: a plurality of memory cells distributed in different layers and stacked along a direction perpendicular to the substrate 10; each layer includes a plurality of memory cells spaced apart along a row direction and a column direction parallel to the substrate 10; the memory cells include capacitors as described above.

[0140] The semiconductor device in this application adopts a three-dimensional (3D) structure, which can integrate more memory cells in a limited area. Moreover, the capacitor has a large capacitance, which can achieve better storage performance in a limited area.

[0141] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. Exemplarily, the row direction can be as follows: Figure 2A AA' direction or as in Figure 2B In the BB' direction, the column direction can be as follows: Figure 2D The DD' direction in the middle.

[0142] Multiple components distributed along the row direction can be referred to as a row of components, for example, a row of memory cells. Multiple components distributed along the column direction can be referred to as a column of components, for example, a column of memory cells. Multiple components distributed along a direction perpendicular to the substrate can be referred to as a string of components, for example, a string of memory cells.

[0143] In some embodiments of this application, such as Figure 2AAs shown, the first capacitor electrode 21 of the capacitor extends along the row direction, and the first capacitor electrodes 21 of multiple memory cells located in the same layer are spaced apart in the column direction.

[0144] In some embodiments of this application, such as Figure 2E As shown, the dielectric layer 23 on the inner wall of the first capacitor electrode 21 of the plurality of memory cells stacked along a direction perpendicular to the substrate 10 is an integral structure.

[0145] In some embodiments of this application, such as Figure 2A As shown, the dielectric layer 23 on the inner wall of the first capacitor electrode 21 of the plurality of storage cells distributed at intervals along the column direction is an integral structure.

[0146] In some embodiments of this application, such as Figure 2E As shown, the second capacitor electrode 22 on the inner wall of the first capacitor electrode 21 of the plurality of memory cells stacked along a direction perpendicular to the substrate 10 is an integral structure.

[0147] In some embodiments of this application, such as Figure 2A As shown, the second capacitor electrode 22 on the inner wall of the first capacitor electrode 21 of the plurality of storage cells distributed at intervals along the column direction is an integral structure.

[0148] In some embodiments of this application, such as Figure 2C As shown, the dielectric layer 23 on the outer wall of the first capacitor electrode 21 of the plurality of memory cells stacked along a direction perpendicular to the substrate 10 is an integral structure.

[0149] In some embodiments of this application, such as Figure 2C As shown, the second capacitor electrode 22 on the outer wall of the first capacitor electrode 21 of the plurality of memory cells stacked along a direction perpendicular to the substrate 10 is an integral structure.

[0150] In some embodiments of this application, such as Figure 2A As shown, the dielectric layers 23 on the opposite outer sidewalls of the first capacitor electrodes 21 of two adjacent storage cells along the column direction are an integral structure.

[0151] In some embodiments of this application, such as Figure 2A As shown, the second capacitor electrodes 22 on the opposite outer sidewalls of the first capacitor electrodes 21 of two adjacent memory cells along the column direction are a single-piece structure. In some embodiments of this application, such as Figure 2AAs shown, a capacitor hole 32 extending toward the substrate 10 is provided between a string of memory cells stacked along a direction perpendicular to the substrate 10 and another string of memory cells adjacent along the column direction. A dielectric layer 23 and a second capacitor electrode 22 are sequentially disposed on the inner wall of the capacitor hole 32.

[0152] In some embodiments of this application, such as Figure 2A As shown, the capacitor hole 32 has support layers 15 on both sides distributed along the row direction, and the support layers 15 on both sides are in contact with the dielectric layer 23 respectively.

[0153] In some embodiments of this application, such as Figures 2A to 2E As shown, the semiconductor device further includes a plurality of first sacrificial layers 11 stacked and alternately distributed and a plurality of insulating layers 16. Capacitor vias 32 penetrate each insulating layer 16.

[0154] In some embodiments of this application, such as Figure 2B As shown, the dielectric layer 23 on the outer sidewall of the first capacitor electrode 21 of the plurality of memory cells distributed at intervals along the column direction is an integral structure.

[0155] The second capacitor electrode 22 on the outer wall of the first capacitor electrode 21 of the plurality of storage cells distributed at intervals along the column direction is an integral structure.

[0156] In some embodiments of this application, the storage cell further includes a transistor, the transistor including a transistor electrode connected to the capacitor, and the first capacitor electrode 21 is shared as the transistor electrode.

[0157] In some embodiments of this application, the material of the first capacitor electrode can be selected from any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The first capacitor electrode can be a single-layer or multi-layer structure; for example, it can be a single-layer structure formed of titanium nitride (TiN).

[0158] In some embodiments of this application, the material of the second capacitor electrode can be selected from any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The second capacitor electrode can be a single-layer or multi-layer structure; for example, it can be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W).

[0159] The materials of the first capacitor electrode and the second capacitor electrode may be the same or different.

[0160] In some embodiments of this application, the dielectric layer may be made of silicon oxide or a high-K dielectric material. High-K materials, in some embodiments, may include any one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0161] In some embodiments of this application, the semiconductor device may be a 3D memory, such as a 3D DRAM. The 3D memory may be a 1T1C or 2T1C structure.

[0162] This application also provides a method for manufacturing a semiconductor device. Figure 3 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application. The semiconductor device described above can be obtained by this method.

[0163] like Figure 3 As shown, the manufacturing method includes:

[0164] Multiple insulating layers and multiple first sacrificial layers are sequentially and alternately deposited on a substrate to obtain a stacked structure;

[0165] In the stacked structure, a plurality of trenches are formed extending toward the substrate, the plurality of trenches being spaced apart in a column direction parallel to the substrate; both sides of the trenches distributed in a row direction parallel to the substrate expose the insulating layer and the first sacrificial layer; one side of the trenches distributed in the row direction is a transistor via, and the other side is a capacitor via;

[0166] A support layer is formed in the transistor hole and on the side of the capacitor hole away from the transistor hole;

[0167] A second sacrificial layer is filled into the capacitor hole;

[0168] Remove the first sacrificial layer from the outer wall of the capacitor hole;

[0169] A tubular first capacitor electrode is formed in the region of the first sacrificial layer between two adjacent capacitor holes along the column direction, and the end of the first capacitor electrode that contacts the first sacrificial layer is closed.

[0170] Remove the second sacrificial layer;

[0171] A dielectric layer and a second capacitor electrode are sequentially formed on the inner wall of the first capacitor electrode and on the inner and outer walls of the capacitor hole.

[0172] The semiconductor device manufacturing method of this application embodiment first forms a hollow tubular structure first capacitor electrode, and then a dielectric layer can be formed on the outer and inner walls of the first capacitor electrode in one process. This not only increases the contact area between the first capacitor electrode and the dielectric layer, but also simplifies the manufacturing process and reduces costs.

[0173] In some embodiments of this application, the manufacturing method further includes: after forming a support layer in the transistor hole and on the side of the capacitor hole away from the transistor hole, and before filling the capacitor hole with a second sacrificial layer.

[0174] Remove the insulating layer exposed between two adjacent capacitor holes along the column direction, and form a connecting hole extending along the column direction in the insulating layer. The connecting hole connects a plurality of capacitor holes spaced apart along the column direction in the insulating layer, and the connected capacitor holes expose the circumferential sidewall of the first sacrificial layer between two adjacent capacitor holes along the column direction.

[0175] In some embodiments of this application, filling the capacitor orifice with a second sacrificial layer includes:

[0176] A second sacrificial layer is filled into the capacitor hole and the connecting hole;

[0177] Removing the first sacrificial layer from the outer wall of the capacitor hole includes:

[0178] Remove the first sacrificial layer on the outer wall of the capacitor hole, and form a capacitor groove between the second sacrificial layer in two adjacent capacitor holes along the column direction and between the second sacrificial layers in two adjacent connecting holes.

[0179] In some embodiments of this application, forming a tubular first capacitor electrode in the region of the first sacrificial layer between two adjacent capacitor holes along the column direction, wherein the end of the first capacitor electrode in contact with the first sacrificial layer is closed, includes:

[0180] A first electrode layer is formed on the inner wall of each capacitor slot, on the exposed outer wall of the capacitor hole, and on the side of each insulating layer distributed along the row direction and away from the first sacrificial layer; the first sacrificial layers on the inner walls of multiple capacitor slots located in the same layer are connected together through the first electrode layer on the exposed outer wall of the capacitor hole, and the first electrode layers on the inner walls of multiple capacitor slots located in different layers are connected together through the first electrode layer on one side of the insulating layer;

[0181] Remove the first electrode layer on the exposed outer wall of the capacitor hole, disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in the same layer; and remove the first electrode layer on one side of each insulating layer, disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in different layers.

[0182] The remaining first electrode layer located on the inner wall of the capacitor tank is the first capacitor electrode; the first capacitor electrode is a hollow tube with one end closed and the other end open, and the closed end of the first capacitor electrode is in contact with the first sacrificial layer.

[0183] In some embodiments of this application, removing the first electrode layer on the exposed outer wall of the capacitor hole disconnects the first electrode layer on the inner wall of the plurality of capacitor slots located on the same layer; and removing the first electrode layer on one side of each insulating layer disconnects the first electrode layer on the inner wall of the plurality of capacitor slots located on different layers, includes:

[0184] After the first electrode layer is formed, a fourth sacrificial layer is filled into each of the capacitor slots, and the fourth sacrificial layer covers the first electrode layer located on the outer wall of the capacitor hole and the first electrode layer located on one side of each of the insulating layers.

[0185] Remove the fourth sacrificial layer covering the first electrode layer located on one side of each of the insulating layers and the fourth sacrificial layer of the first electrode layer located on the outer wall of the capacitor hole, exposing the first electrode layer located on one side of each of the insulating layers and the first electrode layer located on the outer wall of the capacitor hole;

[0186] Remove the first electrode layer located on one side of each of the insulating layers and the first electrode layer located on the outer wall of the capacitor hole; disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in different layers on one side of the insulating layer; and disconnect the first electrode layer on the inner wall of the plurality of capacitor slots located in the same layer on the outer wall of the capacitor hole between the plurality of capacitor slots.

[0187] Remove the fourth sacrificial layer.

[0188] In some embodiments of this application, the step of sequentially forming a dielectric layer and a second capacitor electrode on the inner wall of the first capacitor electrode and on the inner and outer walls of the capacitor hole includes:

[0189] A dielectric layer and a second capacitor electrode are sequentially formed on the inner and outer walls of the capacitor hole, the inner walls of each capacitor slot, and the inner wall of the connecting hole.

[0190] In some embodiments of this application, forming a support layer in the transistor hole and on the side of the capacitor hole away from the transistor hole includes:

[0191] The trench is filled with a third sacrificial layer;

[0192] Remove the third sacrificial layer in the transistor hole and the third sacrificial layer on the side of the capacitor hole away from the transistor hole;

[0193] The support layer is formed in the transistor hole and on the side of the capacitor hole away from the transistor hole;

[0194] Remove the third sacrificial layer.

[0195] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0196] like Figures 4 to 12D As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0197] S10: Provide a substrate 10, and sequentially deposit insulating layers 16 and first sacrificial layers 11 alternately on the substrate 10 to obtain a stacked structure composed of multiple insulating layers 16 and multiple first sacrificial layers 11, such as... Figure 4 As shown.

[0198] In some embodiments of this application, the material forming the insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.

[0199] In some embodiments of this application, the material of the first sacrificial layer is different from the material of the insulating layer, so that when one of the first sacrificial layer and the insulating layer is subsequently etched, the other will not be damaged. For example, the material of the first sacrificial layer may be silicon nitride, and the material of the insulating layer may be silicon oxide.

[0200] For example only. Figure 4The stacked structure shown includes four insulating layers 16 and three first sacrificial layers 11. In other embodiments, the stacked structure may include more or fewer layers of insulating layers 16 and first sacrificial layers 11 arranged alternately.

[0201] S20: In the stacked structure, a plurality of trenches 31 are formed extending toward the substrate 10, such as Figures 5A to 5D As shown.

[0202] in, Figure 5A The AA' section in the middle passes through the first sacrificial layer 11; Figure 5B The BB' section in the middle passes through the insulation layer 16; Figure 5C The CC' section extends along the row direction and passes through the groove 31; Figure 5D The DD' section extends along the column direction through the groove 31.

[0203] For example, step S20 may include: etching the stacked structure along the direction toward the substrate 10, forming a plurality of trenches 31 in the stacked structure that penetrate the stacked structure in the direction toward the substrate 10, the plurality of trenches 31 extending along a row direction parallel to the substrate 10 and spaced apart in a column direction parallel to the substrate 10; both sides of the trenches 31 distributed along the row direction expose an insulating layer 16 and a first sacrificial layer 11, that is, although the trenches 31 extend in the row direction, they do not penetrate the stacked structure in the row direction; one side of the trenches 31 distributed along the row direction is a transistor hole, and the other side is a capacitor hole 32.

[0204] In some embodiments of this application, such as Figures 5A to 5D As shown, the trench 31 can extend along the row direction and in a direction perpendicular to the substrate 10; the trench 31 can penetrate the stacked structure in a direction perpendicular to the substrate 10, thereby exposing the substrate 10.

[0205] S30: A support layer 15 is formed in the transistor hole and on the side of the capacitor hole 32 away from the transistor hole.

[0206] For example, step S30 may include:

[0207] S31: Fill the trench 31 with the third sacrificial layer 13 and treat the third sacrificial layer 13 on the surface of the stacked structure using a chemical mechanical polishing (CMP) process.

[0208] S32: A mask 17 is formed on the surface of the stacked structure. The mask 17 covers the third sacrificial layer of the capacitor hole 32 on the side close to the transistor hole, and exposes the third sacrificial layer 13 in the transistor hole and the third sacrificial layer 13 on the side of the capacitor hole 32 away from the transistor hole.

[0209] S33: Using photolithography and etching processes, remove the third sacrificial layer 13 in the transistor hole and the third sacrificial layer 13 on the side of the capacitor hole 32 away from the transistor hole, such as... Figures 6A to 6D As shown;

[0210] S34: A support layer 15 is formed in the transistor hole and on the side of the capacitor hole 32 away from the transistor hole;

[0211] S35: Remove all third sacrificial layers 13, as follows Figures 7A to 7D As shown.

[0212] In other embodiments, step S30 may include:

[0213] S31': Fill the trench 31 with the support layer 15;

[0214] S32': A mask is formed on the surface of the stacked structure, the mask covering the third sacrificial layer 13 in the transistor hole and the support layer 15 on the side of the capacitor hole 32 away from the transistor hole, the mask exposing the support layer 15 on the side of the capacitor hole 32 close to the transistor hole;

[0215] S33': Using photolithography and etching processes, the support layer 15 on the side of the capacitor hole 32 exposed by the mask near the transistor hole is removed, leaving the support layer 15 in the transistor hole and the support layer 15 on the side of the capacitor hole 32 away from the transistor hole, as shown. Figures 7A to 7D As shown.

[0216] The material of the support layer is different from that of the third sacrificial layer. For example, the material of the support layer can be silicon oxide, while the material of the third sacrificial layer can be polycrystalline silicon, aluminum oxide, etc.

[0217] S40: Remove the insulating layer 16 exposed between two adjacent capacitor holes 32 along the column direction, and form a connecting hole 33 extending along the column direction in the insulating layer 16. The connecting hole 33 connects a plurality of capacitor holes 32 spaced apart along the column direction in the insulating layer 16. The connected capacitor holes 32 expose the circumferential sidewall of the first sacrificial layer 11 between two adjacent capacitor holes 32 along the column direction. Figure 8A and Figure 8B As shown. The schematic diagrams of the semiconductor device's longitudinal cross-sections in sections parallel to the substrate (AA') and perpendicular to the substrate (CC') after the formation of the connecting hole 33 are respectively compared with... Figure 7A and Figure 7C same.

[0218] S50: The second sacrificial layer 12 is filled into the capacitor via 32 and the connecting via 33, and the second sacrificial layer 12 on the surface of the stacked structure is processed using CMP technology, such as... Figures 9A to 9D As shown.

[0219] In some embodiments of this application, the material of the second sacrificial layer may be polycrystalline silicon, alumina, etc. The material of the second sacrificial layer and the material of the third sacrificial layer may be the same or different; for example, the material of the second sacrificial layer and the material of the third sacrificial layer may both be polycrystalline silicon.

[0220] S60: Remove the first sacrificial layer 11 from the outer wall of the capacitor hole 32, such as Figures 10A to 10C As shown.

[0221] For example, step S60 may include:

[0222] S61: A mask 17 covering the second sacrificial layer 12 is formed on the surface of the substrate 10 as a hard mask layer for subsequent etching of the stacked structure away from the transistor hole.

[0223] S62: The stacked structure away from the transistor hole is etched using photolithography and etching processes to expose the first sacrificial layer 11 between adjacent capacitor holes 32;

[0224] S63: By etching, for example, wet etching, the first sacrificial layer 11 exposed between adjacent capacitor holes 32 is etched to remove the first sacrificial layer 11 on the outer wall of the capacitor hole 32, and a capacitor trench 34 is formed between the second sacrificial layers 12 in two adjacent capacitor holes 32 along the column direction and the second sacrificial layers 12 in two adjacent connecting holes 33. Figures 10A to 10C As shown. A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device after the capacitor trench 34 is formed, on a section parallel to the substrate BB'. Figure 9B same.

[0225] like Figure 10A As shown, the capacitor groove 34 can extend along the row direction; one end of the capacitor groove 34 is closed by the first sacrificial layer 11 on both sides of the transistor hole.

[0226] like Figure 10C As shown, the capacitor slots 34 located in different layers are separated by the second sacrificial layer 12 in the connecting hole 33.

[0227] S70: A tubular first capacitor electrode 21 is formed in the region of the first sacrificial layer 11 between two adjacent capacitor holes 32 along the column direction, and the end of the first capacitor electrode 21 that contacts the first sacrificial layer 11 is closed.

[0228] For example, step S70 may include steps S71 to S73 described below.

[0229] S71: A first electrode layer is formed on the substrate 10. The first electrode layer covers the inner wall (including the inner bottom surface and the inner side wall) of each capacitor trench 34 and the exposed outer side wall of the capacitor hole 32. The first electrode layer also covers the side surface of each insulating layer 16 that is distributed along the row direction and away from the first sacrificial layer 11. The first sacrificial layers 11 on the inner wall of multiple capacitor trenches 34 located in the same layer are connected together through the first electrode layer on the exposed outer side wall of the capacitor hole 32. The first electrode layers on the inner wall of multiple capacitor trenches 34 located in different layers are connected together through the first electrode layer on one side surface of the insulating layer 16.

[0230] S72: Remove at least a portion of the first electrode layer on the exposed outer sidewall of the capacitor hole 32, for example, remove the first electrode layer on the sidewall of the support layer 15 away from the transistor hole, disconnect the first electrode layer on the inner wall of the plurality of capacitor slots 34 located in the same layer; and remove the first electrode layer on one side of each insulating layer 16, disconnect the first electrode layer on the inner wall of the plurality of capacitor slots 34 located in different layers.

[0231] For example, step S72 may include steps S721 to S724 described below.

[0232] S721: After the first electrode layer is formed, the fourth sacrificial layer 14 is filled in each capacitor trench 34, and the fourth sacrificial layer 14 covers the first electrode layer located on the outer wall of the capacitor hole 32 and the first electrode layer located on one side of each insulating layer 16.

[0233] In some embodiments of this application, the material of the fourth sacrificial layer may be polycrystalline silicon, alumina, etc. The material of the fourth sacrificial layer may be the same as or different from the material of the second sacrificial layer and / or the third sacrificial layer. For example, the materials of the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer may all be polycrystalline silicon.

[0234] S722: Remove the fourth sacrificial layer 14 covering the first electrode layer on one side of each insulating layer 16, and at least a portion of the fourth sacrificial layer 14 on the outer wall of the capacitor hole 32 (e.g., remove the fourth sacrificial layer 14 on the side wall of the support layer 15 away from the transistor hole), exposing the first electrode layer on one side of each insulating layer 16 and the first electrode layer on the outer wall of the capacitor hole 32.

[0235] S723: Remove the first electrode layer located on one side of each insulating layer 16, and remove at least a portion of the first electrode layer located on the outer wall of the capacitor hole 32 (e.g., remove the first electrode layer located on the side wall of the support layer 15 away from the transistor hole), disconnect the first electrode layers on the inner walls of the plurality of capacitor slots 34 located in different layers on one side of the insulating layer 16, and disconnect the first electrode layers on the inner walls of the plurality of capacitor slots 34 located in the same layer on the outer wall of the capacitor hole 32 between the plurality of capacitor slots 34; the remaining first electrode layer on the inner wall of the capacitor slot 34 is the first capacitor electrode 21; the first capacitor electrode 21 is a hollow tube closed at one end and open at the other end, and the closed end of the first capacitor electrode 21 is in contact with the first sacrificial layer 11, such as Figures 11A to 11C As shown. A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device after the formation of the first capacitor electrode 21 on a section parallel to the substrate BB'. Figure 9B same.

[0236] S724: Through-hole etching, for example, wet etching, to remove the fourth sacrificial layer 14.

[0237] S73: Through-hole etching, for example, wet etching, to remove the second sacrificial layer 12, such as... Figures 12A to 12D As shown.

[0238] like Figures 12A to 12D As shown, the two ends of the first capacitor electrode 21 are supported by the support layer 15, and the middle part is suspended.

[0239] S80: A dielectric layer 23 and a second capacitor electrode 22 are sequentially formed on the inner wall of the first capacitor electrode 21 and on the inner and outer walls of the capacitor hole 32, resulting in the following: Figures 2A to 2E The semiconductor device shown.

[0240] For example, step S80 may include:

[0241] A dielectric layer 23 and a second capacitor electrode 22 are sequentially formed on the inner and outer walls of the capacitor hole 32, the inner walls of each capacitor slot 34, and the inner wall of the connecting hole 33.

[0242] This application also provides an electronic device, which includes a capacitor as described above, or a semiconductor device as described above, or a semiconductor device obtained by the manufacturing method described above.

[0243] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0244] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A capacitor characterized by, Comprising: a first capacitor electrode, a second capacitor electrode, and a dielectric layer between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is a hollow tube with one end closed and the other end open, the first capacitor electrode has an outer sidewall and an inner wall inside the hollow tube; the outer sidewall is sequentially provided with the dielectric layer and the second capacitor electrode, and the inner wall is sequentially provided with the dielectric layer and the second capacitor electrode.

2. The capacitor of claim 1, wherein The dielectric layer at least partially surrounds the outer sidewall of the first capacitor electrode; and / or, the second capacitor electrode at least partially surrounds the outer sidewall of the first capacitor electrode.

3. The capacitor of claim 2, wherein The dielectric layer completely surrounds the outer sidewall of the first capacitor electrode, and the second capacitor electrode completely surrounds the outer sidewall of the first capacitor electrode.

4. The capacitor of claim 1, wherein The dielectric layer and the second capacitor electrode cover the entire inner wall of the first capacitor electrode.

5. The capacitor according to any one of claims 1 to 4, wherein The first capacitor electrode has a support layer on both sides of the opening; The support layer is located on the outer sidewall of the first capacitor electrode and in contact with the dielectric layer on the outer sidewall of the first capacitor electrode.

6. The capacitor of any one of claims 1 to 4, wherein, The dielectric layer on the outer sidewall of the first capacitor electrode is spaced apart from the dielectric layer on the inner wall of the first capacitor electrode; and / or, The second capacitor electrode on the outer sidewall of the first capacitor electrode is spaced apart from the second capacitor electrode on the inner wall of the first capacitor electrode.

7. The capacitor of any one of claims 1 to 4, wherein, The dielectric layer on the outer sidewall of the first capacitor electrode and the dielectric layer on the inner wall of the first capacitor electrode are formed by the same process; and / or, The second capacitor electrode on the outer sidewall of the first capacitor electrode and the second capacitor electrode on the inner wall of the first capacitor electrode are formed by the same process.

8. A semiconductor device, characterized by Comprising: a plurality of storage units, the plurality of storage units are distributed in different layers and stacked along a direction perpendicular to the substrate; each layer comprises a plurality of storage units spaced apart along a row direction and a column direction parallel to the substrate; the storage unit comprises the capacitor according to any one of claims 1 to 7.

9. The semiconductor device of claim 8, wherein, The first capacitor electrode extends along the row direction, and a plurality of first capacitor electrodes of a plurality of storage units in the same layer are spaced apart in the column direction.

10. The semiconductor device of claim 9, wherein, The dielectric layer on the inner wall of the first capacitor electrode of a plurality of storage units stacked along a direction perpendicular to the substrate is an integral structure; and / or, The dielectric layer on the inner wall of the first capacitor electrode of a plurality of storage units spaced apart along the column direction is an integral structure.

11. The semiconductor device of claim 9, wherein, The second capacitor electrode on the inner wall of the first capacitor electrode of a plurality of storage units stacked along a direction perpendicular to the substrate is an integral structure; and / or, The second capacitor electrode on the inner wall of the first capacitor electrode of a plurality of storage units spaced apart along the column direction is an integral structure.

12. The semiconductor device of claim 9, wherein, The dielectric layer on the outer sidewall of the first capacitor electrode of a plurality of storage units stacked along a direction perpendicular to the substrate is an integral structure; and / or, The second capacitor electrode on the outer sidewall of the first capacitor electrode of a plurality of the memory cells stacked and distributed along a direction perpendicular to the substrate is a unitary structure.

13. The semiconductor device according to any one of claims 9 to 12, wherein The dielectric layer on the opposite two outer sidewalls of the first capacitor electrode of two adjacent memory cells along the column direction is a unitary structure; and / or, The second capacitor electrode on the opposite two outer sidewalls of the first capacitor electrode of two adjacent memory cells along the column direction is a unitary structure.

14. The semiconductor device of claim 13, wherein, A capacitor hole extending towards the substrate is provided between a string of the memory cells stacked and distributed along a direction perpendicular to the substrate and another string of the memory cells adjacent along the column direction, and the capacitor hole has the dielectric layer and the second capacitor electrode sequentially arranged on the inner wall thereof.

15. The semiconductor device of claim 14, wherein, The capacitor hole has support layers on both sides distributed along the row direction, and the support layers on both sides are in contact with the dielectric layer, respectively.

16. The semiconductor device of any one of claims 9 to 12, 14, and 15, wherein The dielectric layer on the outer sidewall of the first capacitor electrode of a plurality of the memory cells spaced and distributed along the column direction is a unitary structure; The second capacitor electrode on the outer sidewall of the first capacitor electrode of a plurality of the memory cells spaced and distributed along the column direction is a unitary structure.

17. The semiconductor device of any of claims 9-12, 14, 15, wherein, The memory cell further comprises a transistor, the transistor comprising a transistor electrode connected with the capacitor, and the first capacitor electrode is shared as the transistor electrode.

18. A method of manufacturing a semiconductor device, characterized by Comprising: Depositing a plurality of insulating layers and a plurality of first sacrificial layers on a substrate alternately and sequentially to obtain a stack structure; Forming a plurality of trenches in the stack structure extending towards the substrate, the plurality of trenches being spaced and distributed along a column direction parallel to the substrate; Both sides of the trench distributed along a row direction parallel to the substrate expose the insulating layer and the first sacrificial layer; one side of the trench distributed along the row direction is a transistor hole, and the other side is a capacitor hole; Forming a support layer in the transistor hole and on the side of the capacitor hole away from the transistor hole; Filling the capacitor hole with a second sacrificial layer; Removing the first sacrificial layer on the outer wall of the capacitor hole; Forming a tubular first capacitor electrode in the region between two adjacent capacitor holes along the column direction and located in the first sacrificial layer, and the end of the first capacitor electrode in contact with the first sacrificial layer is closed; Removing the second sacrificial layer; Forming a dielectric layer and a second capacitor electrode on the inner wall of the first capacitor electrode and on the inner wall and the outer wall of the capacitor hole sequentially.

19. The method of manufacturing a semiconductor device according to Claim 18, wherein Further comprising: After forming the support layer in the transistor hole and on the side of the capacitor hole away from the transistor hole, before filling the capacitor hole with the second sacrificial layer, removing the insulating layer exposed between two adjacent capacitor holes in the column direction to form a communication hole extending in the column direction, the communication hole connecting the capacitor holes spaced in the column direction in the insulating layer, and the connected capacitor holes exposing the circumferential sidewall of the first sacrificial layer between two adjacent capacitor holes in the column direction; the filling the capacitor holes with the second sacrificial layer includes: filling the capacitor holes and the communication holes with the second sacrificial layer; the removing the first sacrificial layer on the outer wall of the capacitor hole includes: removing the first sacrificial layer on the outer wall of the capacitor hole to form a capacitor groove between the second sacrificial layer in two adjacent capacitor holes in the column direction and the second sacrificial layer in two adjacent communication holes.

20. The method of manufacturing a semiconductor device according to Claim 19, wherein the region of the first sacrificial layer between two adjacent capacitor holes in the column direction forms a tubular first capacitor electrode, and the end of the first capacitor electrode in contact with the first sacrificial layer is closed, including: forming a first electrode layer on the inner wall of each capacitor groove, on the exposed outer wall of the capacitor hole, and on the side surface of each insulating layer away from the first sacrificial layer in the row direction, the first sacrificial layer on the inner wall of the capacitor groove in the same layer is connected together through the first electrode layer on the exposed outer wall of the capacitor hole, and the first electrode layer on the inner wall of the capacitor groove in different layers is connected together through the first electrode layer on the side surface of the insulating layer; removing the first electrode layer on the exposed outer wall of the capacitor hole to disconnect the first electrode layer on the inner wall of the capacitor groove in the same layer, and removing the first electrode layer on the side surface of each insulating layer to disconnect the first electrode layer on the inner wall of the capacitor groove in different layers; the remaining first electrode layer on the inner wall of the capacitor groove is a first capacitor electrode, the first capacitor electrode is a hollow tubular with one end closed and the other end open, and the closed end of the first capacitor electrode is in contact with the first sacrificial layer.

21. The method of manufacturing a semiconductor device according to Claim 20, wherein the removing the first electrode layer on the exposed outer wall of the capacitor hole to disconnect the first electrode layer on the inner wall of the capacitor groove in the same layer, and removing the first electrode layer on the side surface of each insulating layer to disconnect the first electrode layer on the inner wall of the capacitor groove in different layers, includes: after forming the first electrode layer, filling each capacitor groove with a fourth sacrificial layer, and the fourth sacrificial layer covers the first electrode layer on the outer wall of the capacitor hole and the first electrode layer on the side surface of each insulating layer; ​ removing the fourth sacrificial layer covering the first electrode layer on the side surface of each of the insulating layers and the first electrode layer on the outer sidewall of the capacitor hole to expose the first electrode layer on the side surface of each of the insulating layers and the first electrode layer on the outer sidewall of the capacitor hole; removing the first electrode layer on the side surface of each of the insulating layers and the first electrode layer on the outer sidewall of the capacitor hole to disconnect the first electrode layer on the inner wall of the plurality of capacitor trenches in different layers on the side surface of the insulating layers and disconnect the first electrode layer on the inner wall of the plurality of capacitor trenches in the same layer on the outer sidewall of the capacitor hole between the plurality of capacitor trenches; removing the fourth sacrificial layer.

22. The method of manufacturing a semiconductor device according to Claim 21, wherein the sequentially forming dielectric layers and second capacitor electrodes on the inner wall of the first capacitor electrode and the inner and outer walls of the capacitor hole includes: sequentially forming dielectric layers and second capacitor electrodes on the inner and outer walls of the capacitor hole, the inner wall of each of the capacitor trenches, and the inner wall of the communication hole.

23. The method of manufacturing a semiconductor device according to any one of claims 18 to 22, wherein the forming support layers in the transistor hole and on the side of the capacitor hole away from the transistor hole includes: filling the trench with a third sacrificial layer; removing the third sacrificial layer in the transistor hole and on the side of the capacitor hole away from the transistor hole; forming the support layers in the transistor hole and on the side of the capacitor hole away from the transistor hole; removing the third sacrificial layer.

24. An electronic device, comprising: a capacitor according to any one of claims 1 to 7, or a semiconductor device according to any one of claims 8 to 17, or a semiconductor device obtained by a manufacturing method according to any one of claims 18 to 23.

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