Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate, and forming a mask layer with an opening which exposes a part of the surface of the substrate on the substrate; the mask layer is used as a mask, etching is carried out to form a first sub-groove with a flat side wall, a groove forming process is carried out on the substrate to form a groove, the groove is provided with a concave-convex side wall, the first sub-groove forms a part of the groove, and the groove forming process comprises the steps that a protection layer is conformally formed on the surface of the formed sub-groove; part of the protective layer and part of the substrate at the bottom of the formed sub-groove are etched, a second sub-groove is formed below the formed sub-groove, and the transverse size of the second sub-groove is larger than that of the first sub-groove; removing the protective layer; and forming a capacitor structure in the groove. According to the invention, the grooves are provided with the concave-convex side walls, so that the effective coupling area can be increased, the capacitance density can be improved, and the problem that the depth-to-width ratio of one-time deep groove etching is difficult to increase is effectively avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the continuous improvement of chip integration, deep trench capacitors (DTC) are being used more and more widely. Compared with some other capacitor types in semiconductor integrated circuits, deep trench capacitors exhibit high power density.

[0003] In related technologies, deep trench capacitor technology relies on increasing the depth of the deep trench to improve the capacitance density. However, as the etching depth increases, it is difficult to guarantee that the aspect ratio can continue to improve. In other words, the capacitance density of deep trench capacitors is limited by the etching process and cannot be further improved. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, the first aspect of this application provides a method for manufacturing a semiconductor device, the method comprising: A substrate is provided, on which a mask layer is formed, the mask layer having an opening that exposes a portion of the surface of the substrate; Using the mask layer as a mask, the substrate is etched through a first etching process to form a first sub-trench with flat sidewalls; At least one trench formation process is performed on the substrate to continue etching the substrate to form trenches, the trenches having undulating sidewalls, the first sub-trench forming part of the trenches, wherein the trench formation process includes the following steps performed sequentially: A protective layer is conformally formed on the surface of the existing sub-grooves; A portion of the protective layer and a portion of the substrate at the bottom of the formed sub-trench are etched by a second etching process to form a second sub-trench below the formed sub-trench, wherein the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate. Remove the protective layer; A capacitor structure is formed in the trench.

[0006] In one embodiment, between two adjacent trench forming processes, the manufacturing method further includes the following steps: Using the mask layer as a mask, the substrate is further etched by the first etching process to form another first sub-trench with flat sidewalls below the already formed second sub-trench.

[0007] In one embodiment, the second etching process includes: etching a portion of the substrate below the formed sub-trench using an anisotropic dry etching process to form a groove; etching a portion of the substrate outside the groove using an isotropic etching process to expand the groove and form a second sub-trench; or etching a portion of the substrate using an isotropic etching process to form the second sub-trench.

[0008] In one embodiment, the isotropic etching process includes chemical dry etching or wet etching.

[0009] In one embodiment, when isotropically etching a portion of the substrate outside the groove, the etching rate of the protective layer is less than the etching rate of the substrate.

[0010] In one embodiment, forming a capacitor structure in the trench includes: conformally forming a first dielectric layer on the surface of the trench, the first dielectric layer also covering a portion of the surface of the substrate; forming a first electrode plate covering the surface of the first dielectric layer and filling a portion of the trench; forming a second dielectric layer on the first electrode plate; and forming a second electrode plate on the second dielectric layer, wherein the second electrode plate fills the remaining space in the trench and electrically isolates the second electrode plate from the first electrode plate through the second dielectric layer.

[0011] In one embodiment, before forming the capacitor structure in the trench, the manufacturing method further includes removing the mask layer.

[0012] A third aspect of this application also provides a semiconductor device, the semiconductor device comprising: Substrate; A trench located in the substrate, the trench including a first sub-trench having flat sidewalls and at least one second sub-trench, the first sub-trench being connected to the second sub-trench, the second sub-trench having a lateral dimension in a direction perpendicular to the thickness direction of the substrate being greater than the lateral dimension of the first sub-trench in the same direction. A capacitor structure located in the trench.

[0013] In one embodiment, the trench includes a first sub-trench and a plurality of second sub-trenches, the first sub-trench being located at the top and the second sub-trenches being located below the first trench; or The trench includes multiple first sub-grooves and multiple second sub-grooves, which are arranged alternately from top to bottom.

[0014] In one embodiment, the capacitor structure includes: A first dielectric layer is conformally formed on the surface of the trench, and the first dielectric layer also covers a portion of the surface of the substrate; A first electrode plate, which covers the surface of the first dielectric layer and fills part of the trench; A second dielectric layer is located on the first electrode plate; The second electrode plate is located on the second dielectric layer, wherein the second electrode plate fills the remaining space in the trench and electrically isolates the second electrode plate from the first electrode plate through the second dielectric layer.

[0015] The semiconductor device and manufacturing method of the present application embodiment form a trench in a substrate. During the formation of the trench, at least one first sub-trench with flat sidewalls and at least one second sub-trench are formed. The second sub-trench has a larger lateral dimension in the direction perpendicular to the thickness direction of the substrate than the first sub-trench in the same direction. This gives the trench undulating sidewalls. Then, a capacitor structure is formed in the trench. The undulating sidewalls and the electrodes filled therein form a three-dimensional coupling surface, increasing the effective coupling area and improving the capacitance density. The problem of difficulty in improving the aspect ratio of a single deep trench etching can be effectively avoided by using at least one first etching process and one second etching process. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0017] In the attached image: Figure 1 A flowchart illustrating a method for manufacturing a first semiconductor device according to a specific embodiment of this application is shown; Figure 2 A flowchart illustrating a method for manufacturing a first semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3I This diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Figures 4A-4E A cross-sectional schematic diagram of a semiconductor device is shown, illustrating a portion of the steps in the manufacturing method of the second semiconductor device. Detailed Implementation

[0018] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] With the continuous improvement of chip integration, deep trench capacitors (DTC) are being used more and more widely. Compared with some other capacitor types in semiconductor integrated circuits, deep trench capacitors exhibit high power density.

[0025] In related technologies, deep trench capacitor technology relies on increasing the depth of the deep trench to improve the capacitance density. However, as the etching depth increases, it is difficult to guarantee that the aspect ratio can continue to improve. In other words, the capacitance density of deep trench capacitors is limited by the etching process and cannot be further improved.

[0026] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 1 As shown, it mainly includes the following steps: Step S110: A substrate is provided, and a mask layer is formed on the substrate, the mask layer having an opening that exposes a portion of the surface of the substrate; Step S120: Using the mask layer as a mask, perform at least one trench formation process on the substrate to form a trench in the substrate. The trench has uneven sidewalls. The trench formation process includes the following steps: etching the substrate to form a first sub-trench with flat sidewalls using a first etching process; conformally forming a protective layer on the surface of the formed sub-trench; etching at least a portion of the protective layer and a portion of the substrate at the bottom of the formed sub-trench using a second etching process to form a second sub-trench below the formed sub-trench, wherein the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate; and removing the protective layer. Step S130: A capacitor structure is formed in the trench.

[0027] The semiconductor device and manufacturing method of the present application embodiment form a trench in a substrate. During the formation of the trench, at least one first sub-trench with flat sidewalls and at least one second sub-trench are formed. The second sub-trench has a larger lateral dimension in the direction perpendicular to the thickness direction of the substrate than the first sub-trench in the same direction. This gives the trench undulating sidewalls. Then, a capacitor structure is formed in the trench. The undulating sidewalls and the electrodes filled therein form a three-dimensional coupling surface, increasing the effective coupling area and improving the capacitance density. The problem of difficulty in improving the aspect ratio of a single deep trench etching can be effectively avoided by using at least one first etching process and one second etching process.

[0028] Example 1 Below, for reference Figure 1 , Figure 2 , Figures 3A to 3I , Figures 4A to 4E The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a first semiconductor device according to a specific embodiment of this application is shown; Figure 2 A flowchart illustrating a second method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figure 3A-3I This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Figures 4A to 4E A cross-sectional schematic diagram of a semiconductor device is shown, illustrating a portion of the steps in the manufacturing method of the second semiconductor device.

[0029] For example, the method for manufacturing a semiconductor device according to this application includes the following steps: First, such as Figure 1As shown, step S110 is performed by providing a substrate on which a mask layer is formed, the mask layer having an opening that exposes a portion of the surface of the substrate.

[0030] For example, such as Figure 3A As shown, a hard mask layer 201 and an etch stop layer 202 are sequentially formed on a substrate 200. Exemplarily, the hard mask layer 201 and the etch stop layer 202 can be formed using a thermal oxidation process, and the etch stop layer 202 can be formed using a chemical vapor deposition process. The hard mask layer 201 includes, but is not limited to, a silicon oxide layer, and the etch stop layer 202 includes, but is not limited to, a silicon nitride layer. Next, as... Figure 3B As shown, a photoresist layer 203 is formed on the etch stop layer. The photoresist layer 203 is patterned by photolithography to define the positions of predetermined trenches. The etch stop layer 202 and the hard mask layer 201 are etched using the patterned photoresist layer 203 as a mask to expose a portion of the surface of the substrate 200. The etched hard mask layer 201 and the etch stop layer 202 constitute a mask layer 220. An opening 211 in the mask layer 220 exposes a portion of the surface of the substrate 200.

[0031] For example, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0032] Then, continue as follows Figure 1As shown, in step S120, using the mask layer as a mask, at least one trench formation process is performed on the substrate to form a trench in the substrate. The trench has uneven sidewalls. The trench formation process includes the following steps: etching the substrate to form a first sub-trench with flat sidewalls using a first etching process; conformally forming a protective layer on the surface of the formed sub-trench; forming a second sub-trench below the formed sub-trench by etching a portion of the protective layer and a portion of the substrate at the bottom of the formed sub-trench using a second etching process, wherein the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate; and removing the protective layer.

[0033] For example, firstly, as Figure 3C As shown, using mask layer 220 as a mask, the substrate 200 is etched by a first etching process to form a first sub-trench 204 with flat sidewalls. For example, the first etching process can be anisotropic dry etching.

[0034] Next, as Figure 3D As shown, a protective layer 205 is conformally formed on the surface of the first sub-trench 204. The protective layer 205 covers the sidewalls and bottom of the first sub-trench 204. Exemplarily, the protective layer 205 also covers a mask layer 210. The protective layer 205 can be deposited using a chemical vapor deposition process. The protective layer 205 includes, but is not limited to, a silicon oxide layer or other suitable insulating material layer.

[0035] Next, as Figures 3E to 3FAs shown, at least a portion of the protective layer 205 and a portion of the substrate 200 at the bottom of the first sub-trench 204 are etched using a second etching process, thereby forming a second sub-trench below the first sub-trench 204. Exemplarily, the second etching process may include the following steps: first, etching a portion of the substrate below the formed sub-trench using an anisotropic dry etching process to form a groove; then, etching the substrate using an isotropic etching process to enlarge the groove and form the second sub-trench, wherein the isotropic etching process includes chemical dry etching or wet etching. For example, an anisotropic dry etching process is used to etch a portion of the substrate below the first sub-trench 204 to form a groove with flat sidewalls. Then, an isotropic etching process is used to etch the substrate 200 using a chemical dry etching process. During isotropic etching, because a protective layer 205 is formed on the sidewalls of the first sub-trench 204, but no protective layer is present in the groove, the etching rate of the protective layer 205 is lower than the etching rate of the substrate. For example, the etching rate of the protective layer 205 may be more than five times that of the substrate. Therefore, the groove can be enlarged to form a second sub-trench 206, such that the lateral dimension of the second sub-trench 206 in the direction perpendicular to the thickness direction of the substrate 200 is larger than the lateral dimension of the first sub-trench 204 in the same direction. In some examples, the second etching process may also include isotropic etching of a portion of the substrate to form the second sub-trench.

[0036] It is worth mentioning that anisotropic dry etching and isotropic chemical dry etching can be performed in the same etching equipment. For example, the anisotropy and isotropy of etching can be achieved by adjusting the process parameters of the equipment. Specifically, a combination or alternating circulation of fluorine-containing etching gas (such as SF6) and carbon-containing passivation gas (such as C4F8) can be used, while maintaining a high bias power and a low chamber pressure to achieve anisotropic etching in a generally vertical direction, forming a groove in the substrate. In the same equipment, isotropic chemical dry etching is then performed. For example, the C4F8 is stopped, and only or mainly SF6 is introduced, while the bias power is significantly reduced and the chamber pressure is increased. The generally vertical groove is then etched laterally to increase its size and change the sidewall shape, forming the desired "recessed" contour.

[0037] Next, as Figure 3G As shown, the protective layer 205 is removed, exemplarily using a wet etching process. The first sub-trench 204 and the second sub-trench 206 form a trench, which has undulating sidewalls. Thus, as... Figures 3C to 3G As shown, a trench formation process is performed once in substrate 200. To form multiple uneven sidewalls, the above steps are repeated. Further details are omitted here. Repeating the above trench formation process can form a trench like... Figure 3H The structure shown, Figure 3H A cross-sectional view of a semiconductor device after three cycles of trench formation process is shown. The specific number of cycles can be set as needed and is not limited in this application.

[0038] It is worth mentioning that in some examples, the step of forming the first trench can also be performed after the step of forming the second sub-trench, that is, the second sub-trench is formed first and then the first sub-trench is formed.

[0039] Next, by way of example, the mask layer is removed, for example by wet etching to remove the remaining mask layer.

[0040] Then, continue as follows Figure 1 As shown, step S130 is performed to form a capacitor structure in the trench. For example, as... Figure 3I As shown, forming a capacitor structure in the trench includes: First, a first dielectric layer 207 is conformally formed on the surface of the trench (i.e., the sidewalls and bottom of the trench). The first dielectric layer 207 also covers part of the surface of the substrate 200. The first dielectric layer 207 serves as the first dielectric layer of the capacitor. Its material can be silicon oxide, and its thickness is usually between 5 nm and 20 nm. For example, it is formed by thermal oxidation or atomic layer deposition to ensure that it has good uniformity and insulation. Next, a first electrode 208 is formed on the first dielectric layer 207, covering the first dielectric layer 207. Optionally, the first electrode 208 is conformally formed on the first dielectric layer 207. The first electrode 208 covers the first dielectric layer 207 within the trench and extends to a portion of the area outside the trench. The material of the first electrode 208 is preferably heavily doped polycrystalline silicon or titanium nitride, or other suitable materials may also be used. Heavily doped polycrystalline silicon has good conductivity and step coverage; while titanium nitride, as a metal nitride, has lower resistance and better thermal stability, which is beneficial for reducing electrode losses. A second dielectric layer 209 is formed on the first electrode 208. The second dielectric layer 209 covers the surface of the first electrode 208 within the trench and partially covers the substrate surface of the first electrode 208 outside the trench. Optionally, the second dielectric layer 209 is formed conformally on the first electrode 208. To obtain a higher dielectric constant and lower leakage current with a limited thickness, the material of the second dielectric layer 209 is preferably a high-k dielectric material such as an ONO composite dielectric layer, hafnium oxide, or zirconium oxide. The ONO structure can effectively suppress leakage current; while hafnium oxide and zirconium oxide can significantly increase the capacitance per unit area due to their high dielectric constant.

[0041] A second electrode 210 is formed on the second dielectric layer 209, covering the second dielectric layer 209 and filling the remaining space in the trench, forming an embedded fill. Optionally, the material of the second electrode includes at least one of heavily doped polysilicon, metal nitride, metal silicide, tungsten, copper, and aluminum, or other suitable materials. The first electrode 208 is electrically connected to the substrate 200 through external circuitry (e.g., through contact holes and metal interconnects), jointly serving as the first electrode of the deep trench capacitor, while the second electrode 210 serves as the second electrode of the deep trench capacitor. By constructing a stacked electrode-dielectric layer pair within the same trench, a three-dimensional capacitor is achieved, greatly improving the capacitance density per unit chip area.

[0042] This concludes the description of the key steps in the method for manufacturing a semiconductor device according to the first embodiment of this application. The second aspect of this application provides a method for manufacturing a semiconductor device according to another embodiment.

[0043] Example 2 like Figure 2 As shown, the second method for manufacturing a semiconductor device includes: Step S21: Provide a substrate, on which a mask layer is formed, the mask layer having an opening that exposes a portion of the surface of the substrate; Step S22: Using the mask layer as a mask, the substrate is etched through a first etching process to form a first sub-trench with flat sidewalls; Step S23: Perform at least one trench formation process on the substrate to continue etching the substrate to form trenches, the trenches having uneven sidewalls, the first sub-trench constituting a part of the trenches, wherein the trench formation process includes the following steps performed sequentially: conformally forming a protective layer on the surface of the formed sub-trench; etching a portion of the protective layer and a portion of the substrate at the bottom of the formed sub-trench by a second etching process to form a second sub-trench below the formed sub-trench, wherein the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate; removing the protective layer; Step S24: A capacitor structure is formed in the trench.

[0044] First, step S21 is performed. Step S21 is the same as step S110 in Embodiment 1, and will not be repeated here. For details, please refer to step S110 of the manufacturing method in Embodiment 1.

[0045] Next, step S22 is performed, using the mask layer as a mask, the substrate is etched through a first etching process to form a first sub-trench with flat sidewalls. This step is related to step S120 in Embodiment 1, that is, forming a... Figure 3C The structure shown is not described in detail here; please refer to the previous description.

[0046] Next, step S23 is performed, whereby at least one trench formation process is performed on the substrate to continue etching the substrate to form trenches. The trenches have undulating sidewalls, and the first sub-trench constitutes a part of the trench. The trench formation process includes the following steps performed sequentially: conformally forming a protective layer on the surface of the formed sub-trench; etching a portion of the protective layer and a portion of the substrate at the bottom of the formed sub-trench using a second etching process to form a second sub-trench below the formed sub-trench, wherein the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate; and removing the protective layer.

[0047] The difference between step S23 in this embodiment and step S120 in embodiment one lies in the trench formation process. In embodiment one, each trench formation process first forms a flat sidewall, and then the substrate is etched to form a second sub-trench based on the flat sidewall. In this embodiment, the trench formation process does not include the formation of flat sidewalls. Flat sidewalls are formed before the trench formation process. The trench formation process is used to form uneven sidewalls without flat sidewalls. After the trench formation process is completed, the flat sidewalls and the uneven sidewalls together constitute the sidewalls of the final trench. The following will illustrate this further. Figure 4A Figure 4 illustrates the steps of the trench formation process in this embodiment.

[0048] Specifically, firstly, the first raised sidewall is formed, the process of which is the same as the steps in Embodiment 1, such as... Figure 3D - Figure 3G As shown, the specific process can be found in the previous description.

[0049] Next, the trench forming process is performed, such as... Figure 4A As shown, a protective layer 205 is conformally formed on the surfaces of the formed sub-grooves, namely the first sub-grooves 204 and the second sub-grooves 206, and then as follows: Figure 4B As shown, a portion of the protective layer 205 and a portion of the substrate 200 at the bottom of the second sub-trench 206 are etched using anisotropic dry etching to form a groove located below the second sub-trench 206. Then, as... Figure 4C As shown, the substrate is etched isotropically to enlarge the groove and form a second sub-groove 206. Then, as... Figure 4DAs shown, the protective layer 205 is removed. By repeatedly performing the above trench formation process steps, multiple uneven sidewalls can be created in the substrate 200, such as... Figure 4E As shown, the specific execution process will not be elaborated further. The specific number of loops can be set as needed, and this application does not limit it.

[0050] Next, step S24 is performed. Step S24 is the same as step S130 in Embodiment 1, and will not be described again here. For details, please refer to step S130 of the manufacturing method in Embodiment 1.

[0051] It is worth mentioning that the main difference between the aforementioned Embodiment 1 and Embodiment 2 is that the scheme of Embodiment 1 is equivalent to, based on the scheme of Embodiment 2, between two adjacent trench formation processes, using a mask layer as a mask, continuing to etch the substrate through the first etching process to form another first sub-trench with flat sidewalls below the already formed second sub-trench, thereby also obtaining the device structure that can be obtained in Embodiment 1.

[0052] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0053] The semiconductor device manufacturing method of this application embodiment forms a trench in a substrate. During the trench formation process, at least one first sub-trench with flat sidewalls and at least one second sub-trench are formed. The second sub-trench has a larger lateral dimension in the direction perpendicular to the thickness direction of the substrate than the first sub-trench in the same direction, thus giving the trench an uneven sidewall. A capacitor structure is then formed in the trench, and the uneven sidewall forms a three-dimensional coupling surface with the electrodes filled therein, significantly increasing the effective coupling area of ​​the capacitor and thus effectively improving the capacitance density. Furthermore, this method forms the trench by performing at least a first etching process and a second etching process sequentially. This step-by-step process effectively avoids the aspect ratio limitation problem faced when performing deep trench etching in a single step, improving process feasibility and structural accuracy.

[0054] Example 3 This application also provides a semiconductor device, which can be prepared by the semiconductor device manufacturing method described in Embodiment 1 above. Some details of this embodiment can be found in the relevant descriptions of the methods above, and will not be repeated here.

[0055] Specifically, such as Figure 3G and 3EAs shown, the semiconductor device includes a substrate 200, a trench, and a capacitor structure. The trench is located in the substrate 200, and the capacitor structure is located in the trench. The trench includes a first sub-trench 204 with flat sidewalls and at least one second sub-trench 206. The first sub-trench 204 is connected to the second sub-trench 206, and the lateral dimension of the second sub-trench 206 in a direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench 204 in the same direction.

[0056] In some examples, such as Figure 3H As shown, the trench includes a plurality of first sub-trenches 204 and a plurality of second sub-trenches 206, which are arranged alternately from top to bottom.

[0057] In some examples, such as Figure 4E As shown, the trench includes a first sub-trench 204 and a plurality of second sub-trenches 206, with the first sub-trench 204 located at the top and the second sub-trenches 206 located below the first trench 204.

[0058] In some examples, the capacitor structure includes a first dielectric layer 207, a first electrode 208, a second dielectric layer 209, and a second electrode 210. The first dielectric layer 207 is conformally formed within the trench, the first electrode 208 is located on the first dielectric layer 207, the second dielectric layer 209 is located on the first electrode 208, and the second electrode 210 is located on the second dielectric layer 209, filling the remaining space within the trench. The first electrode 208 is connected to the substrate 200 via an external circuit to form the first electrode of the deep trench capacitor, and the second electrode 210 is the second electrode of the deep trench capacitor.

[0059] In some examples, the first dielectric layer is made of silicon oxide, the second dielectric layer is made of an ONO composite dielectric layer, hafnium oxide or zirconium oxide; the first electrode is made of heavily doped polycrystalline silicon or titanium nitride; and the second electrode is made of heavily doped polycrystalline silicon, metal nitride, metal silicide, tungsten, copper or aluminum.

[0060] Since the semiconductor device of this application is manufactured using the aforementioned semiconductor device manufacturing method, it also possesses the beneficial effects of the aforementioned method. That is, a trench is formed in the substrate, and at least one first sub-trench with flat sidewalls and at least one second sub-trench are formed during the trench formation process. The lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate, thereby giving the trench undulating sidewalls. Then, a capacitor structure is formed in the trench, and a three-dimensional coupling surface is formed with the electrodes filled therein through the undulating sidewalls, increasing the effective coupling area and improving the capacitance density. The problem of difficulty in improving the aspect ratio of a single deep trench etching can be effectively avoided by using at least one first etching process and one second etching process.

[0061] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The manufacturing method comprises: providing a substrate, a mask layer is formed on the substrate, the mask layer has an opening exposing a part of the surface of the substrate; using the mask layer as a mask, etching the substrate by a first etching process to form a first sub-trench having a flat sidewall; performing at least one trench forming process on the substrate to continue etching the substrate to form a trench having a concave-convex sidewall, the first sub-trench constitutes a part of the trench, wherein, the trench forming process comprises the following steps performed in sequence: forming a protection layer conformally on the surface of the formed sub-trench; etching part of the protection layer on the bottom of the formed sub-trench and part of the substrate by a second etching process to form a second sub-trench below the formed sub-trench, wherein the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate; removing the protection layer; forming a capacitor structure in the trench.

2. The production method according to claim 1, wherein between two adjacent times of the trench forming process, the manufacturing method further comprises the following steps: using the mask layer as a mask, continuing to etch the substrate by the first etching process to form another first sub-trench having a flat sidewall below the formed second sub-trench.

3. The production method according to claim 1 or 2, characterized by, the second etching process comprises: etching part of the substrate below the formed sub-trench by an anisotropic dry etching process to form a groove; etching part of the substrate outside the groove by an isotropic etching process to expand the groove to form a second sub-trench; or etching part of the substrate by an isotropic etching process to form the second sub-trench.

4. The production method according to claim 3, wherein the isotropic etching process comprises a chemical dry etching or a wet etching.

5. The production method according to claim 3, wherein when etching part of the substrate outside the groove by the isotropic etching, the etching rate of the protection layer is less than the etching rate of the substrate.

6. The production method according to claim 1 or 2, wherein the forming of the capacitor structure in the trench comprises: forming a first dielectric layer conformally on the surface of the trench, the first dielectric layer also covers part of the surface of the substrate; forming a first electrode plate covering the surface of the first dielectric layer and filling part of the trench; forming a second dielectric layer on the first electrode plate; forming a second electrode plate on the second dielectric layer, wherein the second electrode plate fills the remaining space in the trench, and the second electrode plate and the first electrode plate are electrically isolated by the second dielectric layer.

7. The production method according to claim 1, wherein before the forming of the capacitor structure in the trench, the manufacturing method further comprises removing the mask layer.

8. A semiconductor device, characterized by, the semiconductor device comprises: a substrate; a trench in the substrate, the trench comprises a first sub-trench having a flat sidewall and at least one second sub-trench, the first sub-trench is connected with the second sub-trench, the lateral dimension of the second sub-trench in the direction perpendicular to the thickness direction of the substrate is greater than the lateral dimension of the first sub-trench in the direction perpendicular to the thickness direction of the substrate; a capacitor structure in the trench.

9. The semiconductor device of claim 8, wherein, The trench includes a first sub-trench and a plurality of second sub-trenches, the first sub-trench is located at the top, and the second sub-trenches are located below the first trench; or The trench includes a plurality of first sub-trenches and a plurality of second sub-trenches, the first sub-trenches and the second sub-trenches are arranged alternately from top to bottom.

10. The semiconductor device of claim 9, wherein, The capacitor structure includes: A first dielectric layer conformally formed on the surface of the trench, the first dielectric layer also covers part of the surface of the substrate; A first electrode plate covering the surface of the first dielectric layer and filling part of the trench; A second dielectric layer located on the first electrode plate; A second electrode plate located on the second dielectric layer, wherein the second electrode plate fills the remaining space in the trench, and the second electrode plate and the first electrode plate are electrically isolated by the second dielectric layer.

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