Semiconductor device

Abstract

An object of the present disclosure is to provide a semiconductor device which is low in noise and low in switching loss, and which is capable of suppressing an increase in saturation voltage VCE (sat) between an emitter and a collector. This semiconductor device is provided with: a double-layer active dummy trench having a first upper layer electrode and a first lower layer electrode; and a double-layer active trench having a second upper-layer electrode and a second lower-layer electrode, the first upper-layer electrode, the second upper-layer electrode, and the second lower-layer electrode being connected to the same gate pad, the double-layer active dummy trench and the double-layer active trench extending in the horizontal direction in plan view. The length of a region in which the double-layer active dummy trench and the double-layer active trench are adjacent is longer than the length of a region in which the double-layer active dummy trench and the double-layer active trench are not adjacent in the full length of the double-layer active dummy trench and the full length of the double-layer active trench in the horizontal direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device in which conduction is controlled by a gate signal. BACKGROUND

[0002] In the past, a semiconductor device provided with a double-layer active dummy trench having an upper layer electrode having an upper layer of a gate potential and a lower layer electrode having a lower layer of a potential other than the gate potential has been disclosed (for example, refer to Patent Documents 1 to 5).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-12813

[0004] Patent Document 2: Japanese Patent Application Publication No. 2022-145318

[0005] Patent Document 3: Japanese Patent Application Publication No. 2021-184443

[0006] Patent Document 4: Japanese Patent Application Publication No. 2021-150538

[0007] Patent Document 5: Japanese Patent Application Publication No. 2023-37881

[0008] In the case where the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor), a Cgc / Cge as a gate capacitance ratio is greatly reduced to enable low noise and low switching loss, but an N+ layer cannot be formed around the lower layer electrode in the double-layer active dummy trench. Therefore, a potential barrier of the N+ layer that accumulates holes injected from the back surface side of the semiconductor on the surface side cannot be formed, and conductivity modulation cannot be promoted, and thus there is an issue unique to the IGBT in which an emitter-collector saturation voltage V CE (sat) increases. Here, Cgc is a gate electrode-collector electrode capacitance, and Cge is a gate electrode-emitter electrode capacitance. SUMMARY

[0009] The present disclosure is proposed to solve such a problem, and aims to provide a semiconductor device in which noise is low, switching loss is low, and an increase in an emitter-collector saturation voltage V CE (sat) is suppressed.

[0010] To solve the above problem, the semiconductor device in the present disclosure is provided with:

[0011] a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface;

[0012] at least one double-layer active dummy trench having a first upper electrode as a gate potential in an upper layer and a first lower electrode as an emitter potential in a lower layer inside a trench provided on the first main surface side of the semiconductor substrate;

[0013] at least one double-layer active trench having a second upper electrode as a gate potential in an upper layer and a second lower electrode as a gate potential in a lower layer inside a trench provided on the first main surface side of the semiconductor substrate; and

[0014] a semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate,

[0015] the first upper electrode, the second upper electrode, and the second lower electrode are connected to the same gate pad,

[0016] the double-layer active dummy trench and the double-layer active trench extend in a horizontal direction when viewed in plan,

[0017] of the total length in the horizontal direction of the double-layer active dummy trench and the double-layer active trench, the length of the region where the double-layer active dummy trench and the double-layer active trench are adjacent is longer than the length of the region where the double-layer active dummy trench and the double-layer active trench are not adjacent.

[0018] According to the present disclosure, noise is low and switching loss is low, and an increase in an emitter-collector saturation voltage V CE (sat) can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a cross-sectional view of a semiconductor device according to Embodiment 1.

[0020] Figure 2 is a plan view of the semiconductor device according to Embodiment 1.

[0021] Figure 3 is an enlarged view of a part of Figure 2 .

[0022] Figure 4 is a cross-sectional view of a semiconductor device according to Modified Example 1.

[0023] Figure 5 is a cross-sectional view of a semiconductor device according to Modified Example 2.

[0024] Figure 6 is a cross-sectional view of a semiconductor device according to Modified Example 6.

[0025] Figure 7 is a cross-sectional view of a semiconductor device according to Modified Example 7.

[0026] Figure 8is a sectional view of a semiconductor device according to Modification 8.

[0027] Figure 9 is a sectional view of a semiconductor device according to Modification 9.

[0028] Figure 10 is a sectional view of a semiconductor device according to Modification 10.

[0029] Figure 11 is a sectional view of a semiconductor device according to Modification 11.

[0030] Figure 12 is a sectional view of a semiconductor device according to Modification 12.

[0031] Figure 13 is a sectional view of a semiconductor device according to Modification 13.

[0032] Figure 14 is a sectional view of a semiconductor device according to Modification 14.

[0033] Figure 15 is a sectional view of a semiconductor device according to Modification 15.

[0034] Figure 16 is a sectional view of a semiconductor device according to Modification 18.

[0035] Figure 17 is a sectional view of a semiconductor device according to Modification 19.

[0036] Explanation of Reference Numerals:

[0037] 1...drift layer; 2...base layer; 3...emitter layer; 4...contact layer; 5...buffer layer; 6...collector layer; 7...double-layer dummy trench; 8...first upper electrode; 9...first lower electrode; 10...first oxide film; 11...double-layer active trench; 12...second upper electrode; 13...second lower electrode; 14...second oxide film; 15...element region; 16...gate pad; 17...gate wiring region; 18...terminal region; 19...adjacent region; 20...non-adjacent region; 21...carrier accumulation layer; 22...first portion; 23...second portion; 24...first trench group; 25...second trench group; 26...single-layer dummy trench; 27...dummy electrode; 28...dummy oxide film. DETAILED DESCRIPTION

[0038] <Embodiment 1>

[0039] Hereinafter, a semiconductor device according to Embodiment 1 will be described with reference to the drawings. The semiconductor device is an IGBT. Further, the same reference numerals are sometimes attached to the same or corresponding constituent elements and repeated description is omitted. In the following description, N and P represent the conduction type of a semiconductor. In the present disclosure, the first conduction type is set to N type and the second conduction type is set to P type. The above conduction types can be reversed.

[0040] Figure 1 is a sectional view of the semiconductor device according to Embodiment 1. In Figure 1 , the semiconductor substrate is a range from the emitter layer 3 and the contact layer 4 to the collector layer 6. In Figure 1 , the upper end of the emitter layer 3 and the contact layer 4 is referred to as the first main surface of the semiconductor substrate, and the lower end of the collector layer 6 is referred to as the second main surface of the semiconductor substrate. The first main surface and the second main surface are opposed to each other.

[0041] As shown in Figure 1 , the base layer 2 of P type is provided on the first main surface side of the drift layer 1 of N type. The emitter layer 3 of N+ type and the contact layer 4 of P+ type are provided on the first main surface side of the base layer 2.

[0042] At least one double-layer active dummy trench 7 that reaches the drift layer 1 through the emitter layer 3 and the base layer 2 is provided in the semiconductor substrate. The double-layer active dummy trench 7 has, in the inside of the trench provided on the first main surface side of the semiconductor substrate, the first upper layer electrode 8 as a gate potential in the upper layer, and the first lower layer electrode 9 as an emitter potential in the lower layer.

[0043] At least one double-layer active trench 11 that reaches the drift layer 1 through the emitter layer 3 and the base layer 2 is provided in the semiconductor substrate. The double-layer active trench 11 has, in the inside of the trench provided on the first main surface side of the semiconductor substrate, the second upper layer electrode 12 as a gate potential in the upper layer, and the second lower layer electrode 13 as a gate potential in the lower layer.

[0044] The buffer layer 5 of N type having a higher impurity concentration than the N type of the drift layer 1 is provided on the second main surface side of the drift layer 1. The collector layer 6 (semiconductor layer) of P type is provided on the second main surface side of the buffer layer 5.

[0045] Figure 2 is a plan view of the semiconductor device according to Embodiment 1. In addition, Figure 3 is Figure 2 , an enlarged view of the region A.

[0046] As shown in Figure 2 , in the element region 15, the double-layer active dummy trench 7 and the double-layer active trench 11 extend in the horizontal direction. In Figure 2In the embodiment, an example in which the double-layer active dummy trench 7 and the double-layer active trench 11 are arranged in this order in the vertical direction with respect to the horizontal direction is shown, but the present application is not limited to this. The double-layer active dummy trench 7 and the double-layer active trench 11 can be arranged as appropriate according to necessity.

[0047] As shown in FIG. 1, the double-layer active dummy trench 7 and the double-layer active trench 11 are arranged in this order in the vertical direction with respect to the horizontal direction. Figure 3 As shown in FIG. 1, the length of the region 19 in which the double-layer active dummy trench 7 and the double-layer active trench 11 are adjacent (the total length of the lengths of the two adjacent regions 19 in the horizontal direction) is longer than the length of the region 20 in which the double-layer active dummy trench 7 and the double-layer active trench 11 are not adjacent (the length of the region 20 in the horizontal direction) in the entire length of the double-layer active dummy trench 7 and the double-layer active trench 11 in the horizontal direction (the length between the two ends of the double-layer active dummy trench 7 and the double-layer active trench 11).

[0048] The gate pad 16 is provided in the element region 15. The first upper electrode 8 of the double-layer active dummy trench 7 and the second upper electrode 12 and the second lower electrode 13 of the double-layer active trench 11 are connected to the gate pad 16.

[0049] The gate wiring region 17 is provided so as to surround the element region 15 and is connected to the gate pad 16. The terminal region 18 is provided so as to surround the gate wiring region 17.

[0050] According to Embodiment 1, the N+ layer is formed around the second lower electrode 13 in the double-layer active trench 11. Therefore, the effect of low noise and low switching loss can be obtained by providing the double-layer active dummy trench 7, and the increase in the emitter-collector saturation voltage V CE (sat) can be suppressed.

[0051] In addition, by arranging the double-layer active dummy trench 7 and the double-layer active trench 11 in the horizontal direction, the region 19 in which the double-layer active dummy trench 7 and the double-layer active trench 11 are adjacent can be provided at high density. Therefore, the weakness of the reduction in the carrier accumulation in the double-layer active dummy trench 7 can be compensated for to the maximum extent.

[0052] <Variant 1>

[0053] Figure 4 is a cross-sectional view of the semiconductor device according to Variant 1. As shown in FIG. 2, the double-layer active dummy trench 7 has the first oxide film 10 having a first boundary oxide film between the first upper electrode 8 and the first lower electrode 9. In addition, the double-layer active trench 11 has the second oxide film 14 having a second boundary oxide film between the second upper electrode 12 and the second lower electrode 13. Figure 4

[0054] ​The protruding width Tl is the width between the end surface of the second main surface side of the base layer 2 and the end surface of the second main surface side of the second upper layer electrode 12. The protruding width Tl is larger than the film thickness T2 of the second boundary oxide film.

[0055] Further, in Figure 4 , the relationship between the protruding width Tl of the double-layer active trench 11 and the film thickness T2 of the second boundary oxide film is shown, but the same applies to the double-layer active dummy trench 7. That is, the width between the end surface of the second main surface side of the base layer 2 and the end surface of the second main surface side of the first upper layer electrode 8, that is, the protruding width, is larger than the film thickness of the first boundary oxide film.

[0056] According to Modification 1, by making the protruding width of each of the double-layer active dummy trench 7 and the double-layer active trench 11 longer, the carrier accumulation effect can be improved. In particular, by making the protruding width in the double-layer active dummy trench 7 longer, the carrier accumulation effect can be improved.

[0057] Further, in the case of the double-layer active trench 11 as shown in Figure 4 , the film thickness of the second lower layer oxide film covering the second lower layer electrode 13 is thicker than the film thickness of the second upper layer oxide film covering the second upper layer electrode 12, by making the protruding width Tl of the double-layer active trench 11 longer, the increase in the emitter-collector saturation voltage V CE (sat) can be suppressed. This is because the area to which the second upper layer oxide film with a thin film thickness protrudes increases, and the N+ layer is easily formed.

[0058] <Modification 2>

[0059] Figure 5 is a cross-sectional view of a semiconductor device according to Modification 2. As shown in Figure 5 , in the semiconductor device according to Modification 2, the length T3 between the double-layer active dummy trench 7 and the double-layer active trench 11 is shorter than the length T4 between the end surface of the second main surface side of the base layer 2 and the end surface of the second main surface side of the double-layer active trench 11.

[0060] Further, in Figure 5 , the relationship between the length T3 between the double-layer active dummy trench 7 and the double-layer active trench 11 and the length T4 between the end surface of the second main surface side of the base layer 2 and the end surface of the second main surface side of the double-layer active trench 11 is shown, but the same applies to the double-layer active dummy trench 7. That is, the length T3 between the double-layer active dummy trench 7 and the double-layer active trench 11 is shorter than the length between the end surface of the second main surface side of the base layer 2 and the end surface of the second main surface side of the double-layer active dummy trench 7.

[0061] According to Modification 2, electrons diffused from the channel of the double-layer active dummy trench 7 in the direction of 45° reach the double-layer active trench 11, whereby the carrier accumulation effect based on the double-layer active trench 11 can be improved.

[0062] <Modification 3>

[0063] In the semiconductor device according to Modification 3, the number of the double-layer active trench 11 is the same as the number of the double-layer active dummy trench 7.

[0064] According to Modification 3, the carrier accumulation effect can be improved.

[0065] <Modification 4>

[0066] In the semiconductor device according to Modification 4, the number of the double-layer active trench 11 is more than the number of the double-layer active dummy trench 7. For example, the ratio of the number of the double-layer active trench 11 to the number of the double-layer active dummy trench 7 is 6:4 or more, and preferably 10:1 or less.

[0067] According to Modification 4, the carrier accumulation effect can be improved.

[0068] <Modification 5>

[0069] In the semiconductor device according to Modification 5, the number of the double-layer active trench 11 is less than the number of the double-layer active dummy trench 7. For example, the ratio of the number of the double-layer active trench 11 to the number of the double-layer active dummy trench 7 is 1:10 or more and 4:6 or less.

[0070] According to Modification 5, by increasing the number of the double-layer active dummy trench 7, reduction in switching loss and reduction in DC (Direct Current) loss can be both achieved. Here, the DC loss refers to a loss generated by the resistance of a device when current passes through the device.

[0071] <Modification 6>

[0072] Figure 6 is a cross-sectional view of a semiconductor device according to Modification 6. As shown in Figure 6 the semiconductor device according to Modification 6 further includes a carrier accumulation layer 21. The carrier accumulation layer 21 is provided on the side of the first main surface of the drift layer 1.

[0073] According to Modification 6, by providing the carrier accumulation layer 21, the carrier accumulation effect can be improved. In addition, increase in the emitter-collector saturation voltage V CE (sat) between the emitter and the collector can be suppressed more than in Embodiment 1 and Modifications 1 to 5.

[0074] The carrier accumulation layer 21 in Modification 6 can also be applied to Embodiment 1 and the other modifications.

[0075] <Modification 7>

[0076] Figure 7 is a sectional view of a semiconductor device according to Modification 7. As shown in Figure 7 , in the double-layer active dummy trench 7, the first oxide film 10 has a first upper layer oxide film covering the first upper layer electrode 8 and a first lower layer oxide film covering the first lower layer electrode 9. Also, in the double-layer active trench 11, the second oxide film 14 has a second upper layer oxide film covering the second upper layer electrode 12 and a second lower layer oxide film covering the second lower layer electrode 13.

[0077] In the double-layer active trench 11, the film thickness T5 of the second lower layer oxide film is thicker than the film thickness T6 of the second upper layer oxide film.

[0078] Further, although the relationship between the film thickness T5 of the second lower layer oxide film and the film thickness T6 of the second upper layer oxide film is shown in Figure 7 , the same applies to the double-layer active dummy trench 7. That is, the film thickness of the first lower layer oxide film is thicker than the film thickness of the first upper layer oxide film.

[0079] According to Modification 7, by thickening the film thickness of the second lower layer oxide film of the double-layer active trench 11, an increase in switching loss due to an increase in Cgc can be suppressed.

[0080] Also, by making the film thickness of the first lower layer oxide film thicker than the film thickness of the first upper layer oxide film, the insulation between the first upper layer electrode 8 and the first lower layer electrode 9 is improved, and the gate reliability of TDDB (Time Dependent Dielectric Breakdown) and the like is improved. By making the film thickness of the second lower layer oxide film thicker than the film thickness of the second upper layer oxide film, the same effect can be obtained.

[0081] <Modification 8>

[0082] Figure 8 is a sectional view of a semiconductor device according to Modification 8. As shown in Figure 8 , in the double-layer active trench 11, the length T7 in the depth direction of the second lower layer electrode 13 is longer than the length T8 in the depth direction of the second upper layer electrode 12. As a result, the area of the second upper layer electrode 12 covered by the second upper layer oxide film which is thin in film thickness becomes narrow.

[0083] Also, in the double-layer active dummy trench 7, the length in the depth direction of the first lower layer electrode 9 is longer than the length in the depth direction of the first upper layer electrode 8. As a result, the Cgc connection area of the first upper layer electrode 8 becomes narrow.

[0084] According to Modification 8, an increase in switching loss due to an increase in Cgc can be suppressed.

[0085] <Modification 9>

[0086] Figure 9 is a cross-sectional view of a semiconductor device according to Modification 9. As shown in Figure 9 , in the double-layer active trench 11, the length T7 in the depth direction of the 2nd lower electrode 13 is shorter than the length T8 in the depth direction of the 2nd upper electrode 12. Also, in the double-layer active dummy trench 7, the length in the depth direction of the 1st lower electrode 9 is shorter than the length in the depth direction of the 1st upper electrode 8.

[0087] According to Modification 9, by lengthening the length in the depth direction of the 1st upper electrode 8 of the double-layer active dummy trench 7, the N+ layer is deepened. Also, as shown in Figure 9 , in the case where the 2nd upper oxide film is thin, the region in the double-layer active trench 11 where the 2nd upper oxide film is thin (a region where the N+ layer is easily formed) is also deepened. Therefore, an increase in the emitter-collector saturation voltage V CE (sat) can be suppressed more than in Embodiment 1 and Modifications 1 to 8.

[0088] <Modification 10>

[0089] Figure 10 is a cross-sectional view of a semiconductor device according to Modification 10. As shown in Figure 10 , in the double-layer active trench 11, the 2nd upper electrode 12 has a 1st portion 22 and a 2nd portion 23 which are concave toward the 1st main surface. The 2nd portion 23 is formed so as to protrude from the surface on the 2nd main surface side of the 1st portion. The 2nd lower electrode 13 has a convex portion which is convex on the 1st main surface side.

[0090] Also, in the double-layer active dummy trench 7, the 1st upper electrode 8 has a 1st portion and a 2nd portion which are concave toward the 1st main surface. The 1st lower electrode 9 has a convex portion which is convex on the 1st main surface side.

[0091] According to Modification 10, the N+ layer is formed around the 2nd portion in addition to the 1st portion. Therefore, the N+ layer formed in the double-layer active dummy trench 7 is deepened. Also, as shown in Figure 10 , in the case where the 2nd upper oxide film is thin, the region in the double-layer active trench 11 where the 2nd upper oxide film is thin (a region where the N+ layer is easily formed) is also deepened. Therefore, an increase in the emitter-collector saturation voltage V CE (sat) can be suppressed more than in Embodiment 1 and Modifications 1 to 9.

[0092] <Modification 11>

[0093] Figure 11 is a sectional view of a semiconductor device according to Modification 11. As shown in Figure 11 the semiconductor device according to Modification 11, two or more double-layer active dummy trenches 7 are arranged adjacent to each other, and two or more double-layer active trenches 11 are arranged adjacent to each other. Further, in Figure 11 the example, although two double-layer active dummy trenches 7 and two double-layer active trenches 11 are shown, three or more double-layer active dummy trenches 7 and three or more double-layer active trenches 11 can be provided, respectively.

[0094] In the double-layer active trench 11, an N+ layer is formed around the second lower electrode 13. Therefore, by arranging the double-layer active trench 11 adjacent to each other, the carrier accumulation effect can be improved, and the increase in the emitter-collector saturation voltage V CE (sat) can be suppressed more than in Embodiment 1 and Modifications 1 to 5.

[0095] <Modification 12>

[0096] Figure 12 is a sectional view of a semiconductor device according to Modification 12. As shown in Figure 12 the semiconductor device according to Modification 12 includes a first trench group 24 including the double-layer active dummy trench 7 and the double-layer active trench 11, and a second trench group 25.

[0097] The first trench group 24 includes two double-layer active dummy trenches 7 and two double-layer active trenches 11, and the ratio of the double-layer active trenches 11 is 0.5. Further, the second trench group 25 includes one double-layer active dummy trench 7 and three double-layer active trenches 11, and the ratio of the double-layer active trenches 11 is 0.75. In this way, in the first trench group 24 and the second trench group 25, the ratio of the double-layer active trenches 11 is different.

[0098] Further, in Figure 12 the example, a case where the first trench group 24 and the second trench group 25 each include four trenches is shown, but the present application is not limited thereto. Further, the ratio of the double-layer active trenches 11 included in the first trench group 24 and the second trench group 25 is not limited to Figure 12 the example.

[0099] According to Modification 12, it is possible to arrange the emitter-collector saturation voltage V CE(sat) different regions, the number of double-layer active trenches 11 can be optimized. For example, in the trench group provided in the central portion of the chip where heat is easily concentrated (the central portion of the semiconductor device when viewed from above), the ratio of double-layer active trenches 11 is increased, and in the trench group provided in the outer peripheral portion of the chip where heat is easily dissipated (the outer peripheral portion of the semiconductor device when viewed from above), the ratio of double-layer active trenches 11 is decreased. Thus, the reduction effect of the switching loss due to the double-layer active dummy trench 7 and the reduction effect of the emitter-collector saturation voltage V CE (sat) can be obtained.

[0100] <Variant Example 13>

[0101] Figure 13 is a cross-sectional view of the semiconductor device according to Variant Example 13. As shown in Figure 13 , the semiconductor device according to Variant Example 13 is provided with the second trench group 25 in the central portion and the first trench group 24 in the outer peripheral portion. The ratio of double-layer active trenches 11 in the second trench group 25 is 0.75, and the ratio of double-layer active trenches 11 in the first trench group 24 is 0.5. That is, the ratio of double-layer active trenches 11 in the second trench group 24 provided in the central portion is higher than the ratio of double-layer active trenches 11 in the first trench group 24 provided in the outer peripheral portion.

[0102] In the case where the semiconductor device operates at a low frequency, the number of switching of the semiconductor device is small, and thus the switching loss is small. In such a semiconductor device, it is effective to place more importance on the DC loss than the switching loss. According to Variant Example 13, by making the ratio of double-layer active trenches 11 in the second trench group 25 provided in the central portion higher than the ratio of double-layer active trenches 11 in the first trench group 24 provided in the outer peripheral portion, the DC loss can be reduced.

[0103] <Variant Example 14>

[0104] Figure 14 is a cross-sectional view of the semiconductor device according to Variant Example 14. As shown in Figure 14 , the semiconductor device according to Variant Example 14 is provided with the first trench group 24 in the central portion and the second trench group 25 in the outer peripheral portion. The ratio of double-layer active dummy trenches 7 in the first trench group 24 is 0.5, and the ratio of double-layer active dummy trenches 7 in the second trench group 25 is 0.25. That is, the ratio of double-layer active dummy trenches 7 in the first trench group 24 provided in the central portion is higher than the ratio of double-layer active dummy trenches 7 in the second trench group 25 provided in the outer peripheral portion.

[0105] In a case where the semiconductor device operates at a high frequency, the number of switching of the semiconductor device increases, and thus the switching loss increases. In such a semiconductor device, it is effective to reduce the switching loss. According to Modification 14, by making the ratio of the first trench group 24 provided in the central portion to include the double-layer active dummy trench 7 higher than the ratio of the second trench group 25 provided in the outer peripheral portion to include the double-layer active dummy trench 7, it is possible to reduce the switching loss.

[0106] <Modification 15>

[0107] Figure 15 is a cross-sectional view of the semiconductor device according to Modification 15. As shown in Figure 15 , the semiconductor device according to Modification 15 further includes a single-layer dummy trench 26.

[0108] Specifically, the single-layer dummy trench 26 is provided in the semiconductor substrate so as to penetrate the emitter layer 3 and the base layer 2 and reach the drift layer 1. The single-layer dummy trench 26 has a dummy electrode 27 and a dummy oxide film 28 covering the dummy electrode 27 in the inside of the trench provided on the first main surface side of the semiconductor substrate. The dummy electrode 27 is an emitter potential.

[0109] According to Modification 15, since holes are attracted to the dummy electrode 27 as an emitter potential, the hole density at the interface of the single-layer dummy trench 26 increases. Thus, since it is easy to discharge holes to the emitter electrode, it is possible to reduce the off loss.

[0110] <Modification 16>

[0111] In the semiconductor device according to Modification 16, the number of the single-layer dummy trench 26 is smaller than the number of the double-layer active dummy trench 7.

[0112] According to Modification 16, by reducing the number of the single-layer dummy trench 26, it is possible to suppress an increase in the emitter-collector saturation voltage V CE (sat) due to an increase in the extraction effect of holes.

[0113] <Modification 17>

[0114] In the semiconductor device according to Modification 17, the number of the single-layer dummy trench 26 is smaller than the number of the double-layer active trench 11.

[0115] According to Modification 17, by reducing the number of the single-layer dummy trench 26, it is possible to suppress an increase in the emitter-collector saturation voltage V CE (sat) due to an increase in the extraction effect of holes.

[0116] <Modification 18>

[0117] Figure 16is a sectional view of the semiconductor device according to Modification 18. As shown in Figure 16 In the double-layer active trench 11, the film thickness T5 of the 2nd lower layer oxide film is thinner than the film thickness T6 of the 2nd upper layer oxide film.

[0118] Further, in Figure 16 , although the relationship between the film thickness T5 of the 2nd lower layer oxide film and the film thickness T6 of the 2nd upper layer oxide film is shown, the same applies to the double-layer dummy trench 7. That is, the film thickness of the 1st lower layer oxide film is thinner than the film thickness of the 1st upper layer oxide film.

[0119] According to Modification 18, by making the film thickness of the 2nd lower layer oxide film of the double-layer active trench 11 thinner, the N+ layer formed around the 2nd lower layer electrode 13 in the double-layer active trench 11 can be thickened, and the impurity concentration of the N+ layer can be increased. Therefore, the increase in the emitter-collector saturation voltage V CE (sat) can be suppressed more than in Embodiment 1 and Modifications 1 to 17.

[0120] <Modification 19>

[0121] Figure 17 is a sectional view of the semiconductor device according to Modification 19. As shown in Figure 17 The semiconductor device according to Modification 19 is provided with a 1st resistance Rg1 and a 2nd resistance Rg2.

[0122] The 1st resistance Rg1 is connected between the 1st upper layer electrode 8 and the 2nd upper layer electrode 12 and a gate electrode (not shown). The 2nd resistance Rg2 is connected between the 2nd lower layer electrode 13 and the gate electrode. The resistance value of the 1st resistance Rg1 is larger than the resistance value of the 2nd resistance Rg2.

[0123] According to Modification 19, by making the resistance value of the 1st resistance Rg1 larger than the resistance value of the 2nd resistance Rg2, the charging speed to the 2nd lower layer electrode 13 is increased, the N+ layer formed around the 2nd lower layer electrode 13 can be thickened, and the impurity concentration of the N+ layer can be increased. Therefore, the increase in the emitter-collector saturation voltage V CE (sat) can be suppressed more than in Embodiment 1 and Modifications 1 to 17.

[0124] <Modification 20>

[0125] The semiconductor device according to Modification 20 is an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor).

[0126] Specifically, the semiconductor device according to the modification 20 has an IGBT region and a diode region. For example, a double-layer active trench 11 can be provided in the IGBT region, and a double-layer active dummy trench 7 can be provided in the diode region.

[0127] Further, within the scope of the present disclosure, the embodiments can be appropriately modified or omitted.

[0128] <Notes>

[0129] Hereinafter, each of the modes of the present disclosure will be described as a note.

[0130] (Note 1)

[0131] A semiconductor device, wherein

[0132] comprises:

[0133] a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface;

[0134] at least one double-layer active dummy trench having a first upper electrode as a gate potential in an upper layer and a first lower electrode as an emitter potential in a lower layer inside a trench provided on the first main surface side of the semiconductor substrate;

[0135] at least one double-layer active trench having a second upper electrode as the gate potential in an upper layer and a second lower electrode as the gate potential in a lower layer inside a trench provided on the first main surface side of the semiconductor substrate; and

[0136] a semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate,

[0137] the first upper electrode, the second upper electrode, and the second lower electrode are connected to the same gate pad,

[0138] the double-layer active dummy trench and the double-layer active trench extend in a horizontal direction when viewed from above,

[0139] of the double-layer active dummy trench and the double-layer active trench in the horizontal direction, the length of the region where the double-layer active dummy trench and the double-layer active trench are adjacent is longer than the length of the region where the double-layer active dummy trench and the double-layer active trench are not adjacent.

[0140] (Note 2)

[0141] In the semiconductor device described in Note 1,

[0142] a base layer of the second conductivity type provided on the first main surface side of the semiconductor substrate,

[0143] the double-layer active dummy trench has a first boundary oxide film between the first upper electrode and the first lower electrode,

[0144] the double-layer active trench has a second boundary oxide film between the second upper electrode and the second lower electrode,

[0145] the width between the end surface of the second main surface side of the base layer and the end surface of the second main surface side of the first upper electrode and the second upper electrode, i.e., the overhang width, is larger than the film thickness of the first boundary oxide film and the film thickness of the second boundary oxide film.

[0146] (Note 3)

[0147] the semiconductor device described in Note 1 or 2,

[0148] a base layer of the second conductivity type provided on the first main surface side of the semiconductor substrate,

[0149] the length between the double-layer active dummy trench and the double-layer active trench is shorter than the length between the end surface of the second main surface side of the base layer and the end surface of the second main surface side of the double-layer active dummy trench and the end surface of the second main surface side of the double-layer active trench.

[0150] (Note 4)

[0151] the semiconductor device described in any of Notes 1 to 3,

[0152] the number of the double-layer active trenches is the same as the number of the double-layer active dummy trenches.

[0153] (Note 5)

[0154] the semiconductor device described in any of Notes 1 to 3,

[0155] the number of the double-layer active trenches is larger than the number of the double-layer active dummy trenches.

[0156] (Note 6)

[0157] the semiconductor device described in any of Notes 1 to 3,

[0158] the number of the double-layer active trenches is smaller than the number of the double-layer active dummy trenches.

[0159] (Note 7)

[0160] the semiconductor device described in any of Notes 1 to 6,

[0161] Further provided is a carrier storage layer disposed on the first main surface side of the drift layer.

[0162] (Note 8)

[0163] The semiconductor device according to any one of Notes 1 to 7,

[0164] The double-layer active dummy trench has a first upper layer oxide film covering the first upper layer electrode and a first lower layer oxide film covering the first lower layer electrode,

[0165] The double-layer active trench has a second upper layer oxide film covering the second upper layer electrode and a second lower layer oxide film covering the second lower layer electrode,

[0166] The first lower layer oxide film has a film thickness thicker than that of the first upper layer oxide film,

[0167] The second lower layer oxide film has a film thickness thicker than that of the second upper layer oxide film.

[0168] (Note 9)

[0169] The semiconductor device according to any one of Notes 1 to 8,

[0170] The first lower layer electrode has a length in the depth direction longer than that of the first upper layer electrode,

[0171] The second lower layer electrode has a length in the depth direction longer than that of the second upper layer electrode.

[0172] (Note 10)

[0173] The semiconductor device according to any one of Notes 1 to 8,

[0174] The first lower layer electrode has a length in the depth direction shorter than that of the first upper layer electrode,

[0175] The second lower layer electrode has a length in the depth direction shorter than that of the second upper layer electrode.

[0176] (Note 11)

[0177] The semiconductor device according to any one of Notes 1 to 10,

[0178] The first upper layer electrode and the second upper layer electrode each have a first portion and a second portion recessed toward the first main surface.

[0179] (Note 12)

[0180] The semiconductor device according to any one of the above 1 to 11,

[0181] Two or more of the above double-layer active dummy trenches are arranged adjacently,

[0182] Two or more of the above double-layer active trenches are arranged adjacently.

[0183] (Note 13)

[0184] The semiconductor device according to any one of the above 1 to 12,

[0185] The semiconductor device according to any one of the above 1 to 12,

[0186] The ratio of the above double-layer active trenches in each of the above trench groups is different.

[0187] (Note 14)

[0188] The semiconductor device according to Note 13,

[0189] When viewed in plan, the ratio of the above double-layer active trenches is higher in the trench group located on the inner side than in the trench group located on the outer side.

[0190] (Note 15)

[0191] The semiconductor device according to Note 13,

[0192] When viewed in plan, the ratio of the above double-layer active dummy trenches is higher in the trench group located on the inner side than in the trench group located on the outer side.

[0193] (Note 16)

[0194] The semiconductor device according to any one of the above 1 to 15,

[0195] Further comprising at least one single-layer dummy trench having a dummy electrode inside a trench provided on the first main surface side of the semiconductor substrate.

[0196] (Note 17)

[0197] The semiconductor device according to Note 16,

[0198] The number of the above single-layer dummy trenches is smaller than the number of the above double-layer active dummy trenches.

[0199] (Note 18)

[0200] The semiconductor device according to Note 16,

[0201] The number of the above single-layer dummy trenches is smaller than the number of the above double-layer active trenches.

[0202] (Parenthesis 19)

[0203] The semiconductor device according to any one of the above-mentioned Parenthesis 1 to 7 and Parenthesis 9 to 18,

[0204] The above-mentioned double-layer active dummy trench has a first upper layer oxide film covering the above-mentioned first upper layer electrode and a first lower layer oxide film covering the above-mentioned first lower layer electrode,

[0205] The above-mentioned double-layer active trench has a second upper layer oxide film covering the above-mentioned second upper layer electrode and a second lower layer oxide film covering the above-mentioned second lower layer electrode,

[0206] The film thickness of the above-mentioned first lower layer oxide film is thinner than that of the above-mentioned first upper layer oxide film,

[0207] The film thickness of the above-mentioned second lower layer oxide film is thinner than that of the above-mentioned second upper layer oxide film.

[0208] (Parenthesis 20)

[0209] The semiconductor device according to any one of the above-mentioned Parenthesis 1 to 19,

[0210] Further comprising:

[0211] a first resistance connected between the above-mentioned first upper layer electrode and the above-mentioned second upper layer electrode and the gate electrode; and

[0212] a second resistance connected between the above-mentioned second lower layer electrode and the above-mentioned gate electrode,

[0213] The resistance value of the above-mentioned first resistance is larger than that of the above-mentioned second resistance.

[0214] (Parenthesis 21)

[0215] The semiconductor device according to any one of the above-mentioned Parenthesis 1 to 20,

[0216] The above-mentioned semiconductor device is an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor).

Claims

1. A semiconductor device, wherein provided are: a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface; at least one double-layer active dummy trench having a first upper electrode as a gate potential in an upper layer and a first lower electrode as an emitter potential in a lower layer inside a trench provided on the first main surface side of the semiconductor substrate; at least one double-layer active trench having a second upper electrode as the gate potential in an upper layer and a second lower electrode as the gate potential in a lower layer inside a trench provided on the first main surface side of the semiconductor substrate; and a semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate, the first upper electrode, the second upper electrode, and the second lower electrode are connected to the same gate pad, the double-layer active dummy trench and the double-layer active trench extend in a horizontal direction when viewed from above, a length of a region where the double-layer active dummy trench and the double-layer active trench are adjacent is longer than a length of a region where the double-layer active dummy trench and the double-layer active trench are not adjacent in a total length of the double-layer active dummy trench and the double-layer active trench in the horizontal direction.

2. The semiconductor device according to claim 1, wherein a base layer of the second conductivity type provided on the first main surface side of the semiconductor substrate is further provided, the double-layer active dummy trench has a first boundary oxide film between the first upper electrode and the first lower electrode, the double-layer active trench has a second boundary oxide film between the second upper electrode and the second lower electrode, a width, that is, an overhang width, between an end surface of the second main surface side of the base layer and end surfaces of the second main surface side of the first upper electrode and the second upper electrode is larger than a film thickness of the first boundary oxide film and a film thickness of the second boundary oxide film.

3. The semiconductor device according to claim 1 or 2, wherein a base layer of the second conductivity type provided on the first main surface side of the semiconductor substrate is further provided, a length between the double-layer active dummy trench and the double-layer active trench is shorter than a length between an end surface of the second main surface side of the base layer and end surfaces of the second main surface side of the double-layer active dummy trench and the double-layer active trench.

4. The semiconductor device according to any one of claims 1 to 3, wherein a number of the double-layer active trench is the same as a number of the double-layer active dummy trench.

5. The semiconductor device according to any one of claims 1 to 3, wherein a number of the double-layer active trench is more than a number of the double-layer active dummy trench.

6. The semiconductor device according to any one of claims 1 to 3, wherein a number of the double-layer active trench is less than a number of the double-layer active dummy trench.

7. The semiconductor device according to any one of claims 1 to 6, wherein a carrier accumulation layer provided on the first main surface side of the drift layer is further provided. ​ 8. The semiconductor device according to any one of claims 1 to 7, wherein the double-layer active dummy trench has a first upper layer oxide film covering the first upper layer electrode and a first lower layer oxide film covering the first lower layer electrode, the double-layer active trench has a second upper layer oxide film covering the second upper layer electrode and a second lower layer oxide film covering the second lower layer electrode, the first lower layer oxide film has a film thickness thicker than a film thickness of the first upper layer oxide film, the second lower layer oxide film has a film thickness thicker than a film thickness of the second upper layer oxide film.

9. The semiconductor device according to any one of claims 1 to 8, wherein a length in a depth direction of the first lower layer electrode is longer than a length in a depth direction of the first upper layer electrode, a length in a depth direction of the second lower layer electrode is longer than a length in a depth direction of the second upper layer electrode.

10. The semiconductor device according to any one of claims 1 to 8, wherein a length in a depth direction of the first lower layer electrode is shorter than a length in a depth direction of the first upper layer electrode, a length in a depth direction of the second lower layer electrode is shorter than a length in a depth direction of the second upper layer electrode.

11. The semiconductor device according to any one of claims 1 to 10, wherein the first upper layer electrode and the second upper layer electrode each have a first portion and a second portion which are concave toward the first main surface.

12. The semiconductor device according to any one of claims 1 to 11, wherein two or more of the double-layer active dummy trenches are arranged adjacently, two or more of the double-layer active trenches are arranged adjacently.

13. The semiconductor device according to any one of claims 1 to 12, wherein a plurality of trench groups including the double-layer active dummy trench and the double-layer active trench are provided, a ratio of the double-layer active trench in each of the trench groups is different.

14. The semiconductor device according to claim 13, wherein in a plan view, a ratio of the double-layer active dummy trench in the trench group located on an inner side is higher than a ratio of the double-layer active dummy trench in the trench group located on an outer side.

15. The semiconductor device according to claim 13, wherein in a plan view, a ratio of the double-layer active dummy trench in the trench group located on an inner side is higher than a ratio of the double-layer active dummy trench in the trench group located on an outer side.

16. The semiconductor device according to any one of claims 1 to 15, wherein at least one single-layer dummy trench having a dummy electrode inside a trench provided on the first main surface side of the semiconductor substrate is further provided.

17. The semiconductor device according to claim 16, wherein a number of the single-layer dummy trench is less than a number of the double-layer active dummy trench.

18. The semiconductor device according to claim 16, wherein a number of the single-layer dummy trench is less than a number of the double-layer active trench.

19. The semiconductor device according to any one of claims 1 to 7 and claims 9 to 18, wherein the double-layer active dummy trench has a first upper layer oxide film covering the first upper layer electrode and a first lower layer oxide film covering the first lower layer electrode, The double-layer active trench has a second upper layer oxide film covering the second upper layer electrode and a second lower layer oxide film covering the second lower layer electrode, The first lower layer oxide film has a film thickness thinner than that of the first upper layer oxide film, The second lower layer oxide film has a film thickness thinner than that of the second upper layer oxide film.

20. The semiconductor device according to any one of Claims 1 to 19, wherein Further comprising: a first resistor connected between the first upper layer electrode and the gate electrode and the second upper layer electrode; and a second resistor connected between the second lower layer electrode and the gate electrode, The first resistor has a resistance value larger than that of the second resistor.

21. The semiconductor device according to any one of Claims 1 to 20, wherein The semiconductor device is an RC-IGBT.

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