Insulated gate bipolar transistor device
By designing multiple overlapping gate wiring patterns on the surface of the IGBT device, the problem of uneven electric field distribution is solved, thereby improving the stability and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-10
AI Technical Summary
IGBT multi-gate devices are prone to uneven electric field distribution under different gate states, which leads to a decrease in device reliability.
The gate wiring patterns of multiple gate structures are designed and distributed on the surface of the IGBT device, so that the wiring pattern of each gate structure partially overlaps with the wiring pattern of other gate structures and occupies most of the surface area, ensuring a uniform electric field distribution.
By uniformly distributing the electric field, the stability and reliability of IGBT devices are improved, current fluctuations are reduced, and the lifespan of the devices is extended.
Smart Images
Figure CN121645922A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and in particular to an insulated gate bipolar transistor device. Background Technology
[0002] An IGBT (Insulated Gate Bipolar Transistor) is a three-terminal semiconductor switching device used in various electronic devices to achieve efficient and fast switching. To improve IGBT performance, the single-gate structure has been modified to a multi-gate structure. When multiple gates are connected in series and controlled together, the control area can be expanded and the electric field distribution optimized; when multiple gates are connected in parallel and controlled individually, flexible device control can be achieved, such as full conduction, partial conduction, or even partial reversal.
[0003] In related technologies, the wiring distribution of IGBTs with multiple gates can easily lead to an eccentric electric field distribution when two gates are connected in parallel and controlled separately, with one gate in the on state and the other in the off state. The side in the on state needs higher withstand voltage performance, which can easily lead to a decrease in the reliability of IGBTs in the long term. Summary of the Invention
[0004] This application provides an insulated gate bipolar transistor (IGBT) device that can alleviate the problem of uneven electric field distribution caused when the IGBT device has multiple gates and each gate is individually controlled to be in a different state of being on or off.
[0005] To address the aforementioned technical problems, this application provides an Insulated Gate Bipolar Transistor (IGBT) device, comprising: a semiconductor substrate including a device region for forming the IGBT device; a plurality of gate structures located on one side of a first surface of the device region; wherein each gate structure includes a gate pad and a gate wiring pattern, the gate wiring pattern being electrically connected to a corresponding gate pad, and the gate wiring pattern of each gate structure having a distribution area on the first surface, the distribution area of each gate wiring pattern at least partially overlapping the distribution areas of the gate wiring patterns of other gate structures to form an overlapping area; wherein the distribution area of the gate wiring pattern of each gate structure is a minimum rectangular region surrounding the gate wiring pattern.
[0006] In some embodiments, the area of the distribution region of each gate wiring pattern on the first surface accounts for more than 50% of the area of the first surface of the device region.
[0007] In some embodiments, the area of the distribution region of each gate wiring pattern on the first surface accounts for more than 70% of the area of the first surface of the device region.
[0008] In some embodiments, each of the gate wiring patterns includes at least one gate wiring, and the minimum vertical distance between any two adjacent gate wirings is greater than or equal to 0.8 μm.
[0009] In some embodiments, the gate wiring pattern of each gate structure does not intersect with or connect to the gate wiring patterns of other gate structures; each gate wiring pattern includes a first sub-wiring pattern located in the overlapping region, the first sub-wiring pattern including one or more first gate wirings, and the first gate wirings of the plurality of gate wiring patterns are alternately arranged in the overlapping region.
[0010] In some embodiments, the plurality of gate structures include a first gate structure and a second gate structure, the first gate structure including a first gate pad and a first gate wiring pattern, and the second gate structure including a second gate pad and a second gate wiring pattern; the first gate pad is located on a first side of the first surface, and the second gate pad is located on a second side of the first surface, wherein the first side and the second side are spaced apart along a first direction and opposite to each other; the overlapping region is located between the first gate pad and the second gate pad.
[0011] In some embodiments, each of the first gate wiring pattern and the second gate wiring pattern includes a back comb wiring and a toothed comb wiring connected to the back comb wiring, wherein the toothed comb wiring of the first gate wiring pattern and the toothed comb wiring of the second gate wiring pattern are arranged alternately to each other.
[0012] In some embodiments, each of the first gate wiring pattern and the second gate wiring pattern includes a second sub-wiring pattern located on one side or opposite sides of the corresponding gate pad along the second direction.
[0013] In some embodiments, the first gate wiring pattern includes a first spiral wiring pattern that extends spirally from the first gate pad from the periphery of the first surface to the center of the first surface; the second gate wiring pattern includes a second spiral wiring pattern that extends spirally from the second gate pad from the periphery of the first surface to the center of the first surface; and in the overlapping region, the first spiral wiring pattern and the second spiral wiring pattern are arranged alternately.
[0014] In some embodiments, the gate pads of a plurality of gate structures are located on a first side of the first surface, and the gate wiring pattern of each gate structure extends meanderingly from the corresponding gate pad to a second side of the first surface; wherein the first side and the second side are spaced apart along a first direction and are opposite to each other.
[0015] In some embodiments, the IGBT device further includes an emitter pad and a collector pad, the emitter pad being located on the side of the device region away from the first surface, and the collector pad being located on a second surface of the device region, the second surface being opposite to the first surface.
[0016] Some embodiments of this application provide an insulated-gate bipolar transistor (IGBT) device comprising: a semiconductor substrate including a device region for forming the IGBT device; a plurality of gate structures located on one side of a first surface of the device region; wherein each gate structure includes a gate pad and a gate wiring pattern, the gate wiring pattern being electrically connected to a corresponding gate pad, and the gate wiring pattern of each gate structure having a distribution area on the first surface, the distribution area of each gate wiring pattern at least partially overlapping the distribution areas of the gate wiring patterns of other gate structures to form an overlapping area; wherein the distribution area of the gate wiring pattern of each gate structure is a minimum rectangular area surrounding the gate wiring pattern. This can alleviate the problem of electric field bias or electric field imbalance caused when an IGBT device has multiple gates, and the multiple gates are individually controlled to be in different on or off states. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 A side cross-sectional view of an insulated gate bipolar transistor device provided in some embodiments of this application; Figure 2 A top view schematic diagram of a multi-gate insulated-gate bipolar transistor provided in the first embodiment of this application; Figure 3 A top view schematic diagram of a multi-gate insulated-gate bipolar transistor provided in the second embodiment of this application; Figure 4 This is a top view schematic diagram of a multi-gate insulated-gate bipolar transistor provided in the third embodiment of this application. Detailed Implementation
[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0019] The terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0020] In the embodiments of this application, all directional indicators (such as up, down, left, right, front, back, top, bottom, etc.) are only used to explain the relative positional relationship and movement of each component in a specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0021] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.
[0022] Unless otherwise defined, the term "approximately" as used in this application can be understood, in relation to numerical quantities or quantitative relationships, as a range of approximately ±15% of a certain value.
[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0024] In related technologies, the wiring distribution of IGBTs with multiple gates can easily lead to an eccentric electric field distribution when two gates are connected in parallel and controlled separately, with one gate in the on state and the other in the off state. The side in the on state needs higher withstand voltage performance, which can easily lead to a decrease in the reliability of IGBTs in the long term.
[0025] To address the aforementioned technical problems, this application provides an Insulated Gate Bipolar Transistor (IGBT) device. See also... Figures 1-4 , Figure 1 A side cross-sectional view of an insulated gate bipolar transistor device provided in some embodiments of this application; Figure 2 A top view schematic diagram of a multi-gate insulated-gate bipolar transistor provided in the first embodiment of this application; Figure 3 A top view schematic diagram of a multi-gate insulated-gate bipolar transistor provided in the second embodiment of this application; Figure 4 This is a top view schematic diagram of a multi-gate insulated-gate bipolar transistor provided in the third embodiment of this application.
[0026] See Figures 1-4 In some embodiments of this application, the IGBT device 100 includes a semiconductor substrate 1, a plurality of gate structures, emitter pads (not shown in the figure), and collector pads (not shown in the figure). Each gate structure includes a gate pad 21 and a gate wiring pattern 22. The semiconductor substrate 1 includes a device region 11 for forming the IGBT device 100. The device region 11 has a first surface 111 and a second surface 112 that are opposite to each other. The plurality of gate pads 21 and emitter pads are located on one side of the first surface 111 of the IGBT device 100, and the collector pads are located on the second surface 112.
[0027] In some embodiments, the IGBT device 100 has two gate structures. In some embodiments, the IGBT device 100 has three gate structures. In other embodiments, the IGBT device 100 may also have other numbers of gate structures, such as four, five, six, etc.
[0028] In one embodiment, the gate pad 21, emitter pad, and collector pad are made of aluminum.
[0029] In some embodiments, the gate structure further includes a device gate 26. In one embodiment, the gate wiring pattern 22 and the device gate 26 are made of polysilicon, formed by depositing polysilicon and etching. The device gate 26 is, for example, a planar gate or a... Figure 1 The trench gate is shown. The device gate 26 is connected to the gate pad 21 via the gate wiring pattern 22. Specifically, an interlayer dielectric layer 3 and metal interconnects (not shown) are formed on the device gate 26 and the gate wiring pattern 22, with the metal interconnects formed in the interlayer dielectric layer 3. The gate pad 21 is formed on the third surface 31 of the interlayer dielectric layer 3 on the side of the interlayer dielectric layer 3 away from the device region 11, and is connected to the gate wiring pattern 22 via the metal interconnects. See also... Figure 1In some embodiments, the semiconductor substrate 1 includes a substrate 4. The IGBT device 100 further includes an emitter region 5, a base region 6, a drift region 7, and a collector region 8 formed in the substrate 4. The emitter region 5 is formed on both sides of the device gate 26. An emitter pad is formed on the interlayer dielectric layer 3, specifically on the third surface 31 of the interlayer dielectric layer 3 on the side of the interlayer dielectric layer 3 away from the device region 11, and is connected to the emitter region 5 via a metal interconnect. The emitter region 5 is located in the base region 6 on the side closer to the first surface 111. The drift region 7 is located in the base region 6 on the side away from the emitter region 5. In some embodiments, the device gate 26 extends through the base region 6 from the first surface 111 into the drift region 7. The collector region 8 is located in the drift region 7 on the side away from the base region 6. A collector pad is formed on the second surface 112 of the collector region 8 on the side of the collector region 8 away from the drift region 7 and is electrically connected to the collector region 8.
[0030] In some embodiments, the IGBT device 100 further includes a buffer 9 located between the drift region 7 and the collector region 8. For example... Figure 1 As shown, in some embodiments, emitter region 5, drift region 7, and buffer region 9 can be configured as the first doping type, and base region 6 and collector region 8 as the second doping type. Specifically, emitter region 5 is an N+ emitter region, base region 6 is a P base region, drift region 7 is an N- drift region, buffer region 9 is an N+ buffer, and collector region 8 is a P+ collector region.
[0031] See Figures 2-4 In some embodiments, the semiconductor substrate 1 further includes an electrostatic discharge (ESD) protection region 12. The ESD protection region 12 is located at the edge of the semiconductor substrate 1 and surrounds the device region 11. This mitigates problems such as electrostatic discharge, high-frequency oscillation, and environmental stress in the IGBT device 100, improving the reliability and lifespan of the IGBT device 100. In some embodiments, the width of the ESD protection region 12 in the direction from the edge of the semiconductor substrate 1 to the center of the semiconductor substrate 1 is 0.8 mm to 1.2 mm, for example, 0.8 mm, 1 mm, 1.1 mm, 1.2 mm, etc.
[0032] See Figures 2-4 Each gate structure of the IGBT device 100 includes a gate pad 21 and a gate wiring pattern 22, with the gate wiring pattern 22 electrically connected to the corresponding gate pad 21. The gate pad 21 is used to establish an electrical connection with an external circuit, thereby applying a voltage to the gate structure through the external circuit to achieve switching control of the transistors in the IGBT device 100.
[0033] Each gate wiring pattern 22 of the IGBT device 100 has a distribution area 221 on the first surface 111. The distribution area 221 of each gate wiring pattern 22 at least partially overlaps with the distribution area 221 of the gate wiring patterns 22 of other gate structures to form an overlapping area 222. This ensures that the gate wiring pattern 22 of each gate structure is distributed over a large portion of the first surface 111. When an external circuit applies a voltage to the corresponding gate structure through the gate pad 21, since the gate wiring pattern 22 is electrically connected to the gate pad 21, the distribution area 221 of each gate wiring pattern 22 is the area where the electric field influences the gate wiring pattern 22. In this way, when each gate structure is in the on state, the electric field it generates can be distributed over a large portion of the device region 11, thereby mitigating the problem of electric field bias caused by multiple gate structures being in different states.
[0034] See Figures 2-4 The distribution area 221 of the gate wiring pattern 22 of each gate structure is the smallest rectangular area surrounding the corresponding gate wiring pattern 22. In order to improve the technical effect of mitigating the electric field deviation of the IGBT device 100, the area of the distribution area 221 of the gate wiring pattern 22 on the first surface 111 of each gate structure accounts for more than 50% of the area of the first surface 111 of the device region 11. For example, the area of the distribution area 221 of the gate wiring pattern 22 of each gate structure can be set to account for 55%, 60%, 70% of the area of the first surface 111, etc.
[0035] In some embodiments, the area of the distribution region 221 of the gate wiring pattern 22 of each gate structure on the first surface 111 may be further set to account for more than 70% of the area of the first surface 111 of the device region 11. For example, the area of the distribution region 221 of the gate wiring pattern 22 of each gate structure may be set to account for 80%, 85%, or 90% of the area of the first surface 111. By setting the distribution region 221 of the gate wiring pattern 22 of each gate structure to account for 50% or even more than 70% of the first surface 111, the gate wiring pattern 22 on the first surface 111 can be more uniformly distributed, which can greatly alleviate the electric field edge problem of the IGBT device 100.
[0036] In some embodiments, the gate wiring pattern 22 of each gate structure is distributed as uniformly as possible within its distribution area 221, and the gate wiring patterns 22 of multiple gate structures are distributed as uniformly as possible on the first surface 111. That is, the density of the gate wiring pattern 22 of each gate structure in each region of the first surface 111 is approximately the same. This further enables the electric field generated by the multiple gate structures of the IGBT device 100 to be distributed as uniformly as possible in most regions of the device region 11, regardless of how the multiple gate structures of the IGBT device 100 are turned on. In other words, the electric field influence on most regions of the device region 11 is similar, thereby further alleviating the problem of electric field bias caused by multiple gate structures being in different states and improving the stability of the device.
[0037] In some embodiments, each gate wiring pattern 22 of a gate structure includes at least one gate wiring, and the minimum vertical distance between any two adjacent gate wirings is greater than or equal to 0.8 μm. For example, the distance between adjacent gate wirings can be set to 0.8 μm, 1 μm, or 1.2 μm, etc. By setting the minimum distance between adjacent wiring patterns, on the one hand, it helps to achieve the most uniform distribution of the gate wiring patterns 22 on the first surface 111; on the other hand, it can reduce the risk of mutual interference of electric fields generated between adjacent wiring patterns and improve the stability of the IGBT device 100. It is understood that two adjacent gate wirings can be two parallel gate wirings or two gate wirings that are spaced apart and perpendicular to each other. In some embodiments, two adjacent gate wirings can belong to different gate wiring patterns 22, or they can both belong to the same gate wiring pattern 22. Figure 2 As shown, in some embodiments, a first distance d1 between two parallel gate lines belonging to different gate wiring patterns 22 may be set to be greater than or equal to 0.8 μm. In some embodiments, a second distance d2 between two perpendicular gate lines belonging to the same gate wiring pattern 22 may be set to be greater than or equal to 0.8 μm. In some embodiments, a third distance d3 between two perpendicular gate lines belonging to different gate wiring patterns 22 may be set to be greater than or equal to 0.8 μm. In some embodiments, to further improve the uniformity of the electric field distribution, the minimum perpendicular distance between any two adjacent gate lines may be set to be equal.
[0038] In some embodiments, to reduce the impact on the switching control function of the IGBT device 100, the gate wiring pattern 22 of each gate structure does not intersect with or connect to the gate wiring patterns 22 of other gate structures. Each gate wiring pattern 22 includes a first sub-wiring pattern 22a located in the overlapping region 222. In some embodiments, the first sub-wiring pattern 22a includes multiple first gate wirings. In other embodiments, the first sub-wiring pattern 22a may also include only one first gate wiring. To further achieve the most uniform distribution of the multiple gate wiring patterns 22 on the first surface 111, the first gate wirings of the multiple gate wiring patterns 22 may be arranged alternately in the overlapping region 222.
[0039] In some embodiments, the first surface 111 has a first side 1111 and a second side 1112 spaced apart along a second direction y and facing away from each other, the second direction y intersecting the first direction x. In some embodiments, the first direction x is perpendicular to the second direction y.
[0040] See Figures 2-3 In some embodiments, the multiple gate structures include a first gate structure 23 and a second gate structure 24. The first gate structure 23 includes a first gate pad 231 and a first gate wiring pattern 232. The second gate structure 24 includes a second gate pad 241 and a second gate wiring pattern 242. The first gate pad 231 is located on a first side 1111 of the first surface 111, and the second gate pad 241 is located on a second side 1112 of the first surface 111. That is, the gate pads 21 of the two gate structures are located on opposite sides of the first surface 111, and the first gate pad 231 and the second gate pad 241 are located on opposite sides of the third surface 31. An overlapping region 222 is located between the first gate pad 231 and the second gate pad 241. The first gate wiring pattern 232 and the second gate wiring pattern 242 are collectively referred to as "gate wiring pattern 22". The gate wiring pattern 22 located in the overlapping region 222 of the first gate wiring pattern 232 and the second gate wiring pattern 242 is the aforementioned "first sub-wiring pattern 22a".
[0041] See Figure 2In the first embodiment provided in this application, in the overlapping region 222, each of the first gate wiring pattern 232 and the second gate wiring pattern 242 includes a back-of-branch wiring 220a and a tooth wiring 220b connected to the back-of-branch wiring 220a. The tooth wiring 220b of the first gate wiring pattern 232 and the tooth wiring 220b of the second gate wiring pattern 242 are arranged alternately. In some embodiments, the tooth wiring 220b of each of the first gate structure 23 and the second gate structure 24 extends toward the other of the first gate structure 23 and the second gate structure 24. By connecting the back-of-branch wiring 220a to the tooth wiring 220b, the extension of the first gate wiring pattern 232 and the second gate wiring pattern 242 in the overlapping region 222 along the second direction y is achieved. By arranging the comb-tooth wiring 220b of the first gate wiring pattern 232 and the comb-tooth wiring 220b of the second gate wiring pattern alternately, multiple gate wiring patterns 22 are distributed as evenly as possible on the first surface 111. This ensures that all wiring patterns are distributed as evenly as possible on the first surface 111, and that the overall electric field of the IGBT device 100 is distributed as evenly as possible when both gate structures are turned on, reducing current fluctuations, improving current stability, and thus improving the stability of the IGBT device 100.
[0042] See Figure 2 In the first embodiment provided in this application, each of the first gate wiring pattern 232 and the second gate wiring pattern 242 includes a second sub-wiring pattern 22b located on opposite sides of the corresponding gate pad 21 along the first direction x. That is, the second sub-wiring pattern 22b is a gate wiring pattern 22 disposed in the area outside the overlapping area 222 in the distribution area 221.
[0043] like Figure 2 As shown, in some embodiments, the first gate pad 231 is disposed on the third surface 31 at the middle position of the first side 1111, and the second gate pad 241 is disposed on the third surface 31 at the middle position of the second side 1112. The second sub-wiring pattern 22b of the first gate wiring pattern 232 is disposed on both sides of the first gate pad 231 along the first direction x, and the second sub-wiring pattern 22b of the second gate wiring pattern 242 is disposed on both sides of the second gate pad 241 along the first direction x.
[0044] In other embodiments, the first gate pad 231 and the second gate pad 241 may be located at the edges of the first side 1111 and the second side 1112 of the third surface 31, respectively, with the corresponding second sub-wiring pattern 22b located on opposite sides along the first direction x. By setting the second sub-wiring pattern 22b on both sides of the gate pad 21 on the first surface 111, the area of the wiring distribution is larger, which is beneficial for the gate wiring pattern 22 to be distributed as evenly as possible on the first surface 111.
[0045] like Figure 2 As shown, in some embodiments, the second sub-wiring pattern 22b is in the shape of a fence to extend the second sub-wiring pattern 22b in the first direction x and the second direction y respectively, so that the second sub-wiring pattern 22b is distributed as evenly as possible in the region outside the overlapping region 222 in the distribution region 221, thereby making the electric field generated when a certain gate structure is turned on as evenly distributed as possible, and improving the stability of the device.
[0046] See Figure 3 In the second embodiment provided in this application, the first gate wiring pattern 232 includes a first spiral wiring pattern that extends spirally from the periphery of the first surface 111 to the center of the first surface 111 from the first gate pad 231. The second gate wiring pattern 242 includes a second spiral wiring pattern that extends spirally from the periphery of the first surface 111 to the center of the first surface 111 from the second gate pad 241. In the overlapping region 222, the first spiral wiring pattern and the second spiral wiring pattern are arranged alternately. By setting the first gate wiring pattern 232 and the second gate wiring pattern 242 to a spiral shape, the area of the overlapping region 222 can be increased, and the uniformity of the gate wiring pattern 22 on the first surface 111 can be improved. This results in a more uniform electric field distribution when a certain gate structure is turned on, thereby improving the stability of the device.
[0047] like Figure 3As shown, in some embodiments, the first spiral wiring pattern and the second spiral wiring pattern are formed by a series of mutually perpendicular straight lines connected sequentially. In other embodiments, the first spiral wiring pattern and the second spiral wiring pattern may also be set as continuously spiraling curves, which is not limited here. In some embodiments, the first gate pad 231 is disposed at the middle position of the first side 1111 on the first surface 111, and the second gate pad 241 is disposed at the middle position of the second side 1112 on the first surface 111, that is, the first gate pad 231 is disposed at the middle position of the first side 1111 on the third surface 31, and the second gate pad 241 is disposed at the middle position of the second side 1112 on the third surface 31. This facilitates the first gate wiring pattern 232 and the second gate wiring pattern 242 to be distributed as uniformly as possible on the first surface 111, further improving the uniformity of the electric field distribution, and thus improving the stability of the IGBT device 100. In other embodiments, the first gate pad 231 may be located on the first side 1111 near the edge of the first surface 111, and the second gate pad 241 may be located on the second side 1112 near the edge of the first surface 111. That is, the first gate pad 231 may be located on the first side 1111 near the edge of the third surface 31, and the second gate pad 241 may be located on the second side 1112 near the edge of the third surface 31.
[0048] In some embodiments, the gate pads 21 of the plurality of gate structures of the IGBT device 100 are all located on the first side 1111 of the first surface 111, that is, the plurality of gate pads 21 are all located on the first side 1111 of the third surface 31, and the gate wiring pattern 22 of each gate structure extends meanderingly from the corresponding gate pad 21 from the first side 1111 of the first surface 111 to the second side 1112. The overlapping region 222 is located on the side of the gate pads 21 of the plurality of gate structures away from the first side 1111. Similarly, in the overlapping region 222, the gate wiring patterns 22 of the plurality of gate structures are arranged alternately. By setting multiple gate pads 21 of the IGBT device 100 on the same side of the third surface 31, and extending the overlapping area 222 to the other side of the first surface 111, when the IGBT device 100 is provided with three or more gate structures, multiple corresponding gate wiring patterns 22 can be alternately set, thereby improving the uniformity of multiple gate wiring patterns 22 in the device region 11, and further improving the uniformity of the electric field distribution of the IGBT device 100.
[0049] In some embodiments, see Figure 4In the third embodiment provided in this application, the IGBT device 100 is provided with three gate structures, namely, a first gate structure 23, a second gate structure 24, and a third gate structure 25. The first gate structure 23 includes a first gate pad 231 and a first gate wiring pattern 232, the second gate structure 24 includes a second gate pad 241 and a second gate wiring pattern 242, and the third gate structure 25 includes a third gate pad 251 and a third gate wiring pattern 252. The first gate wiring pattern 232, the second gate wiring pattern 242, and the third gate wiring pattern 253 are collectively referred to as "gate wiring pattern 22".
[0050] like Figure 4 As shown, the first gate pad 231, the second gate pad 241, and the third gate pad 251 are spaced apart on the first side 1111 of the first surface 111, that is, the first gate pad 231, the second gate pad 241, and the third gate pad 251 are spaced apart on the first side 1111 of the third surface 31. In other embodiments, the gate pads 21 of multiple gate structures can also be disposed on other sides, as long as all the gate pads 21 are disposed on the same side. In some embodiments, the first gate pad 231, the second gate pad 241, and the third gate pad 251 are respectively disposed at three equal divisions of the first side 1111 of the first surface 111, that is, the first gate pad 231, the second gate pad 241, and the third gate pad 251 are respectively disposed at three equal divisions of the first side 1111 of the third surface 31. In other embodiments, the first gate pad 231, the second gate pad 241, and the third gate pad 251 may also be located at other positions on the first side 1111 of the third surface 31, without limitation.
[0051] See also Figure 4 In some embodiments, the first gate wiring pattern 232 includes a continuous first "S"-shaped wiring pattern, the second gate wiring pattern 242 includes a continuous second "S"-shaped wiring pattern, and the third gate wiring pattern 252 includes multiple continuous third "S"-shaped wiring patterns. The first, second, and third "S"-shaped wiring patterns all extend to the second side 1112 of the first surface 111 and extend to the edge of the first surface 111 in the second direction y. This arrangement of "S"-shaped wiring patterns allows multiple gate wiring patterns 22 to be distributed over a large portion of the device region 11 when the IGBT device 100 has three or more gate structures, thereby further improving the uniformity of the electric field distribution in the IGBT device 100 and enhancing the device's stability.
[0052] The IGBT device 100 provided in some embodiments of this application includes: a semiconductor substrate 1 including a device region 11 for forming the IGBT device 100; a plurality of gate structures located on one side of a first surface 111 of the device region 11; wherein each gate structure includes a gate pad 21 and a gate wiring pattern 22, the gate wiring pattern 22 being electrically connected to a corresponding gate pad 21, and the gate wiring pattern 22 of each gate structure having a distribution area 221 on the first surface 111, the distribution area 221 of each gate wiring pattern 22 at least partially overlapping the distribution areas 221 of the gate wiring patterns 22 of other gate structures to form an overlapping area 222; wherein the distribution area 221 of the gate wiring pattern 22 of each gate structure is a minimum rectangular area surrounding the gate wiring pattern 22. This can alleviate the problem of electric field bias or electric field imbalance caused when the IGBT device 100 is provided with multiple gate structures, and the multiple gate structures are individually controlled to be in different on or off states.
[0053] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.
Claims
1. An Insulated Gate Bipolar Transistor (IGBT) device, characterized by, Comprising: a semiconductor substrate comprising a device region for forming the IGBT device; a plurality of gate structures located at a first surface side of the device region; wherein each of the gate structures comprises a gate pad and a gate wiring pattern electrically connected with the corresponding gate pad, and the gate wiring pattern of each of the gate structures has a distribution area on the first surface, and the distribution area of each of the gate wiring patterns at least partially overlaps with the distribution area of the gate wiring pattern of other gate structures to form an overlapping area; wherein the distribution area of the gate wiring pattern of each of the gate structures is a minimum rectangular area surrounding the gate wiring pattern.
2. The IGBT device according to claim 1, wherein an area of the distribution area of each of the gate wiring patterns on the first surface accounts for more than 50% of an area of the first surface of the device region.
3. The IGBT device according to claim 1, wherein an area of the distribution area of each of the gate wiring patterns on the first surface accounts for more than 70% of an area of the first surface of the device region.
4. The IGBT device of claim 1, wherein, each of the gate wiring patterns comprises at least one gate wiring, and a minimum vertical distance between any two adjacent gate wirings is greater than or equal to 0.8 μm.
5. The IGBT device according to claim 1, wherein the gate wiring pattern of each of the gate structures and the gate wiring pattern of other gate structures do not intersect and connect with each other; each of the gate wiring patterns comprises a first sub-wiring pattern located in the overlapping area, the first sub-wiring pattern comprises one or more first gate wirings, and the first gate wirings of the plurality of gate wiring patterns are alternately arranged in the overlapping area.
6. The IGBT device according to claim 1, wherein the plurality of gate structures comprises a first gate structure and a second gate structure, the first gate structure comprises a first gate pad and a first gate wiring pattern, and the second gate structure comprises a second gate pad and a second gate wiring pattern; the first gate pad is located at a first side on the first surface, and the second gate pad is located at a second side on the first surface, wherein the first side and the second side are spaced apart along a first direction and opposite to each other; the overlapping area is located between the first gate pad and the second gate pad.
7. The IGBT device according to claim 6, wherein each of the first gate wiring pattern and the second gate wiring pattern comprises a back comb wiring and a tooth comb wiring connected with the back comb wiring, and the tooth comb wirings of the first gate wiring pattern and the second gate wiring pattern are alternately arranged with each other.
8. The IGBT device according to claim 6, wherein each of the first gate wiring pattern and the second gate wiring pattern comprises a second sub-wiring pattern located at one side or opposite sides of the corresponding gate pad along a second direction. 9.The IGBT device of claim 6, wherein, the first gate wiring pattern comprises a first spiral wiring pattern spirally extending from a periphery of the first surface to a center of the first surface from the first gate pad; the second gate wiring pattern comprises a second spiral wiring pattern spirally extending from a periphery of the first surface to a center of the first surface from the second gate pad; in the overlapping region, the first spiral wiring pattern and the second spiral wiring pattern are arranged alternately. 10.The IGBT device of claim 1, wherein, gate pads of the plurality of gate structures are located on a first side of the first surface, and the gate wiring pattern of each of the gate structures spirally extends from the corresponding gate pad to a second side of the first surface; wherein the first side and the second side are spaced apart along a first direction and opposite to each other.
11. The IGBT device according to any one of claims 1 to 10, characterized in that, further comprising: an emitter pad located on a side of the device region distal to the first surface, and a collector pad located on a second surface of the device region, the second surface opposite to the first surface.