Polarized super junction field effect transistor, semiconductor laminated structure, and electrical device

Abstract

Provided is a polarized super-junction GaN-based field effect transistor that can be easily normally off without using a complicated circuit. The field effect transistor has: an undoped GaN layer; an Al < x > Ga < 1-x > N layer having an opening; an undoped GaN layer provided on a portion of the undoped GaN layer inside from a sidewall of the opening; the island-shaped Al < y > Ga < 1-y > N layer extends on the Al < x > Ga < 1-x > N layer, the non-doped GaN layer and the non-doped GaN layer; an undoped GaN layer; a p-type GaN layer; a source electrode and a drain electrode on the Al < x > Ga < 1-x > N layer; and a gate electrode on the p-type GaN layer. The undoped GaN layer and the Al < x > Ga < 1-x > N layer have a c-plane orientation, and at least a part of a portion of the Al < y > Ga < 1-y > N layer on the undoped GaN layer has a plane orientation that is a semi-polar plane inclined with respect to the c-plane or a non-polar plane perpendicular to the c-plane.

Description

Technical Field

[0001] This invention relates to a polarized superjunction field-effect transistor, a semiconductor stack-up structure, and an electrical device using the polarized superjunction field-effect transistor. Background Technology

[0002] Previously, polarization super junction (PSJ) GaN-based field-effect transistors (FETs) were known as power transistors (see Patent Documents 1 and 2). These PSJ GaN-based FETs have a polarization super junction region comprising an undoped GaN layer and an Al layer. x Ga 1-x The structure consists of an N-layer and an undoped GaN layer stacked sequentially. This polarized superjunction GaN-based field-effect transistor can achieve high voltage withstand, high output, high efficiency, and high-speed operation, which are difficult to achieve in silicon (Si)-based power transistors.

[0003] The polarized superjunction GaN-based field-effect transistors described in Patent Documents 1 and 2 are mainly so-called normally-on transistors, namely, in the non-operating state (thermal equilibrium state), including the portion directly below the gate electrode, the lower undoped GaN layer and Al... x Ga 1-x A two-dimensional electron gas exists in the undoped GaN layer near the heterojunction between N layers. Therefore, at a gate voltage V... g When the voltage is 0V or in an open circuit state, current flows between the source and drain electrodes when a voltage is applied between them.

[0004] On the other hand, for transistors, most require a so-called fail-safe action, namely, that the transistor is in a cut-off state when the control signal (gate signal) is lost. In the normally-on polarized superjunction GaN field-effect transistors described in Patent Documents 1 and 2, although it is possible to achieve normally-off operation by assembling a cascode circuit or a modified cascode circuit using a low-voltage normally-off SiMOS transistor, this is disadvantageous in that the circuit becomes more complex.

[0005] Further, a normally-off vertical GaN transistor is proposed in which an n-type GaN drift layer, a p-type GaN well layer, and a carbon-doped GaN layer are sequentially stacked on a GaN substrate, a V groove reaching the n-type GaN drift layer is formed in the carbon-doped GaN layer and the p-type GaN well layer, an undoped GaN layer, an undoped AlGaN layer, and a p-type GaN layer are sequentially stacked in a manner to fill the V groove, a source electrode is formed on the outer periphery of these undoped GaN layer, undoped AlGaN layer, and p-type GaN layer, a drain electrode is formed on the back surface of the GaN substrate, and a gate electrode is formed on the p-type GaN layer (see Non-Patent Document 1).

[0006] Patent Document 1: Japanese Patent No. 5828435

[0007] Patent Document 2: Japanese Patent No. 5669119

[0008] Non-Patent Document 1: Daisuke Shibata et al., "1.7 kV / 1.0 mΩcm2 Normally-off Vertical GaN Transistor on GaN substrate with Regrown p-GaN / AlGaN / GaN Semipolar Gate Structure", IEDM 16-248

[0009] Non-Patent Document 2: Doctoral Thesis of National University Corporation Nagoya University, Tomonori Tani, Title "Study on Selective MOVPE Growth of Semipolar / Apolar Nitride Semiconductors on Processed Silicon Substrates" (2012) SUMMARY

[0010] The present application has an object to provide a polarization super junction GaN-based field effect transistor in which a normally-off transistor can be easily realized without using a complicated circuit, and a high-performance electrical device using the polarization super junction GaN-based field effect transistor.

[0011] The present application has an object to provide a semiconductor layer stack suitable for manufacturing a polarization super junction GaN-based field effect transistor in which a normally-off transistor can be easily realized without using a complicated circuit.

[0012] To solve the above problems, the present application is a polarized super junction field effect transistor, wherein the polarized super junction field effect transistor has: a first semiconductor layer; a second semiconductor layer having an opening portion, which is positioned above the first semiconductor layer; a third semiconductor layer, which is positioned on a portion of the first semiconductor layer inside the opening portion from a sidewall of the opening portion; a fourth semiconductor layer having an island-like shape, which is positioned on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion; a fifth semiconductor layer, which is positioned above the fourth semiconductor layer; a sixth semiconductor layer, which is positioned above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; and a gate electrode electrically connected to the sixth semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are III-nitride semiconductor layers, the band gap of the second semiconductor layer and the fourth semiconductor layer is larger than the band gap of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer, the band gap of the first semiconductor layer and the third semiconductor layer is the same as each other, the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers, the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, at least a portion of the portion of the fourth semiconductor layer on the third semiconductor layer has a face orientation that is a semi-polar face inclined with respect to the c-plane or a non-polar face perpendicular to the c-plane.

[0013] The III-nitride semiconductor layer is typically composed of at least one or more III-group elements selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In), and at least one or more V-group elements selected from the group consisting of N (nitrogen), phosphorus (P), and arsenic (As). The III-nitride semiconductor layer is most typically composed of Al p B q Ga 1-p-q-r In r N (wherein 0≤p≤1, 0≤q≤1, 0≤r≤1, 0≤p+q+r<1) and is typically composed of Al p Ga 1-p-r In r N (wherein 0≤p≤1, 0≤r≤1, 0≤p+r<1). Most typically, the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped GaN layers, the second semiconductor layer is an Al p Ga 1-p N layer (for example, 0.17≤p≤0.35), and the fourth semiconductor layer is an Als Ga 1-s N layer (0 < s < p), the sixth semiconductor layer is a p-type GaN layer (also including a case where it is composed of a plurality of layers having different acceptor concentrations) or a p-type GaN layer and a p-type In t Ga 1-t N layer (0 < t < 1). Al p Ga 1-p N layer is typically undoped, but can also be n-type or p-type doped with a donor (n-type impurity) or an acceptor (p-type impurity). Al p Ga 1-p N layer, for example, n-type Al p Ga 1-p N layer. Al s Ga 1-s N layer is also the same as the Al p Ga 1-p N layer. As for the In t Ga 1-t N layer, the In component t and the thickness u are typically selected in a manner so as to substantially satisfy s x u < 0.20 x 5.

[0014] The Group III nitride semiconductor layer has a wurtzite structure. The face orientation of the semi-polar face which becomes inclined with respect to the c-plane is {11-24} (39.1 degrees), {11-22} (58.4 degrees), {11-21} (72.9 degrees), {1-102} (43.2 degrees), {1-101} (62.0 degrees), {2-201} (75.1 degrees), etc. The numbers in () indicate the angle of inclination with respect to the c-plane in the case where the GaN layer is considered as the Group III nitride semiconductor layer. The face orientation of the non-polar face which becomes perpendicular to the c-plane is {11-20}, {1-100}. The {1-102} face is called the r-face, the {11-20} face is called the a-face, and the {1-100} face is called the m-face.

[0015] In a case where at least a part of the portion of the fourth semiconductor layer on the third semiconductor layer has a face orientation that becomes a semipolar face inclined with respect to the c-plane, a polarization electric field of the fourth semiconductor layer of the portion becomes a direction perpendicular to a face (a growth face) of the fourth semiconductor layer, and thus reduction in polarization electric field strength can be achieved. Also, by the inclined structure of the fourth semiconductor layer / third semiconductor layer, at the time of turning off a gate voltage applied to the gate electrode, two-dimensional electron gas can not be formed in at least a part of the third semiconductor layer at a portion near the hetero interface between the third semiconductor layer and the fourth semiconductor layer, and by the rise in gate threshold voltage, it is possible to contribute to the realization of the normally-off of the polarization super junction field effect transistor. The component and the thickness of the fourth semiconductor layer are selected in a manner that two-dimensional electron gas is not formed in at least a part of the third semiconductor layer at a portion near the hetero interface between the third semiconductor layer and the fourth semiconductor layer, in consideration of the effect of the reduction in polarization electric field strength. In a case where at least a part of the portion of the fourth semiconductor layer on the third semiconductor layer has a face orientation that becomes an a-plane face perpendicular to the c-plane, there is no polarization electric field of the fourth semiconductor layer of the portion. Thus, at the time of turning off a gate voltage applied to the gate electrode, two-dimensional electron gas can not be formed in at least a part of the third semiconductor layer at a portion near the hetero interface between the third semiconductor layer and the fourth semiconductor layer, and by the rise in gate threshold voltage, it is possible to contribute to the realization of the normally-off of the polarization super junction field effect transistor.

[0016] Typically, the third semiconductor layer has a trapezoidal cross-sectional shape. In this case, the opening portion of the second semiconductor layer typically has an inverted trapezoidal cross-sectional shape. With respect to the opening portion, the one-side third semiconductor layer and the opposite-side third semiconductor layer are sometimes provided in a manner that they contact each other at a central portion of the opening portion. In this case, the first semiconductor layer does not expose inside the opening portion.

[0017] In the polarization super junction field effect transistor, a two-dimensional electron gas is formed in the first semiconductor layer at a portion near a hetero interface between the first semiconductor layer and the second semiconductor layer, a two-dimensional electron gas is formed or is not formed in the first semiconductor layer at a portion near a hetero interface between the first semiconductor layer and the fourth semiconductor layer, a two-dimensional electron gas is not formed in at least a portion of the third semiconductor layer at a portion near a hetero interface between the third semiconductor layer and the fourth semiconductor layer, an n channel is formed near a hetero interface between the second semiconductor layer and the third semiconductor layer, and a two-dimensional hole gas is locally formed in the fifth semiconductor layer at a portion near a hetero interface between the fifth semiconductor layer and the fourth semiconductor layer. That is, a two-dimensional electron gas is not formed in at least a portion of the third semiconductor layer at a portion near a hetero interface between the third semiconductor layer and the fourth semiconductor layer, and thus, the n channel between the source electrode and the drain electrode is interrupted at the portion. Therefore, the polarization super junction field effect transistor becomes normally off. On the other hand, when a gate voltage is applied to the gate electrode, a two-dimensional electron gas is induced in the third semiconductor layer at a portion near a hetero interface between the third semiconductor layer and the fourth semiconductor layer, and thus, the n channel between the source electrode and the drain electrode is continuously formed.

[0018] Most typically, the polarization super junction field effect transistor is configured as follows.

[0019] That is, the present application is a polarization super junction field effect transistor including: a first undoped GaN layer; an AlxGa1-xN layer having an opening portion, which is disposed above the first undoped GaN layer; a second undoped GaN layer, which is disposed on a portion of the first undoped GaN layer inside the opening portion from a side wall of the opening; an Al yGa1-yN layer having an island shape, which is disposed on the second undoped GaN layer and the first undoped GaN layer inside the opening portion; a third undoped GaN layer, which is disposed above the Al yGa1-yN layer; a p-type GaN layer, which is disposed above the third undoped GaN layer; a source electrode and a drain electrode, which are disposed on the Al yGa1-yN layer; and a gate electrode, which is electrically connected to the p-type GaN layer. x Ga 1-x N layer, wherein 0 < x < 1; a second undoped GaN layer, which is disposed on a portion of the first undoped GaN layer inside the opening portion from a side wall of the opening; an Al y Ga 1-y N layer, which is disposed on the Al x Ga 1-x N layer, the second undoped GaN layer, and the first undoped GaN layer inside the opening portion, wherein y < x; a third undoped GaN layer, which is disposed above the Al y Ga 1-y N layer; a p-type GaN layer, which is disposed above the third undoped GaN layer; a source electrode and a drain electrode, which are disposed on the Al x Ga 1-x N layer; and a gate electrode, which is electrically connected to the p-type GaN layer, the first undoped GaN layer, and the Al x Ga 1-xN layer has a c-plane orientation, and the Al y Ga 1-y At least a portion of the portion on the second undoped GaN layer in the Al

[0020] In the polarization super junction field effect transistor, in the Al y Ga 1-y At least a portion of the portion on the second undoped GaN layer in the Al y Ga 1- y The polarization electric field of the Al y Ga 1-y N layer becomes perpendicular to the face (growth face) of the Al y Ga 1-y The inclined structure of the Al y Ga 1-y N layer / second undoped GaN layer enables at least a portion of the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y The Al composition y and the thickness of the Al y Ga 1-y N layer are selected in a manner that a two-dimensional electron gas is not formed in at least a portion of the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y N layer on the second undoped GaN layer has a face orientation that becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to a c-plane. y Ga 1-y N layer. Thus, at the time of cutoff of a gate voltage applied to the gate electrode, at least a portion of the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y N layer enables a two-dimensional electron gas to be not formed, and contributes to realization of the normally-off of the polarization super junction field effect transistor through an increase in a gate threshold voltage. In addition, the inclination angle dependence of the polarization electric field of the GaN-based semiconductor with respect to the c-axis is described, for example, in Non-Patent Literature 2.

[0021] Typically, the second undoped GaN layer has a trapezoidal cross-sectional shape. In this case, the Al x Ga 1-x N layer has an inverted trapezoidal cross-sectional shape. With respect to the opening portion, the second undoped GaN layer on one side and the second undoped GaN layer on the opposite side are sometimes provided in a manner that they contact each other at a central portion of the opening portion. In this case, the first undoped GaN layer does not emerge inside the opening portion.

[0022] In the polarization super junction field effect transistor, at the time of cutoff of a gate voltage applied to the gate electrode, a two-dimensional electron gas is formed in the first undoped GaN layer at a portion near a heterointerface between the first undoped GaN layer and the Al x Ga 1-x N layer, a two-dimensional electron gas is formed in the first undoped GaN layer at a portion near a heterointerface between the first undoped GaN layer and the Al y Ga 1-y N layer, or a two-dimensional electron gas is not formed, a two-dimensional electron gas is not formed in at least a portion of the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y N layer, an n channel is formed near a heterointerface between the Al x Ga 1-x N layer and the second undoped GaN layer, and a two-dimensional hole gas is locally formed in the third undoped GaN layer at a portion near a heterointerface between the third undoped GaN layer and the Al y Ga 1-y N layer. That is, a two-dimensional electron gas is not formed in at least a portion of the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y N layer, and thus the n channel between the source electrode and the drain electrode is interrupted at the portion. Therefore, the polarization super junction field effect transistor becomes normally off. On the other hand, at the time of turn-on of the gate voltage applied to the gate electrode, a two-dimensional electron gas is induced in the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y N layer, and thus the n channel between the source electrode and the drain electrode is continuously formed. The n channel formed near the heterointerface between the Al x Ga 1-x N layer and the second undoped GaN layer is caused by the following reason: the Al x Ga 1-xWhen opening an N-layer, the sidewalls (etched end faces) of the opening are typically n-shaped.

[0023] Al y Ga 1-y The tilt angle of at least a portion of the portion of the N layer that is on the second undoped GaN layer relative to the c-plane is typically greater than 5 degrees and less than 90 degrees.

[0024] When the second undoped GaN layer has a trapezoidal cross-sectional shape, Al is then applied. y Ga 1-y In the N-layer, the length of the portion extending from the slope of the second undoped GaN layer on one side to the slope of the second undoped GaN layer on the opposite side, relative to the projection of the first undoped GaN layer, in the direction connecting the source and drain electrodes, is denoted as L. r Let L be the length of the projection of the inclined plane of the second undoped GaN layer on one side relative to the first undoped GaN layer in the direction. s1 Let L be the length of the projection of the second undoped GaN layer on the opposite side relative to the first undoped GaN layer in the direction. s2 , will Al y Ga 1-y The tilt angle of at least a portion of the second undoped GaN layer on one side of the N layer relative to the c-plane is set as θ1, and Al y Ga 1-y The tilt angle of at least a portion of the portion of the second undoped GaN layer on the opposite side of the N layer relative to the c-plane is set as θ2, where typically 0.1cosθ1≤2L. s1 / L r ≤1 and 0.1cosθ2≤2L s2 / L r ≤1, but not limited to this. When the second undoped GaN layer on one side and the second undoped GaN layer on the opposite side are arranged such that they are in contact with each other at the center of the opening, L r =L s1 +L s2 Established.

[0025] Further, the present application is a semiconductor stacked structure, wherein the semiconductor stacked structure has: a first semiconductor layer; a second semiconductor layer having an opening portion, which is positioned above the first semiconductor layer; a third semiconductor layer, which is positioned on a part of the first semiconductor layer inside the opening portion from a side wall of the opening portion; and a fourth semiconductor layer having an island shape, which is positioned on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers, a band gap of the second semiconductor layer and the fourth semiconductor layer is larger than a band gap of the first semiconductor layer and the third semiconductor layer, and a band gap of the fourth semiconductor layer is smaller than a band gap of the second semiconductor layer, the band gap of the first semiconductor layer and the third semiconductor layer are the same as each other, the first semiconductor layer and the third semiconductor layer are undoped semiconductor layers, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, and at least a part of a portion of the fourth semiconductor layer on the third semiconductor layer has a face orientation which becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to a c-plane.

[0026] Further, the present application is a semiconductor stacked structure, wherein the semiconductor stacked structure has: a first undoped GaN layer; an Al x Ga 1-x N layer having an opening portion, which is positioned above the first undoped GaN layer; a second undoped GaN layer, which is positioned on a part of the first undoped GaN layer inside the opening portion from a side wall of the opening; and an Al y Ga 1-y N layer having an island shape, which is positioned on the Al x Ga 1-x N layer, the second undoped GaN layer, and the first undoped GaN layer inside the opening portion, wherein y x Ga 1-x N layer, the first undoped GaN layer, and the Al y Ga 1-y N layer have a c-plane orientation, and at least a part of a portion of the Al

[0027] Further, the present application is an electric device, wherein the electric device has at least one transistor, the transistor is a polarization super junction field effect transistor having: a first semiconductor layer; a second semiconductor layer having an opening portion, which is higher than the first semiconductor layer; a third semiconductor layer, which is provided on a part of the first semiconductor layer inside the opening portion from a side wall of the opening portion; a fourth semiconductor layer having an island-like shape, which is provided extending on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion; a fifth semiconductor layer, which is higher than the fourth semiconductor layer; a sixth semiconductor layer, which is higher than the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; and a gate electrode which is electrically connected to the sixth semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are Group III nitride semiconductor layers, a band gap of the second semiconductor layer and the fourth semiconductor layer is larger than a band gap of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and a band gap of the fourth semiconductor layer is smaller than a band gap of the second semiconductor layer, a band gap of the first semiconductor layer and the third semiconductor layer is the same as each other, the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers, the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, at least a part of a part of the fourth semiconductor layer on the third semiconductor layer has a face orientation which is a semi-polar face inclined with respect to the c-plane or a non-polar face perpendicular to the c-plane.

[0028] Here, the electric device includes substantially all devices using electricity, regardless of use, function, size, and the like, and is, for example, an electronic device, a mobile body, a power device, a construction machine, a machine tool, and the like. The electronic device is a robot, a computer, a game device, a vehicle-mounted device, a home electric appliance (an air conditioner, and the like), an industrial product, a portable telephone, a mobile device, an IT device (a server, and the like), a power conditioner used in a solar power generation system, a power transmission system, and the like. The mobile body is a railway vehicle, an automobile (an electric vehicle, and the like), a two-wheeled vehicle, an airplane, a rocket, a space vehicle, and the like.

[0029] In the application of the electric device, in relation to the above-mentioned other cases, as long as the nature is not violated, it can be described in association with the application of the polarization super junction field effect transistor described above.

[0030] Further, the present application is an electric device, wherein the electric device has at least one transistor, the transistor is a polarization super junction field effect transistor having: a first undoped GaN layer; an Al x Ga 1-x N layer having an opening portion, which is higher than the first undoped GaN layer; a second undoped GaN layer, which is provided on a part of the first undoped GaN layer inside the opening portion from a side wall of the opening; an Al y Ga 1-y N layer having an island shape, which is provided on the second undoped GaN layer and the Al x Ga 1-x N layer, the second undoped GaN layer, and the first undoped GaN layer inside the opening portion, wherein y < x; a third undoped GaN layer, which is higher than the Al y Ga 1-y N layer; a p-type GaN layer, which is higher than the third undoped GaN layer; a source electrode and a drain electrode on the Al x Ga 1-x N layer; and a gate electrode, which is electrically connected to the p-type GaN layer, the first undoped GaN layer, and the Al x Ga 1-x N layer have a c-plane orientation, at least a part of the Al y Ga 1-y N layer on the second undoped GaN layer has a face orientation which becomes a semi-polar plane inclined with respect to the c-plane or a non-polar plane perpendicular to the c-plane.

[0031] In the invention of the electric device, the following can be explained in association with the invention of the above electric device.

[0032] According to the present application, in the third semiconductor layer, at least a part of the third semiconductor layer at a part near a hetero interface between the third semiconductor layer and the fourth semiconductor layer, or in the second undoped GaN layer, at least a part of the second undoped GaN layer at a part near a hetero interface between the second undoped GaN layer and the Al y Ga 1-y N layer, a two-dimensional electron gas is not formed, whereby a normally-off polarization super junction GaN-based field effect transistor can be easily realized without using a complicated circuit, and a high-performance electronic device can be realized using the normally-off polarization super junction GaN-based field effect transistor. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a cross-sectional view showing a polarization super junction GaN-based FET of a first embodiment of the present application.

[0034] Figure 2 is a cross-sectional view showing a state of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-on. y Ga 1-y N layer 15 after being enlarged in part.

[0035] Figure 3 is a cross-sectional view showing a state of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-on. y Ga 1-y N layer 15 after being enlarged in part.

[0036] Figure 4 is a schematic view showing a band diagram in the direction of the single-dot chain line arrow in FIG. 4 along the channel length direction of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-off. Figure 1

[0037] Figure 5 is a schematic view showing a band diagram in the direction of the single-dot chain line arrow in FIG. 4 along the channel length direction of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-on. Figure 1

[0038] Figure 6 is a schematic view showing a band diagram in the direction of the dashed line arrow in FIG. 4 along the channel length direction of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-off. Figure 1

[0039] Figure 7 is a schematic view showing a band diagram in the direction of the dashed line arrow in FIG. 4 along the channel length direction of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-on. Figure 1

[0040] Figure 8 is a cross-sectional view showing a state of the polarization super junction GaN-based FET of the first embodiment of the present application at the time of the gate voltage turn-on.

[0041] Figure 9 is a cross-sectional view for explaining a manufacturing method of the polarization super junction GaN-based FET of the first embodiment of the present application.

[0042] Figure 10 is a cross-sectional view for explaining a manufacturing method of the polarization super junction GaN-based FET of the first embodiment of the present application.

[0043] Figure 11 is a cross-sectional view for explaining a manufacturing method of the polarization super junction GaN-based FET of the first embodiment of the present application.

[0044] ​​​​Figure 12 This is a cross-sectional view illustrating the manufacturing method of a polarized superjunction GaN-based FET according to the first embodiment of the present invention.

[0045] Figure 13 This is a cross-sectional view illustrating the manufacturing method of a polarized superjunction GaN-based FET according to the first embodiment of the present invention.

[0046] Figure 14 This is a cross-sectional view illustrating a polarized superjunction GaN-based FET according to a second embodiment of the present invention.

[0047] Figure 15 This is a cross-sectional view showing a polarized superjunction GaN-based FET according to a third embodiment of the present invention.

[0048] Label Explanation

[0049] 10…substrate; 11…undoped GaN layer; 12…Al x Ga 1-x N layer; 13… opening; 14… undoped GaN layer; 15… Al y Ga 1-y N-layer; 16…undoped GaN layer; 17…p-type GaN layer; 18…gate electrode; 19…source electrode; 20…drain electrode; 21…2DHG; 22…2DEG; 23…n-channel. Detailed Implementation

[0050] The following describes the methods for carrying out the invention (hereinafter referred to as the implementation method).

[0051] <First Implementation>

[0052] [Polarized Superjunction GaN-based FET]

[0053] like Figure 1 As shown, in the polarized superjunction GaN-based FET of the first embodiment, an undoped GaN layer 11 and an Al layer are sequentially stacked on the substrate 10 with a buffer layer (not shown) in between. x Ga 1-x N-layer 12. Undoped GaN layer 11 and Al x Ga 1-x All N layers 12 have a c-plane orientation. The substrate 10 is preferably a substrate for c-plane growth of GaN-based semiconductors, such as a c-plane sapphire substrate, a Si substrate, or a SiC substrate. Alternatively, the substrate 10 may not be present. The buffer layer is, for example, composed of polycrystalline or amorphous GaN, AlN, or AlGaN, as well as an AlGaN / GaN superlattice. x Ga 1-xThe N layer 12 is typically undoped, but can also be n-type or p-type doped with a donor (n-type impurity) or an acceptor (p-type impurity). The Al x Ga 1-x N layer. The Al x Ga 1-x component x and thickness of the N layer 12 are selected in such a manner that a two-dimensional electron gas (2DEG) is formed in the undoped GaN layer 11 at a portion near the heterointerface between the undoped GaN layer 11 and the Al x Ga 1-x N layer 12 at the time of gate voltage cutoff, but x is typically 0.2 ≤ x ≤ 0.3.

[0054] The Al x Ga 1-x N layer 12 is provided with an opening portion 13 reaching the undoped GaN layer 11. This opening portion 13 has an inverted-trapezoidal cross-sectional shape. This opening portion 13 can also stop at the Al x Ga 1-x N layer 12, but can also be provided to a depth reaching the middle of the thickness direction of the undoped GaN layer 11, but in the latter case, the side wall of the opening portion 13 is inclined with respect to the c-plane of the Al Figure 1 plane of the Al x Ga 1-x N layer 12, that is, the c-plane, is inclined. Specifically, the side wall of the opening portion 13 is inclined, for example, by an angle of 60 degrees or more and less than 90 degrees with respect to the c-plane. An undoped GaN layer 14 is provided on a portion of the undoped GaN layer 11 inside the opening portion 13 from both side walls of the opening portion 13. The undoped GaN layer 14 has a trapezoidal cross-sectional shape, the inclined surface of which is inclined with respect to the c-plane, having a face orientation that becomes a semi-polar plane. The undoped GaN layer 14 is not provided in the central portion of the opening portion 13, and the undoped GaN layer 11 is exposed in the central portion of the opening portion 13. The Al x Ga 1-x N layer 15 (y < x) and an undoped GaN layer 16 are sequentially provided. The Al y Ga 1-y N layer 15 has a face orientation that becomes a semi-polar plane inclined with respect to the c-plane, like the undoped GaN layer 14, on a portion of the undoped GaN layer 14. The Al y Ga 1-y N layer 15 on a portion of the undoped GaN layer 14 has a face orientation that becomes a semi-polar plane inclined with respect to the c-plane, like the undoped GaN layer 14. The Al y Ga 1-y N layer 15 on a portion of the undoped GaN layer 14 has a face orientation that becomes a semi-polar plane inclined with respect to the c-plane, like the undoped GaN layer 14. The Al x Ga 1-xThe portion above the N-layer 12 and the portion above the undoped GaN-layer 11 have a c-plane orientation, and their surfaces are called polar planes. Figure 1 The undoped GaN layer 14 on one side of the opening 13 and the undoped GaN layer 14 on the opposite side are generally asymmetric. Regarding Al... y Ga 1-y The Al composition y and thickness of layer N15 are selected as follows: when the gate voltage is off, in Al y Ga 1-y N layer 15 and Al y Ga 1-y 2DEGs are formed in the undoped GaN layers 11 and 14 near the heterostructure between the undoped GaN layers 11 and 14 at the portion where the N-layer 15 contacts. However, sometimes it is chosen not to form 2DEGs. y is typically 0.15 ≤ y ≤ 0.25.

[0055] In Al y Ga 1-y Al is exposed around the N-layer 15 and the undoped GaN layer 16. x Ga 1-x N-layer 12. A p-type GaN layer 17 is stacked above the opening 13 on the undoped GaN layer 16. Magnesium (Mg) is doped into the p-type GaN layer 17 as a p-type impurity. The p-type GaN layer 17 reflects the underlying Al layer. y Ga 1-y The N-layer 15 and the undoped GaN-layer 16 have a centrally recessed shape.

[0056] A gate electrode 18 is disposed on the p-type GaN layer 17. Regarding the gate electrode 18, in order to make ohmic contact with the p-type GaN layer 17, the gate electrode 18 is formed of a metal with a high work function (e.g., typically nickel (Ni)). The gate electrode 18 may also be composed of a laminated film formed by stacking other metal films on a Ni film. Furthermore, in Al... x Ga 1-x On layer N, 12, regarding Al y Ga 1-y The island-like stacked structure, consisting of an N-layer 15 and an undoped GaN layer 16, has a source electrode 19 on one side and a drain electrode 20 on the opposite side. The source electrode 19 and drain electrode 20 are made of a metal with a low work function (typically, for example, titanium (Ti)), as described later, so that they can interact with the undoped GaN layer 11 and Al... x Ga 1-xThe 2DEG ohmic contact formed in the undoped GaN layer 11 at a portion near the heterointerface between the N layers 12. The source electrode 19 and the drain electrode 20 can also be composed of a laminated film in which an aluminum (Al) film, a nickel (Ni) film, a gold (Au) film, or the like is laminated on a Ti film.

[0057] In the polar superlattice GaN-based FET, the end of the p-type GaN layer 17 on the side of the drain electrode 20 is in contact with the Al y Ga 1-y N layer 15 and the undoped GaN layer 16, and the undoped GaN layer 11 constitute a gate electrode contact region. y Ga 1-y N layer 15, the Al x Ga 1-x N layer 12 and the undoped GaN layer 11 constitute a gate electrode contact region. y Ga 1-y The distance between the end of the p-type GaN layer 17 on the side of the drain electrode 20 and the end of the undoped GaN layer 16 on the side opposite to the drain electrode 20 is a psj length L psj . The p-type GaN layer 17, the undoped GaN layer 16 directly below the p-type GaN layer 17, the Al y Ga 1-y N layer 15, the Al x Ga 1-x N layer 12 and the undoped GaN layer 11 constitute a gate electrode contact region.

[0058] As Figure 2 shown in the drawing, in the polar superlattice GaN-based FET, the inclination angle of the Al y Ga 1-y N layer 15 with respect to the c plane is 5 degrees or more and 90 degrees or less. More specifically, as described above, the undoped GaN layer 14 on one side of the opening portion 13 is generally asymmetric with respect to the undoped GaN layer 14 on the opposite side of the opening portion 13, and thus the Al y Ga 1-y N layer 15 on the undoped GaN layer 14 on one side is also asymmetric with respect to the Al y Ga 1-y N layer 15 on the undoped GaN layer 14 on the opposite side, the inclination angle of the Al y Ga 1-yThe inclination angle of the N layer 15 is set to θ2, and 5 degrees ≤ θ1 ≤ 90 degrees and 5 degrees ≤ θ2 ≤ 90 degrees. There is a tendency that the larger θ1 and θ2 are, the higher the gate threshold voltage is. The Al y Ga 1-y N layer 15 is extended from the slope of the undoped GaN layer 14 on one side to the slope of the undoped GaN layer 14 on the opposite side is set to L r , in the direction connecting the source electrode 19 and the drain electrode 20, with respect to the projection of the undoped GaN layer 11. The length of the slope of the undoped GaN layer 14 on one side in the direction is set to L s1 , with respect to the projection of the undoped GaN layer 11. The length of the slope of the undoped GaN layer 14 on the opposite side in the direction is set to L s2 , with respect to the projection of the undoped GaN layer 11. At this time, generally, 0.1 cos θ1 ≤ 2L s1 / L r ≤ 1 and 0.1 cos θ2 ≤ 2L s2 / L r ≤ 1. There is a tendency that the larger L s1 / L r or L s2 / L r is, the higher the gate threshold voltage is. L r is preferably smaller.

[0059] Figure 3 is a portion of the polar superlattice GaN-based FET including the undoped GaN layer 14 on one side and the Al y Ga 1-y N layer 15 above it, which is enlarged and shown in a cross-sectional view. As Figure 3 indicated, the portion of the Al y Ga 1-y N layer 15 above the slope of the undoped GaN layer 14 has a face orientation that becomes a semi-polar face inclined with respect to the c plane. In this case, the Al y Ga 1-y N layer 15 of this portion has a face (growth face) that is perpendicular to the polarization electric field (indicated by an arrow pointing from + to - in Figure 3 ), and thus a reduction in the polarization electric field strength can be achieved. The Al y Ga 1-y N layer 15 of this portion has a face (growth face) that is perpendicular to the polarization electric field (indicated by an arrow pointing from + to - in Figure 3 ), and thus a reduction in the polarization electric field strength can be achieved. The Al y Ga 1-y N layer 15 of this portion has a face (growth face) that is perpendicular to the polarization electric field (indicated by an arrow pointing from + to - in Figure 3 ), and thus a reduction in the polarization electric field strength can be achieved. The Al y Ga 1-yThe tilted structure of N-layer 15 / undoped GaN layer 14 allows for the connection between the undoped GaN layer 14 and the Al layer when the gate voltage applied to the gate electrode 18 is turned off. y Ga 1-y At least a portion of the undoped GaN layer 14 near the heterointerface between N layers 15 does not form 2DEG, which helps to achieve normally-off polarized superjunction GaN-based FETs by increasing the gate threshold voltage. Regarding Al... y Ga 1-y The Al composition y and thickness of layer N15, considering the aforementioned effect of reducing the polarization electric field intensity, are selected as follows: In the undoped GaN layer 14 and the Al layer on the beveled surface... y Ga 1-y No 2DEG is formed in the undoped GaN layer 14 near the heterostructure interface between N layers 15, in Al y Ga 1-y In the N-layer 15, the portion of the undoped GaN layer 14 with c-plane orientation above the upper surface of the undoped GaN layer 14, near the heterostructure interface between the undoped GaN layer 14 and the undoped GaN layer 14, and the c-plane oriented Al within the opening 13. y Ga 1-y 2DEG is formed in the undoped GaN layer 11 in the portion near the heterostructure interface between the N layer 15 and the undoped GaN layer 11.

[0060] [Operation of Polarized Superjunction GaN-based FETs]

[0061] (When the gate voltage is off) in Figure 4 The diagram shows the polarized superjunction GaN-based FET during gate voltage cutoff. Figure 1 The band structure diagram showing the direction of the single-dotted arrow, similarly, in Figure 6 The diagram shows the path along when the gate voltage is off. Figure 1 The energy band diagram showing the direction of the dashed arrows. Figure 4 and Figure 6 In the diagram, the vertical axis represents electron energy, E C E represents the energy at the lower end of the conduction band. V E represents the energy at the upper end of the valence electron band. F The Fermi level (described later) Figure 5 and Figure 7 (The same applies to the middle). When the gate voltage is off, such as... Figure 1 As shown, in the undoped GaN layer 11 and Al x Ga 1-x In the undoped GaN layer 11 near the heterostructure interface between N layers 12, and in the undoped GaN layer 11 and Al... y Ga 1-y2DEG22 is formed in the undoped GaN layer 11 near the heterointerface between the N layers 15, and Al is formed in the portion of the undoped GaN layer 14 at the slope of the half-polar surface. y Ga 1-y No 2DEG22 was formed in the undoped GaN layer 14 near the heterostructure interface between the N layers 15, in Al x Ga 1-x An n-channel 23 is formed near the heterostructure interface between the N-layer 12 and the undoped GaN layer 14, and an n-channel 23 is formed between the undoped GaN layer 16 and the Al layer 14. y Ga 1-y Locally (more specifically, in addition to the portion near the heterostructure interface between N layers 15) in the undoped GaN layer 16, in the portion of the undoped GaN layer 16. y Ga 1-y 2DHG21 is formed on the portion of the N-layer 15 (excluding the portion above the sloped portion of the semi-polar surface). That is, 2DHG21 is formed on the portion of the undoped GaN layer 14 and the Al-doped semi-polar surface. y Ga 1-y In the portion near the heterojunction interface between the N layers 15, 2DEG22 is not formed in the undoped GaN layer 14. Therefore, in this portion, the n-channel between the source electrode 19 and the drain electrode 20 is interrupted. Thus, this polarized superjunction GaN-based FET becomes normally-off. Figure 1 The diagram illustrates the following situation: when the gate voltage is off, in Al... y Ga 1-y N layer 15 and Al y Ga 1-y 2DEG22 is formed in the undoped GaN layer 11 and undoped GaN layer 14 near the hetero interface between the undoped GaN layer 11 and the bottom of the undoped GaN layer 14 in the part that contacts the N layer 15, but there are also cases where 2DEG22 is not formed.

[0062] (When the gate voltage is on) A gate voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 18 of the polarized superjunction GaN FET. Figure 5 The diagram shows the polarized superjunction GaN-based FET during gate voltage turn-on. Figure 1 The band structure diagram showing the direction of the single-dotted arrow, similarly, in Figure 7 The diagram shows the path along when the gate voltage is on. Figure 1 The energy band diagram showing the direction of the dashed arrow. Additionally, in Figure 5 and Figure 7 In the middle, E Fn E represents the quasi-Fermi level of an electron. Fp This represents the quasi-Fermi level of a hole. At this point, as... Figure 8As shown, in the portion of the Al layer between the undoped GaN layer 14 and the semi-polar surface... y Ga 1-y 2DEG22 is induced in the undoped GaN layer 14 near the heterojunction between the N layers 15, thus continuously forming an n-channel between the source electrode 19 and the drain electrode 20. At this time, by applying a positive voltage to the drain electrode 20 relative to the source electrode 19 beforehand, current flows from the drain electrode 20 to the source electrode 19. Thus, the polarized superjunction GaN-based FET is turned on.

[0063] [Fabrication method of polarized superjunction GaN-based FETs]

[0064] like Figure 9 As shown, firstly, on substrate 10, for example, a buffer layer, an undoped GaN layer 11, and an Al layer are sequentially grown using a conventionally known MOCVD (metal-organic chemical vapor deposition) method, employing TMG (trimethylgallium) as the Ga raw material, TMA (trimethylaluminum) as the Al raw material, NH3 (ammonia) as the nitrogen raw material, and N2 gas and H2 gas as carrier gases. x Ga 1-x N-layer 12. Undoped GaN layer 11 and Al x Ga 1-x The growth temperature of the N-layer 12 is, for example, around 1100°C. As for these undoped GaN layers 11 and Al... x Ga 1-x The carrier gas used during the growth of the N-layer 12 is hydrogen (H2) and nitrogen (N2). The substrate 10 can be a sapphire substrate (e.g., a C-side sapphire substrate), a Si substrate, a SiC substrate, etc. Regarding the buffer layer, GaN layers, AlN layers, AlGaN layers, AlGaN / GaN superlattice layers, etc., can be used. When using, for example, a GaN layer as the buffer layer, it is grown at a low temperature of approximately 530°C.

[0065] Next, as Figure 10 As shown, in Al x Ga 1-x A resist pattern or other mask is formed on layer N 12, corresponding to the partial opening 13. Then, the mask is used to apply a photoresist pattern to layer A. x Ga 1-x The N-layer 12 is etched until the undoped GaN layer 11 is exposed. This etching can also be performed as needed until a shallow trench is formed in the undoped GaN layer 11 (over-etching). Figure 10 The image shows the process of etching until a shallow trench is formed on the undoped GaN layer 11.

[0066] Next, as Figure 11As shown, an undoped GaN layer 14 is grown on the sidewall of the opening 13 using MOCVD, extending from the sidewall of the opening 13 onto a portion of the undoped GaN layer 11 inside the opening 13. Then, an Al-containing layer is formed... x Ga 1-x Al was sequentially grown on the entire surface of N-layer 12 and undoped GaN-layer 14 using MOCVD. y Ga 1-y N-layer 15, undoped GaN layer 16, and p-type GaN layer 17. The undoped GaN layer 14 grows laterally from the sidewall of the opening 13, and continues to grow... Figure 1 The state shown indicates that growth has stopped. Undoped GaN layer 14, Al y Ga 1-y The growth temperatures of N-layer 15, undoped GaN layer 16, and p-type GaN layer 17 are the same as those of undoped GaN layer 11 and Al. x Ga 1-x Similarly, the N-layer 12 is grown at around 1100°C. As the p-type dopant for the growth of the p-type GaN layer 17, dicyclopentadienyl magnesium (Cp2Mg) is used. As for these Al... y Ga 1-y The carrier gases used during the growth of N-layer 15, undoped GaN layer 16, and p-type GaN layer 17 are H2 and N2.

[0067] Next, after forming a photoresist pattern (not shown) on the p-type GaN layer 17 with a shape corresponding to the device formation region, the p-type GaN layer 17, the undoped GaN layer 16, and the Al layer are then separated using this photoresist. y Ga 1-y N layer 15, Al x Ga 1-x The N-layer 12 and the undoped GaN layer 11 are sequentially etched to a depth halfway down the thickness direction of the undoped GaN layer 11 to form a predetermined shape, thereby enabling device separation. Afterward, the mask is removed.

[0068] Next, a layer of GaN with... is formed on the p-type GaN layer 17. Figure 1 After applying a photoresist pattern mask (not shown) corresponding to the planar shape of the p-type GaN layer 17, the p-type GaN layer 17 is etched using this mask to form a predetermined shape. Then, the mask is removed. Thus, as shown... Figure 12 As shown, a p-type GaN layer 17 of a specified shape is formed.

[0069] Next, a layer of p-type GaN is formed in a manner that covers the p-type GaN layer 17. Figure 1 After applying a photoresist pattern (not shown) to the planar shape of the undoped GaN layer 16, the undoped GaN layer 16 and Al are then separated using this mask.y Ga 1-y N layer 15 is etched to Al x Ga 1-x N layer 12 is exposed, and is patterned into a prescribed shape. Thereafter, the mask is removed. Thus, as Figure 13 shown, the undoped GaN layer 16 and Al y Ga 1-y N layer 15 is patterned into an island shape.

[0070] Next, after forming the source electrode 19 and the drain electrode 20 on the exposed Al x Ga 1-x N layer 12, the gate electrode 18 is formed on the p-type GaN layer 17.

[0071] Thus, the target polar superjunction GaN-based FET shown in Figure 1 is manufactured.

[0072] (Example) Polar superjunction GaN-based FETs in which L r , θ1, and θ2 were changed were manufactured, and evaluation of the gate threshold voltage was performed. Regarding the Al x Ga 1-x N layer 12, x = 0.25, and the thickness was 40 nm, and regarding the Al y Ga 1-y N layer 15, y = 0.17, and the thickness was 15 nm, and the thickness of the undoped GaN layer 16 was 30 nm. The distance between the side surface of the Al y Ga 1-y N layer 15 on the source electrode 19 side and the source electrode 19, and the distance between the side surface of the Al y Ga 1-y N layer 15 on the drain electrode 20 side and the drain electrode 20 were respectively 3 μm, and the distance between the side surface of the Al y Ga 1-y N layer 15 on the source electrode 19 side and the side surface of the p-type GaN layer 17 on the source electrode 19 side was 1 μm. The results were as follows.

[0073]

[0074] As described above, according to this first embodiment, at the time of gate voltage cutoff, the 2DEG 22 is not formed in the undoped GaN layer 14 at the portion near the heterointerface between the undoped GaN layer 14 and the portion of the semipolar surface of the Al y Ga 1-y N layer 15, and thus it is possible to easily realize a normally-off polar superjunction GaN-based FET.

[0075] 〈Second Embodiment〉

[0076] [Polarized Superjunction GaN-based FET]

[0077] like Figure 14 As shown, in the polarized superjunction GaN-based FET of the second embodiment, similar to Patent Document 2, the p-type GaN layer 17 extends to the psj region, which differs from the polarized superjunction GaN-based FET of the first embodiment. Other aspects are the same as the polarized superjunction GaN-based FET of the first embodiment.

[0078] [Fabrication method of normally off polarized superjunction GaN-based FETs]

[0079] In this normally-off polarized superjunction GaN FET manufacturing method, except that a p-type GaN layer 17 is finally formed on the undoped GaN layer 16 in the gate electrode contact region and the psj region, the rest is the same as the polarized superjunction GaN FET manufacturing method of the first embodiment.

[0080] According to this second embodiment, the same advantages as the first embodiment can be obtained.

[0081] <Third Implementation>

[0082] [Polarized Superjunction GaN-based FET]

[0083] like Figure 15 As shown, in the polarized superjunction GaN-based FET of the third embodiment, the sidewall of the opening 13 is perpendicular to the c-plane, and an undoped GaN layer 14 is disposed on this sidewall. This undoped GaN layer 14 has a rectangular cross-sectional shape, and its side surface is perpendicular to the c-plane. Furthermore, in Al... x Ga 1-x Al is sequentially disposed on the N-layer 12, the undoped GaN layer 14, and the undoped GaN layer 11 inside the opening 13. y Ga 1-y N-layer 15, undoped GaN layer 16, and p-type GaN layer 17. Al y Ga 1-y The N layer 15 reflects the cross-sectional shape of the undoped GaN layer 14 and has a cross-sectional shape that bends perpendicularly to the c-plane at a portion of the side surface of the undoped GaN layer 14. Al y Ga 1-y The undoped GaN layer 16 and the p-type GaN layer 17 on the N-layer 15 have the following cross-sectional shape: (Similar to Al) y Ga 1-y The portion of N-layer 15 that has a cross-sectional shape perpendicular to the c-plane is bent at an angle. In this case, the undoped GaN layer 14 has a planar orientation that forms a non-polar surface perpendicular to the c-plane, therefore Al y Ga 1-yThe portion of the side surface of the undoped GaN layer 14 in the N layer 15 has the same face orientation as the undoped GaN layer 14, which is an a-plane that is perpendicular to the c-plane. Therefore, at the time of gate voltage cutoff, 2DEG 22 is not induced in the undoped GaN layer 14 at the portion of the side surface of the undoped GaN layer 14, and the polarization superlattice GaN-based FET is normally off. At the time of gate voltage conduction, 2DEG 22 is induced in the undoped GaN layer 14 at the portion of the side surface of the undoped GaN layer 14, and the polarization superlattice GaN-based FET is turned on. The polarization superlattice GaN-based FET is the same as the polarization superlattice GaN-based FET of the first embodiment except for the above. y Ga 1-y N layer 15, and 2DEG 22 is not induced in the undoped GaN layer 14 at the portion of the side surface of the undoped GaN layer 14, and the polarization superlattice GaN-based FET is normally off. At the time of gate voltage conduction, 2DEG 22 is induced in the undoped GaN layer 14 at the portion of the side surface of the undoped GaN layer 14, and the polarization superlattice GaN-based FET is turned on. The polarization superlattice GaN-based FET is the same as the polarization superlattice GaN-based FET of the first embodiment except for the above. y Ga 1-y N layer 15, and 2DEG 22 is not induced in the undoped GaN layer 14 at the portion of the side surface of the undoped GaN layer 14, and the polarization superlattice GaN-based FET is normally off. At the time of gate voltage conduction, 2DEG 22 is induced in the undoped GaN layer 14 at the portion of the side surface of the undoped GaN layer 14, and the polarization superlattice GaN-based FET is turned on. The polarization superlattice GaN-based FET is the same as the polarization superlattice GaN-based FET of the first embodiment except for the above.

[0084] [Method for manufacturing normally-off polarization superlattice GaN-based FET]

[0085] The method for manufacturing the normally-off polarization superlattice GaN-based FET is the same as the method for manufacturing the polarization superlattice GaN-based FET of the first embodiment.

[0086] According to the third embodiment, the same advantages as the first embodiment can be obtained.

[0087] The embodiments and examples of the present application have been described above, but the present application is not limited to the above-described embodiments and examples, and various modifications can be made based on the technical idea of the present application.

[0088] For example, the values, structures, shapes, materials, and the like exemplified in the above-described embodiments and examples are merely examples, and different values, structures, shapes, materials, and the like can be used as needed.

Claims

1. A polarization super junction field effect transistor, wherein the polarization super junction field effect transistor has: a first semiconductor layer; a second semiconductor layer having an opening portion, which is positioned above the first semiconductor layer; a third semiconductor layer, which is positioned on a part of the first semiconductor layer inside the opening portion from a side wall of the opening portion; a fourth semiconductor layer having an island shape, which is positioned on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion; a fifth semiconductor layer, which is positioned above the fourth semiconductor layer; a sixth semiconductor layer, which is positioned above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; and a gate electrode electrically connected to the sixth semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are group III nitride semiconductor layers, a band gap of the second semiconductor layer and the fourth semiconductor layer is larger than a band gap of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and a band gap of the fourth semiconductor layer is smaller than a band gap of the second semiconductor layer, a band gap of the first semiconductor layer and the third semiconductor layer is the same as each other, the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers, the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, at least a part of a part of the fourth semiconductor layer on the third semiconductor layer has a face orientation which becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to a c-plane.

2. The polarization super junction field effect transistor according to claim 1, wherein the third semiconductor layer has a trapezoidal cross-sectional shape.

3. The polarization super junction field effect transistor according to claim 1 or 2, wherein the opening portion has an inverted trapezoidal cross-sectional shape.

4. The polarization super junction field effect transistor according to claim 1 or 2, wherein when a gate voltage applied to the gate electrode is cut off, a two-dimensional electron gas is formed in the first semiconductor layer at a part near a hetero interface between the first semiconductor layer and the second semiconductor layer, a two-dimensional electron gas is formed or is not formed in the first semiconductor layer at a part near a hetero interface between the first semiconductor layer and the fourth semiconductor layer, at least a part of the third semiconductor layer at a part near a hetero interface between the third semiconductor layer and the fourth semiconductor layer does not form a two-dimensional electron gas, an n channel is formed near a hetero interface between the second semiconductor layer and the third semiconductor layer, and a two-dimensional hole gas is locally formed in the fifth semiconductor layer at a part near a hetero interface between the fifth semiconductor layer and the fourth semiconductor layer.

5. A polarization super junction field effect transistor, wherein the polarization super junction field effect transistor has: a first semiconductor layer; a second semiconductor layer having an opening portion, which is positioned above the first semiconductor layer; a third semiconductor layer, which is positioned on a part of the first semiconductor layer inside the opening portion from a side wall of the opening portion; a fourth semiconductor layer having an island shape, which is positioned on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion; a fifth semiconductor layer, which is positioned above the fourth semiconductor layer; a sixth semiconductor layer, which is positioned above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; and a gate electrode electrically connected to the sixth semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are group III nitride semiconductor layers, a band gap of the second semiconductor layer and the fourth semiconductor layer is larger than a band gap of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and a band gap of the fourth semiconductor layer is smaller than a band gap of the second semiconductor layer, a band gap of the first semiconductor layer and the third semiconductor layer is the same as each other, the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers, the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, at least a part of a part of the fourth semiconductor layer on the third semiconductor layer has a face orientation which becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to a c-plane. a first undoped GaN layer; AlxGa1-xN layer having an opening portion x Ga 1-x N layer, where 0 < x < 1; a second undoped GaN layer provided on a part of the first undoped GaN layer inside the opening portion from a side wall of the opening; Al with an island-like shape y Ga 1-y N layers, which are in Al x Ga 1-x The N-layer, the second undoped GaN layer, and the first undoped GaN layer inside the opening are extended and disposed thereon, wherein y < x; than the Al y Ga 1-y N layer is a third undoped GaN layer on the upper layer. a p-type GaN layer which is upper than the third undoped GaN layer; the Al x Ga 1-x source and drain electrodes on the GaN layer; and a gate electrode electrically connected to the p-type GaN layer, The first undoped GaN layer and the Al x Ga 1-x N layer has a c-plane orientation, The Al y Ga 1-y At least a portion of the portion in the AlGaN layer on the second undoped GaN layer has a face orientation that becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to the c-plane.

6. The polarization super junction field effect transistor according to claim 5, wherein the second undoped GaN layer has a trapezoidal cross-sectional shape.

7. The polarization super junction field effect transistor according to claim 5 or 6, wherein the opening portion has an inverted trapezoidal cross-sectional shape.

8. The polarization super junction field effect transistor according to claim 5 or 6, wherein A two-dimensional electron gas is formed in the first undoped GaN layer at a portion near a heterointerface between the first undoped GaN layer and the Al x Ga 1-x N layer, or is not formed, in the second undoped GaN layer at a portion near a heterointerface between the second undoped GaN layer and the Al y Ga 1-y N layer, and a two-dimensional hole gas is locally formed in the third undoped GaN layer at a portion near a heterointerface between the third undoped GaN layer and the Al y Ga 1-y N layer, and a two-dimensional hole gas is locally formed in the third undoped GaN layer at a portion near a heterointerface between the third undoped GaN layer and the Al x Ga 1-x N layer, and a two-dimensional hole gas is locally formed in the third undoped GaN layer at a portion near a heterointerface between the third undoped GaN layer and the Al y Ga 1-y N layer, and a two-dimensional hole gas is locally formed in the third undoped GaN layer at a portion near a heterointerface between the third undoped GaN layer and the Al 9. The polarization super junction field effect transistor according to claim 5, wherein The Al y Ga 1-y An inclination angle of at least a part of the portion in the AlGaN layer on the second undoped GaN layer with respect to the c-plane is 5 degrees or more and 90 degrees or less.

10. The polarization super junction field effect transistor according to claim 5, wherein The second undoped GaN layer has a trapezoidal cross-sectional shape, and the Al... y Ga 1-y The length of the portion of the N-layer extending from the slope of the second undoped GaN layer on one side to the slope of the second undoped GaN layer on the opposite side, projected relative to the first undoped GaN layer, in the direction connecting the source electrode and the drain electrode, is denoted as L. r Let L be the length of the projection of the inclined surface of the second undoped GaN layer on one side relative to the first undoped GaN layer in the direction. s1 Let L be the length of the projection of the inclined surface of the second undoped GaN layer on the opposite side relative to the first undoped GaN layer in the direction. s2 , to the Al y Ga 1-y The tilt angle of at least a portion of the second undoped GaN layer on one side of the N layer relative to the c-plane is set as θ1, and the Al y Ga 1-y The tilt angle of at least a portion of the portion of the second undoped GaN layer on the opposite side of the N layer relative to the c-plane is set to θ2, where 0.1cosθ1≤2L s1 / L r ≤1 and 0.1cosθ2≤2L s2 / L r ≤1.

11. A semiconductor layered structure, wherein the semiconductor layered structure has: a first semiconductor layer; a second semiconductor layer having an opening portion which is upper than the first semiconductor layer; a third semiconductor layer provided on a part of the first semiconductor layer inside the opening portion from a side wall of the opening portion; and a fourth semiconductor layer having an island-like shape which is provided extending on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers, a band gap of the second semiconductor layer and the fourth semiconductor layer is larger than a band gap of the first semiconductor layer and the third semiconductor layer, and a band gap of the fourth semiconductor layer is smaller than a band gap of the second semiconductor layer, the band gap of the first semiconductor layer and the third semiconductor layer are the same as each other, the first semiconductor layer and the third semiconductor layer are undoped semiconductor layers, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, at least a part of a part on the third semiconductor layer in the fourth semiconductor layer has a face orientation which becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to a c-plane.

12. A semiconductor layered structure, wherein the semiconductor layered structure has: a first undoped GaN layer; AlxGa1-xN layer having an opening portion x Ga 1-x N layer, where 0 < x < 1; a second undoped GaN layer provided on a part of the first undoped GaN layer inside the opening portion from a side wall of the opening; and Al having an island shape y Ga 1-y N layer, which is provided on the Al x Ga 1-x N layer, the second undoped GaN layer, and the first undoped GaN layer inside the opening portion, wherein y < x, The first undoped GaN layer and the Al x Ga 1-x N layer has a c-plane orientation, The Al y Ga 1-y At least a portion of the portion in the AlGaN layer on the second undoped GaN layer has a face orientation that becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to the c-plane.

13. An electrical device, wherein the electrical device has at least one transistor, the transistor is a polarization super junction field effect transistor, the polarization super junction field effect transistor has: a first semiconductor layer; a second semiconductor layer having an opening portion which is upper than the first semiconductor layer; a third semiconductor layer provided on a part of the first semiconductor layer inside the opening portion from a side wall of the opening portion; a fourth semiconductor layer having an island-like shape which is provided extending on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening portion. a fifth semiconductor layer that is positioned above the fourth semiconductor layer; a sixth semiconductor layer that is positioned above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; and a gate electrode that is electrically connected to the sixth semiconductor layer, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are Group III nitride semiconductor layers, the band gap of the second semiconductor layer and the fourth semiconductor layer is larger than the band gap of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer, the band gap of the first semiconductor layer and the third semiconductor layer is the same as each other, the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers, the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation, at least a part of the portion of the fourth semiconductor layer that is on the third semiconductor layer has a face orientation that is a semi-polar face inclined with respect to a c-face or a non-polar face perpendicular to a c-face.

14. An electrical device, wherein the electrical device has at least one transistor, the transistor is a polarized super junction field effect transistor, the polarized super junction field effect transistor has: a first undoped GaN layer; AlxGa1-xN layer having an opening portion x Ga 1-x N layer, where 0 < x < 1; a second undoped GaN layer that is provided on a part of the first undoped GaN layer inside the opening portion from a side wall of the opening; Al with an island-like shape y Ga 1-y N layers, which are in Al x Ga 1-x The N-layer, the second undoped GaN layer, and the first undoped GaN layer inside the opening are extended and disposed thereon, wherein y < x; than the Al y Ga 1-y N layer is a third undoped GaN layer on the upper layer. a p-type GaN layer that is positioned above the third undoped GaN layer; the Al x Ga 1-x source and drain electrodes on the GaN layer; and a gate electrode that is electrically connected to the p-type GaN layer, The first undoped GaN layer and the Al x Ga 1-x N layer has a c-plane orientation, The Al y Ga 1-y At least a portion of the portion in the AlGaN layer on the second undoped GaN layer has a face orientation that becomes a semi-polar face inclined with respect to a c-plane or a non-polar face perpendicular to the c-plane.

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