Semiconductor device and preparation method
By designing progressively larger gate trenches and using step-by-step etching techniques in gallium nitride semiconductor devices, the problems of insufficient trench corner filling and etching control were solved, thereby improving the two-dimensional electron gas concentration and conductivity of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-16
- Publication Date
- 2026-03-10
AI Technical Summary
The performance of existing gallium nitride semiconductor devices needs to be improved, especially due to insufficient filling at the corners of the gate trench and the difficulty in controlling the etching process, which affects device performance.
By gradually increasing the size of the gate trench along the direction from the substrate structure to the strain layer, and making the angle between the sidewall and the bottom of the gate trench greater than 90 degrees, the gate structure is formed by step etching technology, avoiding dead corners in the trench corners and ensuring sufficient material deposition.
This improved the two-dimensional electron gas concentration and conductivity of the device, reduced the difficulty of the etching process, and enhanced the overall performance of the device.
Smart Images
Figure CN121645935A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Enhanced high electron mobility transistors (HEMTs) have important applications in modern electronics. However, the performance of gallium nitride (GaN) semiconductor devices in related technologies needs further improvement. Summary of the Invention
[0003] This invention provides a semiconductor device and its fabrication method to improve device performance.
[0004] According to one aspect of the present invention, a semiconductor device is provided, comprising:
[0005] Substrate structure;
[0006] A channel layer, wherein the channel layer is disposed on one side of the substrate structure;
[0007] A barrier layer is disposed on the side of the channel layer away from the substrate structure;
[0008] A strain layer is disposed on the side of the barrier layer away from the channel layer. The strain layer has a source trench, a drain trench, and a gate trench. The source trench, the drain trench, and the gate trench penetrate the strain layer along the direction from the strain layer to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer. Along the direction from the substrate structure to the strain layer, the first dimension of the gate trench gradually increases in a predetermined direction. The angle between the sidewall and the bottom of the gate trench is greater than 90 degrees. The predetermined direction is parallel to the surface of the substrate structure where the channel layer is disposed.
[0009] The system includes a source, a drain, and a gate structure; the source is disposed within the source trench, the drain is disposed within the drain trench, and the gate structure is disposed within the gate trench.
[0010] Optionally, the angle between the sidewall of the gate trench and the bottom of the gate trench is greater than or equal to 95 degrees and less than or equal to 120 degrees.
[0011] Optionally, the gate trench includes a first sub-trench and a second sub-trench that are interconnected, wherein the first sub-trench is disposed on the side of the second sub-trench away from the substrate structure;
[0012] The minimum dimension of the first sub-slot along the preset direction is greater than the maximum dimension of the second sub-slot along the preset direction.
[0013] Optionally, the sidewall of the first sub-slot is connected to the sidewall of the second sub-slot through the bottom of the first sub-slot, the bottom of the first sub-slot has a second dimension along the preset direction, and the bottom of the gate trench has a third dimension along the preset direction;
[0014] The ratio of the second dimension to the third dimension is greater than or equal to one-tenth and less than or equal to one-fifth.
[0015] Optionally, the gate structure includes a first insulating layer and a gate, the first insulating layer covering the sidewalls and bottom of the gate trench, and the gate disposed on the surface of the first insulating layer away from the sidewalls and bottom of the gate trench;
[0016] The semiconductor device further includes a second insulating layer and a third insulating layer; the second insulating layer is disposed on the side of the gate structure away from the substrate structure, and the second insulating layer covers the gate structure; the third insulating layer is disposed on the side of the source electrode away from the substrate structure, and the third insulating layer covers the source electrode and the drain electrode.
[0017] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising:
[0018] Provide substrate structure;
[0019] A trench layer is provided on one side of the substrate structure;
[0020] A barrier layer, a strain layer, a source, a drain, and a gate structure are disposed on the side of the channel layer away from the substrate structure.
[0021] The strain layer is disposed on the side of the barrier layer away from the channel layer; the strain layer has a source trench, a drain trench, and a gate trench; the source trench, the drain trench, and the gate trench penetrate the strain layer along the direction from the strain layer to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; along the direction from the substrate structure to the strain layer, the first dimension of the gate trench gradually increases along a predetermined direction; the angle between the sidewall of the gate trench and the bottom of the gate trench is greater than 90 degrees; wherein the predetermined direction is a direction parallel to the surface of the substrate structure where the channel layer is disposed; the source is disposed in the source trench, the drain is disposed in the drain trench, and the gate structure is disposed in the gate trench.
[0022] Optionally, a barrier layer, a strain layer, a source electrode, a drain electrode, and a gate structure are disposed on the side of the channel layer away from the substrate structure, including:
[0023] A first sub-barrier layer is disposed on the side of the channel layer away from the substrate structure;
[0024] A sacrificial layer is disposed on the surface of the first sub-barrier layer away from the channel layer; wherein the sacrificial layer includes an opening in the direction of the substrate structure pointing to the sacrificial layer, and the opening gradually increases in a fourth dimension along the preset direction;
[0025] A virtual gate is provided within the opening, and the virtual gate fills the opening;
[0026] Remove the sacrificial layer;
[0027] A second sub-barrier layer is disposed on the surface of the first sub-barrier layer; wherein, the second sub-barrier layer covers the area of the first sub-barrier layer where the virtual gate is not disposed, and the barrier layer includes the first sub-barrier layer and the second sub-barrier layer;
[0028] A strain material layer is disposed on the side of the virtual gate away from the substrate structure, and the strain material layer covers the virtual gate and the second sub-barrier layer.
[0029] Source trench, drain trench, source, and drain are formed in the strained material layer;
[0030] Remove the strain material layer from the surface of the virtual gate to form the strain layer with the first sub-groove;
[0031] Remove the dummy gate to form a second sub-groove; wherein the gate trench includes the first sub-groove and the second sub-groove;
[0032] The gate structure is formed within the gate trench.
[0033] Optionally, removing the strain material layer on the surface of the virtual gate to form the strain layer having a first sub-groove includes: removing the strain material layer on the surface of the virtual gate by dry etching;
[0034] Removing the dummy gate to form a second sub-groove includes: removing the dummy gate by wet etching;
[0035] Wherein, the minimum dimension of the first sub-slot along the preset direction is greater than the maximum dimension of the second sub-slot along the preset direction.
[0036] Optionally, a sacrificial layer is disposed on the surface of the first sub-barrier layer away from the channel layer, including:
[0037] A barrier material layer is disposed on the surface of the first sub-barrier layer away from the channel layer;
[0038] A sacrificial material layer is disposed on the surface of the barrier material layer;
[0039] The sacrificial material layer is patterned by dry etching to form a third sub-groove penetrating the sacrificial material layer;
[0040] The barrier material layer is patterned by wet etching to form a fourth sub-groove penetrating the barrier material layer; wherein the opening includes the third sub-groove and the fourth sub-groove, and the sacrificial layer includes the patterned barrier material layer and the patterned sacrificial material layer.
[0041] Optionally, the material of the virtual gate includes silicon, the material of the sacrificial material layer includes silicon oxide, and the material of the blocking material layer includes aluminum nitride or aluminum oxide.
[0042] In this embodiment of the invention, by setting the first dimension of the gate trench gradually increases along the direction of the substrate structure pointing towards the strain layer, the gate trench has no inward dead corners at the trench corners, and the angle between the sidewall and the bottom of the gate trench is greater than 90 degrees, so that the sidewall of the gate trench is inclined away from the center of the gate trench. This makes it easier for the material to be deposited on the sidewall of the gate trench when the gate structure is set in the gate trench, thereby making the trench corners more fully filled and improving device performance.
[0043] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention.
[0046] Figure 2 This is a schematic diagram of a gate trench in related technologies.
[0047] Figure 3 This is a schematic diagram of a gate trench provided in an embodiment of the present invention.
[0048] Figure 4This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0049] Figure 5 This is a process flow diagram of the formation of gate trenches in related technologies.
[0050] Figure 6 This is a schematic diagram of the second sub-barrier layer formed in related technologies.
[0051] Figure 7 This is a schematic diagram of the formation of the first barrier layer provided in an embodiment of the present invention.
[0052] Figure 8 This is a process diagram of forming a sacrificial layer provided in an embodiment of the present invention.
[0053] Figure 9 This is a schematic diagram of the formation of a sacrificial layer provided in an embodiment of the present invention.
[0054] Figure 10 This is a schematic diagram of forming a virtual gate provided in an embodiment of the present invention.
[0055] Figure 11 This is a schematic diagram of removing the sacrificial layer provided in an embodiment of the present invention.
[0056] Figure 12 This is a schematic diagram of the formation of the second sub-barrier layer provided in an embodiment of the present invention.
[0057] Figure 13 This is a schematic diagram of the formation of a strain material layer provided in an embodiment of the present invention.
[0058] Figure 14 This is a schematic diagram of the formation of the source and drain provided in an embodiment of the present invention.
[0059] Figure 15 This is a schematic diagram of the formation of the third insulating material layer provided in an embodiment of the present invention.
[0060] Figure 16 This is a schematic diagram of the formation of the first sub-groove provided in an embodiment of the present invention.
[0061] Figure 17 This is a schematic diagram of the formation of the second insulating material layer provided in an embodiment of the present invention. Detailed Implementation
[0062] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0063] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0064] This invention provides a semiconductor device. Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1 Semiconductor devices include:
[0065] Substrate structure 10;
[0066] The channel layer 20 is disposed on one side of the substrate structure 10;
[0067] Barrier layer 30 is disposed on the side of channel layer 20 away from substrate structure 10;
[0068] A strain layer 40 is disposed on the side of the barrier layer 30 away from the channel layer 20. The strain layer 40 has a source trench 41, a drain trench 42, and a gate trench 43. The source trench 41, drain trench 42, and gate trench 43 penetrate the strain layer 40 along the direction pointing from the strain layer 40 to the substrate structure 10, and the gate trench 43 extends into the barrier layer 30 after penetrating the strain layer 40. Along the direction X pointing from the substrate structure 10 to the strain layer 40, the first dimension D of the gate trench 43 gradually increases along a preset direction, and the angle A between the sidewall and the bottom of the gate trench 43 is greater than 90 degrees. The preset direction is a direction parallel to the surface of the substrate structure 10 where the channel layer 20 is disposed.
[0069] The source 50, drain 60, and gate structure 70 are provided; the source 50 is disposed in the source trench 41, the drain 60 is disposed in the drain trench 42, and the gate structure 70 is disposed in the gate trench 43.
[0070] The substrate structure 10 may include a substrate and a buffer layer. The substrate may be a Si substrate, a sapphire substrate, or a GaN substrate. The buffer layer alleviates the lattice mismatch problem between the substrate and the channel layer 20. The buffer layer material may include aluminum nitride, aluminum gallium nitride, a multilayer superlattice structure with alternating aluminum nitride / gallium nitride growth, a multilayer superlattice structure with alternating aluminum gallium nitride / gallium nitride growth, or carbon-doped gallium nitride. The channel layer 20 may be one or more of GaN, AlGa, and InGaN. The channel layer 20 and the barrier layer 30 form a heterojunction, and a two-dimensional electron gas is formed at the interface between the channel layer 20 and the barrier layer 30, thereby generating a conductive channel using the two-dimensional electron gas. The barrier layer 30 may include an AlGaN layer. The strain layer 40 is used to adjust the stress within the device, adjust the piezoelectric polarization effect between the channel layer 20 and the barrier layer 30, thereby adjusting the two-dimensional electron gas concentration of the device to achieve a higher two-dimensional electron gas concentration. The strain layer 40 may be made of materials such as AlN. The gate structure 70 may include a first insulating layer 71 and a gate 72. The gate 72, source 50, and drain 60 may be made of a metallic material or other conductive material. When a suitable bias voltage is applied between the gate 72 and the source 50 of the semiconductor device, a conductive channel is formed, thereby turning on the semiconductor device.
[0071] Along the direction X from the substrate structure 10 to the strain layer 40, the first dimension D of the gate trench 43 gradually increases along the preset direction. The first dimension D can increase linearly or non-linearly, for example, it can increase in a gradient or in the form of a set curve. Figure 2 This is a schematic diagram of a gate trench in related technologies, for reference. Figure 2 In related technologies, after the gate trench 43 is formed, part of the barrier layer at the corner of the gate trench 43 shrinks inward to form a shrinkage dead angle 4301. As a result, after the gate structure 70 is formed, the gate structure 70 cannot fill the shrinkage dead angle 4301, which affects the device performance.
[0072] refer to Figure 1 In this embodiment, by setting the direction X along the substrate structure 10 to the strain layer 40, the first dimension D of the gate trench 43 gradually increases along the preset direction, so that there is no dead angle at the corner of the gate trench 43, and the angle A between the sidewall of the gate trench 43 and the bottom of the gate trench 43 is greater than 90 degrees, so that the sidewall of the gate trench 43 is inclined away from the center of the gate trench 43, making it easier for the material to be deposited on the sidewall of the gate trench 43 when the gate structure 70 is set in the gate trench 43, thereby making the corner of the gate trench 43 more fully filled and improving the device performance.
[0073] Based on the above embodiments, optionally, the angle A between the sidewall of the gate trench 43 and the bottom of the gate trench 43 is greater than or equal to 95 degrees and less than or equal to 120 degrees.
[0074] Specifically, if the angle A between the sidewall and the bottom of the gate trench 43 is too small, the inclination of the sidewall of the gate trench 43 is too small, which is not conducive to the deposition of the gate structure 70. If the angle A between the sidewall and the bottom of the gate trench 43 is too large, the opening size of the gate trench 43 will be too large, and the gate trench 43 will occupy too much space, affecting the overall device size. By setting the angle A between the sidewall and the bottom of the gate trench 43 to be greater than or equal to 95 degrees and less than or equal to 120 degrees, more sufficient filling can be ensured at the corner of the gate trench 43, while avoiding the gate trench 43 being too large and affecting the device size. For example, the angle A can be 100 degrees, 105 degrees, or 110 degrees, etc.
[0075] Figure 3 This is a schematic diagram of a gate trench provided in an embodiment of the present invention. Optionally, based on the above embodiment, refer to... Figure 1 and Figure 3 The gate trench 43 includes a second sub-trench 432 and a first sub-trench 431 that are interconnected, with the first sub-trench 431 disposed on the side of the second sub-trench 432 away from the substrate structure 10.
[0076] The minimum dimension D1 of the first sub-slot 431 along the preset direction is greater than the maximum dimension D2 of the second sub-slot 432 along the preset direction.
[0077] Specifically, the minimum dimension D1 of the first sub-slot 431 along the preset direction is the dimension of the position of the first sub-slot 431 closest to the substrate structure 10 along the preset direction, and the maximum dimension D2 of the second sub-slot 432 along the preset direction is the dimension of the position of the second sub-slot 432 furthest from the substrate structure 10 along the preset direction.
[0078] The minimum dimension D1 of the first sub-slot 431 along the preset direction is greater than the maximum dimension D2 of the second sub-slot 432 along the preset direction. The opening of the first sub-slot 431 is larger. When the gate structure 70 is formed in the first sub-slot 431 and the second sub-slot 432, the material is more easily deposited on the sidewall of the trench. This can further prevent the corner of the gate trench 43 from being filled more fully and improve the device performance.
[0079] Furthermore, when the gate trench 43 is formed, it can be formed by step etching. First, the first sub-trench 431 can be etched to expose the material to be etched through the first sub-trench 431. The material to be etched is then etched to form the second sub-trench 432. The minimum dimension D1 of the first sub-trench 431 along the preset direction is greater than the maximum dimension D2 of the second sub-trench 432 along the preset direction. The opening of the first sub-trench 431 is larger, making the etching process easier to control when etching to form the second sub-trench 432 and less likely to damage the barrier layer 30.
[0080] Based on the above embodiments, optionally, the sidewall 03 of the first sub-slot 431 and the sidewall 04 of the second sub-slot 432 are connected through the bottom 05 of the first sub-slot 431. The bottom 05 of the first sub-slot 431 has a second dimension B along a preset direction, and the bottom of the gate trench 43 has a third dimension C along a preset direction.
[0081] The ratio of the second dimension B to the third dimension C is greater than or equal to one-tenth and less than or equal to one-fifth.
[0082] Specifically, the third dimension C at the bottom of the gate trench 43 is set according to device requirements. The larger the second dimension B, the larger the opening of the first sub-trench 431, which easily increases the device size. By setting the ratio of the second dimension B to the third dimension C to be greater than or equal to one-tenth and less than or equal to one-fifth, it is possible to ensure that the first sub-trench 431 has a large opening, which allows for better deposition of the gate structure 70, and to ensure that the barrier layer 30 is not damaged when forming the second sub-trench 432, while avoiding an excessively large opening of the first sub-trench 431 that would increase the device size.
[0083] Based on the above embodiments, optionally, refer to Figure 1 The gate structure 70 includes a first insulating layer 71 and a gate 72. The first insulating layer 71 covers the sidewalls and bottom of the gate trench 43, and the gate 72 is disposed on the surface of the first insulating layer 71 away from the sidewalls and bottom of the gate trench 43.
[0084] The semiconductor device further includes a second insulating layer 82 and a third insulating layer 81; the second insulating layer 82 is disposed on the side of the gate structure 70 away from the substrate structure 10, and the second insulating layer 82 covers the gate structure 70; the third insulating layer 81 is disposed on the side of the source 50 away from the substrate structure 10, and the third insulating layer 81 covers the source 50 and the drain 60.
[0085] Specifically, the first insulating layer 71 is a gate insulating layer, and the first insulating layer 71 can be made of materials such as Al2O3. The gate 72 can be made of materials such as TiN. The second insulating layer 82 and the third insulating layer 81 serve an insulating function and can be made of materials such as silicon dioxide.
[0086] This invention also provides a method for fabricating a semiconductor device. Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, see reference. Figure 4 The methods for fabricating semiconductor devices include:
[0087] S110 provides a substrate structure.
[0088] S120. A trench layer is formed on one side of the substrate structure.
[0089] S130. A barrier layer, a strain layer, a source, a drain, and a gate structure are disposed on the side of the channel layer away from the substrate structure.
[0090] The strain layer is disposed on the side of the barrier layer away from the channel layer; the strain layer has a source trench, a drain trench, and a gate trench; the source trench, drain trench, and gate trench penetrate the strain layer along the direction from the strain layer to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; along the direction from the substrate structure to the strain layer, the first dimension of the gate trench gradually increases along a predetermined direction; the angle between the sidewall and the bottom of the gate trench is greater than 90 degrees; wherein, the predetermined direction is a direction parallel to the surface of the substrate structure where the channel layer is disposed; the source is disposed in the source trench, the drain is disposed in the drain trench, and the gate structure is disposed in the gate trench.
[0091] In this embodiment, by setting the direction along the substrate structure towards the strain layer, the first dimension of the gate trench gradually increases along the preset direction, so that there is no inward dead angle at the corner of the gate trench, and the angle between the sidewall and the bottom of the gate trench is greater than 90 degrees, so that the sidewall of the gate trench is inclined away from the center of the gate trench, making it easier for the material to be deposited on the sidewall of the gate trench when the gate structure is set in the gate trench, thereby making the corner of the gate trench more fully filled and improving the device performance.
[0092] Figure 5 This is a process flow diagram for forming gate trenches in related technologies, for reference. Figure 5In related technologies, after forming a substrate structure 10, a channel layer 20, and a first sub-barrier layer 31, an oxide layer 01 is formed on the surface of the first sub-barrier layer 31. The oxide layer 01 is etched to form a positive trapezoidal virtual gate 02, the width of the positive trapezoidal virtual gate 02 adjacent to the substrate structure 10 being greater than the width of the side away from the substrate structure 10. Then, a second sub-barrier layer 32 is formed on the surface of the first sub-barrier layer 31. A strain material layer 401 is formed on the surface of the positive trapezoidal virtual gate 02 and the second sub-barrier layer 32. After forming a source trench 41 and a drain trench 42 in the strain material layer 401, a source 50 and a drain 60 are formed in the source trench 41 and the drain trench 42, respectively. Then, a third insulating material layer 810 is formed on the surface of the source 50 and the drain 60. After forming the third insulating material layer 810, the third insulating material layer 810, the strain material layer 401, and the positive trapezoidal virtual gate 02 are etched to form a gate trench 43.
[0093] Figure 6 This is a schematic diagram of the second sub-barrier layer formed in related technologies, for reference. Figure 5 and Figure 6 Because the trapezoidal virtual gate 02 is wider at the bottom and narrower at the top, the second sub-barrier layer 32 does not grow sufficiently at the angle formed by the trapezoidal virtual gate 02 and the first sub-barrier layer 31. Figure 6 In the area circled in red, the second sub-barrier layer 32 has a large gap between its side adjacent to the positive trapezoidal virtual gate 02 and the positive trapezoidal virtual gate 02. This results in a low concentration of two-dimensional electron gas in the region near the gate of the final semiconductor device, affecting the device resistance.
[0094] refer to Figure 2 and Figure 5 Because the trapezoidal virtual gate 02 is wider at the bottom and narrower at the top, the etching process window for etching the strain material layer 401 and the trapezoidal virtual gate 02 is difficult to control. If the etching process window is too small, it is easy to form Figure 2 In the structure shown, the opening of the gate trench 43 is too small. After etching the trapezoidal virtual gate 02 near the second sub-barrier layer 32, a recessed dead angle 4301 is formed, shrinking inwards towards both sides of the gate trench 43. This makes it difficult for the material to fill during the subsequent formation of the gate structure 70. (Reference) Figure 5 In the last figure, if the etching process window is too large, it can easily lead to an excessively large opening in the gate trench 43, resulting in damage to the second sub-barrier layer 32.
[0095] Figures 7-17 A schematic diagram of each process step in the formation of a semiconductor device is shown. (Refer to...) Figure 3 , Figures 7-17 Based on the above embodiments, optionally, a barrier layer 30, a strain layer 40, a source 50, a drain 60, and a gate structure 70 are disposed on the side of the channel layer 20 away from the substrate structure 10, including:
[0096] A first sub-barrier layer 31 is disposed on the side of the channel layer 20 away from the substrate structure 10;
[0097] A sacrificial layer 100 is disposed on the surface of the first sub-barrier layer 31 away from the channel layer 20; wherein, the sacrificial layer 100 includes an opening 101, which is located along the direction of the substrate structure 10 toward the sacrificial layer 100, and the opening 101 gradually increases in size along a fourth dimension W in a predetermined direction.
[0098] A virtual gate 110 is provided in the opening 101, and the virtual gate 110 fills the opening 101.
[0099] Remove sacrificial layer 100;
[0100] A second sub-barrier layer 32 is disposed on the surface of the first sub-barrier layer 31, and the second sub-barrier layer 32 covers the area of the first sub-barrier layer 31 where no virtual gate 110 is disposed; wherein, the barrier layer 30 includes the first sub-barrier layer 31 and the second sub-barrier layer 32.
[0101] A strain material layer 401 is disposed on the side of the virtual gate 110 away from the substrate structure 10, and the strain material layer 401 covers the virtual gate 110 and the second sub-barrier layer 32.
[0102] A source trench 41, a drain trench 42, a source 50, and a drain 60 are provided in the strain material layer 401;
[0103] Remove the strain material layer 401 from the surface of the virtual gate 110 to form a strain layer 40 with a first sub-groove 431;
[0104] Remove the dummy gate 110 to form a second sub-groove 432; wherein, the gate trench 43 includes a first sub-groove 431 and a second sub-groove 432;
[0105] A gate structure 70 is formed within the gate trench 43.
[0106] For details, please refer to Figure 7 First, a channel layer 20 and a first sub-barrier layer 31 are formed on the surface of the substrate structure 10. The first sub-barrier layer 31 is made of AlGaN material. (Reference) Figure 8 and Figure 9 A sacrificial layer 100 with an opening 101 is formed on the surface of the first sub-barrier layer 31. Along the direction of the substrate structure 10 pointing to the sacrificial layer 100, the opening 101 gradually increases in the fourth dimension W along a preset direction. For example, along the direction of the substrate structure 10 pointing to the sacrificial layer 100, the opening 101 increases linearly in the fourth dimension W along the preset direction. The longitudinal section of the opening 101 can be an inverted trapezoid, which is the section perpendicular to the surface of the substrate structure 10 where the channel layer 20 is provided.
[0107] refer to Figure 10 and Figure 11 The opening 101 is filled with silicon material, and the sacrificial layer 100 is removed to form the desired shape. Figure 11 The virtual gate 110 is shown. (Reference) Figure 12 A second sub-barrier layer 32 is formed on the surface of the first sub-barrier layer 31, and the second sub-barrier layer 32 is made of the same material as the first sub-barrier layer 31. The dummy gate 110 has the same opening size as the sacrificial layer. Along the direction from the substrate structure 10 to the dummy gate 110, the fifth dimension S of the dummy gate 110 gradually increases along a predetermined direction, so that the second sub-barrier layer 32 can grow more fully at the angle formed between the dummy gate 110 and the first sub-barrier layer 31.
[0108] refer to Figure 13 A strain material layer 401 is formed on the surfaces of the second sub-barrier layer 32 and the dummy gate 110, covering the second sub-barrier layer 32 and the dummy gate 110. (See reference...) Figure 14 A source trench 41 and a drain trench 42 are formed in the strained material layer 401 by an etching process. The source trench 41 and the drain trench 42 penetrate the strained material layer 401. A source 50 is formed in the source trench 41, and a drain 60 is formed in the drain trench 42. The source trench 41 and the drain trench 42 may penetrate only the strained material layer 401, or they may penetrate the strained material layer 401 and extend into or through the barrier layer 30.
[0109] refer to Figure 15 A third insulating material layer 810 is formed on the surface of the source electrode 50 and the drain electrode 60, and the third insulating material layer 810 covers the source electrode 50, the drain electrode 60 and the strain material layer 401.
[0110] refer to Figure 16 and Figure 17The third insulating material layer 810 and the strain material layer 401 covering the surface of the virtual gate 110 can be etched using a dry etching process to expose the virtual gate 110. Afterward, the virtual gate 110 can be wet-etched. Since the fifth dimension S of the virtual gate 110 gradually increases along the preset direction from the substrate structure 10 towards the virtual gate 110, the etching process window for the strain material layer 401 can be set according to the fifth dimension S on the side of the virtual gate 110 away from the substrate structure 10, ensuring that the strain material layer 401 can expose the virtual gate 110. After exposing the virtual gate 110, since the fifth dimension S of the virtual gate 110 gradually increases along the preset direction from the substrate structure 10 towards the virtual gate 110, the phenomenon of inward shrinkage of the gate trench 43 will not occur after etching the virtual gate 110. This avoids insufficient filling of the gate structure at the corner of the gate trench 43, which could affect device performance. Furthermore, by etching the virtual gate 110 and the strain material layer 401 in stages, there will be no situation where the etching opening is too large and damages the second sub-barrier layer 32.
[0111] refer to Figure 17 A first insulating material layer 710, a gate material layer 720, and a second insulating material layer 820 are formed in the gate trench 43. The first insulating material layer 710, the gate material layer 720, and the second insulating material layer 820 are etched to form a first insulating layer 71, a gate 72, and a second insulating layer 82.
[0112] This embodiment forms an inverted trapezoidal virtual gate on the surface of the first sub-barrier layer, allowing for more complete growth of the second sub-barrier layer grown on the surface of the first sub-barrier layer. This ensures a high two-dimensional electron gas concentration in the region near the gate, reducing device resistance. Furthermore, by forming the inverted trapezoidal virtual gate and step-by-step etching of the strain material layer on the virtual gate surface to form a gate trench, it avoids the problem of insufficient gate filling due to inward shrinkage at the trench corners caused by excessively small gate trenches, and also avoids damage to the second sub-barrier layer caused by excessively large gate trenches, thus improving device performance.
[0113] Based on the above embodiments, optionally, refer to Figure 3 , Figure 16 and Figure 17 The strain material layer 401 on the surface of the dummy gate 110 is removed to form a strain layer 40 with a first sub-groove 431, including:
[0114] The strain material layer 401 on the surface of the virtual gate 110 is removed by dry etching;
[0115] Removing the dummy gate 110 to form the second sub-groove 432 includes: removing the dummy gate 110 by wet etching.
[0116] Specifically, the strain material layer 401 may be made of aluminum nitride, which can be etched using dry etching to form a first sub-groove 431 with an inverted trapezoidal longitudinal section, the longitudinal section being perpendicular to the surface of the trench layer 20 on the substrate structure 10. The first sub-groove 431 completely exposes the virtual gate 110. The bottom dimension of the first sub-groove 431 along a preset direction can be greater than the maximum value of the fifth dimension S of the virtual gate 110, thereby providing a larger process window when etching the virtual gate 110, making the etching process easier to control.
[0117] refer to Figure 5 In related technologies, the strain material layer 401 and the trapezoidal dummy gate 02 are first etched using dry etching, and then the trapezoidal dummy gate 02 that was not removed by dry etching is etched using wet etching. In related technologies, to avoid forming recessed grooves at the corners of the gate trench 43, the remaining thickness of the trapezoidal dummy gate 02 after dry etching is generally small, around 200 Å. This small thickness makes it easy to damage the second sub-barrier layer 32 during dry etching. In this embodiment, the strain material layer 401 on the surface of the dummy gate 110 is removed by dry etching, and the dummy gate 110 is removed by wet etching, thus avoiding damage to the second sub-barrier layer 32 during dry etching.
[0118] Based on the above embodiments, optionally, refer to Figure 9 and Figure 10 A sacrificial layer 100 is disposed on the surface of the first sub-barrier layer 31 away from the channel layer 20, comprising:
[0119] A barrier material layer 11 is disposed on the surface of the first sub-barrier layer 31 away from the channel layer 20;
[0120] A sacrificial material layer 12 is disposed on the surface of the barrier material layer 11;
[0121] A third sub-groove is formed by dry etching the patterned sacrificial material layer 12;
[0122] The barrier material layer 11 is patterned by wet etching to form a fourth sub-groove penetrating the barrier material layer 11; wherein the opening 101 includes a third sub-groove and a fourth sub-groove.
[0123] The sacrificial layer 100 includes a barrier layer 111 and a sub-sacrificial layer 121. The barrier layer 111 is the patterned barrier material layer 11, and the sub-sacrificial layer 121 is the patterned sacrificial material layer 12. The barrier material layer 11 protects the first sub-barrier layer 31 from damage during dry etching of the sacrificial material layer 12. After the sacrificial material layer 12 is patterned to form the sub-sacrificial layer 121, the barrier material layer 11 is etched using a wet etching process without damaging the first sub-barrier layer 31. For example, the barrier material layer 11 can be made of materials such as aluminum nitride.
[0124] Based on the above embodiments, optionally, the material of the virtual gate 110 includes silicon, the material of the sacrificial material layer 12 includes silicon oxide, and the material of the barrier material layer 11 includes aluminum nitride or aluminum oxide.
[0125] Specifically, the dummy gate 110 can also be made of materials other than silicon, as long as the etching solution does not damage the second sub-barrier layer 32 and the strain layer 40 during wet etching of the dummy gate 110. Using aluminum nitride or aluminum oxide as the barrier material layer 11 can provide good protection for the second sub-barrier layer 32 during dry etching of the sacrificial material layer 12, and the etching solution will not damage the second sub-barrier layer 32 when removing aluminum nitride or aluminum oxide by wet etching.
[0126] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0127] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate structure; a channel layer disposed on one side of the substrate structure; a barrier layer disposed on a side of the channel layer away from the substrate structure; a strain layer disposed on a side of the barrier layer away from the channel layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in a direction pointing to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; in the direction pointing to the strain layer along the substrate structure, the first dimension of the gate trench in a preset direction gradually increases; the angle between the sidewall of the gate trench and the bottom of the gate trench is greater than 90 degrees; wherein the preset direction is parallel to the surface of the substrate structure provided with the channel layer; a source electrode, a drain electrode and a gate structure; the source electrode is disposed in the source trench, the drain electrode is disposed in the drain trench, and the gate structure is disposed in the gate trench.
2. The semiconductor device according to claim 1, wherein: the angle between the sidewall of the gate trench and the bottom of the gate trench is greater than or equal to 95 degrees and less than or equal to 120 degrees.
3. The semiconductor device according to claim 1, wherein: the gate trench comprises a first sub-trench and a second sub-trench in communication with each other, and the first sub-trench is disposed on a side of the second sub-trench away from the substrate structure; the minimum dimension of the first sub-trench in the preset direction is greater than the maximum dimension of the second sub-trench in the preset direction.
4. The semiconductor device according to claim 3, wherein: the sidewall of the first sub-trench and the sidewall of the second sub-trench are connected through the bottom of the first sub-trench, the bottom of the first sub-trench has a second dimension in the preset direction, and the bottom of the gate trench has a third dimension in the preset direction; the ratio of the second dimension to the third dimension is greater than or equal to one-tenth and less than or equal to one-fifth.
5. The semiconductor device according to claim 1, wherein: the gate structure comprises a first insulating layer and a gate electrode, the first insulating layer covers the sidewall and the bottom of the gate trench, and the gate electrode is disposed on a surface of the first insulating layer away from the sidewall and the bottom of the gate trench; the semiconductor device further comprises a second insulating layer and a third insulating layer; the second insulating layer is disposed on a side of the gate structure away from the substrate structure, and the second insulating layer covers the gate structure; and the third insulating layer is disposed on a side of the source electrode away from the substrate structure, and the third insulating layer covers the source electrode and the drain electrode.
6. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate structure; disposing a channel layer on one side of the substrate structure; disposing a barrier layer, a strain layer, a source electrode, a drain electrode and a gate structure on a side of the channel layer away from the substrate structure; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in a direction pointing to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; in the direction pointing to the strain layer along the substrate structure, the first dimension of the gate trench in a preset direction gradually increases; the angle between the sidewall of the gate trench and the bottom of the gate trench is greater than 90 degrees; wherein the preset direction is parallel to the surface of the substrate structure provided with the channel layer; a source electrode, a drain electrode and a gate structure; the source electrode is disposed in the source trench, the drain electrode is disposed in the drain trench, and the gate structure is disposed in the gate trench.
2. The semiconductor device according to claim 1, wherein: the angle between the sidewall of the gate trench and the bottom of the gate trench is greater than or equal to 95 degrees and less than or equal to 120 degrees.
3. The semiconductor device according to claim 1, wherein: the gate trench comprises a first sub-trench and a second sub-trench in communication with each other, and the first sub-trench is disposed on a side of the second sub-trench away from the substrate structure; the minimum dimension of the first sub-trench in the preset direction is greater than the maximum dimension of the second sub-trench in the preset direction.
4. The semiconductor device according to claim 3, wherein: the sidewall of the first sub-trench and the sidewall of the second sub-trench are connected through the bottom of the first sub-trench, the bottom of the first sub-trench has a second dimension in the preset direction, and the bottom of the gate trench has a third dimension in the preset direction; the ratio of the second dimension to the third dimension is greater than or equal to one-tenth and less than or equal to one-fifth.
5. The semiconductor device according to claim 1, wherein: the gate structure comprises a first insulating layer and a gate electrode, the first insulating layer covers the sidewall and the bottom of the gate trench, and the gate electrode is disposed on a surface of the first insulating layer away from the sidewall and the bottom of the gate trench; the semiconductor device further comprises a second insulating layer and a third insulating layer; the second insulating layer is disposed on a side of the gate structure away from the substrate structure, and the second insulating layer covers the gate structure; and the third insulating layer is disposed on a side of the source electrode away from the substrate structure, and the third insulating layer covers the source electrode and the drain electrode. The strain layer is arranged on a side of the barrier layer away from the channel layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in a direction of the strain layer pointing to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; in the direction of the substrate structure pointing to the strain layer, a first size of the gate trench in a preset direction gradually increases; an angle between a side wall of the gate trench and a bottom of the gate trench is greater than 90 degrees; the preset direction is parallel to a surface of the substrate structure provided with the channel layer; the source is arranged in the source trench, the drain is arranged in the drain trench, and the gate structure is arranged in the gate trench.
7. The method of producing a semiconductor device according to claim 6, wherein The barrier layer, the strain layer, the source, the drain and the gate structure are arranged on a side of the channel layer away from the substrate structure, and the method comprises the following steps of: A first sub-barrier layer is arranged on a side of the channel layer away from the substrate structure; A sacrificial layer is arranged on a surface of the first sub-barrier layer away from the channel layer; the sacrificial layer comprises an opening, and a fourth size of the opening in the preset direction gradually increases in a direction of the substrate structure pointing to the sacrificial layer; A virtual gate is arranged in the opening, and the virtual gate fills the opening; The sacrificial layer is removed; A second sub-barrier layer is arranged on a surface of the first sub-barrier layer; the second sub-barrier layer covers a region of the first sub-barrier layer in which the virtual gate is not arranged, and the barrier layer comprises the first sub-barrier layer and the second sub-barrier layer; A strain material layer is arranged on a side of the virtual gate away from the substrate structure, and the strain material layer covers the virtual gate and the second sub-barrier layer; A source trench, a drain trench, a source and a drain are arranged in the strain material layer; The strain material layer on a surface of the virtual gate is removed, and the strain layer with a first sub-trench is formed; The virtual gate is removed, and a second sub-trench is formed; the gate trench comprises the first sub-trench and the second sub-trench; The gate structure is formed in the gate trench.
8. The method according to claim 7, wherein: The strain material layer on the surface of the virtual gate is removed to form the strain layer with the first sub-trench, which comprises removing the strain material layer on the surface of the virtual gate by dry etching; The virtual gate is removed to form the second sub-trench, which comprises removing the virtual gate by wet etching; The minimum size of the first sub-trench in the preset direction is greater than the maximum size of the second sub-trench in the preset direction.
9. The method of producing a semiconductor device according to Claim 7, wherein The sacrificial layer is arranged on the surface of the first sub-barrier layer away from the channel layer, which comprises: A barrier material layer is arranged on the surface of the first sub-barrier layer away from the channel layer; A sacrificial material layer is arranged on the surface of the barrier material layer; The sacrificial material layer is patterned by dry etching to form a third sub-trench penetrating the sacrificial material layer; The barrier material layer is patterned by wet etching to form a fourth sub-groove penetrating through the barrier material layer; wherein the opening comprises the third sub-groove and the fourth sub-groove, and the sacrificial layer comprises the patterned barrier material layer and the patterned sacrificial material layer.
10. The method of claim 9, wherein: The material of the dummy gate comprises silicon, the material of the sacrificial material layer comprises silicon oxide, and the material of the barrier material layer comprises aluminum nitride or aluminum oxide.