Power device for improving dynamic avalanche robustness and preparation method

Abstract

The invention discloses a power device for improving dynamic avalanche robustness and a preparation method, and relates to the technical field of power half devices, the power device comprises a semiconductor substrate, an active region prepared in the central region of the semiconductor substrate and a terminal region surrounding the active region; the terminal region comprises a terminal protection ring of a second conductive type prepared in the semiconductor substrate, an oxide layer arranged above the semiconductor substrate and a terminal first electrode metal region; on the cross section of the power device, the terminal first electrode metal region is arranged above one end, far away from the active region, of the terminal protection ring, a large contact hole or a plurality of small contact holes which are arranged at intervals are formed below the terminal first electrode metal region, and the large contact hole and the small contact holes penetrate through the oxide layer and extend into the terminal protection ring; the contact large hole and the contact small holes are filled with metal, and the terminal protection ring is electrically connected with the terminal first electrode metal area through the metal in the contact large hole or the contact small holes. The device can improve the dynamic avalanche robustness.

Description

Technical Field

[0001] This invention relates to the field of power device technology, and in particular to a power device and its fabrication method for improving dynamic avalanche robustness. Background Technology

[0002] The higher the voltage level of a power device, the lower the doping concentration and the greater the thickness of its N-drift region, and the wider the termination. This makes the device particularly sensitive to dynamic avalanche when turned off, which is a side effect of the structural characteristics it adopts to achieve high withstand voltage.

[0003] like Figure 1 As shown, when the high-voltage device is turned off, the cells near the terminal protection ring not only have to withstand holes injected from the bottom of the corresponding cell region, but also holes injected from the bottom of the chip corresponding to the terminal protection ring region. According to the Poisson equation:

[0004] in, q For charge quantity, N D The doping concentration in the drift region, ε s Dielectric constant, p Hole concentration, n For electron concentration, the higher the voltage of the device, the lower the doping concentration of the N-drift region, the larger the thickness of the N-drift region, and the wider the termination width (the hole injected at the bottom of the chip corresponding to the termination guard ring region). p termianal (The higher the voltage, the greater the cellular electric field near the terminal when the device is turned off, and the more likely dynamic avalanche will occur.) Summary of the Invention

[0005] To address the aforementioned problems and technical needs, the inventors have proposed a power device and its fabrication method for improving dynamic avalanche robustness. The technical solution of this invention is as follows: A power device for improving dynamic avalanche robustness includes a semiconductor substrate of a first conductivity type, an active region fabricated in the central region of the semiconductor substrate, and a terminal region surrounding the active region. The terminal region includes a terminal protection ring of the second conductivity type formed in the semiconductor substrate, an oxide layer disposed above the semiconductor substrate, and a terminal first electrode metal region disposed above the oxide layer. On the cross-section of the power device, the terminal first electrode metal region is located above the end of the terminal protection ring away from the active region, and a large contact hole or multiple small contact holes spaced apart are provided below the terminal first electrode metal region. The large contact hole and the small contact holes penetrate the oxide layer and extend into the terminal protection ring. The contact large hole and contact small hole are filled with metal, and the terminal protection ring is electrically connected to the terminal first electrode metal area through the metal in the contact large hole or multiple contact small holes.

[0006] A further technical solution is that the active region includes an active first electrode metal region disposed above the semiconductor substrate, and the active first electrode metal region extends from the active region to the terminal region. On the cross-section of the power device, the active first electrode metal region extending to the terminal region overlaps with the end of the terminal protection ring near the active region.

[0007] A further technical solution is that a first contact hole is provided below the active first electrode metal region extending to the terminal region. The first contact hole penetrates the oxide layer and extends into the terminal protection ring. The first contact hole is filled with metal, and the terminal protection ring is electrically connected to the active first electrode metal region through the metal in the first contact hole.

[0008] A further technical solution is that the diameter of the large contact hole is larger than the diameter of the small contact hole.

[0009] A further technical solution is that the diameter of the contact aperture ranges from 5 to 8 μm.

[0010] A further technical solution is that the oxide layer includes an insulating protective layer and a passivation layer located above the insulating protective layer.

[0011] A further technical solution is that a second electrode metal region is provided between the active first electrode metal region and the terminal first electrode metal region above the oxide layer, and a polysilicon bus is provided below the second electrode metal region. The polysilicon bus is isolated from the semiconductor substrate by an insulating protective layer, and the passivation layer covers the polysilicon bus. A second contact hole is provided in the passivation layer above the polysilicon bus. The second contact hole penetrates the passivation layer above the polysilicon bus and is filled with metal. The second electrode metal region is electrically connected to the polysilicon bus through the metal filled in the second contact hole.

[0012] A further technical solution is that a polycrystalline silicon field plate is provided below the metal region of the second electrode of the terminal. The polycrystalline silicon field plate is isolated from the semiconductor substrate by an insulating protective layer, and the passivation layer covers the polycrystalline silicon field plate. A third contact hole is provided in the passivation layer above the polycrystalline silicon field plate. The third contact hole penetrates the passivation layer above the polycrystalline silicon field plate and is filled with metal. The terminal first electrode metal area is electrically connected to the polycrystalline silicon field plate through the metal filled in the third contact hole.

[0013] A further technical solution is that, on the cross-section of the power device, the edge of the polycrystalline silicon field plate overlaps with the edge of the terminal protection ring on the side away from the active region.

[0014] A method for fabricating a power device with improved dynamic avalanche robustness, the method comprising: A semiconductor substrate of a first conductivity type is provided, and a terminal protection ring of a second conductivity type is formed in the terminal region of the semiconductor substrate and an oxide layer is formed on the top of the semiconductor substrate. Large contact holes or multiple spaced small contact holes are etched in the oxide layer above the terminal protection ring. The large contact holes and small contact holes penetrate the oxide layer and extend into the terminal protection ring. Metal is filled into the contact large hole or contact small hole, and a terminal first electrode metal region is prepared above the contact large hole or contact small hole. On the cross-section of the power device, the terminal first electrode metal region is disposed above the end of the terminal protection ring away from the active region. The terminal protection ring is electrically connected to the terminal first electrode metal region through the metal in the contact large hole or multiple contact small holes.

[0015] For N-type power devices, the first conductivity type refers to N-type and the second conductivity type refers to P-type; for P-type power devices, the first conductivity type and the second conductivity type refer to the opposite types as those for N-type devices.

[0016] The beneficial technical effects of this invention are: By photolithographically etching a large contact hole (5~8µm) or multiple (2~8) small contact holes (with the same aperture as the cell region) on the outer side of the terminal guard ring (the end away from the active region), the hole discharge path in the terminal region is increased, and the high electric field generated by the holes injected from the bottom of the chip corresponding to the terminal guard ring region is reduced in the active region near the terminal region, thereby improving the dynamic avalanche robustness of the device. Attached Figure Description

[0017] Figure 1 This is a cross-sectional schematic diagram of an embodiment of a conventional power device provided by the present invention.

[0018] Figure 2 This is a cross-sectional schematic diagram of an embodiment of the power device for improving dynamic avalanche robustness provided by the present invention.

[0019] Figures 3-5 This is a cross-sectional schematic diagram of the process steps of an embodiment of the power device fabrication method for improving dynamic avalanche robustness provided by the present invention, wherein, Figure 3This is a cross-sectional schematic diagram of one embodiment of the terminal protection ring and other terminal structures prepared by the present invention.

[0020] Figure 4 This is a cross-sectional schematic diagram of one embodiment of the present invention after hole etching.

[0021] Figure 5 This is a cross-sectional schematic diagram of one embodiment of the third electrode metal region prepared according to the present invention.

[0022] Figure label: 1-Semiconductor substrate, 2-Terminal protection ring, 3-Terminal first electrode metal region, 4-Contact macrohole, 5-Active first electrode metal region, 6-First contact hole, 7-Insulating protective layer, 8-Passivation layer, 9-Second electrode metal region, 10-Polysilicon bus, 11-Second contact hole, 12-Polysilicon field plate, 13-Third contact hole, 14-P-type collector region. Detailed Implementation

[0023] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0024] The present invention provides a power device for improving dynamic avalanche robustness. Taking N-type as an example, it includes a semiconductor substrate 1 with N-type conductivity, an active region prepared in the central region of the semiconductor substrate 1, and a terminal region surrounding the active region (Cell region). like Figure 2 As shown, the terminal region includes a P-type terminal protection ring 2 fabricated in the semiconductor substrate 1, an oxide layer disposed above the semiconductor substrate, and a terminal first electrode metal region 3 disposed above the oxide layer. The terminal protection ring 2 surrounds the active region. On the cross-section of the power device, the terminal first electrode metal region 3 is located above the end of the terminal protection ring 2 away from the active region. Below the terminal first electrode metal region 3, there is a contact large hole 4 or a plurality of contact small holes spaced apart. The contact large hole 4 and the contact small holes penetrate the oxide layer and extend vertically into the terminal protection ring 2. The contact large hole 4 and the contact small holes are filled with metal. The terminal protection ring 2 is electrically connected to the terminal first electrode metal region 3 through the metal in the contact large hole 4 or the plurality of contact small holes.

[0025] Specifically, the metal filling the contact large hole 4 / contact small hole contacts the upper terminal first electrode metal region 3 and makes ohmic contact with the terminal protection ring 2, thereby electrically connecting the terminal protection ring 2 and the terminal first electrode metal region 3. The diameter of the contact large hole 4 is larger than the diameter of the contact small hole, and the diameter of the contact large hole ranges from 5-8 μm. The number of contact small holes can be 2-8. The active region contains several parallelly distributed cells, which can be trench cells, planar cells, or planar-trench combined cells, etc., and their specific forms are not limited in this invention. The cell structure usually has contact holes to connect with the corresponding metal region on the semiconductor substrate 1. The diameter of the contact small hole can be consistent with the diameter of the contact hole in the cell structure. The specific functions and distribution of the active region and the terminal protection zone can be consistent with existing technologies. The semiconductor substrate 1 can use existing commonly used materials, such as silicon substrates or SiC substrates, to meet application requirements.

[0026] By photolithographically etching a large contact hole 4 or multiple small contact holes on the outer side of the terminal protection ring (the end away from the active region), the hole discharge path in the terminal region can be increased, and the high electric field generated by the holes injected from the bottom of the chip corresponding to the terminal protection ring 2 region near the terminal region can be reduced, thereby effectively improving the dynamic avalanche robustness of the device.

[0027] Further, the active region includes an active first electrode metal region 5 disposed above the semiconductor substrate 1, which extends laterally from the active region to the terminal region. In the cross-section of the power device, the active first electrode metal region 5 extending to the terminal region overlaps with the end of the terminal protection ring 2 near the active region. Specifically, this overlap refers to the projection of the active first electrode metal region 5 onto the terminal protection ring 2 overlapping with the terminal protection ring 2. A first contact hole 6 is disposed below the active first electrode metal region 5 extending to the terminal region. The first contact hole 6 penetrates the oxide layer and extends vertically into the terminal protection ring 2. The first contact hole 6 is filled with metal, which contacts the active first electrode metal region 5 and makes ohmic contact with the terminal protection ring 2. Thus, the terminal protection ring 2 is electrically connected to the active first electrode metal region 5 through the metal in the first contact hole 6. The first contact hole 6 also provides a hole discharge path for the terminal region.

[0028] Furthermore, the oxide layer includes an insulating protective layer 7 and a passivation layer 8 located above the insulating protective layer 7. A second electrode metal region 9 is disposed between the active first electrode metal region 5 and the terminal first electrode metal region 3 above the oxide layer. A polysilicon bus 10 is disposed below the second electrode metal region 9. The polysilicon bus 10 is isolated from the semiconductor substrate 1 by the insulating protective layer 7, and the passivation layer 8 covers the polysilicon bus 10. A second contact hole 11 is provided in the passivation layer 8 above the polysilicon bus 10. The second contact hole 11 penetrates the passivation layer 8 above the polysilicon bus 10 and is filled with metal. The second electrode metal region 9 is electrically connected to the polysilicon bus 10 through the metal filled in the second contact hole 11. The polysilicon bus 10 is connected to the gate polysilicon in the cell structure of the active region.

[0029] Below the metal region 3 of the second electrode of the terminal, a polysilicon field plate 12 is also provided. The polysilicon field plate 12 is isolated from the semiconductor substrate 1 by an insulating protective layer 7, and the passivation layer 8 covers the polysilicon field plate 12. A third contact hole 13 is provided within the passivation layer 8 above the polysilicon field plate 12. The third contact hole 13 penetrates the passivation layer 8 above the polysilicon field plate 12 and is filled with metal. The terminal first electrode metal region 3 is electrically connected to the polysilicon field plate 12 through the metal filled in the third contact hole 13. In the cross-section of the power device, the edge of the terminal first electrode metal region 3 away from the active region is flush with the edge of the polysilicon field plate 12 away from the active region. The polysilicon field plate 12 overlaps with the edge of the terminal protection ring 2 away from the active region, that is, the projection of the polysilicon field plate 12 onto the terminal protection ring 2 overlaps with the edge of the terminal protection ring 2 away from the active region. The diameters of the first to third contact holes can all be consistent with the diameters of the contact holes provided in the cell structure.

[0030] Typically, a third electrode metal region is also provided on the back side of the semiconductor substrate 1, and the power device can be formed as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) type device or an IGBT (Insulated Gate Bipolar Transistor) type device. For a MOSFET type device, the first electrode is the source, the second electrode is the gate, and the third electrode is the drain; for an IGBT type device, the first electrode is the emitter, the second electrode is the gate, and the third electrode is the collector.

[0031] It should be noted that the semiconductor substrate 1 includes an N-type substrate and an N-type drift region fabricated on the N-type substrate, and the termination guard ring 2 is disposed within the N-type drift region. In addition to the termination guard ring 2, other termination structures can be formed in the termination region to improve the device's withstand voltage, such as... Figure 2 As shown, in this embodiment, an FLR terminal structure is formed in the terminal area. That is, multiple floating field limiting rings are also set on the side of the terminal protection ring 2 away from the active area. In specific implementation, the terminal structure includes, but is not limited to, JTE, VLD, multi-level JTE, FLR and VLD or JTE composite terminal, etc.

[0032] This invention also provides a method for fabricating a power device with improved dynamic avalanche robustness, used to fabricate the aforementioned power device with improved dynamic avalanche robustness, the fabrication method comprising: An N-type semiconductor substrate 1 is provided, and a P-type terminal protection ring 2 disposed within the semiconductor substrate 1 and an oxide layer disposed above the semiconductor substrate 1 are prepared in the terminal region of the semiconductor substrate 1. A large contact hole 4 or multiple small contact holes spaced apart are etched in the oxide layer above the terminal protection ring 2. The large contact holes and small contact holes penetrate the oxide layer and extend into the terminal protection ring 2. Metal is filled into the contact large hole 4 or contact small hole, and a terminal first electrode metal region 3 is prepared above the contact large hole 4 or contact small hole. On the cross-section of the power device, the terminal first electrode metal region 3 is disposed above the end of the terminal protection ring 2 away from the active region. The terminal protection ring 2 is electrically connected to the terminal first electrode metal region 3 through the metal in the contact large hole 4 or multiple contact small holes.

[0033] Specifically, the power device is fabricated by sequentially performing front-side and back-side processes. The following explanation uses an IGBT as an example to illustrate the fabrication method for power devices with improved dynamic avalanche robustness: Please refer to Figure 3 An N-type substrate is provided, and an N-type epitaxial layer is grown on the N-type substrate to form an N-type drift region. The N-type substrate and the N-type drift region form a semiconductor substrate. A terminal protection ring 2 and other terminal structures (taking multiple floating field limiting rings as an example) are obtained by implantation in the N-type drift region of the terminal region.

[0034] Please refer to Figure 4 In the active region, a partially doped region in the cell structure is prepared. Then, an oxide layer is deposited on the semiconductor substrate 1 to form an insulating protective layer 7, and a polysilicon layer is deposited on the oxide layer. The polysilicon layer in the active region and the terminal region is etched. A polysilicon bus 10 and a polysilicon field plate 12 are formed in the terminal region, and a planar gate polysilicon is formed in the active region. An oxide layer is deposited again on the front side of the semiconductor substrate 1 to form a passivation layer 8, and hole etching is performed. The hole etching includes etching a first contact hole 6, a second contact hole 11, a third contact hole 13, and a contact macrohole 4 in the terminal region, and etching a source region contact hole in the active region. Subsequently, the doped region of the cell structure in the active region is fabricated using the source region contact hole. The doped region structure of the cell structure is consistent with the prior art, and the specific positions and forms of the first contact hole 6, the second contact hole 11, the third contact hole 13, and the contact macrohole 4 are consistent with those described above, and will not be repeated here.

[0035] Please refer to Figure 5Metal is deposited on the front side of the semiconductor substrate 1 and within each of the aforementioned contact holes. The metal on the front side of the semiconductor substrate 1 is etched to fabricate the active first electrode metal region 5, the second electrode metal region 9, and the terminal first electrode metal region 3. The active first electrode metal region 5, the second electrode metal region 9, and the terminal first electrode metal region 3 are electrically connected to the doped region within the cell structure, the terminal guard ring 2, the polysilicon bus 10, the terminal guard ring 2, and the polysilicon field plate 12 through the metal filled in the corresponding contact holes, thus completing the front-side process. The distribution positions of the active first electrode metal region 5, the second electrode metal region 9, and the terminal first electrode metal region 3 are consistent with those described above and will not be repeated here. Subsequently, the back-side process is performed, where a P-type collector region 14 is implanted on the back side of the semiconductor substrate 1 and a third electrode metal region (not shown in the figure) is deposited to complete the fabrication of the IGBT device.

[0036] In the description of this specification, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0037] The use of terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example, which is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0038] In the description of this application, if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0039] It should be noted that, in this application, unless otherwise explicitly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact, or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0040] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A power device with improved dynamic avalanche robustness, characterized in that, The power device comprises a semiconductor substrate of a first conductivity type, an active region prepared in a central region of the semiconductor substrate, and a termination region surrounding the active region; The termination region comprises a termination guard ring of a second conductivity type prepared in the semiconductor substrate, an oxide layer disposed above the semiconductor substrate, and a termination first electrode metal region disposed above the oxide layer; In a cross-section of the power device, the termination first electrode metal region is disposed above one end of the termination guard ring away from the active region, and a contact large hole or a plurality of contact small holes spaced apart is disposed below the termination first electrode metal region, the contact large hole and the contact small holes penetrating through the oxide layer and extending into the termination guard ring; The contact large hole and the contact small holes are filled with metal, and the termination guard ring is electrically connected to the termination first electrode metal region through the metal in the contact large hole or the plurality of contact small holes.

2. The power device with improved dynamic avalanche robustness of claim 1, wherein, The active region comprises an active first electrode metal region disposed above the semiconductor substrate, and the active first electrode metal region extends to the termination region; In a cross-section of the power device, the active first electrode metal region extending to the termination region overlaps with one end of the termination guard ring close to the active region.

3. The power device with improved dynamic avalanche robustness of claim 2, wherein, A first contact hole is disposed below the active first electrode metal region extending to the termination region, the first contact hole penetrating through the oxide layer and extending into the termination guard ring, the first contact hole is filled with metal, and the termination guard ring is electrically connected to the active first electrode metal region through the metal in the first contact hole.

4. The power device with improved dynamic avalanche robustness of claim 1, wherein, The diameter of the contact large hole is greater than the diameter of the contact small hole.

5. The power device with improved dynamic avalanche robustness of claim 4, wherein, The diameter of the contact large hole ranges from 5 to 8 μm.

6. The power device with improved dynamic avalanche robustness of claim 2, wherein, The oxide layer comprises an insulating protective layer and a passivation layer above the insulating protective layer.

7. The power device with improved dynamic avalanche robustness of claim 6, wherein, A second electrode metal region is disposed between the active first electrode metal region and the termination first electrode metal region above the oxide layer, a polysilicon bus is disposed below the second electrode metal region, the polysilicon bus is isolated from the semiconductor substrate by the insulating protective layer, and the passivation layer covers the polysilicon bus; A second contact hole is disposed in the passivation layer above the polysilicon bus, the second contact hole penetrates through the passivation layer above the polysilicon bus, the second contact hole is filled with metal, and the second electrode metal region is electrically connected to the polysilicon bus through the metal filled in the second contact hole.

8. The power device with improved dynamic avalanche robustness of claim 6, wherein, A polysilicon field plate is further disposed below the termination second electrode metal region, the polysilicon field plate is isolated from the semiconductor substrate by the insulating protective layer, and the passivation layer covers the polysilicon field plate; A third contact hole is disposed in the passivation layer above the polysilicon field plate, the third contact hole penetrates through the passivation layer above the polysilicon field plate, the third contact hole is filled with metal, and the termination first electrode metal region is electrically connected to the polysilicon field plate through the metal filled in the third contact hole.

9. The power device with improved dynamic avalanche robustness of claim 8, wherein, In a cross-section of the power device, the polysilicon field plate overlaps with an edge of the termination guard ring away from the active region.

10. A method for fabricating a power device with improved dynamic avalanche robustness, characterized in that, A method for preparing the power device with improved dynamic avalanche robustness according to any one of claims 1-9, the method comprising: providing a semiconductor substrate of a first conductivity type, preparing a termination guard ring of a second conductivity type disposed in the semiconductor substrate and an oxide layer disposed above the semiconductor substrate in a termination region of the semiconductor substrate; etching a contact large hole or a plurality of contact small holes arranged at intervals in the oxide layer above the terminal protection ring, the contact large hole and the contact small holes penetrating the oxide layer and extending into the terminal protection ring; filling the contact large hole or the contact small holes with metal, and preparing a terminal first electrode metal region above the contact large hole or the contact small holes, the terminal first electrode metal region being arranged above an end of the terminal protection ring away from the active region in a cross section of the power device, the terminal protection ring being electrically connected with the terminal first electrode metal region through the metal in the contact large hole or the plurality of contact small holes.

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