Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a substrate; a first well having a first conductivity type; a second well disposed in the substrate and surrounded by the first well, the second well having a second conductivity type; a first doped region having a first conductivity type and a second doped region having a second conductivity type disposed in the first well; a third doped region disposed in the second well and having a second conductivity type; and a segmented gate, where the segmented gate includes a first gate electrode segment of the second conductivity type, a second gate electrode segment of the first conductivity type, and a third gate electrode segment of the first conductivity type, and where the first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment. According to the invention, the semiconductor device can be controlled to achieve expected on-resistance and off-capacitance through a segmented gate mode, the semiconductor device is suitable for different application scenes and requirements, and the universality and design flexibility of the semiconductor device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor devices. Background Technology

[0002] In recent years, with the increasing demand for high-voltage devices, research interest in high-voltage metal-oxide-semiconductor (MOS) transistors for use in high-voltage applications has grown significantly. High-voltage (HV) MOS devices are suitable for high-voltage environments, where the voltage may be higher than (but not limited to) the supply voltage of input / output (I / O) circuits. MOS devices, such as HVMOS (high-voltage metal-oxide-semiconductor field-effect transistor) devices, can be used as switches and are widely applied in audio output drivers, CPU (Central Processing Unit) power supplies, power management systems, AC / DC converters, LCD (Liquid Crystal Display) or plasma TV drivers, automotive electronic components, PC (personal computer) peripherals, small DC motor controllers, and other consumer electronics devices.

[0003] While existing semiconductor devices (such as MOS devices) and their manufacturing methods have met their intended uses, they are not entirely satisfactory in all aspects. For example, it is difficult to strike a balance between low on-resistance (Rdson) and low off-capacitance (Coff). Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor device to provide a smaller on-resistance (Rdson) and a lower off-resistance (Coff).

[0005] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first well disposed in the substrate and having a first conductivity type; a second well disposed in the substrate and surrounded by the first well and having a second conductivity type; a first doped region having a first conductivity type and a second doped region having a second conductivity type disposed in the first well, wherein the first doped region and the second doped region are separated from each other by a first isolation structure; a third doped region disposed in the second well and having a second conductivity type; and a segmented gate disposed on the first well and the second well, wherein the segmented gate includes a first gate electrode segment of the second conductivity type, a second gate electrode segment of the first conductivity type, and a third gate electrode segment of the first conductivity type, and wherein the first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment.

[0006] Furthermore, the first doped region serves as the body region or bulk region of the semiconductor device. This enables the realization of the components and functions of the high-voltage metal-oxide-semiconductor field-effect transistor and the laterally diffused metal-oxide-semiconductor field-effect transistor.

[0007] Furthermore, the second doped region serves as the source region of the semiconductor device. The third doped region serves as the drain region of the semiconductor device. This realizes the components and functions of a high-voltage metal-oxide-semiconductor field-effect transistor and a laterally diffused metal-oxide-semiconductor field-effect transistor.

[0008] Furthermore, the segmented gate includes a first work function metal of a first conductivity type and a second work function metal of a second conductivity type disposed on the first work function metal.

[0009] Furthermore, when the first conductivity type is p-type and the second conductivity type is n-type, the first work function metal includes TiN and the second work function metal includes TiAl; or when the first conductivity type is n-type and the second conductivity type is p-type, the first work function metal includes TiAl and the second work function metal includes TiN. This achieves segmented gates with different conductivity types.

[0010] Furthermore, the first work function metal of the first gate electrode segment has a first height, the first work function metal of the second gate electrode segment has a second height, and the first work function metal of the third gate electrode segment has a third height. The first height is lower than the second height, and the first height is lower than the third height. This achieves a segmented gate, different from conventional gates. The different gate electrode segments of this segmented gate can have different conductivity types to adjust and control the on-resistance and off-resistance, achieving the desired effect.

[0011] Furthermore, the second work function metal of the first gate electrode segment has a fourth height, the second work function metal of the second gate electrode segment has a fifth height, and the second work function metal of the third gate electrode segment has a sixth height, with the fourth height being higher than the fifth height and the sixth height being higher than the sixth height. Thus, the different gate electrode segments of this segmented gate can have different conductivity types to achieve adjustment and control of the on-resistance and off-resistance, achieving the desired effect.

[0012] Furthermore, the sum of the first height and the fourth height is equal to the sum of the second height and the fifth height, and the sum of the first height and the fourth height is equal to the sum of the third height and the sixth height. This ensures that the upper surface of the entire gate structure is flush, and the height of the entire gate structure is essentially uniform.

[0013] Furthermore, the first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, wherein the first width is greater than the second width, and the first width is also greater than the third width. This allows for the adjustment and control of the on-resistance and off-resistance by controlling the widths of different gate electrode segments, achieving the desired effect.

[0014] Furthermore, the first gate electrode segment of the segmented gate covers both the first well and the second well. The first gate electrode segment of the second conductivity type formed in this manner, simultaneously over both the first and second wells, enables control of the channel region, thereby achieving adjustment and control of the on-resistance and off-resistance, and achieving the desired effect.

[0015] Furthermore, the second gate electrode segment of the segmented gate covers the first well, and the third gate electrode segment of the segmented gate covers the second well.

[0016] Furthermore, the first interface between the first gate electrode segment and the second gate electrode segment of the segmented gate is directly located on the first well. In this way, different gate electrode segments are used to control different communication regions, thereby achieving adjustment and control of the on-resistance and off-resistance, achieving the desired effect.

[0017] Furthermore, the second interface between the first gate electrode segment and the third gate electrode segment of the segmented gate is directly located on the first well, the second well, or the third interface between the first well and the second well. In this way, different gate electrode segments are used to control the regional control of different communication regions, thereby achieving the adjustment and control of the on-resistance and off-resistance, and achieving the desired effect.

[0018] Furthermore, the second gate electrode segment of the segmented gate is adjacent to the second doped region, and the third gate electrode segment of the segmented gate is separated from the third doped region in a direction substantially parallel to the upper surface of the substrate. By using different gate electrode segments to control different communication regions, the on-resistance and off-resistance can be adjusted and controlled, achieving the desired effect.

[0019] Furthermore, it also includes a second isolation feature disposed in the second well and adjacent to the third doped region, wherein the segmented gate partially overlaps with the second isolation feature. In this way, different gate electrode segments are used to control the region control of different communication regions, thereby achieving adjustment and control of the on-resistance and off-resistance, achieving the desired effect.

[0020] Another embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first well disposed in the substrate having a first conductivity type; a first doped region and a second doped region disposed in the first well, wherein the first doped region and the second doped region are separated from each other by a portion of the first well; and a segmented gate disposed on the portion of the first well, wherein the segmented gate includes a first gate electrode segment of a second conductivity type, a second gate electrode segment of a first conductivity type, and a third gate electrode segment of a first conductivity type, and wherein the first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment.

[0021] Furthermore, this portion of the first well serves as the channel region of the semiconductor device. Thus, segmented gates are used to control the channel region, thereby enabling adjustment and control of the on-resistance and off-resistance to achieve the desired effect.

[0022] Furthermore, the segmented gate includes a first work function metal of a first conductivity type and a second work function metal of a second conductivity type disposed on the first work function metal. The first work function metal of the first gate electrode segment has a first height, the first work function metal of the second gate electrode segment has a second height, and the first work function metal of the third gate electrode segment has a third height. The first height is lower than the second height, and the first height is lower than the third height. Thus, different gate electrode segments of the segmented gate can have different conductivity types to achieve adjustment and control of the on-resistance and off-resistance, achieving the desired effect.

[0023] Furthermore, the first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, wherein the first width is greater than the second width, and the first width is also greater than the third width. This allows for the adjustment and control of the on-resistance and off-resistance by controlling the widths of different gate electrode segments, achieving the desired effect.

[0024] The semiconductor device of this invention includes: a substrate; a first well disposed in the substrate and having a first conductivity type; a second well disposed in the substrate and surrounded by the first well, having a second conductivity type; a first doped region having the first conductivity type and a second doped region having the second conductivity type, disposed in the first well, wherein the first doped region and the second doped region are separated from each other by a first isolation structure; a third doped region disposed in the second well and having the second conductivity type; and a segmented gate disposed on the first well and the second well, wherein the segmented gate includes a first gate electrode segment of the second conductivity type, a second gate electrode segment of the first conductivity type, and a third gate electrode segment of the first conductivity type, and wherein the first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment. In this invention, the segmented gate allows control of the semiconductor device to achieve the desired on-resistance and off-resistance, making it easier to achieve a balance between on-resistance and off-resistance, thus adapting to different application scenarios and requirements, and improving the versatility and design flexibility of the semiconductor device. Attached Figure Description

[0025] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0026] Figure 2 for Figure 1 (or Figure 5 An enlarged view of a segmented gate of a semiconductor device according to some embodiments of the present invention is shown;

[0027] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0028] Figure 4 for Figure 3 (or Figure 6 An enlarged view of a segmented gate of a semiconductor device according to some embodiments of the present invention is shown;

[0029] Figure 5 A schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention; and

[0030] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0031] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when an element or layer is referred to as being “located,” “connected to,” or “coupled to” another element or layer, it may be directly located, connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly located,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers. The same numbers always refer to the same element. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. “Directly above” or “directly below” may indicate that the projections of two or more of them at least partially overlap, while “not directly above” or “directly below” may indicate that the projections of two or more of them do not overlap at all.

[0032] Figure 1 This is a schematic cross-sectional view of a semiconductor device 500A according to some embodiments of the present invention.

[0033] Figure 2 yes Figure 1 The enlarged view shows the gate electrode 250G of the segmented gate 250 of a semiconductor device 500A according to some embodiments of the present invention. In some embodiments, the semiconductor device 500A may include a high-voltage metal-oxide-semiconductor field-effect transistor (HV MOS FET), such as a laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor fabricated using an alternative gate (gate-last) process. Figure 1 As shown, the semiconductor device 500A may include a substrate 200, a first well PW, a second well NW, a first doped region P1-1, a second doped region N1-1, a third doped region N2-1, and a segmented gate 250.

[0034] like Figure 1As shown, substrate 200 includes a semiconductor substrate, such as a silicon (Si) substrate or a silicon-germanium (SiGe) substrate. In some embodiments, substrate 200 includes a bulk semiconductor substrate, a strained semiconductor substrate, or a compound semiconductor substrate. In some embodiments, substrate 200 may be a semiconductor substrate or a wafer substrate having a P-type or N-type conductivity type. In this embodiment, substrate 200 is P-type.

[0035] A first well PW is disposed in the substrate 200. In some embodiments, the first well PW has a first conductivity type. For example, when the first conductivity type is P-type, the first well PW is a P-type well PW. Furthermore, the first well PW and the substrate 200 may have the same or opposite conductivity types. In this embodiment, the first well PW and the substrate 200 have the same conductivity type.

[0036] A second well NW is disposed in the substrate 200. The second well NW is adjacent to and surrounded by the first well PW. In some embodiments, the second well NW has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the second well NW is an N-type well NW. In some embodiments, the first well PW and the second well NW may have the same depth in direction 110 (a direction substantially perpendicular to the upper surface 200T of the substrate 200).

[0037] One or more heavily doped regions are formed on both the first well PW and the second well NW. For example, the first doped region P1-1 (i.e., the first heavily doped region P1-1) and the second doped region N1-1 (i.e., the second heavily doped region N1-1) are located directly on different portions of the first well PW. Furthermore, the third doped region N2-1 (i.e., the third heavily doped region N2-1) is located directly on a portion of the second well NW. The first doped region P1-1 and the third doped region N2-1 are located on opposite sides of the second doped region N1-1 in direction 100 (a direction substantially parallel to the upper surface 200T of the substrate 200). The first doped region P1-1 (i.e., the first heavily doped region P1-1), the second doped region N1-1 (i.e., the second heavily doped region N1-1), and the third doped region N2-1 (i.e., the third heavily doped region N2-1) are all close to or adjacent to the upper surface 200T of the substrate 200.

[0038] In some embodiments, the first doped region P1-1 has a first conductivity type. The second doped region N1-1 and the third doped region N2-1 have a second conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the first doped region P1-1 is a P-type doped region P1-1. The second doped region N1-1 and the third doped region N2-1 are N-type doped regions N1-1 and N2-1, respectively.

[0039] In some embodiments, the conductivity type of the first doped region P1-1 is the same as that of the first well PW. The conductivity types of the second doped region N1-1 and the third doped region N2-1 are opposite to those of the first well PW and the first doped region P1-1. The conductivity types of the second doped region N1-1 and the third doped region N2-1 are the same as those of the second well NW.

[0040] In some embodiments, the doping concentrations of the second doped region N1-1 and the third doped region N2-1 may be the same and greater than the doping concentration of the second well NW. In some embodiments, the doping concentration of the first doped region P1-1 is greater than the doping concentration of the first well region PW.

[0041] Semiconductor device 500A also includes isolation components 201 (including isolation components 201-1, 201-2, 201-3, and 201-4), such as shallow trench isolation (STI) disposed in a first well PW and a second well NW in the substrate 200. Isolation components 201-1, 201-2, 201-3, and 201-4 may define active regions 205-1, 205-2, and 205-3. Figure 1 As shown, the first doped region P1-1 and the second doped region N1-1 can be located in different active regions 205-1 and 205-2 defined by isolation features 201-1, 201-2, and 201-3. The second doped region N1-1 is adjacent to isolation feature 201-2. The two sides of the first doped region P1-1 are adjacent to isolation features 201-1 and 201-2, respectively. Furthermore, the first doped region P1-1 and the second doped region N1-1 can be separated from each other by isolation feature 201-2.

[0042] like Figure 1As shown, the second doped region N1-1 and the third doped region N2-1 can be located in different active regions 205-2 and 205-3 defined by isolation features 201-2, 201-3, and 201-4. One side of the second doped region N1-1 is adjacent to isolation feature 201-2, and the other side of the second doped region N1-1 is separated from isolation feature 201-3 in direction 100. The opposite sides of the third doped region N2-1 are adjacent to isolation features 201-3 and 201-4, respectively. Furthermore, the second doped region N1-1 and the third doped region N2-1 can be separated from each other by isolation feature 201-3.

[0043] Segmented gate 250 is disposed on the first well PW and the second well NW. Furthermore, the segmented gate 250 is located on the substrate 200 along direction 100 (lateral) between the second doped region N1-1 and the third doped region N2-1. Figure 1 As shown, the segmented gate 250 is adjacent to the second doped region N1-1 and spaced apart from the third doped region N2-1 in direction 100. The segmented gate 250 may extend along direction 100 to cover a portion of the isolation member 201-3. In some embodiments, the segmented gate 250 (e.g., a metal gate) includes a gate dielectric layer 250D disposed on the substrate 200 and a gate electrode 250G disposed above the gate dielectric layer 250D.

[0044] In some embodiments, the gate dielectric layer 250D includes a high-k dielectric material (dielectric constant k is greater than that of silicon dioxide, approximately 3.9), such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials and / or combinations thereof.

[0045] In some embodiments, the segmented gate 250 may further include an interface layer (not shown) formed between the substrate 200 and the gate dielectric layer 250D to enhance the adhesion between the gate dielectric layer 250D and the gate dielectric layer 250D. In some embodiments, the interface layer includes, for example, SiON or SiO2.

[0046] The gate electrode 250G of the segmented gate 250 includes a first gate electrode segment 250N1, a second gate electrode segment 250P1, and a third gate electrode segment 250P2. In some embodiments, the first gate electrode segment 250N1 is disposed between and adjacent to the second gate electrode segment 250P1 and the third gate electrode segment 250P2. Figure 1As shown, the second gate electrode segment 250P1 of the gate electrode 250G of the segmented gate 250 is adjacent to the second doped region N1-1. Furthermore, the third gate electrode segment 250P2 of the gate electrode 250G of the segmented gate 250 is separated from the third doped region N2-1 in a direction 100 substantially parallel to the upper surface 200T of the substrate 200. In direction 100, the second gate electrode segment 250P1 and the third gate electrode segment 250P2 are close to the edge of the segmented gate 250, and the first gate electrode segment 250N1 is located at the center portion of the segmented gate 250.

[0047] like Figure 1 As shown, the segmented gate 250 may partially overlap with the isolation member 201-3 in a direction 110 substantially perpendicular to the upper surface 200T of the substrate 200. More specifically, the third gate electrode segment 250P2 of the gate electrode 250G of the segmented gate 250 partially overlaps with the isolation member 201-3. The first gate electrode segment 250N1 and the second gate electrode segment 250P1 of the gate 250G of the segmented gate 250 are offset from the isolation member 201-3 in a direction 100.

[0048] In some embodiments, the first gate electrode segment 250N1 has a second conductivity type. The second gate electrode segment 250P1 and the third gate electrode segment 250P2 have a first conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, then the first gate electrode segment 250N1 is an N-type gate electrode segment 250N1, the second gate electrode segment 250P1 is a P-type gate electrode segment 250P1, and the third gate electrode segment 250P2 is a P-type gate electrode segment 250P2.

[0049] like Figure 2 As shown, the gate electrode 250G of the segmented gate 250 also includes a first work function metal PMA and a second work function metal NMA disposed on the first work function metal PMA. It should be noted that the positions of the first work function metal PMA and the second work function metal NMA can be interchanged (upside down), and are not limited to the disclosed embodiments. For example, as... Figure 1 As shown, the first work function metal PMA is located along direction 110 between the gate dielectric layer 250D and the second work function metal NMA. Alternatively, the second work function metal NMA can also be disposed along direction 110 between the gate dielectric layer 250D and the first work function metal PMA.

[0050] In some embodiments, the first work function metal PMA has a first conductivity type, and the second work function metal NMA has a second conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the first work function metal PMA is a P-type work function metal PMA, and the second work function metal NMA is an N-type work function metal NMA. In some embodiments, the first work function metal PMA includes TiN (titanium nitride), and the second work function metal NMA includes TiAl (titanium aluminum nitride).

[0051] In some embodiments, the first gate electrode segment 250N1, the second gate electrode segment 250P1, and the third gate electrode segment 250P2 may each include a portion of the first work function metal PMA and a portion of the second work function metal NMA. For example... Figure 1 As shown, in direction 110 (vertical direction), the first work function metal PMA of the first gate electrode segment 250N1 has a first height H1A, the first work function metal PMA of the second gate electrode segment 250P1 has a second height H2A, and the first work function metal PMA of the third gate electrode segment 250P2 has a third height H3A. In some embodiments, the first height H1A is less than (or lower than) the second height H2A, and the first height H1A is less than (or lower than) the third height H3A. In some embodiments, the second height H2A may be the same as or different from the third height H3A. Thus, the different gate electrode segments of the segmented gate can have different conductivity types to achieve adjustment and control of the on-resistance and off-resistance, achieving the desired effect.

[0052] like Figure 2 As shown, the second work function metal NMA of the first gate electrode segment 250N1 has a fourth height H4A, the second work function metal NMA of the second gate electrode segment 250P1 has a fifth height H5A, and the second work function metal NMA of the third gate electrode segment 250P2 has a sixth height H6A. In some embodiments, the fourth height H4A is greater than (or higher than) the fifth height H5A, and the fourth height H4A is greater than (or higher than) the sixth height H6A. In some embodiments, the fifth height H5A may be the same as or different from the sixth height H6A.

[0053] In some embodiments, in the first gate electrode segment 250N1, the second gate electrode segment 250P1, and the third gate electrode segment 250P2, the sum of the heights of the first work function metal PMA and the second work function metal NMA can be equal to the total height HTA of the gate electrode 250G of the segmented gate 250. For example, the sum of the first height H1A and the fourth height H4A is equal to the height HTA of the gate electrode 250G of the segmented gate 250. Furthermore, the sum of the first height H1A and the fourth height H4A is equal to the sum of the second height H2A and the fifth height H5A. Further, the sum of the first height H1A and the fourth height H4A is equal to the sum of the third height H3A and the sixth height H6A. Therefore, the sum of the second height H2A and the fifth height H5A is equal to the height HTA of the segmented gate 250. The sum of the third height H3A and the sixth height H6A is also equal to the height HTA of the gate electrode 250G of the segmented gate 250. This makes the upper surface of the entire gate structure flush, and the height of the entire gate structure substantially uniform.

[0054] In some embodiments, the sum of the widths of the first gate electrode segment 250N1, the second gate electrode segment 250P1, and the third gate electrode segment 250P2 is equal to the total width of the segmented gate 250G. For example, as Figure 2 As shown, the first gate electrode segment 250N1 has a first width W1A, the second gate electrode segment 250P1 has a second width W2A, and the third gate electrode segment 250P3 has a third width W3A. In some embodiments, the sum of the first width W1A, the second width W2A, and the third width W3A is equal to the width WTA of the gate electrode 250G of the segmented gate 250.

[0055] In some embodiments, the first width W1A is greater than the second width W2A, and the first width W1A is also greater than the third width W3A. In some embodiments, the second width W2A may be the same as or different from the third width W3A. This allows for the adjustment and control of the on-resistance and off-resistance by controlling the widths of different gate electrode segments, achieving the desired effect.

[0056] In some embodiments, the first gate electrode segment 250N1 of the gate electrode 250G of the segmented gate 250 may cover a portion of the first well PW and the second well NW. Alternatively, the first gate electrode segment 250N1 of the gate electrode 250G of the segmented gate 250 may cover the first well PW without extending to the second well NW.

[0057] like Figure 1As shown, the second gate electrode segment 250P1 of the gate electrode 250G of the segmented gate 250 can cover a portion of the first well PW. For example, the second gate electrode segment 250P1 can cover a portion of the first well PW without extending into the second well NW. Furthermore, the third gate electrode segment 250P2 of the gate electrode 250G of the segmented gate 250 can cover a portion of the second well NW. For example, the third gate electrode segment 250P2 can cover a portion of the second well NW without extending into the first well PW.

[0058] In the gate electrode 250G of the segmented gate 250, the interface F1A between the first gate electrode segment 250N1 and the second gate electrode segment 250P1 is directly located on the first well PW. In some embodiments, the second interface F2A between the first gate electrode segment 250N1 and the third gate electrode segment 250P2 is directly located on the first well PW, the second well NW, or the third interface F3A between the first well PW and the second well NW.

[0059] like Figure 1 As shown, the segmented gate 250, the first well PW, the second well NW, the first doped region P1-1, the second doped region N1-1, and the second doped region N2-1 can collectively form a first-type metal-oxide-semiconductor field-effect transistor (MOS FET). The MOS FET is formed within the first well PW and the second well NW. In the MOS FET, the segmented gate 250 can serve as the gate (electrode) of the MOS FET. The first doped region P1-1 can serve as the body region of the MOS FET. The second doped region N1-1 can serve as the source region of the MOS FET. The third doped region N2-1 can serve as the drain region of the MOS FET. Furthermore, the second well region NW can serve as the drain extension region of the MOS FET. The portion of substrate 200 near the segmented gate 250 and located between the second doped region N1-1 and the second well region NW can be used as the channel region of a first-type metal-oxide-semiconductor field-effect transistor. The channel region has a second conductivity type. In some embodiments, for example, the segmented gate 250 or the gate electrode 250G is a PNP-type gate structure.

[0060] In this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, and the first type of metal-oxide-semiconductor field-effect transistor (MOS FET) is an N-type metal-oxide-semiconductor field-effect transistor (NMOS FET), wherein the conductivity type of the channel region is N-type. The semiconductor device 500A can be used as a laterally diffused N-type metal-oxide-semiconductor field-effect transistor (LD NMOS FET).

[0061] Compared to conventional LD ​​NMOS FETs with gates composed solely of N-type work function metal, the N-type conductivity type semiconductor device 500A of this embodiment includes a segmented gate (e.g., segmented gate 250), wherein the gate electrode (e.g., gate electrode 250G) is composed of both N-type and P-type work function metals. By adjusting the height ratio of the N-type and P-type work function metals (e.g., the difference or ratio between heights H1A and H4A, H2A and H5A, H3A and H6A), the segmented gate comprises multiple gate electrode segments with different conductivity types. For example, in direction 100 (also serving as the channel direction), by adjusting the height ratio of the N-type and P-type work function metals to be greater than 1 (e.g., the fourth height H4A is greater than (or higher than) the first height H1A), the conductivity type of the central gate electrode segment (e.g., the first gate electrode segment 250N1) of the segmented gate is the same as that of the channel region, such as N-type. Furthermore, by adjusting the height ratio of the N-type work function metal to the P-type work function metal to be less than 1 (e.g., the fourth height H5A is less than (or lower than) the second height H2A, and the sixth height H6A is less than (or lower than) the third height H3A), the edge gate electrode segments (e.g., the second gate electrode segment 250P1 and the third gate electrode segment 250P2) located on the source and drain sides of the segmented gate are converted into gate electrode segments opposite to the channel region, such as P-type gate electrode segments. The center gate electrode segment (e.g., the first gate electrode segment 250N1) and the edge gate electrode segments (e.g., the second gate electrode segment 250P1 and the third gate electrode segment 250P2) can have the same height (i.e., the total height HTA of the gate electrode 250G). Furthermore, the width (e.g., width W1A) of the central gate electrode segment (e.g., the first gate electrode segment 250N1) is greater than the width of the edge gate electrode segments (e.g., the second electrode segment 250P1 and the third electrode segment 250P2), so that the conductivity type of the entire gate electrode 250G can remain the same as that of the channel region, such as N-type.

[0062] In a segmented gate, the central gate electrode segment located above the channel region (e.g., the first gate electrode segment 250N1) can have a lower threshold voltage to reduce the on-resistance (Rdson) of the semiconductor device 500A. The edge gate electrode segments located on the source and drain sides (e.g., the second electrode segment 250P1 and the third electrode segment 250P2) can have higher threshold voltages to reduce the off-capacitance (Coff) and improve the reliability of the drain side of the semiconductor device 500A.

[0063] Figure 3 This is a schematic cross-sectional view of a semiconductor device 500B according to some embodiments of the present invention.

[0064] Figure 4 yes Figure 3 The enlarged view shows the gate electrode 350G of the segmented gate 350 of the semiconductor device 500B according to some embodiments of the present invention. The following embodiments are consistent with previous references. Figure 1 and Figure 2 Components that are identical or similar to those described will not be repeated for the sake of brevity. One difference between semiconductor device 500A and semiconductor device 500B is that semiconductor device 500B can have a conductivity type opposite to that of semiconductor device 500A. For example, in semiconductor device 500A, components with a first conductivity type are P-type components, while components with a second conductivity type are N-type components. In semiconductor device 500B, components with a first conductivity type are N-type components, while components with a second conductivity type are P-type components.

[0065] like Figure 3 As shown, the semiconductor device 500B may include a substrate 200, a first well NW, a second well PW, a first doped region N1-2, a second doped region P1-2, a third doped region P2-2, and a segmented gate 350.

[0066] like Figure 3 As shown, substrate 200 includes a semiconductor substrate, such as a silicon (Si) substrate or a silicon-germanium (SiGe) substrate. In some embodiments, substrate 200 includes a bulk semiconductor substrate, a strained semiconductor substrate, or a compound semiconductor substrate. In some embodiments, substrate 200 may be a semiconductor substrate having a P-type or N-type conductivity type. In this embodiment, substrate 200 is P-type.

[0067] A first well NW is disposed in the substrate 200. In some embodiments, the first well NW has a first conductivity type. For example, when the first conductivity type is N-type, the first well NW is an N-type well NW. Furthermore, the first well NW and the substrate 200 may have the same or opposite conductivity types. In this embodiment, the first well NW and the substrate 200 have opposite conductivity types.

[0068] A second well PW is disposed in the substrate 200. The second well PW is adjacent to and surrounded by the first well NW. In some embodiments, the second well PW has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the second well PW is an N-type well NW. In some embodiments, the first well NW and the second well PW may have the same depth in the direction 110 (a direction substantially perpendicular to the upper surface 200T of the substrate 200).

[0069] The first well NW and the second well PW each have one or more heavily doped regions formed thereon. For example, the first doped region N1-2 (i.e., the first heavily doped region N1-2) and the second doped region P1-2 (i.e., the second heavily doped region P1-2) are located directly on different portions of the first well NW. Furthermore, the third doped region P2-2 (i.e., the third heavily doped region P2-2) is located directly on a portion of the second well PW. The first doped region N1-2 and the third doped region P2-2 are located on opposite sides of the second doped region P1-2 in direction 100 (a direction substantially parallel to the upper surface 200T of the substrate 200). The first doped region N1-2 (i.e., the first heavily doped region N1-2), the second doped region P1-2 (i.e., the second heavily doped region P1-2), and the third doped region P2-2 (i.e., the third heavily doped region P2-2) are close to or adjacent to the upper surface 200T of the substrate 200.

[0070] In some embodiments, the first doped region N1-2 has a first conductivity type. The second doped region P1-2 and the third doped region P2-2 have a second conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the first doped region N1-2 is a P-type doped region N1-2. The second doped region P1-2 and the third doped region P2-2 are N-type doped regions P1-2 and P2-2, respectively.

[0071] In some embodiments, the conductivity type of the first doped region N1-2 is the same as that of the first well NW. The conductivity types of the second doped region P1-2 and the third doped region P2-2 are opposite to those of the first well NW and the first doped region N1-2. The conductivity types of the second doped region P1-2 and the third doped region P2-2 are the same as those of the second well PW.

[0072] In some embodiments, the doping concentrations of the second doped region P1-2 and the third doped region P2-2 may be the same and greater than the doping concentration of the first well region PW. In some embodiments, the doping concentration of the first doped region N1-2 is greater than the doping concentration of the first well region PW.

[0073] like Figure 3 As shown, the first doped region N1-2 and the second doped region P1-2 can be located in different active regions 205-1 and 205-2 defined by isolation features 201-1, 201-2, and 201-3. The second doped region P1-2 is adjacent to the isolation feature 201-2. The opposite side regions N1-2 of the first doped region P1-2 are adjacent to the isolation features 201-1 and 201-2. Furthermore, the first doped region N1-2 and the second doped region P1-2 can be separated from each other by the isolation feature 201-2.

[0074] like Figure 3 As shown, the second doped region P1-2 and the third doped region P2-2 can be located in different active regions 205-2 and 205-3 defined by isolation features 201-2, 201-3, and 201-4. One side of the second doped region P1-2 is adjacent to isolation feature 201-2, and the other side of the second doped region P1-2 is separated from isolation feature 201-3 in direction 100. The opposite side of the third doped region P2-2 is adjacent to isolation features 201-3 and 201-4. Furthermore, the second doped region P1-2 and the third doped region P2-2 can be separated from each other by isolation component 201-3.

[0075] Segmented gate 350 is disposed on the first well NW and the second well PW. Furthermore, segmented gate 350 is located on the portion of substrate 200 between the second doped region P1-2 and the third doped region P2-2 in direction 100 (lateral). Figure 3 As shown, the segmented gate 350 is adjacent to the second doped region P1-2 and separated from the third doped region P2-2 in direction 100. The segmented gate 350 may extend in direction 100 to cover a portion of the isolation member 201-3. In some embodiments, the segmented gate 350 includes a gate dielectric layer 250D disposed on the substrate 200 and a gate electrode 350G disposed above the gate dielectric layer 250D.

[0076] In some embodiments, the segmented gate 350 may further include an interface layer (not shown) formed between the substrate 200 and the gate dielectric layer 250D to improve the adhesion between the gate dielectric layer 250D and the gate dielectric layer 250D. In some embodiments, the interface layer includes, for example, SiON or SiO2.

[0077] The gate electrode 350G of the segmented gate 350 includes a first gate electrode segment 350P1, a second gate electrode segment 350N1, and a third gate electrode segment 350N2. In some embodiments, the first gate electrode segment 350P1 is disposed between and adjacent to the second gate electrode segment 350N1 and the third gate electrode segment 350N2. Figure 3 As shown, the second gate electrode segment 350N1 of the gate electrode 350G of the segmented gate 350 is adjacent to the second doped region P1-2. Furthermore, the third gate electrode segment 350N2 of the gate electrode 350G of the segmented gate 350 is separated from the third doped region P2-2 in a direction 100 substantially parallel to the upper surface 200T of the substrate 200. In direction 100, the second gate electrode segment 350N1 and the third gate electrode segment 350N2 are close to the edge of the segmented gate 350, and the first gate electrode segment 350P1 is located at the center portion of the segmented gate 350.

[0078] like Figure 3 As shown, the segmented gate 350 may partially overlap with the isolation member 201-3 in a direction 110 substantially perpendicular to the upper surface 200T of the substrate 200. More specifically, the third gate electrode segment 350N2 of the gate electrode 350G of the segmented gate 350 partially overlaps with the isolation member 201-3. The first gate electrode segment 350P1 and the second gate electrode segment 350N1 of the gate electrode 350G of the segmented gate 350 are offset from the isolation member 201-3 in a direction 100.

[0079] In some embodiments, the first gate electrode segment 350P1 has a second conductivity type. The second gate electrode segment 350N1 and the third gate electrode segment 350N2 have a first conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, then the first gate electrode segment 350P1 is an N-type gate electrode segment 350P1, the second gate electrode segment 350N1 is a P-type gate electrode segment 350N1, and the third gate electrode segment 350N2 is a P-type gate electrode segment 350N2.

[0080] like Figure 4 As shown, the gate electrode 350G of the segmented gate 350 also includes a first work function metal NMB and a second work function metal PMB disposed on the first work function metal NMB (in the negative (opposite) direction of direction 110). It should be noted that the positions of the first work function metal NMB and the second work function metal PMB can be interchanged (upside down), and are not limited to the disclosed embodiments. For example, as... Figure 3 As shown, the second work function metal PMB is located between the gate dielectric layer 250D and the first work function metal NMB in direction 110. Alternatively, the first work function metal NMB may also be disposed between the gate dielectric layer 250D and the second work function metal PMB in direction 110.

[0081] In some embodiments, the first work function metal NMB has a first conductivity type, and the second work function metal PMB has a second conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the first work function metal NMB is a P-type work function metal NMB, and the second work function metal PMB is an N-type work function metal PMB. In some embodiments, the first work function metal NMB includes TiN, and the second work function metal PMB includes TiAl.

[0082] In some embodiments, the first gate electrode segment 350P1, the second gate electrode segment 350N1, and the third gate electrode segment 350N2 may each include a portion of the first work function metal NMB and a portion of the second work function metal PMB. For example... Figure 4 As shown, in direction 110 (vertical direction), the first work function metal NMB of the first gate electrode segment 350P1 has a first height H1B, the first work function metal NMB of the second gate electrode segment 350N1 has a second height H2B, and the first work function metal NMB of the third gate electrode segment 350N2 has a third height H3B. In some embodiments, the first height H1B is less than (or lower than) the second height H2B, and the first height H1B is less than (or lower than) the third height H3B. In some embodiments, the second height H2B may be the same as or different from the third height H3B.

[0083] like Figure 4 As shown, the second work function metal PMB of the first gate electrode segment 350P1 has a fourth height H4B, the second work function metal PMB of the second gate electrode segment 350N1 has a fifth height H5B, and the second work function metal PMB of the third gate electrode segment 350N2 has a sixth height H6B. In some embodiments, the fourth height H4B is greater than (or higher than) the fifth height H5B, and the fourth height H4B is greater than (or higher than) the sixth height H6B. In some embodiments, the fifth height H5B may be the same as or different from the sixth height H6B.

[0084] In some embodiments, in the first gate electrode segment 350P1, the second gate electrode segment 350N1, and the third gate electrode segment 350N2, the sum of the heights of the first work function metal NMB and the second work function metal PMB can be equal to the total height HTB of the gate electrode 350G of the segmented gate 350. For example, the sum of the first height H1B and the fourth height H4B is equal to the height HTB of the gate electrode 350G of the segmented gate 350. Furthermore, the sum of the first height H1B and the fourth height H4B is equal to the sum of the second height H2B and the fifth height H5B. Further, the sum of the first height H1B and the fourth height H4B is equal to the sum of the third height H3B and the sixth height H6B. Therefore, the sum of the second height H2B and the fifth height H5B is equal to the height HTB of the segmented gate 350. The sum of the third height H3B and the sixth height H6B is also equal to the height HTB of the gate electrode 350G of the segmented gate 350.

[0085] In some embodiments, the sum of the widths of the first gate electrode segment 350P1, the second gate electrode segment 350N1, and the third gate electrode segment 350N2 is equal to the total width of the segmented gate 350G. For example, as Figure 4 As shown, the first gate electrode segment 350P1 has a first width W1B, the second gate electrode segment 350N1 has a second width W2B, and the third gate electrode segment 350P3 has a third width W3B. In some embodiments, the sum of the first width W1B, the second width W2B, and the third width W3B is equal to the width WTB of the gate electrode 350G of the segmented gate 350.

[0086] In some embodiments, the first width W1B is greater than the second width W2B, and the first width W1B is also greater than the third width W3B. In some embodiments, the second width W2B may be the same as or different from the third width W3B.

[0087] In some embodiments, the first gate electrode segment 350P1 of the gate electrode 350G of the segmented gate 350 may cover portions of the first well NW and the second well PW. Alternatively, the first gate electrode segment 350P1 of the gate electrode 350G of the segmented gate 350 may cover the first well NW without extending to the second well PW.

[0088] like Figure 3 As shown, the second gate electrode segment 350N1 of the gate electrode 350G of the segmented gate 350 can cover a portion of the first well NW. For example, the second gate electrode segment 350N1 can cover a portion of the first well NW without extending into the second well PW. Furthermore, the third gate electrode segment 350N2 of the gate electrode 350G of the segmented gate 350 can cover a portion of the second well PW. For example, the third gate electrode segment 350N2 can cover a portion of the second well PW without extending into the first well NW.

[0089] In the gate electrode 350G of the segmented gate 350, the first interface F1B between the first gate electrode segment 350P1 and the second gate electrode segment 350N1 is directly located on the first well NW. In some embodiments, the second interface F2B between the first gate electrode segment 350P1 and the third gate electrode segment 350N2 is directly located on the third interface F3B between the first well NW, the second well PW, or the first well NW and the second well PW.

[0090] like Figure 3 As shown, the segmented gate 350, the first well NW, the second well PW, the first doped region N1-2, the second doped region P1-2, and the second doped region P2-2 can collectively form a second type of metal-oxide-semiconductor field-effect transistor (MOS FET). The MOS FET is formed within the first well NW and the second well PW. In the MOS FET, the segmented gate 350 can serve as the gate of the MOS FET. The first doped region N1-2 can serve as the body region of the MOS FET. The second doped region P1-2 can serve as the source region of the MOS FET. The third doped region P2-2 can serve as the drain region of the MOS FET. Furthermore, the second well region NW can serve as the drain extension region of the MOS FET. The portion of the substrate 200 adjacent to the segmented gate 350 and located between the second doped region P1-2 and the second well region PW can serve as the channel region of the MOS FET. The channel region has a second conductivity type. In some embodiments, for example, the segmented gate 350 or the gate electrode 350G is an NPN type gate structure.

[0091] In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the second type of metal-oxide-semiconductor field-effect transistor (MOS FET) is a P-type metal-oxide-semiconductor field-effect transistor (PMOS FET), with its channel region having a P-type conductivity type. The semiconductor device 500B can be used as a laterally diffused P-type metal-oxide-semiconductor field-effect transistor (LD PMOS FET).

[0092] Compared to a conventional LD ​​PMOS FET with a gate composed solely of P-type work function metal, the P-type conductivity type semiconductor device 500B includes a segmented gate (e.g., segmented gate 350), wherein the gate (e.g., gate 350G) is composed of both N-type and P-type work function metals. By adjusting the height ratio of the N-type and P-type work function metals (e.g., the difference or ratio between heights H1B and H4B, H2B and H5B, H3B and H6B), the segmented gate comprises multiple gate electrode segments with different conductivity types. For example, in direction 100 (also serving as the channel direction), by adjusting the height ratio of the P-type and N-type work function metals to be greater than 1 (e.g., the fourth height H4B is greater than (or higher than) the first height H1B), the conductivity type of the central gate electrode segment (e.g., the first gate electrode segment 350P1) of the segmented gate is the same as that of the channel region, such as P-type. Furthermore, by adjusting the height ratio of the P-type work function metal to the N-type work function metal to be less than 1 (e.g., the fourth height H5B is less than (or lower than) the second height H2B, and the sixth height H6B is less than (or lower than) the third height H3B), the edge gate electrode segments (e.g., the second gate electrode segment 350N1 and the third gate electrode segment 350N2) located on the source and drain sides are converted to the opposite type to the channel region, such as N-type. The center gate electrode segment (e.g., the first gate electrode segment 350P1) and the edge gate electrode segments (e.g., the second gate electrode segment 350N1 and the third gate electrode segment 350N2) can have the same height (i.e., the total height HTB of the gate electrode 350G). Furthermore, the width (e.g., width W1B) of the central gate electrode segment (e.g., the first gate electrode segment 350P1) is greater than the width of the edge gate electrode segments (e.g., the second electrode segment 350N1 and the third electrode segment 350N2), so that the conductivity type of the entire gate electrode 350G can remain the same as that of the channel region, such as P-type.

[0093] In a segmented gate, the central gate electrode segment located above the channel region (e.g., the first gate electrode segment 350P1) can have a lower threshold voltage to reduce the on-resistance (Rdson) of the semiconductor device 500B. The edge gate electrode segments located on the source and drain sides (e.g., the second electrode segment 350N1 and the third electrode segment 350N2) can have higher threshold voltages to reduce the off-capacitance (Coff) and improve the reliability of the drain side of the semiconductor device 500B.

[0094] Figure 5 This is a schematic cross-sectional view according to some embodiments of the present invention, in which a semiconductor device 500C is provided. Figure 2 Too Figure 5The enlarged view shows the gate electrode 251G of the segmented gate 251 of the semiconductor device 500C according to some embodiments of the present invention. The following embodiments are consistent with previous references. Figure 1 and Figure 2 Components that are identical or similar to those described will not be repeated for the sake of brevity. In some embodiments, the segmented gate 251 of semiconductor device 500C is similar to that of semiconductor device 500A (e.g., Figure 1 and Figure 2 The segmented gates 250 shown are the same or similar. The difference between semiconductor device 500A and semiconductor device 500C lies at least in the substrate, wherein the substrate 210 in semiconductor device 500C is different from the substrate 200 in semiconductor device 500A.

[0095] like Figure 5 As shown, the semiconductor device 500C may include a substrate 210, a first well PW, a first doped region N3, a second doped region N4, and a segmented gate 251. The substrate 210 includes a semiconductor substrate, such as a silicon (Si) substrate or a silicon-germanium (SiGe) substrate. In some embodiments, the substrate 210 includes a bulk semiconductor substrate, a strained semiconductor substrate, or a compound semiconductor substrate. In some embodiments, the substrate 210 may be a semiconductor substrate having a P-type or N-type conductivity type. In this embodiment, the substrate 210 is P-type. The first well PW is disposed in the substrate 210. In some embodiments, the first well PW has a first conductivity type. For example, when the first conductivity type is P-type, the first well PW is a P-type well PW. Furthermore, the first well PW and the substrate 210 may have the same or opposite conductivity types. In this embodiment, the first well PW and the substrate 210 have the same conductivity type. In some embodiments, only the first well PW is disposed in the substrate 210, and the second well (NW) is not present in the substrate 210.

[0096] The first doped region N3 (i.e., the first heavily doped region N3) and the second doped region N4 (i.e., the second heavily doped region N4) are located directly on different portions of the first well PW. In some embodiments, the first doped region N3 is adjacent to the first sidewall of the segmented gate 251, and the second doped region N4 is adjacent to the second sidewall of the segmented gate 251. Furthermore, the first sidewall and the second sidewall are two opposing sidewalls of the segmented gate 251. In some embodiments, the first doped region N3 and the second doped region N4 have a second conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the first doped region N3 and the second doped region N4 are N-type doped regions N3 and N4, respectively. In some embodiments, the first doped region N3 and the second doped region N4 may have the same doping concentration.

[0097] The semiconductor device 500C also includes an isolation component 202, such as a shallow trench isolation (STI), disposed within a first well PW in the substrate 210. The isolation component 202 may define an active region of the semiconductor device 500C and may be used to isolate the first doped region N3 and the second doped region N4 from other regions.

[0098] The segmented gate 251 is directly disposed on the first well PW. The portion of the first well PW near the segmented gate 251 and located between the first doped region N3 and the second doped region N4 can be used as a channel region of a first type of metal-oxide-semiconductor field-effect transistor. This channel region has a second conductivity type. In some embodiments, the segmented gate 251 is directly disposed on this portion of the first well PW or directly disposed on the channel region. The first doped region N3 and the second doped region N4 are separated by the first well PW or a portion of the channel region. In some embodiments, for example, the segmented gate 251 or the gate electrode 251G is a PNP type gate structure.

[0099] In this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, and the first type of metal-oxide-semiconductor field-effect transistor (MOS FET) is an N-type metal-oxide-semiconductor field-effect transistor (NMOS FET), wherein the conductivity type of the channel region is N-type. The semiconductor device 500C can be used as an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET).

[0100] In some embodiments, the segmented gate 251 of the semiconductor device 500C (e.g., Figure 5 and Figure 2 (as shown) and the segmented gate 250 of semiconductor device 500A (as shown) Figure 1 and Figure 2The same as shown. Compared to a conventional NMOS field-effect transistor whose gate electrode is composed solely of N-type work function metal, the N-type conductive semiconductor device 500C includes a segmented gate (e.g., segmented gate 251), wherein the gate electrode (e.g., gate electrode 251G) is composed of N-type work function metal (e.g., second work function metal NMA) and P-type work function metal (e.g., first work function metal PMA). By adjusting the height ratio of the N-type work function metal to the P-type work function metal, the segmented gate includes multiple gate electrode segments with different conductivity types. For example, in direction 100 (also as the channel direction), by adjusting the height ratio of the N-type work function metal to the P-type work function metal to be greater than 1 (e.g., the fourth height H4A is greater than (or higher than) the first height H1A), the conductivity type of the central gate electrode segment (e.g., the first gate electrode segment 251N1) of the segmented gate is the same as that of the channel region, for example, N-type. Furthermore, by adjusting the height ratio of the N-type work function metal to the P-type work function metal to be less than 1 (e.g., the fourth height H5A is less than (or lower than) the second height H2A, and the sixth height H6A is less than (or lower than) the third height H3A), the edge gate electrode segments (e.g., the second gate electrode segment 251P1 and the third gate electrode segment 251P2) located on the source and drain sides of the segmented gate are converted into gate electrode segments opposite to the channel region, such as P-type gate electrode segments. The center gate electrode segment (e.g., the first gate electrode segment 251N1) and the edge gate electrode segments (e.g., the second gate electrode segment 251P1 and the third gate electrode segment 251P2) can have the same height (i.e., the total height HTA of the gate electrode 251G). Furthermore, the width (e.g., width W1A) of the central gate electrode segment (e.g., the first gate electrode segment 251N1) is greater than the width of the edge gate electrode segments (e.g., the second gate electrode segment 251P1 and the third gate electrode segment 251P2), allowing the conductivity type of the entire gate electrode 251G to remain the same as that of the channel region, for example, N-type. In the segmented gate, the central gate electrode segment (e.g., the first gate electrode segment 251N1) located above the channel region can have a lower threshold voltage, thereby reducing the on-resistance (Rdson) of the semiconductor device 500C. The edge gate electrode segments (e.g., the second electrode segment 251P1 and the third electrode segment 251P2) located on the source and drain sides can have higher threshold voltages to reduce the off-capacitance (Coff) and improve the reliability of the drain side of the semiconductor device 500C.

[0101] Figure 6 This is a schematic cross-sectional view of a semiconductor device 500D according to some embodiments of the present invention. Figure 4 Too Figure 6 The enlarged view shows the gate electrode 351G of the segmented gate 351 of the semiconductor device 500D according to some embodiments of the present invention. The following embodiments are consistent with previous references. Figure 3and Figure 4 The same or similar elements described will not be repeated. In some embodiments, the semiconductor device 500D (such as...) Figure 6 and Figure 4 The segmented gate 351 (as shown) and the semiconductor device 500B (as shown) Figure 3 and Figure 4 The segmented gate 350 shown is the same or similar to that of the semiconductor device 500B. The difference between semiconductor device 500B and semiconductor device 500D lies at least in the substrate, wherein the substrate 210 in semiconductor device 500D is different from the substrate 200 in semiconductor device 500B.

[0102] like Figure 6 As shown, the semiconductor device 500D may include a substrate 210, a first well NW, a first doped region P3, a second doped region P4, and a segmented gate 351. The substrate 210 includes a semiconductor substrate, such as a silicon (Si) substrate or a silicon-germanium (SiGe) substrate. In some embodiments, the substrate 210 includes a bulk semiconductor substrate, a strained semiconductor substrate, or a compound semiconductor substrate. In some embodiments, the substrate 210 may be a semiconductor substrate having a P-type or N-type conductivity type. In this embodiment, the substrate 210 is P-type. The first well NW is disposed in the substrate 210. In some embodiments, the first well NW has a first conductivity type. For example, when the first conductivity type is N-type, the first well NW is an N-type well NW. Furthermore, the first well NW and the substrate 210 may have the same or opposite conductivity types. In this embodiment, the first well NW and the substrate 210 have opposite conductivity types. In some embodiments, only the first well NW is disposed in the substrate 210, and there is no second well (PW) in the substrate 210.

[0103] The first doped region P3 (i.e., the first heavily doped region P3) and the second doped region P4 (i.e., the second heavily doped region P4) are located directly on different portions of the first well NW. In some embodiments, the first doped region P3 is adjacent to the first sidewall of the segmented gate 351, and the second doped region P4 is adjacent to the second sidewall of the segmented gate 351. Furthermore, the first sidewall and the second sidewall are two opposing sidewalls of the segmented gate 351. In some embodiments, the first doped region P3 and the second doped region P4 have a second conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the first doped region P3 and the second doped region P4 are P-type doped regions P3 and P4, respectively. In some embodiments, the first doped region P3 and the second doped region P4 may have the same doping concentration.

[0104] The semiconductor device 500D also includes an isolation component 202, such as a shallow trench isolation (STI), disposed within a first well NW in the substrate 210. The isolation component 202 may define an active region of the semiconductor device 500D and may be used to isolate the first doped region P3 and the second doped region P4 from other regions.

[0105] The segmented gate 351 is directly disposed on the first well NW. The portion of the first well NW adjacent to the segmented gate 351 and located between the first doped region P3 and the second doped region P4 can be used as a channel region of a second type of metal-oxide-semiconductor field-effect transistor. This channel region has a second conductivity type. In some embodiments, the segmented gate 351 is directly disposed on this portion of the first well NW or directly disposed on the channel region. The first doped region P3 and the second doped region P4 are separated by a portion of the first well NW or the channel region. In some embodiments, for example, the segmented gate 351 or the gate electrode 351G is an NPN type gate structure.

[0106] In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the second type of metal-oxide-semiconductor field-effect transistor (MOS FET) is a P-type metal-oxide-semiconductor field-effect transistor (PMOS FET), wherein the conductivity type of the channel region is P-type. The semiconductor device 500D can be used as a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET).

[0107] In some embodiments, the segmented gate 351 of the semiconductor device 500D (e.g. Figure 6 and Figure 4 (as shown) and the segmented gate 350 of semiconductor device 500B (as shown) Figure 3 and Figure 4The same as shown. Compared to a conventional PMOSFET with a gate composed solely of P-type work function metal, the P-type conductivity semiconductor device 500D includes a segmented gate (e.g., segmented gate 351), wherein the gate (e.g., gate 351G) is composed of N-type work function metal (e.g., first work function metal NMB) and P-type work function metal (e.g., second work function metal PMB). By adjusting the height ratio of the P-type work function metal to the N-type work function metal, the segmented gate comprises multiple gate segments with different conductivity types. For example, in direction 100 (also serving as the channel direction), by adjusting the height ratio of the P-type work function metal to the N-type work function metal to be greater than 1 (e.g., the fourth height H4B is greater than (or higher than) the first height H1B), the conductivity type of the central gate electrode segment (e.g., the first gate electrode segment 351P1) of the segmented gate remains the same as that of the channel region, such as P-type. Furthermore, by adjusting the height ratio of the P-type work function metal to the N-type work function metal to be less than 1 (e.g., the fourth height H5B is less than (or lower than) the second height H2B, and the sixth height H6B is less than (or lower than) the third height H3B), the edge gate segments (e.g., the second gate segment 351N1 and the third gate segment 351N2) located on the source and drain sides of the segmented gate are converted to gate segments opposite to the channel region, such as P-type. The central gate segment (e.g., the first gate segment 351P1) and the edge gate segments (e.g., the second gate segment 351N1 and the third gate segment 351N2) can have the same height (i.e., the total height HTB of the gate segment 351G). Furthermore, the width (e.g., width W1B) of the central gate electrode segment (e.g., the first gate electrode segment 351P1) is greater than the width of the edge gate electrode segments (e.g., the second electrode segment 351N1 and the third electrode segment 351N2), so that the conductivity type of the entire gate electrode 351G can remain the same as the channel region, such as P-type. In a segmented gate, the central gate electrode segment located above the channel region (e.g., the first gate electrode segment 351P1) can have a lower threshold voltage to reduce the on-resistance (Rdson) of the semiconductor device 500D. The edge gate electrode segments located on the source side (e.g., the second electrode segment 351N1 and the third electrode segment 351N2) and the drain side can have higher threshold voltages to reduce the off-capacitance (Coff) and improve the reliability of the drain side of the semiconductor device 500D.

[0108] This invention provides a semiconductor device. The semiconductor device includes a substrate, a first well, a second well, a first doped region, a second doped region, a third doped region, and a segmented gate. The first well, having a first conductivity type, is disposed in the substrate. The second well, having a second conductivity type, is disposed in the substrate and surrounded by the first well. The first doped region, having a first conductivity type, and the second doped region, having a second conductivity type, are disposed in the first well. The first doped region and the second doped region are separated by a first isolation feature. The third doped region, having a second conductivity type, is disposed in the second well. The segmented gate is disposed on the first well and the second well. The segmented gate includes a first gate electrode segment, a second gate electrode segment, and a third gate electrode segment, all of the second conductivity type. The first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment.

[0109] In some embodiments, the first doped region serves as the body region or bulk region of the semiconductor device.

[0110] In some embodiments, the second doped region serves as the source region of a semiconductor device.

[0111] In some embodiments, the third doped region serves as the drain region of the semiconductor device, thereby forming a semiconductor device with complete and normal functionality.

[0112] In some embodiments, the segmented gate includes a first work function metal of a first conductivity type and a second work function metal of a second conductivity type disposed on the first work function metal.

[0113] In some embodiments, when the first conductivity type is p-type and the second conductivity type is n-type, the first work function metal includes TiN and the second work function metal includes TiAl.

[0114] In some embodiments, when the first conductivity type is n-type and the second conductivity type is p-type, the first work function metal includes TiAl and the second work function metal includes TiN.

[0115] In some embodiments, the first work function metal of the first gate electrode segment has a first height, the first work function metal of the second gate electrode segment has a second height, and the first work function metal of the third gate electrode segment has a third height, wherein the first height is less than (or lower than) the second height, and the first height is less than (or lower than) the third height. This achieves a segmented gate, different from a conventional gate, where different gate electrode segments can have different conductivity types to achieve adjustment and control of the on-resistance and off-resistance, thus achieving the desired effect.

[0116] In some embodiments, the second work function metal of the first gate electrode segment has a fourth height, the second work function metal of the second gate electrode segment has a fifth height, and the second work function metal of the third gate electrode segment has a sixth height, wherein the fourth height is greater than (or higher than) the fifth height, and the fourth height is greater than (or higher than) the sixth height. This achieves a segmented gate, different from a conventional gate, where different gate electrode segments can have different conductivity types to achieve adjustment and control of the on-resistance and off-resistance, thus achieving the desired effect.

[0117] In some embodiments, the sum of the first height and the fourth height is equal to the height of the gate electrode of the segmented gate.

[0118] In some embodiments, the sum of the first height and the fourth height is equal to the sum of the second height and the fifth height, and the sum of the first height and the fourth height is equal to the sum of the third height and the sixth height. Thus, the thickness or height of the formed gate electrode is substantially uniform.

[0119] In some embodiments, the first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, and the sum of the first width, the second width, and the third width is equal to the width of the gate electrode of the segmented gate. This achieves a segmented gate, different from a conventional gate, where different gate electrode segments can have different conductivity types to adjust and control the on-resistance and off-resistance, achieving the desired effect.

[0120] In some embodiments, the first width is greater than the second width, and the first width is also greater than the third width.

[0121] In some embodiments, the first gate electrode segment of the segmented gate covers the first well and the second well.

[0122] In some embodiments, the second gate electrode segment of the segmented gate covers the first well, and the third gate electrode segment of the segmented gate covers the second well.

[0123] In some embodiments, the first interface between the first gate electrode segment of the segmented gate and the second gate electrode segment of the segmented gate is located directly on the first well.

[0124] In some embodiments, the second interface between the first gate electrode segment of the segmented gate and the third gate electrode segment of the segmented gate is directly located on the third interface between the first well, the second well, or the first well and the second well.

[0125] In some embodiments, the second gate electrode segment of the segmented gate is adjacent to the second doped region, and the third gate electrode segment of the segmented gate is adjacent to the second doped region. It is released from the third doped region in a direction substantially parallel to the upper surface of the substrate.

[0126] In some embodiments, the semiconductor device further includes a second isolation feature disposed in the second well and adjacent to the third doped region. The segmented gate partially overlaps with the second isolation feature.

[0127] In some embodiments, the first gate electrode segment and the second gate electrode segment of the segmented gate are offset from the second isolation feature.

[0128] This invention provides a semiconductor device. The semiconductor device includes a substrate, a first well, a first doped region, a second doped region, a third doped region, and a segmented gate. The first well, having a first conductivity type, is disposed in the substrate. The first doped region and the second doped region, having a second conductivity type, are disposed in the first well. The first doped region and the second doped region are separated from each other by a portion of the first well. The segmented gate is disposed on this portion of the first well. The segmented gate includes a first gate electrode segment of the second conductivity type, a second gate electrode segment of the first conductivity type, and a third gate electrode segment of the first conductivity type. The first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment.

[0129] In some embodiments, a portion of the first well serves as the channel region of the semiconductor device.

[0130] In some embodiments, the segmented gate includes a first work function metal of a first conductivity type and a second work function metal of a second conductivity type disposed on the first work function metal, wherein the first work function metal of the first gate electrode segment has a first height, the first work function metal of the second gate electrode segment has a second height, and the first work function metal of the third gate electrode segment has a third height, the first height being less than (or lower than) the second height, and the first height being less than (or lower than) the third height.

[0131] In some embodiments, the first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, wherein the first width is greater than the second width and the third width is also greater than the third width.

[0132] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; a first well disposed in the substrate, having a first conductivity type; a second well disposed in the substrate and surrounded by the first well, having a second conductivity type; a first doped region having the first conductivity type and a second doped region having the second conductivity type, disposed in the first well, wherein the first doped region and the second doped region are separated from each other by a first isolation structure; a third doped region disposed in the second well, having the second conductivity type; and a segmented gate disposed on the first well and the second well, wherein the segmented gate comprises a first gate electrode segment of the second conductivity type, a second gate electrode segment of the first conductivity type, and a third gate electrode segment of the first conductivity type, and wherein the first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment.

2. The semiconductor device according to claim 1, wherein The first doped region serves as a body region or bulk region of the semiconductor device, the second doped region serves as a source region of the semiconductor device, and the third doped region serves as a drain region of the semiconductor device.

3. The semiconductor device according to claim 1, wherein The segmented gate comprises a first work function metal of the first conductivity type and a second work function metal of the second conductivity type disposed on the first work function metal, wherein when the first conductivity type is p-type and the second conductivity type is n-type, the first work function metal comprises TiN and the second work function metal comprises TiAl; or when the first conductivity type is n-type and the second conductivity type is p-type, the first work function metal comprises TiAl and the second work function metal comprises TiN.

4. The semiconductor device according to claim 3, wherein The first work function metal of the first gate electrode segment has a first height, the first work function metal of the second gate electrode segment has a second height, and the first work function metal of the third gate electrode segment has a third height, the first height being lower than the second height and the first height being lower than the third height.

5. The semiconductor device according to claim 4, wherein The second work function metal of the first gate electrode segment has a fourth height, the second work function metal of the second gate electrode segment has a fifth height, and the second work function metal of the third gate electrode segment has a sixth height, the fourth height being higher than the fifth height and the fourth height being higher than the sixth height.

6. The semiconductor device according to claim 5, wherein The sum of the first height and the fourth height is equal to the sum of the second height and the fifth height, and the sum of the first height and the fourth height is equal to the sum of the third height and the sixth height.

7. The semiconductor device according to claim 1, wherein The first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, wherein the first width is greater than the second width and the first width is also greater than the third width.

8. The semiconductor device according to claim 1, wherein The first gate electrode segment of the segmented gate covers the first well and the second well.

9. The semiconductor device according to claim 8, wherein The second gate electrode segment of the segmented gate covers the first well, and the third gate electrode segment of the segmented gate covers the second well, a first interface between the first gate electrode segment of the segmented gate and the second gate electrode segment of the segmented gate is directly on the first well, a second interface between the first gate electrode segment of the segmented gate and the third gate electrode segment of the segmented gate is directly on the first well, the second well, or a third interface between the first well and the second well.

10. The semiconductor device according to claim 1, wherein A second gate electrode segment of the segmented gate is adjacent to the second doped region, and a third gate electrode segment of the segmented gate is spaced apart from the third doped region in a direction substantially parallel to the substrate upper surface.

11. A semiconductor device, characterized by comprising: Comprise: a substrate; a first well disposed in the substrate having a first conductivity type; a first doped region and a second doped region disposed in the first well, wherein the first doped region and the second doped region are spaced apart from each other by a portion of the first well; and a segmented gate disposed on the portion of the first well, wherein the segmented gate comprises a first gate electrode segment of a second conductivity type, a second gate electrode segment of the first conductivity type, and a third gate electrode segment of the first conductivity type, and wherein the first gate electrode segment is disposed between the second gate electrode segment and the third gate electrode segment.

12. The semiconductor device according to claim 11, wherein The segmented gate comprises a first work function metal of the first conductivity type and a second work function metal of the second conductivity type disposed on the first work function metal, wherein the first work function metal of the first gate electrode segment has a first height, the first work function metal of the second gate electrode segment has a second height, the first work function metal of the third gate electrode segment has a third height, the first height is lower than the second height, and the first height is lower than the third height.

13. The semiconductor device according to claim 11, wherein The first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, wherein the first width is greater than the second width, and the first width is also greater than the third width. The first gate electrode segment has a first width, the second gate electrode segment has a second width, and the third gate electrode segment has a third width, wherein the first width is greater than the second width, and the first width is also greater than the third width.

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