Complementary inverter, preparation method thereof and electronic equipment

Abstract

The invention provides a complementary inverter, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and aims to improve the interconnection density of the complementary inverter and reduce the static power consumption of the complementary inverter. The complementary inverter comprises an N-type oxide transistor and a P-type oxide transistor which are electrically connected. The complementary inverter also includes a substrate. A first conductive through hole and a second conductive through hole are formed in the substrate in a penetrating mode. The N-type oxide transistor comprises a first grid electrode and a first drain electrode, the first drain electrode is arranged on the first surface of the substrate, and the first grid electrode is arranged on the side, away from the first surface, of the first drain electrode. The P-type oxide transistor comprises a second grid electrode and a second drain electrode, the second drain electrode is arranged on the second surface of the substrate, and the second grid electrode is arranged on the side, away from the second surface, of the second drain electrode. Wherein the first grid electrode and the second grid electrode are electrically connected through the first conductive through hole, and the first drain electrode and the second drain electrode are electrically connected through the second conductive through hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a complementary inverter, a preparation method thereof, and an electronic device. BACKGROUND

[0002] In the field of semiconductor technology, oxide semiconductor is a research hotspot for three-dimensional integration due to low-temperature process compatibility and high carrier mobility. Traditional silicon-based complementary metal oxide semiconductor (CMOS) process is difficult to realize multi-layer stacking due to high-temperature annealing, while oxide semiconductor thin film can be prepared at low temperature, which provides the possibility for vertical and front and back surface stacking integration. Such a process can save manufacturing area and provide a new path for improving integrated circuit density in the post-Moore era. SUMMARY

[0003] The present application provides a complementary inverter, a preparation method thereof, and an electronic device, which aims to improve the interconnection density of the complementary inverter and reduce the static power consumption of the complementary inverter.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions: In one aspect, a complementary inverter is provided, which includes an N-type oxide transistor and a P-type oxide transistor electrically connected. The complementary inverter further includes a substrate including a first surface and a second surface oppositely arranged. The substrate is provided with a first conductive via and a second conductive via penetrating therethrough. The N-type oxide transistor includes a first gate and a first drain, and the first drain is arranged on the first surface and the first gate is arranged on a side of the first drain away from the first surface. The P-type oxide transistor includes a second gate and a second drain, and the second drain is arranged on the second surface and the second gate is arranged on a side of the second drain away from the second surface. The first gate and the second gate are electrically connected through the first conductive via, and the first drain and the second drain are electrically connected through the second conductive via.

[0005] The complementary inverter provided by the embodiments of the present application includes an N-type oxide transistor and a P-type oxide transistor electrically connected. The complementary inverter further includes a substrate including a first surface and a second surface oppositely arranged. The substrate is provided with a first conductive via and a second conductive via penetrating therethrough. The first gate of the N-type oxide transistor and the second gate of the P-type oxide transistor are electrically connected through the first conductive via. The first drain of the N-type oxide transistor and the second drain of the P-type oxide transistor are electrically connected through the second conductive via.

[0006] It can be understood that the N-type oxide transistor is located on the first surface of the substrate, and the P-type oxide transistor is located on the second surface of the substrate. The N-type oxide transistor and the P-type oxide transistor are respectively arranged on opposite sides of the substrate in a direction perpendicular to the substrate, and are electrically connected, so as to realize vertical stacking and three-dimensional integration of transistors of different conductivity types, and improve the interconnection density of transistors in a unit area.

[0007] Further, the first gate and the second gate are supplied with power through the first conductive via, and the first drain and the second drain are supplied with power through the second conductive via, so as to form a complementary inverter of a CMOS structure. Due to the presence of the P-type oxide transistor, an upper pull network is provided for the complementary inverter, that is, the output node is pulled from a low level to a high level, so as to reduce the static power consumption of the complementary inverter.

[0008] In some embodiments, the N-type oxide transistor further comprises a first active layer arranged between the first drain and the first gate. The P-type oxide transistor further comprises a second active layer arranged between the first drain and the second gate. The material of the first active layer and the second active layer comprises an oxide semiconductor material.

[0009] In some embodiments, the material of the first active layer comprises at least one of indium gallium zinc oxide, indium tin oxide, tungsten-doped indium oxide, or indium oxide. The material of the second active layer comprises at least one of tin oxide or tellurium oxide.

[0010] In some embodiments, the N-type oxide transistor further comprises a first isolation layer and a first source, which are sequentially arranged on the side of the first drain away from the substrate. The P-type oxide transistor further comprises a second isolation layer and a second source, which are sequentially arranged on the side of the second drain away from the substrate. The complementary inverter further comprises a power supply line and a ground line, the power supply line is electrically connected with the second source, and the ground line is electrically connected with the first source.

[0011] In some embodiments, the N-type oxide transistor and the P-type oxide transistor overlap in a projection on the substrate.

[0012] In some embodiments, the first conductive via comprises an input voltage electrode, and the second conductive via comprises an output voltage electrode.

[0013] In another aspect, the application further provides a preparation method of a complementary inverter, which comprises: providing a substrate, the substrate comprising a first surface and a second surface arranged oppositely; forming a first conductive via and a second conductive via through the substrate; An N-type oxide transistor is formed on a first surface. The N-type oxide transistor includes a first gate and a first drain. The first drain is disposed on the first surface, and the first gate is disposed on the side of the first drain away from the first surface. A P-type oxide transistor is formed on the second surface. The P-type oxide transistor includes a second gate and a second drain. The second drain is disposed on the second surface, and the second gate is disposed on the side of the second drain away from the second surface.

[0014] The first gate and the second gate are electrically connected through a first conductive via, and the first drain and the second drain are electrically connected through a second conductive via, so as to realize the electrical connection between the N-type oxide transistor and the P-type oxide transistor.

[0015] In some embodiments, the N-type oxide transistor further includes a first isolation layer and a first source, the first isolation layer and the first source being sequentially stacked on the side of the first drain away from the substrate. Forming the N-type oxide transistor further includes providing a ground line and electrically connecting the ground line to the first source. The P-type oxide transistor further includes a second isolation layer and a second source, the second isolation layer and the second source being sequentially stacked on the side of the second drain away from the substrate. Forming the P-type oxide transistor further includes providing a power line and electrically connecting the power line to the second source.

[0016] In the method for fabricating a complementary inverter provided in the embodiments of this application, a first conductive via and a second conductive via are formed through a substrate. An N-type oxide transistor is formed on a first surface of the substrate, and a P-type oxide transistor is formed on a second surface of the substrate. The first gate of the N-type oxide transistor is electrically connected to the second gate of the P-type oxide transistor through the first conductive via. The first drain of the N-type oxide transistor is electrically connected to the second drain of the P-type oxide transistor through the second conductive via.

[0017] Understandably, the N-type oxide transistor is located on the first surface of the substrate, and the P-type oxide transistor is located on the second surface of the substrate. Along a direction perpendicular to the substrate, the N-type and P-type oxide transistors are respectively disposed on opposite sides of the substrate and are electrically connected, thereby achieving vertical stacking and three-dimensional integration of transistors with different conductivity types, increasing the interconnect density of transistors per unit area.

[0018] Furthermore, both the first gate and the second gate are powered through the first conductive via, and both the first drain and the second drain are powered through the second conductive via, thus forming a complementary inverter with a CMOS structure. The presence of the P-type oxide transistor provides a pull-up network for the complementary inverter, pulling the output node from a low level to a high level, thereby reducing the static power consumption of the complementary inverter.

[0019] On the other hand, this application also provides an electronic device including a complementary inverter as described in any of the above embodiments and a circuit board. The circuit board is electrically connected to the complementary inverter.

[0020] The above-described electronic device has the same structure and beneficial technical effects as the complementary inverters provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0022] Figure 1 A schematic diagram of the structure of a complementary inverter provided in an embodiment of this application; Figure 2 A circuit diagram of a complementary inverter provided for an embodiment of this application; Figure 3 A flowchart illustrating the fabrication method of the complementary inverter provided in the embodiments of this application; Figures 4-14 Schematic diagrams illustrating the steps of the preparation method provided for embodiments of this application; Figure 15 A schematic diagram of an electronic device provided for an embodiment of this application. Detailed Implementation

[0023] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0024] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0025] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0026] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0027] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0028] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0029] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0030] Oxide semiconductors (such as IGZO, IZTO, TeO) x SnO xDue to their low-temperature process compatibility (<200℃) and high carrier mobility (greater than 1cm² / Vs), silicon-based complementary metal-oxide-semiconductor (CMOS) technology has become a research hotspot in the field of 3D integration. Traditional silicon-based complementary metal-oxide-semiconductor (CMOS) processes are limited by high-temperature annealing temperatures (>1000℃), making multilayer stacking difficult. However, oxide semiconductor thin films can be prepared at low temperatures using physical vapor deposition (PVD) or atomic layer deposition (ALD), providing possibilities for vertical integration and front-and-back stacking of silicon wafers. This CMOS manufacturing process based on vertical integration and front-and-back stacking of silicon wafers can significantly save the manufacturing area of ​​logic processes, providing a new path to increase the density of integrated circuits from a system-wide perspective in the post-Moore's Law era.

[0031] However, a major challenge in existing technologies is finding P-type semiconductor materials with high consistency, high performance, and low process thermal budgets to form complementary CMOS inverters with N-type oxide semiconductors. Another major challenge is the miniaturization of transistors and interconnect density; complementary inverters based on oxide semiconductors often use planar transistors, which are vertically stacked on one side of a silicon wafer, but planar transistors face challenges in miniaturization. Yet another significant challenge is the interconnect density challenge inherent in traditional vertically stacked 3D integration, as the interconnects between N-type MOSFETs and P-type MOSFETs occupy a considerable area.

[0032] To address at least one of the aforementioned problems, in one aspect, embodiments of this application provide a complementary inverter. Figure 1 This is a schematic diagram of the structure of a complementary inverter provided in an embodiment of this application.

[0033] See Figure 1 The complementary inverter 10 includes an N-type oxide transistor 1 and a P-type oxide transistor 2 that are electrically connected.

[0034] For example, the complementary inverter 10 can be CMOS. Both the N-type oxide transistor 1 and the P-type oxide transistor 2 can be MOSFETs.

[0035] The complementary inverter 10 also includes a substrate 3, which includes a first surface 301 and a second surface 302 disposed opposite to each other. Exemplarily, the material of the substrate 3 may be silicon.

[0036] The substrate 3 has a through-hole 41 and a through-hole 42. For example, the first conductive via 41 and the second conductive via 42 can both be through-silicon vias (TSVs). For example, a through-hole can be formed in the substrate 3 and a conductive metal can be filled in the via to form the first conductive via 41 and the second conductive via 42.

[0037] See also Figure 1 The N-type oxide transistor 1 includes a first gate 11 and a first drain 12. The first drain 12 is disposed on a first surface 301, and the first gate 11 is disposed on the side of the first drain 12 away from the first surface 301.

[0038] For example, the N-type oxide transistor 1 further includes a first gate insulating layer 16, which is disposed on the side of the first gate 11 near the first surface 301. Along the Z direction, the first gate insulating layer 16 is used to achieve electrical isolation between the first gate 11 and the conductive layer located below the first gate 11.

[0039] For example, the material of the first gate insulating layer 16 can be at least one of hafnium oxide (HfO2), aluminum oxide (AlO2) or silicon oxide (SiO2).

[0040] See also Figure 1 The P-type oxide transistor 2 includes a second gate 21 and a second drain 22. The second drain 22 is disposed on the second surface 302, and the second gate 21 is disposed on the side of the second drain 22 away from the second surface 302.

[0041] For example, the P-type oxide transistor 2 further includes a second gate insulating layer 26 disposed on the side of the second gate 21 near the first surface 301. Along the Z direction, the second gate insulating layer 26 serves to provide electrical isolation between the second gate 21 and the conductive layer located below the second gate 21.

[0042] For example, the material of the second gate insulating layer 26 can be at least one of hafnium oxide (HfO2), aluminum oxide (AlO2) or silicon oxide (SiO2).

[0043] The first gate 11 and the second gate 21 are electrically connected through the first conductive via 41, and the first drain 12 and the second drain 22 are electrically connected through the second conductive via 42 to form a three-dimensional stacked complementary inverter 10.

[0044] It is understandable that the first gate 11 of the N-type oxide transistor 1 and the second gate 21 of the P-type oxide transistor 2 share the same voltage input terminal, namely the first conductive via 41, and both can be turned on by the voltage in the first conductive via 41.

[0045] The complementary inverter 10 provided in the embodiments of this application includes an N-type oxide transistor 1 and a P-type oxide transistor 2 electrically connected. The complementary inverter 10 also includes a substrate 3, which includes a first surface 301 and a second surface 302 disposed opposite to each other. A first conductive via 41 and a second conductive via 42 are disposed through the substrate 3. The first gate 11 of the N-type oxide transistor 1 is electrically connected to the second gate 21 of the P-type oxide transistor 2 through the first conductive via 41. The first drain 12 of the N-type oxide transistor 1 is electrically connected to the second drain 22 of the P-type oxide transistor 2 through the second conductive via 42.

[0046] It is understood that N-type oxide transistor 1 is located on the first surface 301 of substrate 3, and P-type oxide transistor 2 is located on the second surface 302 of substrate 3. Along the direction Z perpendicular to substrate 3, N-type oxide transistor 1 and P-type oxide transistor 2 are respectively disposed on opposite sides of substrate 3 and are electrically connected, thereby realizing the vertical stacking and three-dimensional integration of transistors with different conductivity types, and improving the interconnection density of transistors per unit area.

[0047] Furthermore, both the first gate 11 and the second gate 21 are powered through the first conductive via 41, and both the first drain 12 and the second drain 22 are powered through the second conductive via 42, thus forming a complementary inverter 10 with a CMOS structure. Due to the presence of the P-type oxide transistor 2, a pull-up network is provided for the complementary inverter 10, which pulls the output node from a low level to a high level, thereby reducing the static power consumption of the complementary inverter 10.

[0048] In some embodiments, see Figure 1 The N-type oxide transistor 1 further includes a first active layer 13, which is disposed between the first drain 12 and the first gate 11. For example, the first active layer 13 is disposed on the side of the first gate insulating layer 16 away from the first gate 11.

[0049] The P-type oxide transistor 2 further includes a second active layer 23 disposed between the first drain 12 and the second gate 21. For example, the second active layer 23 is disposed on the side of the second gate insulating layer 26 away from the second gate 21.

[0050] It is understandable that both the first active layer 13 and the second active layer 23 have channel regions. By controlling the movement of charge carriers in the aforementioned channel regions, the N-type oxide transistor 1 and the P-type oxide transistor 2 can be turned on or off.

[0051] For example, see [link to example]. Figure 1 The channel regions in the first active layer 13 and the second active layer 23 can both extend along the Z direction, thereby forming a transistor device structure with a vertical channel, breaking through the process limitations of device size miniaturization.

[0052] The materials of the first active layer 13 and the second active layer 23 both include oxide semiconductor materials.

[0053] In related technologies, the active layer material in the two different types of transistors of CMOS inverters is usually polysilicon or silicon.

[0054] When the active layer is made of polycrystalline silicon, which is composed of many small single-crystal grains of varying sizes and orientations, grain boundaries exist between these grains. These grain boundaries are regions of irregular atomic arrangement, and their presence significantly affects the electrical and mechanical properties of the material. In polycrystalline silicon, the different crystal orientations of different grains lead to anisotropy in the material as a whole, meaning that the physical properties (such as conductivity and mobility) of the material differ in different directions. During the formation of the active layer, due to the polycrystalline nature of polycrystalline silicon and variations in process conditions, the consistency of the active layer in different transistors is poor.

[0055] When silicon is used as the active layer material, its poor thermal stability and oxidation resistance lead to a thermal budget problem. This thermal budget problem refers to the combined impact of the time and cumulative temperature effects of silicon materials or device structures being exposed to high-temperature environments during the manufacturing process on device performance, reliability, and yield.

[0056] Understandably, see [link / reference] Figure 1 In the embodiments of this application, the materials of the first active layer 13 and the second active layer 23 both include oxide semiconductor materials. On the one hand, oxide semiconductor materials are isotropic, and the consistency of oxide semiconductor materials is better during the formation of the first active layer 13 and the second active layer 23, thereby improving the consistency of the complementary inverter 10.

[0057] On the other hand, oxide semiconductor materials have high thermal stability and oxidation resistance, so the possibility of thermal budget problems in the first active layer 13 and the second active layer 23 is small, which is beneficial to improving the performance, reliability and yield of the complementary inverter 10.

[0058] Furthermore, since the first active layer 13 and the second active layer 23 are made of the same material, the compatibility of the three-dimensional integration of the complementary inverter 10 is also improved.

[0059] In some embodiments, see Figure 1 The first active layer 13 is made of at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), or indium oxide (InO). The second active layer 23 is made of tin oxide (SnO). x ) or tellurium oxide (TeO) x At least one of the following.

[0060] For example, setting the material of the first active layer 13 of the N-type oxide transistor 1 to a material system such as IGZO, ITO, IWO, or InO can better adapt to the N-type conductive ions in the first active layer 13, thereby further improving the overall performance of the N-type oxide transistor 1. Setting the material of the second active layer 23 of the P-type oxide transistor 2 to SnO... x TeO x The material system can better adapt to the P-type conductive ions in the second active layer 23, thereby further improving the overall performance of the P-type oxide transistor 2.

[0061] In some embodiments, see Figure 1 The N-type oxide transistor 1 further includes a first isolation layer 14 and a first source 15, which are stacked sequentially on the side of the first drain 12 away from the substrate 3. The first isolation layer 14 can be used to achieve electrical isolation between the first source 15 and the first drain 12.

[0062] The P-type oxide transistor 2 further includes a second isolation layer 24 and a second source 25, which are stacked sequentially on the side of the second drain 22 away from the substrate 3. The second isolation layer 24 can be used to achieve electrical isolation between the second source 25 and the second drain 22.

[0063] For example, the materials of the first isolation layer 14 and the second isolation layer 24 can both be silicon dioxide (SiO2).

[0064] Figure 2 This is a circuit diagram of a complementary inverter provided for an embodiment of this application.

[0065] See Figure 2 The complementary inverter 10 also includes a power line VDD and a ground line VSS. The power line VDD is electrically connected to the second source 25, and the ground line VSS is electrically connected to the first source 15.

[0066] For example, the ground wire VSS can be a ground electrode with a voltage of 0V. The power wire VDD can be a positive power electrode with a positive voltage value.

[0067] It is understood that in the embodiments of this application, by vertically stacking the N-type oxide transistor 1 and the P-type oxide transistor 2, the second source 25 and the first source 15 are located on opposite sides of the substrate 3, thereby separating the two long power lines VDD and ground lines VSS, increasing the trace space, and reducing noise interference, thereby improving the overall performance of the complementary inverter 10.

[0068] In some embodiments, the orthogonal projection of the N-type oxide transistor 1 onto the substrate 3 overlaps with the orthogonal projection of the P-type oxide transistor 2 onto the substrate 3.

[0069] It is understandable that, along the direction Z perpendicular to the substrate 3, the N-type oxide transistor 1 and the P-type oxide transistor 2 are completely opposite to each other. That is, on the plane XY, the two transistors occupy only the plane area of ​​one transistor, which can further reduce the required plane area of ​​the substrate 3 and further improve the interconnection density of transistors per unit area in the vertically stacked complementary inverter 10.

[0070] In some embodiments, see Figure 1 The first conductive via 41 includes an input voltage electrode (Vin), and the second conductive via 42 includes an output voltage electrode (Vout).

[0071] It is understandable that the first gate 11 and the second gate 21 can obtain the same input voltage through the input voltage electrode, thereby simultaneously controlling the turn-on or turn-off of the N-type oxide transistor 1 and the P-type oxide transistor 2. Furthermore, the first drain 12 and the second drain 22 can obtain the same output voltage through the output voltage electrode, enabling the N-type oxide transistor 1 and the P-type oxide transistor 2 to be synchronously turned on or off, thus improving the performance, optimizing power consumption, and enhancing the reliability of the complementary inverter 10.

[0072] On the other hand, this application also provides a method for fabricating a complementary inverter. Figure 3 A flowchart illustrating the fabrication method of the complementary inverter provided in the embodiments of this application; Figures 4-14 The diagram shows the steps of the preparation method provided in the embodiments of this application.

[0073] See Figure 3 The preparation method includes the following steps S1 to S4: Step S1: See Figure 4 and Figure 5A substrate 3 is provided, which includes a first surface 301 and a second surface 302 disposed opposite to each other. Exemplarily, the material of the substrate 3 may be silicon.

[0074] For example, see Figure 4 A silicon wafer 30 is provided, and its thickness is reduced to the micrometer level by grinding and chemical mechanical polishing (CMP) to obtain a silicon wafer 30 such as Figure 5 The substrate 3 is shown. Furthermore, since the silicon wafer 30 has undergone CMP processing, both the first surface 301 and the second surface 302 are flat and smooth surfaces.

[0075] For example, since the substrate 3 is relatively thin at this time, in order to prevent the substrate 3 from cracking and being damaged in subsequent processes, the substrate 3 can be placed on a temporary carrier.

[0076] Step S2: See Figure 6 A first conductive via 41 and a second conductive via 42 are formed through the substrate 3.

[0077] For example, see Figure 6 Two through-holes can be formed on substrate 3 using a TSV process, and conductive metal can be filled into the two through-holes to form a first conductive via 41 and a second conductive via 42. For example, the conductive metal filled in the first conductive via 41 can serve as an input voltage electrode (Vin), and the conductive metal filled in the second conductive via 42 can serve as an output voltage electrode (Vout).

[0078] Step S3: See Figures 7-10 An N-type oxide transistor 1 is formed on the first surface 301. The N-type oxide transistor 1 includes a first gate 11 and a first drain 12. The first drain 12 is disposed on the first surface 301, and the first gate 11 is disposed on the side of the first drain 12 away from the first surface 301.

[0079] For example, see Figure 7 Electron beam evaporation can be used to deposit conductive metal on the first surface 301 to form a first drain 12, and the first drain 12 is electrically connected to the Vout electrode in the second conductive via 42. Then, plasma-enhanced chemical vapor deposition (PECVD) can be used to form a first isolation layer 14 on the side of the first drain 12 away from the substrate 3. Next, electron beam evaporation can be used again to deposit conductive metal on the side of the first isolation layer 14 away from the substrate 3 to form a first source 15. For example, the material of the first isolation layer 14 can be SiO2.

[0080] Next, see Figure 8 The first active layer 13 can be formed at low temperature using an ALD process. For example, the material of the first active layer 13 can be IGZO, ITO, IWO, InO, or other material systems.

[0081] For example, after forming the first active layer 13, N-type conductive ions can be implanted into a portion of the first active layer 13 to make that portion conductive, and the remaining unconductive portion of the first active layer 13 can serve as a channel region. For example, see below. Figure 8 The channel region of the first active layer 13 can be a portion extending along the Z direction.

[0082] Then, see Figure 9 The first gate insulating layer 16 can be formed on the first active layer 13 using an ALD process. See [link to ALD process]. Figure 10 An N-type oxide transistor 1 is formed on a first gate insulating layer 16 using an electron beam evaporation process. The first gate 11 is electrically connected to the Vin electrode in the first conductive via 41. The first gate insulating layer 16 can be used to achieve electrical isolation between the first gate 11 and the first active layer 13.

[0083] For example, see Figure 11 After forming the N-type oxide transistor 1, it will be as follows Figure 10 The structure shown is flipped so that the second surface 302 of the substrate 3 faces upward, so that a P-type oxide transistor 2 can be formed on the second surface 302 subsequently.

[0084] Step S4: Figures 12-14 A P-type oxide transistor 2 is formed on the second surface 302. The P-type oxide transistor 2 includes a second gate 21 and a second drain 22. The second drain 22 is disposed on the second surface 302, and the second gate 21 is disposed on the side of the second drain 22 away from the second surface 302, to form a P-type oxide transistor 2. Figure 1 The complementary inverter 10 is shown.

[0085] For example, see Figure 12 Electron beam evaporation can be used to deposit conductive metal on the second surface 302 to form the second drain 22, and the second drain 22 is electrically connected to the Vout electrode in the second conductive via 42. Then, a PECVD process can be used to form a second isolation layer 24 on the side of the second drain 22 away from the substrate 3. Next, an electron beam evaporation process can be used again to deposit conductive metal on the side of the second isolation layer 24 away from the substrate 3 to form the second source 25. For example, the material of the second isolation layer 24 can be SiO2.

[0086] Next, seeFigure 13 The second active layer 23 can be formed at low temperatures using a reactive DC sputtering process. For example, the material of the second active layer 23 can be SnO. x TeO x Materials systems, etc.

[0087] For example, after forming the second active layer 23, P-type conductive ions can be implanted at a portion of the second active layer 23 to make that portion conductive, and the remaining unconductive portion of the second active layer 23 can serve as a channel region. For example, see below. Figure 13 The channel region of the second active layer 23 can be a portion extending along the Z direction.

[0088] Then, see Figure 14 The second gate insulating layer 26 can be formed on the second active layer 23 using an ALD process. See [link to ALD process]. Figure 1 A second gate 21 is formed on the second gate insulating layer 26 using an electron beam evaporation process to form a P-type oxide transistor 2. Furthermore, the second gate 21 is electrically connected to the Vin electrode in the first conductive via 41. The second gate insulating layer 26 can be used to achieve electrical isolation between the second gate 21 and the second active layer 23.

[0089] Among them, see Figure 1 The first gate 11 and the second gate 21 are electrically connected through the first conductive via 41, and the first drain 12 and the second drain 22 are electrically connected through the second conductive via 42, so as to realize the electrical connection between the N-type oxide transistor 1 and the P-type oxide transistor 2.

[0090] In the method for fabricating the complementary inverter 10 provided in the embodiments of this application, a first conductive via 41 and a second conductive via 42 are formed through a substrate 3. An N-type oxide transistor 1 is formed on a first surface 301 of the substrate 3, and a P-type oxide transistor 2 is formed on a second surface 302 of the substrate 3. The first gate 11 of the N-type oxide transistor 1 is electrically connected to the second gate 21 of the P-type oxide transistor 2 through the first conductive via 41. The first drain 12 of the N-type oxide transistor 1 is electrically connected to the second drain 22 of the P-type oxide transistor 2 through the second conductive via 42.

[0091] It is understood that N-type oxide transistor 1 is located on the first surface 301 of substrate 3, and P-type oxide transistor 2 is located on the second surface 302 of substrate 3. Along the direction Z perpendicular to substrate 3, N-type oxide transistor 1 and P-type oxide transistor 2 are respectively disposed on opposite sides of substrate 3 and are electrically connected, thereby realizing the vertical stacking and three-dimensional integration of transistors with different conductivity types, and improving the interconnection density of transistors per unit area.

[0092] Furthermore, both the first gate 11 and the second gate 21 are powered through the first conductive via 41, and both the first drain 12 and the second drain 22 are powered through the second conductive via 42, thus forming a complementary inverter 10 with a CMOS structure. Due to the presence of the P-type oxide transistor 2, a pull-up network is provided for the complementary inverter 10, which pulls the output node from a low level to a high level, thereby reducing the static power consumption of the complementary inverter 10.

[0093] In some embodiments, see Figure 7 The N-type oxide transistor 1 further includes a first isolation layer 14 and a first source 15, which are stacked sequentially on the side of the first drain 12 away from the substrate 3. The process of forming the N-type oxide transistor 1 in step S3 above also includes providing a ground line VSS and electrically connecting the ground line VSS to the first source 15.

[0094] Understandably, the first source 15 can serve as the VSS electrode of the complementary inverter 10.

[0095] See Figure 12 The P-type oxide transistor 2 further includes a second isolation layer 24 and a second source 25, which are sequentially stacked on the side of the second drain 22 away from the substrate 3. The process of forming the P-type oxide transistor 2 in step S4 also includes providing a power line VDD and electrically connecting the power line VDD to the second source 25.

[0096] Understandably, the second source 25 can serve as the 10VDD electrode of the complementary inverter.

[0097] See Figure 1 In the above-mentioned fabrication process, by vertically stacking the N-type oxide transistor 1 and the P-type oxide transistor 2, the second source 25 and the first source 15 are located on opposite sides of the substrate 3, thereby separating the two long power lines VDD and ground lines VSS, increasing the trace space and reducing noise interference, thereby improving the overall performance of the complementary inverter 10.

[0098] On the other hand, embodiments of this application also provide an electronic device. Figure 15 A schematic diagram of an electronic device provided for an embodiment of this application.

[0099] See Figure 15 The electronic device 200 includes a complementary inverter 10 and a circuit board 300. The circuit board 300 is electrically connected to the complementary inverter 10. For example, the complementary inverter 10 may be disposed on and electrically connected to the circuit board 300.

[0100] For example, the electronic device 200 can be an array substrate or logic circuit or other device that requires the complementary inverter 10.

[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A complementary inverter, characterized by, The N-type oxide transistor and the P-type oxide transistor are electrically connected; The complementary type reverser further comprises a substrate, the substrate comprises a first surface and a second surface arranged oppositely; the substrate is provided with a first conductive via and a second conductive via penetrating through; The N-type oxide transistor comprises a first gate and a first drain, the first drain is arranged on the first surface, and the first gate is arranged on the side of the first drain away from the first surface; The P-type oxide transistor comprises a second gate and a second drain, the second drain is arranged on the second surface, and the second gate is arranged on the side of the second drain away from the second surface; The first gate and the second gate are electrically connected through the first conductive via, and the first drain and the second drain are electrically connected through the second conductive via.

2. The reverser of Claim 1 wherein, The N-type oxide transistor further comprises a first active layer arranged between the first drain and the first gate; The P-type oxide transistor further comprises a second active layer arranged between the first drain and the second gate; The materials of the first active layer and the second active layer both comprise oxide semiconductor materials.

3. The reverser of Claim 2 wherein, The material of the first active layer comprises at least one of indium gallium zinc oxide, indium tin oxide, tungsten-doped indium oxide or indium oxide; The material of the second active layer comprises at least one of tin oxide or tellurium oxide.

4. The reverser of Claim 1 wherein, The N-type oxide transistor further comprises a first isolation layer and a first source, the first isolation layer and the first source are sequentially arranged on the side of the first drain away from the substrate; The P-type oxide transistor further comprises a second isolation layer and a second source, the second isolation layer and the second source are sequentially arranged on the side of the second drain away from the substrate; The complementary type reverser further comprises a power line and a ground line, the power line is electrically connected with the second source, and the ground line is electrically connected with the first source.

5. The reverser of claim 1 wherein, The N-type oxide transistor in the substrate overlaps with the P-type oxide transistor in the substrate.

6. The reverser of claim 1 wherein, The first conductive via comprises an input voltage electrode, and the second conductive via comprises an output voltage electrode.

7. A method for fabricating a complementary inverter, characterized in that, The method comprises: providing a substrate, the substrate comprises a first surface and a second surface arranged oppositely; forming a first conductive via and a second conductive via penetrating through in the substrate; forming an N-type oxide transistor on the first surface; the N-type oxide transistor comprises a first gate and a first drain, the first drain is arranged on the first surface, and the first gate is arranged on the side of the first drain away from the first surface; forming a P-type oxide transistor on the second surface; the P-type oxide transistor comprises a second gate and a second drain, the second drain is arranged on the second surface, and the second gate is arranged on the side of the second drain away from the second surface; The first gate and the second gate are electrically connected through the first conductive via, and the first drain and the second drain are electrically connected through the second conductive via, so as to realize the electrical connection of the N-type oxide transistor and the P-type oxide transistor.

8. The production method according to claim 7, characterized by, The N-type oxide transistor further comprises a first isolation layer and a first source, which are sequentially stacked on the side of the first drain away from the substrate. The N-type oxide transistor is formed, and the forming further comprises: A ground wire is provided, and the ground wire is electrically connected with the first source; The P-type oxide transistor further comprises a second isolation layer and a second source, which are sequentially stacked on the side of the second drain away from the substrate. The P-type oxide transistor is formed, and the forming further comprises: A power supply wire is provided, and the power supply wire is electrically connected with the second source.

9. An electronic device, comprising: Comprises: The complementary inverter according to any one of claims 1-6; The circuit board is electrically connected with the complementary inverter.

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