Semiconductor device, display device, and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device, a display device, and a method of manufacturing the semiconductor device. The present invention suppresses a decrease in channel resistance of a semiconductor device using an oxide semiconductor. A method of manufacturing a semiconductor device includes forming an oxide semiconductor layer on a first insulating layer, forming a second insulating layer on the oxide semiconductor layer, forming a conductive layer on the second insulating layer, and forming a second insulating layer on the conductive layer. A resist mask having an opening overlapping at least a portion of the oxide semiconductor layer is formed over the second insulating layer and the conductive layer, and impurities are implanted into the oxide semiconductor layer via the second insulating layer using the resist mask.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor, a display device including the semiconductor device, and a method for manufacturing the semiconductor device. Background Technology

[0002] In recent years, the development of semiconductor devices using oxide semiconductors has been continuously advancing, replacing silicon semiconductors such as amorphous silicon, low-temperature polycrystalline silicon, and monocrystalline silicon (see, for example, Patent Document 1). For instance, transistors utilizing an oxide semiconductor layer as the channel have a simple structure and can be manufactured using low-temperature processes, similar to transistors containing an amorphous silicon layer. Transistors containing an oxide semiconductor layer are known to have higher field-effect mobility than transistors containing an amorphous silicon layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-006730 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] Transistors that use an oxide semiconductor layer as the channel often suffer from degraded electrical characteristics due to a decrease in channel resistance. For example, if hydrogen diffuses excessively into the oxide semiconductor forming the channel, the channel resistance decreases, and the transistor may unexpectedly operate in depletion mode.

[0008] One of the objectives of one embodiment of the present invention is to suppress the decrease in channel resistance of a semiconductor device using an oxide semiconductor.

[0009] Methods for solving problems

[0010] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, comprising: forming an oxide semiconductor layer on a first insulating layer, forming a second insulating layer on the oxide semiconductor layer, forming a conductive layer on the second insulating layer, forming a photoresist mask having an opening that overlaps at least a portion of the oxide semiconductor layer on the second insulating layer and the conductive layer, and using the photoresist mask to implant impurities into the oxide semiconductor layer through the second insulating layer.

[0011] An embodiment of the present invention relates to a semiconductor device comprising: an oxide semiconductor layer above a first insulating layer; a second insulating layer above the oxide semiconductor layer; and a conductive layer above the second insulating layer, wherein the oxide semiconductor layer includes a first region overlapping the conductive layer and a second region not overlapping the conductive layer, and the concentration of a predetermined impurity contained in the region of the second insulating layer overlapping the second region is higher than the concentration of the impurity contained in the region of the second insulating layer not overlapping the oxide semiconductor layer.

[0012] An embodiment of the present invention relates to a semiconductor device comprising: an oxide semiconductor layer above a first insulating layer; a second insulating layer above the oxide semiconductor layer; and a conductive layer above the second insulating layer, wherein the oxide semiconductor layer comprises a first region overlapping the conductive layer and a second region not overlapping the conductive layer, and the concentration of a predetermined impurity contained in the region of the first insulating layer overlapping the second region is higher than the concentration of the impurity contained in the region of the first insulating layer not overlapping the oxide semiconductor layer. Attached Figure Description

[0013] Figure 1 This is a schematic top view showing the configuration of a display device including a semiconductor device according to an embodiment of the present invention.

[0014] Figure 2 This is a schematic circuit diagram showing the equivalent circuit of a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0015] Figure 3 This is a schematic cross-sectional view showing the configuration of pixels of a semiconductor device according to an embodiment of the present invention.

[0016] Figure 4 This is a flowchart illustrating a method for manufacturing pixels comprising a semiconductor device according to an embodiment of the present invention.

[0017] Figure 5 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0018] Figure 6 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0019] Figure 7 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0020] Figure 8This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0021] Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0022] Figure 10A This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0023] Figure 10B This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0024] Figure 11 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0025] Figure 12 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0026] Figure 13 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0027] Figure 14 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0028] Figure 15 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0029] Figure 16 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0030] Figure 17 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0031] Figure 18 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0032] Figure 19A This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0033] Figure 19BThis is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0034] Figure 20A This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0035] Figure 20B This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0036] Figure 21 This is a schematic cross-sectional view showing the configuration of pixels of a semiconductor device according to an embodiment of the present invention.

[0037] Figure 22 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0038] Figure 23 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0039] Figure 24 This is a schematic cross-sectional view illustrating a method for manufacturing pixels of a semiconductor device according to an embodiment of the present invention.

[0040] Explanation of reference numerals in the attached figures

[0041] 10…Display device, 11…Substrate, 12…Display section, 13, 13a…Pixel, 14-1…Gate driving circuit, 14-2…Gate driving circuit, 16…Terminal, 17…Terminal section, 18…Flexible printed circuit, 19…Peripheral section, 20…Touch sensor, 100…Substrate, 110…Conductive layer, 120…Insulating layer, 130, 130a…Oxide semiconductor layer, 140…Insulating layer, 150…Conductive layer, 160…Insulating layer, 161, 162…Contact hole, 181, 182…Conductive layer, 190…Insulating layer, 191…Contact hole, 200…Pixel electrode, 210…Dike section, 212…Opening section, 220…Light-emitting layer, 230…Common electrode, 240…Sealing layer Detailed Implementation

[0042] The various embodiments of the present invention will now be described with reference to the accompanying drawings. The following disclosure is merely an example. Configurations readily conceived by those skilled in the art, while maintaining the spirit of the invention, through appropriate modifications to the configuration of the embodiments, are of course included within the scope of the present invention. Regarding the drawings, to make the description clearer, the width, thickness, and shape of the constituent elements are sometimes schematically shown compared to the actual embodiment. However, the shapes illustrated are merely examples and do not limit the interpretation of the present invention. In this specification, claims, and drawings (hereinafter referred to as "this specification, etc."), for constituent elements identical to those described with respect to previously presented drawings, there are instances where the same reference numerals are used and detailed descriptions are appropriately omitted.

[0043] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below." For ease of explanation, the terms "up" or "below" are used, but the vertical relationship between the substrate and the oxide semiconductor layer can also be configured as the opposite of the illustration. Furthermore, the phrase "oxide semiconductor layer on the substrate" simply describes the vertical relationship between the substrate and the oxide semiconductor layer; other components may be arranged between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking order in a structure composed of multiple layers. When described as "pixel electrode above the semiconductor device," it can also refer to the non-overlapping position of the semiconductor device and the pixel electrode when viewed from above. On the other hand, when described as "pixel electrode vertically above the semiconductor device," it indicates the overlapping position of the semiconductor device and the pixel electrode when viewed from above. It should be noted that "viewing from above" refers to viewing from a direction perpendicular to the surface of the substrate.

[0044] In this specification, multiple elements formed by etching or other processing of a single film are sometimes described as elements with different functions or effects. Elements composed of the same layer structure and the same material are described as elements composed of the same layer. That is, in this specification, when it is described as "A and B are the same layer," element A and element B are both elements formed by processing a single layer.

[0045] In this specification and other documents, unless otherwise specified, statements such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one of the groups selected from A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these statements do not exclude the possibility that α includes other constituent elements.

[0046] In this specification and the like, the term "semiconductor device" refers to any device capable of functioning by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are included in one type of semiconductor device. The semiconductor devices of the embodiments shown below can be used, for example, in display devices, integrated circuits (ICs) such as microprocessors (MPUs), or memory circuits.

[0047] In this specification and the like, the term "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure on which other optical components (such as polarizing components, backlights, touch panels, etc.) are mounted. The "electro-optical layer" can include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, provided there is no technical contradiction. Therefore, in the embodiments described later, an organic EL display device including an organic EL layer will be exemplified as a display device, but the structure in this embodiment can be applied to display devices that include the other electro-optical layers mentioned above.

[0048] In this specification and other materials, the term "membrane" and the term "layer" may be used interchangeably as appropriate.

[0049] Regarding the source and drain of a transistor, their functions can sometimes be interchanged depending on the voltage supplied to them. Therefore, in this specification and other documents, terms such as "source" and "drain" can be used interchangeably depending on the context.

[0050] It should be noted that the following implementation methods can be combined with each other as long as there is no technical contradiction.

[0051] <First Embodiment>

[0052] (Composition of the display device)

[0053] Hereinafter, a display device 10 according to an embodiment of the present invention will be described. In this embodiment, an organic EL display device is exemplified as the display device 10. An organic EL display device is a display device in which each pixel includes an organic EL element as a light-emitting element and a semiconductor device for driving the light-emitting element.

[0054] Figure 1 This is a schematic top view illustrating the configuration of a display device 10 including a semiconductor device according to an embodiment of the present invention. Figure 1As shown, the display device 10 includes a display portion 12 and a peripheral portion 19 disposed on a substrate 11. The display portion 12 has a plurality of pixels 13 arranged in a matrix. Each of the plurality of pixels 13 has a semiconductor device composed of a plurality of transistors and a light-emitting element, which will be described later. A touch sensor 20 is disposed on the display portion 12 and on the display portion 12.

[0055] The peripheral portion 19 is provided in a manner that surrounds the display portion 12. The peripheral portion 19 refers to the portion of the substrate 11 from the display portion 12 to the end of the substrate 11. That is, the peripheral portion 19 refers to the portion of the substrate 11 other than the portion where the display portion 12 is disposed (specifically, the outer portion of the display portion 12). The peripheral portion 19 has gate drive circuits 14-1 and 14-2, and a terminal portion 17 containing multiple terminals 16. The gate drive circuits 14-1 and 14-2 are provided in a manner that sandwiches the display portion 12. A flexible printed circuit 18, on which a driver IC 15 is mounted, is connected to the terminal portion 17. Multiple wirings (not shown) contained in the flexible printed circuit 18 are connected to the driver IC 15 and the terminal portion 17. Figure 1 In the example shown, the source drive circuit is assembled on the driver IC15. However, it is not limited to this example; the source drive circuit can also be formed using transistors on the substrate 11.

[0056] Driver IC 15 is connected to gate drive circuits 14-1 and 14-2 and multiple image signal lines VL. Gate drive circuit 14-1 or gate drive circuit 14-2 is connected to pixel 13 via selection control line Sg. Among the multiple selection control lines Sg, for example, the selection control lines Sg of odd-numbered rows are connected to gate drive circuit 14-1, and the selection control lines Sg of even-numbered rows are connected to gate drive circuit 14-2. Image signal lines VL are connected to pixel 13. Control signals SG for selecting each pixel 13 are supplied from driver IC 15 to display unit 12 via gate drive circuits 14-1 and 14-2 and selection control lines Sg (see...). Figure 2 Additionally, an image signal Vsig is supplied from the driver IC15 to the display unit 12 via the image signal line VL (see [link]). Figure 2 These signals can drive multiple transistors contained in pixel 13, thereby enabling image display on display unit 12 corresponding to the image signal Vsig. The high-potential power line SLa and the low-potential power line SLb connected to pixel 13 are respectively connected to different terminals 16.

[0057] As the substrate 11, a glass substrate, a quartz substrate, a ceramic substrate, a flexible plastic substrate, or a resin substrate can be used. When a flexible plastic substrate or a resin substrate is used as the substrate 11, the substrate 11 can be bent between the display section 12 and the terminal section 17. As a result, the area of ​​the bezel portion of the display device 10 can be reduced.

[0058] (The structure of a pixel circuit)

[0059] Figure 2 This is a schematic circuit diagram illustrating the circuit configuration of a pixel 13 comprising a semiconductor device according to an embodiment of the present invention. Each pixel 13 constituting the display device 10 is connected to a high-potential power line SLa, a low-potential power line SLb, a selection control line Sg, and an image signal line VL. The high-potential power line SLa is connected to a high-potential power supply Pvdd. The low-potential power line SLb is connected to a low-potential power supply Pvss. The selection control line Sg is connected to gate drive circuits 14-1 and 14-2. The image signal line VL is connected to a driver IC 15 that supplies the image signal Vsig.

[0060] Each pixel 13 has at least a driving transistor DRT, a selection transistor SST, and a light-emitting element OLED. A high-potential power supply Pvdd is connected to the anode of the light-emitting element OLED via the driving transistor DRT. A low-potential power supply Pvss is connected to the cathode of the light-emitting element OLED. In this embodiment, the anode of the light-emitting element OLED and the pixel electrode 200 (see...) Figure 3 ) connection, cathode and common electrode 230 (see Figure 3 )connect.

[0061] The driving transistor DRT is connected in series with the light-emitting element (OLED) between the high-potential power line SLa and the low-potential power line SLb. The driving transistor DRT functions as a current control element, controlling the current flowing through the OLED based on the gate-source voltage. The selection transistor SST functions as a switching element, selecting whether the two nodes are on or off, applying a voltage to the gate of the driving transistor DRT corresponding to the luminous intensity of the OLED. A holding capacitor Cs is provided between the gate and source of the driving transistor DRT. The holding capacitor Cs maintains the gate-source voltage of the driving transistor DRT.

[0062] In the select transistor SST, the gate is connected to the select control line Sg, one of the source or drain is connected to the image signal line VL, and the other of the source or drain is connected to the gate of the drive transistor DRT and the holding capacitor Cs. In the drive transistor DRT, the drain is connected to the high-potential power line SLa, and the source is connected to the holding capacitor Cs and the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is connected to the low-potential power line SLb. The drive transistor DRT outputs a drive current to the light-emitting element OLED corresponding to the image signal Vsig.

[0063] Although the illustration is omitted, pixel 13 may further include other transistors such as a correction transistor for the threshold of the correction drive transistor DRT, a reset transistor for resetting the voltage held by the holding capacitor Cs, etc.

[0064] In this embodiment, oxide semiconductors are used as the semiconductors employed in the select transistor SST and the drive transistor DRT. Since transistors using oxide semiconductors have low turn-off leakage current and can be driven at low frequencies, they have the characteristic of low power consumption. Therefore, by using oxide semiconductors to construct pixels, the power consumption of the display device 10 can be reduced. Furthermore, compared to transistors using so-called low-temperature polysilicon, transistors using oxide semiconductors have the characteristics of no observable kink effect and good saturation characteristics.

[0065] (Pixel structure)

[0066] Figure 3 This is a schematic cross-sectional view showing the configuration of pixel 13, which includes a semiconductor device according to an embodiment of the present invention. Figure 3 In pixel 13 shown, a driving transistor DRT, which supplies current to the light-emitting element OLED, is illustrated as a semiconductor device. Additionally, in Figure 3 Although not shown in the diagram, pixel 13 contains... Figure 2 The selection transistor SST is shown. Besides the drive transistor DRT and the selection transistor SST... Figure 3 Pixel 13 shown can also contain more transistors.

[0067] The driving transistor DRT of this embodiment includes: a conductive layer 110, an insulating layer 120, an oxide semiconductor layer 130, an insulating layer 140, a conductive layer 150, an insulating layer 160, a conductive layer 181, and a conductive layer 182 disposed on a substrate 100 having an insulating surface.

[0068] The substrate 100 is, for example, a glass substrate on which one or more insulating layers are formed, consisting of insulating oxides selected from silicon oxide (SiOx) or silicon nitride oxide (SiOxNy), or insulating nitrides selected from silicon nitride (SiNx) or silicon nitride oxide (SiNxOy). Here, silicon nitride oxide (SiNxOy) is a silicon oxide containing oxygen in a ratio less than nitrogen (x > y). Silicon nitride oxide (SiOxNy) is a silicon nitride containing nitrogen (N) in a ratio less than oxygen (O) (x > y).

[0069] In this embodiment, a substrate 100 having an insulating surface is formed by sequentially stacking a silicon nitride layer and a silicon oxide layer on a glass substrate from bottom to top. The silicon nitride layer serves as a protective layer to prevent contaminants (e.g., alkaline substances) from penetrating the glass substrate. However, this is not a limited example; a quartz substrate, ceramic substrate, plastic substrate, or resin substrate may be used instead of a glass substrate. Furthermore, the stacking order of the silicon oxide layer, silicon nitride layer, silicon nitride oxide layer, or silicon nitride oxide layer is optional.

[0070] A conductive layer 110 is disposed on the substrate 100. The conductive layer 110 functions as the gate electrode on the lower side of the driving transistor DRT. The conductive layer 110 can be made of aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material constituting the conductive layer 110. The conductive layer 110 also functions as a light-shielding layer to reduce light reaching the oxide semiconductor layer 130 from the lower side.

[0071] An insulating layer 120 is disposed on the conductive layer 110. The insulating layer 120 functions as a gate insulating layer on the lower side of the driving transistor DRT. As the insulating layer 120, one or more layers selected from silicon oxide, silicon nitride, silicon nitride oxide, or silicon oxide nitride can be used. In this embodiment, as the insulating layer 120, an insulating layer formed by sequentially stacking a silicon nitride layer and a silicon oxide layer from bottom to top is used. As will be described later, since an oxide semiconductor layer 130 is disposed on the insulating layer 120, the surface of the insulating layer 120 that is in contact with the oxide semiconductor layer 130 is preferably a silicon oxide layer.

[0072] The thickness of the insulating layer 120 is not particularly limited. In this embodiment, the thickness of the insulating layer 120 is set to 200 nm or more and 600 nm or less (preferably 300 nm or more and 500 nm or less, more preferably 350 nm or more and 450 nm or less). In this embodiment, the insulating layer 120 is a laminated structure composed of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm.

[0073] An oxide semiconductor layer 130 is disposed on top of the insulating layer 120. The oxide semiconductor layer 130 functions as the active layer in the driving transistor DRT. As the material constituting the oxide semiconductor layer 130, an amorphous oxide semiconductor (e.g., IGZO) can be used. The thickness of the oxide semiconductor layer 130 can be set to 10 nm or more and 100 nm or less (preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 40 nm or less).

[0074] The oxide semiconductor layer 130 can be formed by sputtering. The composition of the oxide semiconductor layer 130 formed by sputtering depends on the composition of the sputtering target.

[0075] In addition, such as Figure 3 As shown, the oxide semiconductor layer 130 is divided into a channel region CR, a source region SR, and a drain region DR. The channel region CR is the region overlapping with the conductive layer 150, which functions as a gate electrode, and forms a channel when a gate voltage is applied to the conductive layer 150. The source region SR and the drain region DR are regions with lower resistance compared to the channel region CR, and function as conductive regions. That is, the source region SR and the drain region DR have a higher conductivity than the channel region CR. In other words, the source region SR and the drain region DR have the properties of conductors, and the channel region has the properties of a semiconductor. As described later, the source region SR and the drain region DR are formed by adding impurities to the oxide semiconductor layer 130 using methods such as ion implantation.

[0076] An insulating layer 140 is disposed on the oxide semiconductor layer 130. The insulating layer 140 functions as the gate insulating layer on the upper side of the driving transistor DRT. One or more layers selected from silicon oxide, silicon nitride, silicon nitride oxide, or silicon oxide nitride can be used as the insulating layer 140. In this embodiment, a silicon oxide layer is used as the insulating layer 140. The insulating layer 140 preferably has a composition with few defects and close to stoichiometry. Specifically, the insulating layer 140 is preferably free of defects when evaluated by electron spin resonance (ESR) method. The thickness of the insulating layer 140 is not particularly limited. In this embodiment, the thickness of the insulating layer 140 is set to 50 nm or more and 300 nm or less (preferably 60 nm or more and 200 nm or less, more preferably 70 nm or more and 150 nm or less).

[0077] A conductive layer 150 is disposed on top of the insulating layer 140. The conductive layer 150 functions as the gate electrode on the upper side of the driving transistor DRT. The conductive layer 150 can be made of aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a molybdenum-tungsten alloy is used as the material constituting the conductive layer 150. The conductive layer 150 also functions as a light-shielding layer to reduce light reaching the oxide semiconductor layer 130 from the upper side.

[0078] As described above, the conductive layer 150 functions as the gate electrode on the upper side of the driving transistor DRT, and also as a gate wiring. In other words, the conductive layer 150 functions as a gate wiring, and the portion of the gate wiring that overlaps with the oxide semiconductor layer, which functions as the active layer of the transistor, functions as the gate electrode. Therefore, in this specification, the gate electrode and the gate wiring are sometimes described separately for ease of explanation, but sometimes they are integral components.

[0079] An insulating layer 160 is disposed on the conductive layer 150. The insulating layer 160 functions as an interlayer insulating layer in the driving transistor DRT. As the insulating layer 160, one or more layers selected from silicon oxide, silicon nitride, silicon nitride oxide, or silicon oxide nitride can be used. In this embodiment, a stacked structure including a silicon oxide layer and a silicon nitride layer is used as the insulating layer 160.

[0080] Conductive layers 181 and 182 are disposed on the insulating layer 160. Conductive layer 181 is connected to the source region SR of the oxide semiconductor layer 130 via a contact hole 161 disposed in the insulating layer 160, and functions as the source electrode in the driving transistor DRT. Conductive layer 182 is connected to the drain region DR of the oxide semiconductor layer 130 via a contact hole 162 disposed in the insulating layer 160, and functions as the drain electrode in the driving transistor DRT. That is, conductive layers 181 and 182 respectively function as terminal electrodes in the driving transistor DRT.

[0081] Materials constituting conductive layers 181 and 182 may include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. In this embodiment, a laminated structure comprising titanium and aluminum layers is used as the materials constituting conductive layers 181 and 182.

[0082] As explained above, the driving transistor DRT in this embodiment is a dual-gate transistor, comprising a lower side gate electrode (conductive layer 110) opposed to the oxide semiconductor layer 130 separated by an insulating layer 120, and an upper side gate electrode (conductive layer 150) opposed to the oxide semiconductor layer 130 separated by an insulating layer 140. However, not limited to this example, the driving transistor DRT can also be a top-gate transistor. For example, in the case of… Figure 3 When the conductive layer 110 is not used as a gate electrode, such as when a fixed voltage is applied to the conductive layer 110, the driving transistor DRT functions as a top-gate transistor.

[0083] An insulating layer 190 is provided on top of the driving transistor DRT as a planarization layer made of resin material. The pixel electrode 200 is connected to the conductive layer 181 (i.e., the source electrode of the driving transistor DRT) through a contact hole 191 provided in the insulating layer 190. In this embodiment, the pixel electrode 200 uses a stacked structure of a layer containing silver (Ag) and a layer containing a metal oxide (e.g., ITO), but is not limited to this example.

[0084] A dam 210 made of resin material is provided on top of the pixel electrode 200. The dam is also referred to as a partition or rib. The dam 210 is provided in such a way that it covers a portion of the pixel electrode 200. That is, the dam 210 has an opening 212 at the position where it overlaps with the pixel electrode 200. The area of ​​the pixel electrode 200 not covered by the dam 210 (exposed area) functions as the light-emitting area of ​​the pixel 13. A light-emitting layer 220 made of organic EL (electroluminescent) material is provided in such a way that it covers the exposed area of ​​the pixel electrode 200.

[0085] Furthermore, a common electrode 230 is provided in a manner that covers the embankment 210 and the light-emitting layer 220. Figure 3 Although not shown in the diagram, the common electrode 230 is arranged across multiple pixels 13. The pixel electrode 200, the light-emitting layer 220, and the common electrode 230 constitute the light-emitting element OLED. The pixel electrode 200 functions as the anode of the light-emitting element OLED. The common electrode 230 functions as the cathode of the light-emitting element OLED.

[0086] A sealing layer 240 is provided on top of the light-emitting element OLED. The sealing layer 240 is a protective layer for preventing moisture and other substances from intruding from the outside. In this embodiment, the sealing layer 240 is a laminated structure formed by stacking an inorganic insulating layer, an organic insulating layer, and another inorganic insulating layer in that order from the bottom layer. For example, a silicon nitride layer can be used as the inorganic insulating layer. For example, an organic resin layer (e.g., a resin layer made of polyimide or acrylic acid) can be used as the organic insulating layer.

[0087] As explained above, a driving transistor DRT is provided in pixel 13, and in connection with the manufacturing method described later, a characteristic impurity distribution exists around the driving transistor DRT. This will be described in detail along with the manufacturing method of the semiconductor device described below.

[0088] (Methods for manufacturing pixels)

[0089] Figure 4 This is a flowchart illustrating a method for manufacturing a pixel 13 comprising a semiconductor device according to an embodiment of the present invention. Figures 5 to 18This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13 of a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the semiconductor device manufacturing method of this embodiment includes steps S1010 to S1130. Hereinafter, steps S1010 to S1130 will be described sequentially, but the order of the steps may sometimes be changed in the semiconductor device manufacturing method of this embodiment. Furthermore, in the semiconductor device manufacturing method of this embodiment, one or more steps may be omitted, or further steps may be included.

[0090] First, such as Figure 4 and Figure 5 As shown, a conductive layer 110 (first conductive layer) with a predetermined pattern shape is formed on the substrate 100 (step S1010). The patterning of the conductive layer 110 is performed using photolithography. In this embodiment, the conductive layer 110 functions as a light-shielding layer.

[0091] Next, as Figure 4 and Figure 6 As shown, an insulating layer 120 (first insulating layer) is formed by covering the conductive layer 110. The insulating layer 120 is formed using chemical vapor deposition (CVD). In this embodiment, the insulating layer 120 is a stacked structure consisting of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm.

[0092] Next, as Figure 4 and Figure 7 As shown, an oxide semiconductor layer 130 with a predetermined pattern shape is formed on the insulating layer 120 (step S1030). The oxide semiconductor layer 130 is formed in a manner that overlaps with the conductive layer 110. The oxide semiconductor layer 130 is formed by patterning an oxide semiconductor film deposited by sputtering into a predetermined shape using photolithography.

[0093] Amorphous oxide semiconductor films can be easily patterned using photolithography. When etching oxide semiconductor films, either wet etching or dry etching can be used. In the case of wet etching, an acidic etching solution can be used to etch the oxide semiconductor film. For example, oxalic acid solution, PAN (a mixture of phosphoric acid, nitric acid, and acetic acid) solution, sulfuric acid solution, hydrogen peroxide, or hydrofluoric acid solution can be used as the etching solution.

[0094] Furthermore, the oxide semiconductor layer 130 having a prescribed pattern shape is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1030 will be referred to as "OS annealing". In OS annealing, the oxide semiconductor layer 130 is held at a prescribed arrival temperature for a prescribed time. The prescribed arrival temperature is 300°C or higher and 500°C or lower (preferably 350°C or higher and 450°C or lower). Additionally, the holding time at the arrival temperature is 15 minutes or higher and 120 minutes or lower (preferably 30 minutes or higher and 60 minutes or lower).

[0095] Next, as Figure 4 and Figure 8 As shown, an insulating layer 140 (second insulating layer) is formed on the oxide semiconductor layer 130 (step S1040). In this embodiment, a silicon oxide layer with a thickness of 100 nm is used as the insulating layer 140. Furthermore, the insulating layer 140 is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1040 will be referred to as "oxidative annealing". Due to the formation of the oxide semiconductor layer 130 and the insulating layer 140, a large number of oxygen defects are generated inside the oxide semiconductor layer 130. If oxidative annealing is performed, oxygen is supplied from the insulating layer 140 to the oxide semiconductor layer 130, and the oxygen defects in the oxide semiconductor layer 130 are repaired.

[0096] In this embodiment, an example is shown where oxidation annealing is performed in the state after the insulating layer 140 has been formed. However, it is also possible to introduce oxygen into the insulating layer 140 before oxidation annealing. For example, an aluminum oxide layer can be formed on the insulating layer 140 by sputtering, and oxidation annealing can be performed in the state where the aluminum oxide layer has been formed. In this case, oxygen is injected into the interior of the insulating layer 140 during the formation of the aluminum oxide layer, thereby increasing the oxygen content inside the insulating layer 140. Therefore, a sufficient amount of oxygen can be supplied to the oxide semiconductor layer 130 by oxidation annealing.

[0097] Next, as Figure 4 and Figure 9 As shown, a conductive layer 150 (second conductive layer) is formed on the insulating layer 140 (step S1050). In this embodiment, the conductive layer 150 functions as a gate wiring. In this embodiment, a metal film made of molybdenum-tungsten alloy is formed by sputtering, and the metal film is patterned into a predetermined shape to form the conductive layer 150. In this embodiment, the thickness of the conductive layer 150 is set to 300 nm, but it is not limited to this example.

[0098] Next, as Figure 4 , Figure 10A and Figure 10BAs shown, a resist mask RM is formed on the insulating layer 140 (step S1060). In this embodiment, the resist mask RM is formed in a region that does not overlap with the oxide semiconductor layer 130. Specifically, the resist mask RM has an opening RM1 that completely overlaps with the oxide semiconductor layer 130. That is, as... Figure 10A As shown, the position of the inner wall of the opening RM1 and the position of the end of the oxide semiconductor layer 130 are aligned in a direction perpendicular to the substrate 100. In other words, as... Figure 10A and Figure 10B As shown, when viewed from above, the shape of the edge of the opening RM1 in the resist mask RM is consistent with the shape of the edge of the oxide semiconductor layer 130. Here, "consistent" includes not only the case of complete consistency, but also the case where it is within the range of alignment error during the formation of the resist mask RM. For example, even if the position of the edge of the opening RM1 differs from the position of the edge of the oxide semiconductor layer 130 within a range of 1.5 μm (preferably 1.0 μm, more preferably 0.5 μm), it is considered that the edge of the opening RM1 is consistent with the edge of the oxide semiconductor layer 130.

[0099] Next, as Figure 4 and Figure 11 As shown, impurities are implanted into the oxide semiconductor layer 130 through the insulating layer 140 (step S1070). For example, impurities can be implanted into the oxide semiconductor layer 130 using ion implantation. As impurities, for example, argon (Ar), phosphorus (P), or boron (B) can be used. However, it is not limited to this example, and other elements can also be used.

[0100] In this embodiment, since a conductive layer 150 is formed on the oxide semiconductor layer 130, the conductive layer 150 functions as a mask, preventing impurity implantation into a portion of the oxide semiconductor layer 130. Therefore, impurities are not implanted into the region of the oxide semiconductor layer 130 that overlaps with the conductive layer 150, forming a channel region CR in that region. Furthermore, a source region SR and a drain region DR are formed in the oxide semiconductor layer 130 in regions where impurities are implanted because they do not overlap with the conductive layer 150. In the source region SR and drain region DR, oxygen defects are generated inside the oxide semiconductor layer 130 through impurity implantation, and hydrogen is captured by these oxygen defects. Thus, the source region SR and drain region DR are conductive and have a higher conductivity than the channel region CR.

[0101] Here, the technical implications of configuring the resist mask RM in this embodiment will be explained. In this embodiment, impurities are added to the oxide semiconductor layer 130 through the insulating layer 140. In this embodiment, since a silicon oxide layer is used as the insulating layer 140, the Si-O bonds and Si-H bonds contained in the silicon oxide layer are sometimes broken due to collisions with the impurities. As a result, oxygen and hydrogen are generated in the regions through which the impurities pass during ion implantation in the insulating layer 140. In particular, the generated hydrogen readily moves within the insulating layer 140 when heated in subsequent processes. Such hydrogen diffusion can, for example, become a major cause of low resistance in the channel region CR (i.e., a decrease in channel resistance).

[0102] Therefore, in this embodiment, a resist mask RM is disposed around the oxide semiconductor layer 130 to minimize the area of ​​the insulating layer 140 exposed to ion implantation. In the region where the resist mask RM is disposed, impurities do not penetrate the interior of the insulating layer 140, thus preventing the generation of hydrogen within the insulating layer 140. During ion implantation, the area where the oxide semiconductor layer 130 is not formed occupies a much larger area than the area where the oxide semiconductor layer 130 is formed. That is, by disposing the resist mask RM around the oxide semiconductor layer 130, the amount of hydrogen generated near the oxide semiconductor layer 130 can be significantly reduced, effectively suppressing the decrease in channel resistance caused by hydrogen diffusion.

[0103] As described above, in this embodiment, when impurities are added to the oxide semiconductor layer 130 to form the source region SR and drain region DR, a resist mask RM is disposed around the oxide semiconductor layer 130, thereby reducing the amount of hydrogen generated inside the insulating layer 140. This suppresses the decrease in channel resistance caused by hydrogen diffusion, enabling the manufacture of a highly reliable semiconductor device.

[0104] In this embodiment, when adding impurities via ion implantation, the accelerating voltage and dosage are determined with the oxide semiconductor layer 130 as the target in the depth direction. That is, when the impurities implanted into the oxide semiconductor layer 130 and the insulating layer 140 via ion implantation have a predetermined distribution in the depth direction, the accelerating voltage is adjusted so that the peak of the distribution is located in the oxide semiconductor layer 130. Conversely, according to this embodiment, the insulating layer 120 contains impurities that have passed through the oxide semiconductor layer 130, and the insulating layer 140 contains impurities that have not reached the oxide semiconductor layer 130. This means that in the implementation... Figure 11 In the process shown, a characteristic impurity distribution is formed around the oxide semiconductor layer 130.

[0105] Figure 12This is a schematic cross-sectional view illustrating a method for manufacturing pixels comprising a semiconductor device according to an embodiment of the present invention. Figure 12 The text shows the implementation details. Figure 11 The diagram shows the state after the process (bottom image) and an enlarged view of the vicinity of the source region SR of the oxide semiconductor layer 130 (top image). Figure 12 In the enlarged view shown, insulating layers 120 and 140 are each divided into three regions. The following is a description of each region.

[0106] The insulating layer 120 is divided into a first region BR1, a second region BR2, and a third region BR3. The first region BR1 overlaps with both the oxide semiconductor layer 130 and the conductive layer 150. The second region BR2 overlaps with the oxide semiconductor layer 130 but not with the conductive layer 150. The third region BR3 does not overlap with either the oxide semiconductor layer 130 or the conductive layer 150. It should be noted that in this embodiment, the insulating layer 120 has a stacked structure consisting of a silicon nitride layer and a silicon oxide layer sequentially from the substrate 100 side. That is, the three divisions in the insulating layer 120 substantially correspond to dividing the silicon oxide layer adjacent to the oxide semiconductor layer 130 into three regions.

[0107] The insulating layer 140 is also divided into three regions, GR1, GR2, and GR3, similar to the insulating layer 120. Region GR1 overlaps with both the oxide semiconductor layer 130 and the conductive layer 150. Region GR2 overlaps with the oxide semiconductor layer 130 but not with the conductive layer 150. Region GR3 does not overlap with either the oxide semiconductor layer 130 or the conductive layer 150.

[0108] According to this embodiment, the conductive layer 150 and the resist mask RM function as masks, therefore no impurities are added directly beneath the conductive layer 150 and the resist mask RM. That is, in the case of the insulating layer 120, the first region BR1 and the third region BR3 are free of impurities, while the second region BR2 contains impurities. In other words, the concentration of impurities in the region of the insulating layer 120 overlapping with the source region SR (the second region BR2) is higher than the concentration of impurities in the region of the insulating layer 120 not overlapping with the oxide semiconductor layer 130 (the third region BR3). Furthermore, the concentration of impurities in the region of the insulating layer 120 overlapping with the source region SR (the second region BR2) is higher than the concentration of impurities in the region of the insulating layer 120 overlapping with the channel region CR (the first region BR1). The difference in impurity concentration varies depending on the accelerating voltage and dosage. It can be said that the concentration of impurities contained in the second region BR2 is more than 100 times (preferably 1000 times) the concentration of impurities contained in the first region BR1 and the third region BR3.

[0109] The insulating layer 140 can also be described as being the same as the insulating layer 120. That is, in the case of the insulating layer 140, the first region GR1 and the third region GR3 are free of impurities, while the second region GR2 contains impurities. In other words, the concentration of impurities in the region of the insulating layer 140 that overlaps with the source region SR (the second region GR2) is higher than the concentration of impurities in the region of the insulating layer 140 that does not overlap with the oxide semiconductor layer 130 (the third region GR3). Furthermore, the concentration of impurities in the region of the insulating layer 140 that overlaps with the source region SR (the second region GR2) is higher than the concentration of impurities in the region of the insulating layer 140 that overlaps with the channel region CR (the first region GR1). The difference in impurity concentration varies depending on the accelerating voltage and the dose, but it can be said that the concentration of impurities in the second region GR2 is 100 times (preferably 1000 times) or more than the concentration of impurities in the first region GR1 and the third region GR3.

[0110] As mentioned above, in implementation Figure 11 In the process illustrated, whether the insulating layer 120 or the insulating layer 140 contains impurities can be clearly distinguished based on whether it overlaps with the oxide semiconductor layer 130. That is, by analyzing the impurity concentration around the oxide semiconductor layer 130 using methods such as SIMS, it is easy to determine whether impurities have been present. Figure 11 The process shown.

[0111] Next, as Figure 4 and Figure 13As shown, a third insulating layer (insulating layer 160) is formed by covering the conductive layer 150 (step S1080). In this embodiment, the insulating layer 160 is formed by plasma CVD, having a stacked structure of silicon oxide layers and silicon nitride layers sequentially stacked from the bottom layer. The insulating layer 160 can be a stacked structure of silicon nitride layers and silicon oxide layers sequentially stacked from the bottom layer, or it can be a single-layer structure of either silicon nitride or silicon oxide layers. Furthermore, contact holes 161 and 162 are formed in the portions of the insulating layers 140 and 160 that overlap with the source region SR and drain region DR of the oxide semiconductor layer 130, respectively.

[0112] Next, as Figure 4 and Figure 14 As shown, a third conductive layer (conductive layers 181 and 182) is formed on the insulating layer 160 (step S1090). Specifically, a three-layer metal layer consisting of a titanium layer, an aluminum layer, and another titanium layer is formed by sputtering, and the metal layer is patterned into a predetermined shape to form conductive layers 181 and 182. Conductive layers 181 and 182 are electrically connected to the oxide semiconductor layer 130 via contact holes 161 and 162, respectively. That is, conductive layer 181 is connected to the source region SR and functions as a source electrode, and conductive layer 182 is connected to the drain region DR and functions as a drain electrode.

[0113] Next, as Figure 4 and Figure 15 As shown, a fourth insulating layer (insulating layer 190) is formed by covering conductive layers 181 and 182 (step S1100). In this embodiment, the insulating layer 190 is formed by coating a resin material (e.g., acrylic or polyimide) using a solution coating method. In this embodiment, a photosensitive acrylic material is used as the insulating layer 190. By exposing and photosensitive using the photosensitive resin material, an insulating layer 190 having contact holes 191 can be formed. In this embodiment, the contact holes 191 are formed in the portion of the insulating layer 190 that overlaps with the conductive layer 181.

[0114] In this embodiment, an example of forming the insulating layer 190 by solution coating is shown, but it is not limited to this example; it can also be formed by other methods such as printing. The insulating layer 190 functions as a planarization layer. Therefore, the thickness of the insulating layer 190 is preferably 1 μm or more and 4 μm or less (preferably 2 μm or more and 3 μm or less).

[0115] Next, as Figure 4 and Figure 16As shown, a pixel electrode 200 is formed on the insulating layer 190 (step S1110). Specifically, a transparent conductive film (metal oxide film) is formed on the insulating layer 190 by sputtering and patterned into a predetermined pattern shape, thereby forming the pixel electrode 200. In this embodiment, ITO (indium tin oxide) is used as the material constituting the pixel electrode 200. The pixel electrode 200 is electrically connected to the conductive layer 181, which functions as a source electrode, via a contact hole 191.

[0116] Next, as Figure 4 and Figure 17 As shown, a dam 210 is formed on the pixel electrode 200 (step S1120). A resin material (e.g., a photosensitive acrylic material) can be used as the material constituting the dam 210. Specifically, after coating the resin material by a solution coating method or the like, exposure and development are performed to form the dam 210, which includes the opening 212. Figure 17 As shown, the opening 212 provided in the embankment 210 exposes most of the upper surface of the pixel electrode 200.

[0117] After the embankment 210 is formed, a light-emitting layer 220 made of organic EL material is formed, overlapping with the opening 212. In this embodiment, the light-emitting layer 220 is formed by vapor deposition of an organic EL material that emits red, green, or blue light. The light-emitting layer 220 is formed according to the emission color of the pixel 13. That is, the pixel 13 that emits red light uses an organic EL material that emits red light, the pixel 13 that emits green light uses an organic EL material that emits green light, and the pixel 13 that emits blue light uses an organic EL material that emits blue light. In addition to the light-emitting layer made of a light-emitting material, the light-emitting layer 220 may also include an electron injection layer, an electron transport layer, an electron blocking layer, a hole injection layer, a hole transport layer, or a hole blocking layer as a functional layer made of a functional material.

[0118] A common electrode 230 is formed on the light-emitting layer 220. In this embodiment, the common electrode 230 is formed by vapor deposition of a layer containing magnesium and silver. The common electrode 230 may also be provided across multiple pixels. By forming the common electrode 230, an OLED light-emitting element composed of pixel electrode 200, light-emitting layer 220 and common electrode 230 is formed.

[0119] Finally, as Figure 4 and Figure 18As shown, a sealing layer 240 is formed to cover the light-emitting element OLED (step S1130). Although not shown in the figure, the sealing layer 240 has a stacked structure in which a silicon nitride layer, an organic resin layer (e.g., an acrylic layer), and a silicon nitride layer are stacked sequentially from the bottom layer. However, it is not limited to this example; a silicon oxide layer and an amorphous silicon layer may also be provided between the silicon nitride layer and the organic resin layer. By providing these layers, the adhesion between the silicon nitride layer and the organic resin layer can be improved. In addition, in this embodiment, a touch sensor 20 (see [reference]) is provided on the sealing layer 240. Figure 1 Therefore, an outer coating layer can also be provided on the sealing layer 240 for the purpose of planarization.

[0120] Pixel 13, which includes a driving transistor DRT as a semiconductor device, is fabricated using the process described above. In this embodiment, the amount of hydrogen generated in insulating layers 120 and 140 during ion implantation can be significantly reduced. Therefore, hydrogen diffusion after ion implantation can be effectively suppressed, enabling the fabrication of a highly reliable semiconductor device with suppressed channel resistance reduction.

[0121] (A variation of the first embodiment)

[0122] like Figure 10A and Figure 10B As shown, in this embodiment, the position of the inner wall of the opening RM1 of the resist mask RM and the position of the end of the oxide semiconductor layer 130 are aligned in a direction perpendicular to the substrate 100. However, this is not limited to this example; the size of the opening RM1 may be larger or smaller than the size of the oxide semiconductor layer 130.

[0123] Figure 19A and Figure 19B This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13 of a semiconductor device according to a modified embodiment of the present invention. In this modified embodiment, the resist mask RM is configured to overlap the end of the oxide semiconductor layer 130 by a predetermined distance (L1 in this case). Specifically, as Figure 19B As shown, the resist mask RM is disposed along the outer periphery of the oxide semiconductor layer 130 in an overlapping manner with a width of L1. The acceptable range of distance L1 is not particularly limited, but it is desirable to be 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less). If the distance L1 is too large, the effective area of ​​the oxide semiconductor layer 130 decreases. Furthermore, if the distance L1 is too small, sometimes when the resist mask RM shifts position, portions of the oxide semiconductor layer 130 and the resist mask RM may not overlap.

[0124] As described above, in the case of Modified Example 1, the size of the opening RM1 of the resist mask RM is smaller than the size of the oxide semiconductor layer 130. That is, when viewed from above, the outline of the edge of the oxide semiconductor layer 130 encloses the outline of the edge of the opening RM1. By adopting this configuration, the area in the insulating layer 140 where impurities are added can be minimized. Therefore, the amount of hydrogen generated around the oxide semiconductor layer 130 can be significantly suppressed.

[0125] Next, Figure 20A and Figure 20B This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13 of a semiconductor device according to a modified embodiment of the present invention. In this modified embodiment, the resist mask RM is arranged at a predetermined distance (L2 in this case) from the end of the oxide semiconductor layer 130. Specifically, as Figure 20B As shown, the resist mask RM is disposed along the outer periphery of the oxide semiconductor layer 130 with a width L2 separating it from the oxide semiconductor layer 130. The acceptable range of distance L2 is not particularly limited, but it is desirable to be 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less). If the distance L2 is too large, the exposed area of ​​the insulating layer 140 increases, potentially leading to an increase in the amount of hydrogen generated inside the insulating layer 140. Conversely, if the distance L2 is too small, the oxide semiconductor layer 130 overlaps with the resist mask RM when the resist mask RM shifts position, sometimes reducing the effective area of ​​the oxide semiconductor layer 130.

[0126] As described above, in the case of Modification 2, the size of the opening RM1 of the resist mask RM is larger than the size of the oxide semiconductor layer 130. That is, when viewed from above, the outline of the edge of the opening RM1 encloses the outline of the edge of the oxide semiconductor layer 130. By adopting this configuration, the oxide semiconductor layer 130 (especially the source region SR and drain region DR) can be manufactured to the designed dimensions without compromising the area. Therefore, it is possible to prevent defects such as poor contact between the conductive layer 181 and the source region SR or between the conductive layer 182 and the drain region DR.

[0127] <Second Implementation>

[0128] In the first embodiment, an example in which a channel region CR, a source region SR, and a drain region DR are provided in the oxide semiconductor layer 130 was described. However, in this embodiment, an example in which a low-resistance region HRR is provided in addition to these regions is described. In the description of this embodiment, elements that are the same as those in the first embodiment are sometimes marked with the same reference numerals in the drawings and are omitted from the description.

[0129] (Pixel structure)

[0130] Figure 21 This is a schematic cross-sectional view showing the configuration of a pixel 13a of a semiconductor device according to an embodiment of the present invention. Figure 21 Basic structure and Figure 3 The pixel 13 shown is the same, but the structure of the oxide semiconductor layer 130a, which functions as the active layer of the semiconductor device, is different. Specifically, the oxide semiconductor layer 130a has low-resistance regions HRR between the channel region CR and the source region SR, and between the channel region CR and the drain region DR.

[0131] The low-resistance region (HRR) is a region with a relatively lower resistance than the channel region (CR). However, the resistance of the HRR is higher than that of the source region (SR) and the drain region (DR). The HRR functions as a buffer region, suppressing the movement of charge carriers from the channel region (CR) towards the source region (SR) or the drain region (DR). That is, functionally, it is similar to the region commonly referred to as the LDD region.

[0132] (Methods for manufacturing pixels)

[0133] Figure 22 and Figure 23 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13a of a semiconductor device according to an embodiment of the present invention.

[0134] First, implementation in the first embodiment Figure 4 Steps S1010 to S1060, as shown, involve forming a resist mask RM on the insulating layer 140. Figure 22 As shown, the difference between this embodiment and the first embodiment is that a photoresist mask RM is provided on the oxide semiconductor layer 130 to cover the conductive layer 150. In this case, the width of the photoresist mask RM covering the conductive layer 150 in the channel direction is set to be wider than the width of the conductive layer 150 in the channel direction. That is, the opening RM1 of the photoresist mask RM is separated from the conductive layer 150 by a predetermined distance (here, L3) in the channel direction. The range of the distance L3 is not particularly limited, but it is preferably 0.5 μm or more and 3.0 μm or less (preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.5 μm or more and 2.0 μm or less). In this case, the opening RM1 is formed to overlap with the region in the oxide semiconductor layer 130 that subsequently functions as the source region SR and the drain region DR.

[0135] Next, as Figure 22 As shown, a resist mask RM is used as a mask to implant impurities into the oxide semiconductor layer 130. The impurity implantation process is similar to... Figure 4 The process described in step S1070 is the same. By performing an impurity implantation process, a channel region CR, a source region SR, and a drain region DR are formed in the oxide semiconductor layer 130. In this embodiment, the area directly below the resist mask RM covering the conductive layer 150, that is, the area covered by the resist mask RM covering the conductive layer 150, is called the channel region CR (the area without impurities).

[0136] Next, as Figure 23 As shown, after removing the resist mask RM, the conductive layer 150 is used as a mask to implant impurities into the oxide semiconductor layer 130 again. That is, impurities are implanted into the oxide semiconductor layer 130 through... Figure 22 Impurities are injected into a region of the channel region CR that does not overlap with the conductive layer 150, formed by the process shown. Therefore, impurities are selectively injected into a portion of the channel region CR, forming a region with a lower resistance than the channel region CR.

[0137] At this time, Figure 23 In the process shown, with Figure 22 Compared to the process shown, the dosage (amount) of impurities is reduced. As a result, a low-resistance region HRR is formed between the channel region CR and the source region SR, and between the channel region CR and the drain region DR, where the resistance is lower than that of the channel region CR and higher than that of the source region SR and the drain region DR. Thus, in this embodiment, the channel region CR and the low-resistance region HRR are formed in a self-aligned manner.

[0138] In this embodiment, similarly to the first embodiment, when impurities are implanted into the oxide semiconductor layer 130, a photoresist mask RM is disposed around the oxide semiconductor layer 130, thereby suppressing the amount of hydrogen generated inside the insulating layer 120 or the insulating layer 140. Therefore, according to this embodiment, the decrease in channel resistance caused by hydrogen diffusion can be effectively suppressed.

[0139] (A variation of the second embodiment)

[0140] like Figure 23 As shown in this embodiment, an example is illustrated where the resist mask RM is removed during the formation of the low-resistance region HRR, and impurities are injected using the conductive layer 150 as a mask. However, this is not limited to this example; a new resist mask RMa may be formed during the formation of the low-resistance region HRR.

[0141] Figure 24 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13a of a semiconductor device according to a modified embodiment of the present invention. Figure 22Following the process shown, a new resist mask RMa is formed after the resist mask RM is removed. In this variation, an example is shown where the resist mask RMa is disposed around the oxide semiconductor layer 130 in the same manner as in the first embodiment. That is, it is shown that the position of the inner wall of the opening RMa1 of the resist mask RMa is aligned with the position of the end of the oxide semiconductor layer 130 in a direction perpendicular to the substrate 100. However, this example is not limited to this one. Similar to the variation of the first embodiment, when viewed from above, the size of the outline of the edge of the opening RMa1 can be larger or smaller than the size of the outline of the edge of the oxide semiconductor layer 130.

[0142] According to this modified example, the exposed area of ​​the insulating layer 140 is also reduced during the impurity implantation process used to form the low-resistance region HRR, thus suppressing the amount of hydrogen generated inside the insulating layers 120 and 140. Therefore, according to this modified example, the decrease in channel resistance caused by hydrogen diffusion can be suppressed more effectively.

[0143] The various embodiments (including modifications) described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing constituent elements or adding, omitting or changing conditions based on the various embodiments and modifications, as long as they possess the spirit of the present invention, are also included in the scope of the present invention.

[0144] Even if other effects are different from those achieved through the above-described embodiments, if they are clearly known from the description in this specification or can be easily predicted by those skilled in the art, they shall of course be understood as effects achieved through the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an oxide semiconductor layer over a first insulating layer, forming a second insulating layer over the oxide semiconductor layer, forming a conductive layer over the second insulating layer, forming a resist mask having an opening portion overlapping with at least part of the oxide semiconductor layer over the second insulating layer and the conductive layer, injecting impurities into the oxide semiconductor layer through the second insulating layer using the resist mask.

2. The method for manufacturing a semiconductor device according to claim 1, wherein An outline of an edge of the opening portion coincides with an outline of an edge of the oxide semiconductor layer in plan view.

3. The method for manufacturing a semiconductor device according to Claim 1, wherein An outline of an edge of the oxide semiconductor layer encloses an outline of an edge of the opening portion in plan view.

4. The method for manufacturing a semiconductor device according to Claim 1, wherein An outline of an edge of the opening portion encloses an outline of an edge of the oxide semiconductor layer in plan view.

5. The method for manufacturing a semiconductor device according to Claim 4, wherein A distance from an edge of the opening portion to an edge of the oxide semiconductor layer is greater than or equal to 0.3 μm and less than or equal to 1.2 μm.

6. The method for manufacturing a semiconductor device according to Claim 1, wherein The opening portion is separated from the conductive layer in a channel direction in a region overlapping with the oxide semiconductor layer.

7. The method for manufacturing a semiconductor device according to Claim 6, wherein The method further comprises a step of injecting impurities into the oxide semiconductor layer after the resist mask is removed.

8. A semiconductor device comprising: an oxide semiconductor layer over a first insulating layer; a second insulating layer over the oxide semiconductor layer; and a conductive layer over the second insulating layer, the oxide semiconductor layer includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer, a concentration of a prescribed impurity contained in a region of the second insulating layer overlapping with the second region is higher than a concentration of the impurity contained in a region of the second insulating layer not overlapping with the oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein The concentration of the impurity contained in the region of the second insulating layer overlapping with the second region is higher than the concentration of the impurity contained in the region of the second insulating layer not overlapping with the oxide semiconductor layer by more than 100 times.

10. The semiconductor device according to claim 8, wherein The concentration of the impurity contained in the region of the second insulating layer overlapping with the second region is higher than the concentration of the impurity contained in a region of the second insulating layer overlapping with the first region.

11. The semiconductor device according to claim 10, wherein The concentration of the impurity contained in the region of the second insulating layer overlapping with the second region is higher than the concentration of the impurity contained in the region of the second insulating layer overlapping with the first region by more than 100 times.

12. A semiconductor device comprising: an oxide semiconductor layer over a first insulating layer; a second insulating layer over the oxide semiconductor layer; and a conductive layer over the second insulating layer, the oxide semiconductor layer includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer, a concentration of a prescribed impurity contained in a region of the first insulating layer overlapping with the second region is higher than a concentration of the impurity contained in a region of the first insulating layer not overlapping with the oxide semiconductor layer.

13. The semiconductor device of claim 12, wherein, The concentration of the impurity contained in a region of the first insulating layer overlapping with the second region is higher than the concentration of the impurity contained in a region of the first insulating layer not overlapping with the oxide semiconductor layer by 100 times or more.

14. The semiconductor device of claim 12, wherein, The concentration of the impurity contained in a region of the first insulating layer overlapping with the second region is higher than the concentration of the impurity contained in a region of the first insulating layer overlapping with the first region.

15. The semiconductor device of claim 14, wherein, The concentration of the impurity contained in a region of the first insulating layer overlapping with the second region is higher than the concentration of the impurity contained in a region of the first insulating layer overlapping with the first region by 100 times or more.

16. A display device comprising the semiconductor device according to any one of claims 1 to 15.

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