Phosphorus diffusion annealing method and preparation method of TBC battery

Abstract

The invention discloses a phosphorus diffusion annealing method and a preparation method of a TBC battery, and the phosphorus diffusion annealing method comprises the following steps: A1, carrying out the high-temperature heating of a silicon wafer in a quartz furnace tube, carrying out the pressure pumping, first-time heating and leakage detection, carrying out the second-time heating and boosting, introducing nitrogen, carrying out the annealing crystallization, and crystallizing a boron-doped microcrystalline silicon layer into a P-type polycrystalline silicon layer; a2, cooling, and introducing oxygen and nitrogen for pre-oxidation; a3, phosphorus oxychloride, oxygen and nitrogen are introduced for deposition to form a phosphorus-rich layer, then pressure returning is carried out, nitrogen is introduced, temperature rising is carried out, an N-type polycrystalline silicon poly layer is formed, winding and expanding layers are formed on the front face and the edge at the same time, nitrogen is introduced for purging, pressure returning is carried out, nitrogen is introduced, and temperature rising is carried out; and A4, cooling and boosting, introducing oxygen to form a PSG layer, cooling, introducing nitrogen, and returning pressure out of the quartz furnace tube. According to the invention, a boron diffusion process with high investment and high operation cost can be canceled in a TBC battery preparation process, and the investment cost of 1500-20 million yuan / GW can be reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of battery preparation, and particularly relates to a phosphorus diffusion annealing method and a preparation method of a TBC battery. BACKGROUND

[0002] At present, in the manufacturing process of the back cross-shaped p-type doped region and n-type doped region of the TBC battery, two high-temperature amorphous silicon deposition and two high-temperature diffusion doping are required. From the technical point of view, too many high-temperature processes are passed, which leads to great difficulty in process control, and at the same time, long-time high-temperature treatment also has an impact on the performance of the battery. From the investment and operation point of view, the high-temperature equipment investment is high, and the electric power consumption and quartz auxiliary material loss are also high during the later operation. Therefore, the present application is started from the two dimensions of technology and investment and operation, reduces the whole process flow of the TBC battery, uses the VHF&PECVD (ultra / very high frequency plasma enhanced chemical vapor deposition) mode to replace the original LPCVD (low pressure chemical vapor deposition) and boron diffusion mode to prepare the back P-type poly silicon scheme, directly cancels a boron diffusion process which requires the highest temperature and has the longest process time (the temperature needs to be as high as 800-1050 DEG C, and the high-temperature time is 2.5-3.5 h), so that the whole preparation process of the TBC battery is significantly reduced in the three dimensions of equipment investment, operation cost and production line control difficulty, and the high-efficiency and high-quality production efficiency is achieved. SUMMARY

[0003] Therefore, the present application aims to provide a phosphorus diffusion annealing method and a preparation method of a TBC battery to solve at least one technical problem in the background art.

[0004] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows: A phosphorus diffusion annealing method, comprising the following steps: A1: a silicon wafer with a first tunnel oxide layer, an amorphous silicon poly layer and a boron-doped microcrystalline silicon layer is subjected to high-temperature heating in a quartz furnace tube, then subjected to pressure extraction and first temperature rising, after leakage detection, subjected to second temperature rising and pressure rising, nitrogen gas is introduced for annealing crystallization, and the boron-doped microcrystalline silicon layer is crystallized into a P-type polycrystalline silicon layer; A2: temperature reduction, pre-oxidation by introducing oxygen and nitrogen; A3: a phosphorus-rich layer is formed by introducing phosphorus oxychloride, oxygen and nitrogen for deposition, then back pressure is introduced for nitrogen gas and temperature rising, and the phosphorus impurities are pushed forward, so as to form an N-type polycrystalline silicon poly layer, and at the same time, a diffusion layer is formed around the front and edge, nitrogen gas is introduced for purging, back pressure is introduced for nitrogen gas and temperature rising; A4: temperature reduction and pressure rising, oxygen is introduced to form a PSG layer, nitrogen is introduced for temperature reduction, and back pressure is introduced to take out the quartz furnace tube.

[0005] Further, the temperature of the high-temperature heating in step A1 is 800-850℃, and the time is 800-1500s: The pressure extraction and the first temperature rise in step A1 include extracting the pressure of the quartz furnace tube to a bottom pressure state of 0-200mbar, and rising the temperature to 850-900℃, and the time of the pressure extraction and the first temperature rise is 500-1500s: The second temperature rise and pressure rise in step A1 include continuing to rise the temperature to 900-1000℃, and rising the pressure to 100-400mbar, and introducing nitrogen gas into the quartz furnace tube at a flow rate of 1000-6000sccm, and the time of the second temperature rise and pressure rise is 1500-3500s: The annealing and crystallization in step A1 include maintaining the temperature at 900-1000℃ under a low-pressure environment of 100-400mbar, and continuously introducing nitrogen gas at a flow rate of 1000-6000sccm for a time of 1000s-2000s.

[0006] Further, the temperature lowering in step A2 includes lowering the temperature to 770-820℃; The pre-oxidation by introducing oxygen and nitrogen gas in step A2 includes maintaining the temperature at 770-820℃ under a pressure of 100-400mbar, and introducing oxygen gas at a flow rate of 300-2000sccm and nitrogen gas at a flow rate of 300sccm-3000sccm into the quartz furnace tube to form an oxide layer on the surface of the silicon wafer.

[0007] Further, the deposition of the phosphorus-rich layer by introducing phosphorus oxychloride, oxygen and nitrogen gas in step A3, and then back-pressurizing nitrogen gas and rising the temperature to push the phosphorus impurities, thereby forming an N-type polysilicon poly layer includes introducing phosphorus oxychloride at a flow rate of 90-180sccm, oxygen at a flow rate of 300-1000sccm, and nitrogen gas at a flow rate of 1000-5000sccm into the quartz furnace tube under a pressure of 100-400mbar to deposit, and the deposition temperature is 770-820℃, thereby forming an N-type polysilicon poly layer; The nitrogen gas purging in step A3 includes purging nitrogen gas at a flow rate of 1000-4000sccm; The back-pressurization of nitrogen gas and temperature rise in step A3 includes back-pressurizing to 200-400mbar, introducing nitrogen gas at a flow rate of 2000-5000sccm, and rising the temperature to 850-900℃ for a time of 1000-1500s.

[0008] Further, the temperature lowering and pressure rising and the introduction of oxygen to form a PSG layer in step A4 include lowering the temperature to 800-850℃, rising the pressure to 500-950mbar, and introducing oxygen gas at a flow rate of 5000-20000sccm to control the oxygen gas introduction time to 500-1000s to form a PSG layer by oxidation.

[0009] A preparation method of a TBC battery, comprising the following steps: S1: selecting a silicon wafer and polishing both sides of the silicon wafer; S2: sequentially depositing a laminated structure of a first tunneling oxide layer, an amorphous silicon poly layer, a boron-doped microcrystalline silicon layer and a surface silicon oxide layer on the polished silicon wafer from bottom to top; S3: locally removing the surface silicon oxide layer formed in step S2 to form a P-poly opening film area; S4: etching the boron-doped microcrystalline silicon layer in the laser region of the opening film silicon wafer until the silicon substrate is etched; S5: forming a second tunneling oxide layer and an amorphous silicon layer on the etched silicon wafer by an LPCV process; S6: performing phosphorus diffusion annealing by using the phosphorus diffusion annealing method in any one of claims 1-5, so that the boron-doped microcrystalline silicon layer under the P-poly opening film area is crystallized into a P-type polysilicon layer, an N-type polysilicon layer is formed in the etched region by phosphorus diffusion, and a PSG layer and a diffusion layer are generated; S7: using a laser to open the PSG layer in the connecting region of the P-type polysilicon layer and the N-type polysilicon layer; S8: removing the diffusion layer on the edge and the front surface by using an acidic solution; S9: performing low-temperature texturing on the front surface of the silicon wafer with diffusion, etching the connecting region of the P-type polysilicon layer and the N-type polysilicon layer on the back surface to form a GAP area, and removing all the silicon oxide layers on the back surface by using HF; S10: depositing aluminum oxide on both surfaces, depositing SiNx thin film on the front and back surfaces of the silicon wafer with the deposited aluminum oxide layer, and preparing metal electrodes of the P region and the N region on the back surface of the silicon wafer with the deposited film by screen printing and sintering.

[0010] Further, the silicon wafer in step S1 is an N-type single crystal; The step S2 of sequentially depositing a laminated structure of a first tunneling oxide layer, an amorphous silicon poly layer, a boron-doped microcrystalline silicon layer and a surface silicon oxide layer on the polished silicon wafer from bottom to top comprises: B1: placing the polished silicon wafer into a reaction cavity through a carrier in an environment of 400-500 DEG C, and passing 10000-15000 sccm of nitrous oxide gas to grow a first tunneling oxide layer of 1-2 nm on the back surface of the battery wafer; B2: At a temperature of 400-500℃, oxygen or nitrous oxide is removed, and a mixed gas of 3000-4000 sccm of silane, 100-300 sccm of borane, and 2000-20000 sccm of hydrogen is passed through to perform very high frequency plasma-enhanced chemical vapor deposition. The discharge frequency is 30MHz-100MHz to grow a 5-20nm low-doped amorphous silicon poly layer. B3: At a temperature of 400-500℃, oxygen or nitrous oxide is removed, and a mixed gas of 3000-4000 sccm of silane, 500-1000 sccm of borane and 5000-10000 sccm of hydrogen is passed through. Very high frequency plasma-enhanced chemical vapor deposition is performed, and discharge is carried out at a frequency of 30MHz-100MHz to grow a highly doped boron-doped microcrystalline silicon layer of 100nm-200nm. B4: At a temperature of 400-500℃, a mixture of 500-1000 sccm of borane and 5000-10000 sccm of hydrogen is removed, and 8000-12000 sccm of nitrous oxide and 1500-2000 sccm of silane are passed through to generate a 10-50 nm surface silicon oxide layer.

[0011] Furthermore, in step S4, the P-type microcrystalline silicon layer in the laser area of ​​the silicon wafer after the film is opened is etched using alkali and additives until the silicon substrate is reached. The alkali is NaOH or KOH, with a concentration of 5% to 18%, and the additive is polishing additives such as Shichuang CW20V01, with a concentration of 1% to 3% by volume. In step S5, the thickness of the second tunneling oxide layer is 1-2 nm and the thickness of the amorphous silicon poly layer is 150-200 nm. Furthermore, the pickling solution in step S8 is a mixed solution of HF, H2SO4 and HNO3; The concentrations of HF, HNO3, and H2SO4 are 8%-30%, 5%-15%, and 5%-15%, respectively.

[0012] Furthermore, the thickness of the SiNx thin film in step S10 is 60~80nm on the front side and 80~130nm on the back side.

[0013] Compared with existing technologies, the phosphorus diffusion annealing method and the TBC battery preparation method described in this invention have the following advantages: This application enables the elimination of a high-investment, high-operating-cost boron diffusion process in the TBC battery manufacturing process, reducing investment costs by 15-20 million RMB / GW. Furthermore, by eliminating the high-temperature boron diffusion process, the LPCVD (low-pressure chemical vapor deposition) method for preparing poly silicon is designed as VHF & PECVD to prepare microcrystalline silicon, which is then crystallized into poly silicon using the existing phosphorus diffusion equipment. Therefore, the overall operating energy consumption and process control difficulty will be significantly reduced. This not only reduces operating costs by approximately 350-450℃ / 10,000 cells of electricity consumption, resulting in direct revenue, but also reduces the consumption of quartz equipment. At the same time, by preparing boron-doped poly silicon through VHF & PECVD, precise control of the flow rate and doping concentration can be achieved, producing high-quality, high-crystallinity P-type poly silicon, thus improving battery performance. Detailed Implementation

[0014] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0015] The present invention will now be described in detail with reference to the embodiments.

[0016] This invention is based on the underlying structure of a TBC battery, which is fully transparent on the front and has interdigitated electrodes and tunneling passivation contacts on the back. First, instead of using the conventional LPCVD (low-pressure chemical vapor deposition) + boron diffusion method, it uses VHF & PECVD (very high frequency plasma enhanced chemical vapor deposition) for in-situ doping to form P-type microcrystalline silicon. Second, the P-type microcrystalline silicon formed by in-situ doping using the VHF & PECVD method has a certain degree of crystallinity. Then, a new process is developed using existing phosphorus diffusion equipment to add annealing function, further crystallizing the P-type microcrystalline silicon into P-type polycrystalline silicon, thereby realizing a P-type poly structure. This invention is mainly carried out through two variables: the P-type poly preparation scheme and the new phosphorus diffusion process scheme.

[0017] I. Preparation scheme of P-type poly: The high-temperature LPCVD1 and boron diffusion process are eliminated and replaced with a VHF & PECVD (Very High Frequency Plasma Enhanced Chemical Vapor Deposition) process. In-situ doping is carried out using VHF & PECVD technology to form P-type microcrystalline silicon with a certain degree of crystallinity, which lays an excellent foundation for the subsequent more efficient formation of high-quality P-type poly silicon. A novel phosphorus diffusion process: Utilizing phosphorus diffusion equipment, a new process has been developed that transforms the original function of phosphorus diffusion, which only aimed to form N-type polysilicon, into one that not only ensures high-quality N-type polysilicon formation but also adds a high-efficiency annealing function. This allows P-type microcrystalline silicon to crystallize into highly crystalline P-type polycrystalline silicon, thereby achieving a more efficient tunneling passivation effect in the battery. Because the crystallization of non- / microcrystalline silicon into polycrystalline silicon requires relatively high annealing temperatures, typically above 900 degrees Celsius, and phosphorus is highly reactive, high temperatures can easily cause phosphorus diffusion to penetrate the tunneling layer, causing the tunneling layer to lose its essential function—tunneling. This not only affects the passivation effect but also increases the risk of leakage and reduces battery efficiency. The phosphorus diffusion annealing process of this invention is based on this theoretical foundation. In practice, it ensures the crystallization of P-type microcrystalline silicon into highly crystalline P-type polycrystalline silicon while preventing phosphorus from penetrating the tunneling layer during phosphorus diffusion. This scheme adopts a three-step key process framework design: high-temperature crystallization annealing, low-temperature diffusion, and finally medium-temperature propagation.

[0018] 1. Boat heating: Place the silicon wafer with the first tunneling oxide layer and the amorphous silicon poly layer formed after LPCVD into the quartz boat, and then send the quartz boat into the quartz furnace tube. The standby temperature of the quartz furnace tube is set to 800-850℃ and the time is 800-1500s.

[0019] 2. Pressure pumping and heating: Set the gas flow rate to 0, start the pump to draw a vacuum, and draw the pressure of the furnace tube to a low pressure state of 0-200 mbar. The temperature rises to 850-900℃. The time for pressure pumping and the first heating is 500-1500 seconds. 3. Leak detection: Under low pressure (0-200 mbar) and with the airflow set to 0, leak detection is performed at standby temperature to ensure the furnace tube is sealed and to guarantee the stability of subsequent processes.

[0020] 4. Heating and stabilizing: Continue heating to 900-1000℃ and pressurizing to 100-400mbar. Introduce nitrogen gas at a flow rate of 1000-6000sccm into the quartz furnace tube. The heating and pressurizing time is 1500-3500s, in preparation for the next step of high-temperature crystallization annealing. 5. Annealing and crystallization: Under a low pressure of 100-400 mbar and a temperature of 900-1000℃, nitrogen gas is continuously introduced at a flow rate of 1000-6000 sccm for 1000-2000 s. The purpose is to anneal and crystallize the boron-doped microcrystalline silicon layer and the intrinsic amorphous silicon. 6. Cooling: The temperature is lowered to 770-820℃ to prepare for low-temperature phosphorus diffusion; 7. Pre-oxidation: Maintain a pressure of 100-400 mbar and a temperature of 770-820℃. Introduce oxygen at a flow rate of 300-2000 sccm and nitrogen at a flow rate of 300-3000 sccm into the quartz furnace tube to create an oxidation environment. This forms an oxide layer on the silicon wafer surface, which acts as a getter and provides conditions for subsequent reactions.

[0021] 8. Deposition: Phosphorus oxychloride at a flow rate of 90-180 sccm, oxygen at a flow rate of 300-1000 sccm, and nitrogen at a flow rate of 1000-5000 sccm are introduced into a quartz furnace tube at a pressure of 100-400 mbar to carry out deposition at a temperature of 770-820℃ to form a phosphorus-rich layer. 9. Purging: Nitrogen gas at a flow rate of 1000-4000 sccm is introduced to purge the waste gas generated during the deposition process out of the furnace tube, providing a buffer time for subsequent deposition or advancement to raise the temperature. 10. Heating and Propulsion: Back pressure to 200-400 mbar, introduce nitrogen gas at a flow rate of 2000-5000 sccm, heat to 850-900℃ for 1000-1500s to promote the phosphorus impurities, thereby forming an excellent N-type polycrystalline silicon poly structure and secondary crystallizing the boron-doped microcrystalline silicon layer poly.

[0022] 11. Post-oxidation: Cool to 800-850 degrees Celsius, pressurize to 500-950 mbar, and introduce oxygen at a flow rate of 5000-20000 sccm for 500-1000 s. Oxidation is carried out to form a PSG layer as a mask, which prepares for the differentiated reaction in the subsequent wet process to achieve P / N separation. 12. Cooling: Cool the quartz furnace tube to 700-800℃ and introduce a certain amount of nitrogen gas; 13. Press back and release the boat.

[0023] Example 2 This invention discloses a novel method for preparing TBC batteries, and the specific process of the entire preparation is illustrated below: S1. Cleaning 1: Select a standard N-type monocrystalline silicon wafer, place it in an alkaline polishing machine, and use an appropriate concentration of KOH or NaOH solution to polish both sides of the silicon wafer to obtain a smooth and clean surface.

[0024] S2. Backside Stacked Structure Deposition: This step uses a VHF-PECVD equipment to sequentially deposit four thin films on the backside of the silicon wafer. The stacked structure is deposited sequentially from bottom to top on the polished silicon wafer: first tunneling oxide layer, intrinsic amorphous silicon layer, second tunneling oxide layer, boron-doped microcrystalline silicon layer, and surface silicon oxide layer. The specific steps are as follows: Step 1: The polished silicon wafer is placed into the reaction chamber through a carrier. Nitrous oxide gas at 12000 sccm is introduced at 450°C to grow a 1.5 nm first tunneling oxide layer on the back of the cell. Step 2: At 450°C, stop the flow of nitrous oxide and introduce a mixed gas of 3500 sccm silane, 200 sccm borane and 10000 sccm hydrogen. Discharge under 60MHz very high frequency plasma (VHF-PECVD) to grow a low-doped amorphous silicon layer with a thickness of about 10nm. Step 3: At 450°C, a mixed gas of 3500 sccm silane, 800 sccm borane and 8000 sccm hydrogen is introduced, and discharge is performed under VHF-PECVD at 60MHz to grow a highly doped boron-doped microcrystalline silicon layer with a thickness of about 150nm. Step 4: At 450℃, remove the mixed gas of 500-1000 sccm borane and 5000-10000 sccm hydrogen, and pass in 10000 sccm nitrous oxide gas and 1800 sccm silane gas to generate a surface silicon oxide layer of a certain thickness of 30nm.

[0025] S3, (First Laser Deposition) Laser 1: Using a laser, the outermost surface silicon oxide mask layer of the deposited silicon wafer is locally removed to form a patterned structure of the P-poly deposition area. S4. First cleaning and etching (cleaning 2): The boron-doped microcrystalline silicon layer in the laser area of ​​the silicon wafer after the film is opened is etched using a mixed solution of alkali and additives, continuing until the silicon substrate is reached. The alkali is KOH with a concentration of 10%. The additive is polishing additive CW20V01 with a volume fraction of 2%.

[0026] S5, LPCVD Deposition: The cleaned silicon wafer is subjected to LPCVD (Low Pressure Chemical Vapor Deposition) to sequentially form: a second tunneling oxide layer (SiOx) with a thickness of approximately 1.5 nm, and an intrinsic amorphous silicon layer with a thickness of approximately 180 nm.

[0027] S6. Perform phosphorus diffusion annealing on the silicon wafer processed in S5, using the following steps, which correspond to the phosphorus diffusion annealing method defined in claims 1-5: 1. Preheating the furnace: Place the silicon wafer into the quartz furnace tube and heat it at 830°C for 1000 seconds.

[0028] 2. Vacuuming and heating: The pressure in the furnace tube is reduced to 100 mbar by vacuuming, while the temperature is raised to 880°C. This process lasts for about 1000 seconds. 3. Leak detection: Under low pressure (0-200 mbar) and with the airflow set to 0, leak detection is performed at standby temperature to ensure the furnace tube is sealed and to guarantee the stability of subsequent processes.

[0029] 4. Heating and stabilizing: Continue heating to 960℃ and pressurizing to 200mbar. Introduce nitrogen gas at a flow rate of 4000sccm into the furnace tube to prepare for the next step of high-temperature crystallization annealing. 5. Annealing and crystallization: Under a low pressure of 100-400 mbar and a temperature of 900-1000℃, nitrogen gas is continuously introduced at a flow rate of 1000-6000 sccm for 1500 seconds. This process crystallizes the boron-doped microcrystalline silicon layer into a P-type polycrystalline silicon layer. 6. Cooling: Reduce the temperature to 800℃ to prepare for low-temperature phosphorus diffusion; 7. Pre-oxidation: At a pressure of 200 mbar and a temperature of 800°C, oxygen at a flow rate of 1000 sccm and nitrogen at a flow rate of 2000 sccm are introduced into the furnace tube for pre-oxidation. This forms an oxide layer on the silicon wafer surface, which acts as a getter and provides conditions for subsequent reactions.

[0030] 8. Deposition: Under a pressure of 200 mbar, phosphorus oxychloride, oxygen, and nitrogen at flow rates of 120 sccm, 600 sccm, and 3000 sccm are introduced, and deposition is carried out at 800℃ to form a phosphorus-rich layer. 9. Purging: Nitrogen gas at a flow rate of 2000 sccm is introduced to purge the waste gas generated during the deposition process out of the furnace tube, providing a buffer time for subsequent deposition or advancement to raise the temperature. 10. Heating and Propulsion: The pressure is reduced to 300 mbar, nitrogen gas is introduced at a flow rate of 3500 sccm, and the temperature is raised to 880°C and maintained for 1200 s to propel the phosphorus impurities, thereby forming an N-type polycrystalline silicon poly layer in the etched area and performing secondary crystallization on the P-type polycrystalline silicon layer. This process simultaneously forms a wraparound layer on the front side and edges of the silicon wafer.

[0031] 11. Post-oxidation: Cool to 820℃, pressurize to 700 mbar, introduce oxygen at a flow rate of 15000 sccm, and oxidize for 600 seconds to form a PSG layer. The PSG layer formed during oxidation serves as a mask, preparing for the subsequent wet process's differentiated reaction to achieve P / N separation. 12. Cooling: Cool the furnace tubes to 750℃ and introduce nitrogen gas; 13. Press back and release the boat.

[0032] S7. Second laser film opening (laser 2): Use a laser to open the PSG mask layer in the area where the P-type polysilicon layer and the N-type polysilicon layer are connected, in order to prepare for subsequent wet etching to separate the P / N region and remove the N-poly on the P-poly. S8. Second cleaning (cleaning 3): Chain pickling using an acidic solution removes the spread layer from the edges and the front surface. The acidic solution is a mixture of HF, H2SO4, and HNO3. The concentrations are 20% HF, 10% HNO3, and 10% H2SO4. Chain pickling utilizes HF + HNO3 to remove the spread layer from the edges and the front surface, preparing for the next texturing step. S9. Third cleaning and texturing (cleaning 4): The silicon wafer with the front-side coating removed is texturized at low temperature, and the P / N connection area on the back side (i.e., the laser 2 mold opening area) is etched to form the GAP area (P / N separation area). Subsequently, all silicon oxide layers on the back side (including the initial mask layer) are removed using an HF solution; S10, ALD: Deposit double-sided aluminum oxide on the silicon wafer after cleaning step 4; S11, Front and Back PECVD: A silicon wafer with aluminum oxide deposited is subjected to a SiNx film with a thickness of about 70nm on the front side and a SiNx film with a thickness of about 100nm on the back side.

[0033] S12, Printing and Sintering: The coated silicon wafer is screen printed and sintered to prepare metal electrodes on the back side that are in contact with the P-region and N-region respectively.

[0034] Traditional polycrystalline silicon fabrication may require separate preparation of P-type and N-type polycrystalline silicon followed by annealing. This invention integrates several key steps—P-type polycrystalline silicon crystallization, N-type polycrystalline silicon formation and doping, and PSG mask layer fabrication—into a single, continuous process within a single quartz furnace. This significantly shortens the process cycle, reduces equipment usage and inter-wafer contamination, and improves production efficiency and product consistency. Due to the excellent passivation achieved by the ultra-thin oxide layer and high-quality polycrystalline silicon, the open-circuit voltage of this cell can reach 730mV to 745mV, significantly higher than mainstream PERC cells (~690mV) and conventional TOPCon cells (~710mV). Thanks to the effective physical isolation (GAP region) between the P / N regions and the low-resistance metal-polysilicon contact, the fill factor of the cell can be maintained at a high level of 83.5% to 85.5%, indicating that the cell has low series resistance and excellent carrier collection efficiency.

[0035] The TBC battery manufacturing solution provided by this invention successfully simplifies the complex back-contact battery manufacturing process through its highly integrated phosphorus diffusion annealing core process. Simultaneously, it achieves a synergistic improvement in battery performance, including Voc, FF, and η, and possesses characteristics of low degradation and high reliability. This solution not only demonstrates significant technological advancement but also possesses strong industrial application potential and market competitiveness.

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method of phosphorus extended annealing, characterized by: The method comprises the following steps: A1: high-temperature heating of a silicon wafer with a first tunneling oxide layer, an amorphous silicon poly layer and a boron-doped microcrystalline silicon layer in a quartz furnace tube, followed by pressure reduction and first temperature rise, leakage detection, second temperature rise and pressure rise, nitrogen gas is introduced for annealing and crystallization, the boron-doped microcrystalline silicon layer is crystallized into a P-type polysilicon layer; A2: temperature reduction, pre-oxidation by introducing oxygen and nitrogen; A3: phosphorus-rich layer deposition by introducing phosphorus oxychloride, oxygen and nitrogen, followed by back pressure reduction, nitrogen introduction and temperature rise to promote phosphorus impurities, thereby forming an N-type polysilicon poly layer, while forming a wrap-around layer on the front surface and edges, nitrogen is introduced for purging, back pressure reduction and nitrogen introduction for temperature rise; A4: temperature reduction and pressure rise, PSG layer formation by introducing oxygen, temperature reduction and nitrogen introduction, back pressure reduction and exit from the quartz furnace tube.

2. A method of phosphorus reflow annealing as claimed in claim 1, wherein: The temperature of high-temperature heating in step A1 is 800-850℃, and the time is 800-1500s; The pressure reduction and first temperature rise in step A1 include reducing the pressure of the quartz furnace tube to a bottom pressure of 0-200mbar, and raising the temperature to 850-900℃, the pressure reduction and first temperature rise time is 500-1500s; The second temperature rise and pressure rise in step A1 include continuing to raise the temperature to 900-1000℃, and raising the pressure to 100-400mbar, nitrogen gas with a flow rate of 1000-6000sccm is introduced into the quartz furnace tube, the second temperature rise and pressure rise time is 1500-3500s; The annealing and crystallization in step A1 includes maintaining a low pressure environment of 100-400mbar, a temperature of 900-1000℃, and continuously introducing nitrogen gas with a flow rate of 1000-6000sccm, the time is 1000s-2000s.

3. A method of phosphorus reflow annealing as claimed in claim 1, wherein: The temperature reduction in step A2 includes reducing the temperature to 770-820℃; The pre-oxidation by introducing oxygen and nitrogen in step A2 includes maintaining a pressure of 100-400mbar and a temperature of 770-820℃, introducing oxygen with a flow rate of 300-2000sccm and nitrogen with a flow rate of 300sccm-3000sccm into the quartz furnace tube, and forming an oxide layer on the surface of the silicon wafer.

4. The method of phosphorous extended annealing as claimed in claim 1, wherein: The deposition of phosphorus-rich layer by introducing phosphorus oxychloride, oxygen and nitrogen in step A3, followed by back pressure reduction, nitrogen introduction and temperature rise to promote phosphorus impurities, thereby forming an N-type polysilicon poly layer, includes introducing phosphorus oxychloride with a flow rate of 90-180sccm, oxygen with a flow rate of 300-1000sccm and nitrogen with a flow rate of 1000-5000sccm into the quartz furnace tube with a pressure of 100-400mbar, depositing at a temperature of 770-820℃ to form an N-type polysilicon poly layer; The purging by introducing nitrogen in step A3 includes introducing nitrogen with a flow rate of 1000-4000sccm for purging; The back pressure reduction, nitrogen introduction and temperature rise in step A3 include back pressure reduction to 200-400mbar, nitrogen introduction with a flow rate of 2000-5000sccm, temperature rise to 850-900℃, and the time is 1000-1500s.

5. The method of phosphorous reflow annealing as claimed in claim 1, wherein: The temperature lowering and pressure increasing in step A4, and the PSG layer formed by introducing oxygen include lowering the temperature to 800-850℃, increasing the pressure to 500-950mbar, introducing oxygen at a flow rate of 5000-20000sccm, controlling the time of oxygen introduction to be 500-1000s, and performing oxidation to form the PSG layer.

6. A method of making a TBC battery, characterized by: The method comprises the following steps: S1: selecting a silicon wafer and polishing both sides of the silicon wafer; S2: sequentially depositing a stack structure from bottom to top on the polished silicon wafer: a first tunneling oxide layer, an amorphous silicon poly layer, a boron-doped microcrystalline silicon layer, and a surface silicon oxide layer; S3: performing local removal of the surface silicon oxide layer formed in step S2 to form a P-poly opening film area; S4: etching the boron-doped microcrystalline silicon layer in the laser area of the opening film silicon wafer until the silicon substrate is etched; S5: forming a second tunneling oxide layer and an amorphous silicon layer on the etched silicon wafer by an LPCVD process; S6: performing phosphorus diffusion annealing by using the phosphorus diffusion annealing method in any one of claims 1-5 to crystallize the boron-doped microcrystalline silicon layer under the P-poly opening film area into a P-type polysilicon layer, form an N-type polysilicon layer in the etched area by phosphorus diffusion, and generate a PSG layer and a diffusion layer; S7: using a laser to open the PSG layer in the connecting area of the P-type polysilicon layer and the N-type polysilicon layer; S8: removing the diffusion layer on the edge and the front surface by using an acidic solution; S9: performing low-temperature texturing on the front surface of the silicon wafer plated with the diffusion layer, etching the connecting area of the P-type polysilicon layer and the N-type polysilicon layer on the back surface to form a GAP area, and removing all the silicon oxide layers on the back surface by using HF; S10: depositing double-sided aluminum oxide, depositing SiNx thin film on the front and back surfaces of the silicon wafer after depositing the aluminum oxide layer, and preparing metal electrodes of the P area and the N area on the back surface of the silicon wafer by screen printing and sintering.

7. The method of claim 6, wherein: The silicon wafer in step S1 is an N-type single crystal; The step S2 of sequentially depositing a stack structure from bottom to top on the polished silicon wafer: a first tunneling oxide layer, an amorphous silicon poly layer, a boron-doped microcrystalline silicon layer, and a surface silicon oxide layer includes: B1: placing the polished silicon wafer into a reaction chamber through a carrier, introducing 10000-15000sccm of nitrous oxide gas at 400-500℃, and growing a 1-2nm first tunneling oxide layer on the back surface of the cell wafer; B2: removing oxygen or nitrous oxide at a temperature of 400-500℃, introducing a mixed gas of 3000-4000sccm of silane, 100-300sccm of borane, and 2000-20000sccm of hydrogen, performing very high frequency plasma enhanced chemical vapor deposition at a frequency of 30MHz-100MHz to discharge, and growing a 5-20nm low-doped amorphous silicon poly layer; B3: at 400-500℃, remove oxygen or nitrous oxide, pass 3000-4000sccm of mixed gas of silane, 500-1000sccm of borane, 5000-10000sccm of hydrogen, discharge at a frequency of 30MHz-100MHz by very high frequency plasma enhanced chemical vapor deposition, so as to grow a 100nm-200nm high-doped boron-doped microcrystalline silicon layer; B4: at 400-500℃, remove 500-1000sccm of mixed gas of borane and 5000-10000sccm of hydrogen, pass 8000-12000sccm of nitrous oxide gas and 1500-2000sccm of silane gas, to generate a 10-50nm surface silicon oxide layer.

8. The method of claim 6, wherein: In step S4, the opened silicon wafer is etched by alkali and additives to the P-type microcrystalline silicon layer in the laser region, until the silicon substrate is etched; The alkali is: NAOH or KOH, with a concentration of 5%-18%, and the additives are polishing additives such as Shichuang CW20V01, with a concentration of 1%-3% by volume fraction: In step S5, the thickness of the second tunneling oxide layer is 1-2nm, and the thickness of the amorphous silicon poly layer is 150-200nm.

9. The method of claim 6, wherein: In step S8, the acid washing solution is a mixed solution of HF, H2SO4 and HNO3; The concentration of HF is 8%-30%, the concentration of HNO3 is 5%-15%, and the concentration of H2SO4 is 5%-15%.

10. The method of claim 6, wherein: In step S10, the thickness of the SiNx thin film is 60-80nm on the front side and 80-130nm on the back side.