Display substrate and display device

Abstract

A display substrate comprises a substrate, a plurality of first area light-emitting elements located in a first display area, a plurality of second area light-emitting elements located in a second display area, a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of first invalid pixel circuits, a plurality of second invalid pixel circuits and a first power transmission network. The first power transmission network includes a plurality of first transmission lines extending in a first direction and a plurality of second transmission lines extending in a second direction. The second display area comprises a first sub-display area located on at least one side of the first display area and a second sub-display area located on at least one side of the first sub-display area. In the first sub-display area, at least one second transmission line is connected with a plurality of first invalid pixel circuits arranged in the second direction, and orthographic projections of the second transmission line and the first invalid pixel circuits on the substrate are overlapped; in the second sub-display area, at least one second transmission line is connected with a plurality of second invalid pixel circuits arranged in the second direction, and orthographic projections of the second transmission line and the second invalid pixel circuits on the substrate are overlapped.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to increase the screen-to-body ratio of display devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a first display area and a second display area located at least one side of the first display area; the second display area includes: a first sub-display area located at least one side of the first display area and a second sub-display area located at least one side of the first sub-display area. The display substrate includes: a substrate, a plurality of first-area light-emitting elements, a plurality of second-area light-emitting elements, a plurality of first-type pixel circuits, a plurality of second-type pixel circuits, and a first power transmission network. The plurality of first-area light-emitting elements are disposed on the substrate and located in the first display area. The plurality of second-area light-emitting elements, the plurality of first-type pixel circuits, and the plurality of second-type pixel circuits are disposed on the substrate and located in the second display area. The plurality of second pixel circuits and the plurality of first-type pixel circuits are spaced apart along a first direction; the plurality of first-type pixel circuits include: a plurality of first pixel circuits located in the first sub-display area and a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits include: a plurality of first invalid pixel circuits located in the first sub-display area and a plurality of second invalid pixel circuits located in the second sub-display area; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first-area light-emitting elements through at least one conductive connection line, and at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second-area light-emitting elements. A first power transmission network is disposed on the substrate and located in the second display area, the first power transmission network including a plurality of first transmission lines extending along a first direction and a plurality of second transmission lines extending along a second direction; the first direction and the second direction intersect. In the first sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of first invalid pixel circuits arranged along the second direction, and their orthogonal projections onto the substrate overlap; in the second sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of second invalid pixel circuits arranged along the second direction, and their orthogonal projections onto the substrate overlap.

[0006] In some exemplary embodiments, at least one of the plurality of invalid pixel circuits is connected to a plurality of invalid pixel connection electrodes located on the same conductive layer, and at least a portion of the invalid pixel connection electrodes connected to the plurality of invalid pixel circuits arranged sequentially along the second direction are connected to form a second transmission line.

[0007] In some exemplary embodiments, the first sub-display area is provided with a plurality of first invalid pixel circuit groups and a plurality of first pixel circuit groups. Each first invalid pixel circuit group includes a plurality of first invalid pixel circuits arranged sequentially along the second direction, and each first pixel circuit group includes a plurality of first pixel circuits arranged sequentially along the second direction. At least one of the plurality of first invalid pixel circuit groups is located on the side of the plurality of first pixel circuit groups closest to the first display area.

[0008] In some exemplary embodiments, the plurality of first pixel circuit groups and the plurality of first invalid pixel circuit groups within the first sub-display area are sequentially numbered in the first direction and along a direction away from the first display area. Specifically, the numbering of at least a portion of the plurality of first invalid pixel circuit groups conforms to an arithmetic sequence; or, the numbering of at least a portion of the plurality of first pixel circuit groups conforms to an arithmetic sequence.

[0009] In some exemplary embodiments, the number of each first pixel circuit group is even and the number of each first invalid pixel circuit group is odd; or, the number of each first invalid pixel circuit group is even and the number of each first pixel circuit group is odd; or, the numbering of the plurality of first invalid pixel circuit groups conforms to the following relationship: 1+(i-1)×3, where i is an integer greater than 0.

[0010] In some exemplary embodiments, the display substrate further includes: a plurality of data lines and a first peripheral power line. The plurality of data lines are disposed on the substrate and located in the second display area; at least one of the plurality of data lines is connected to a plurality of invalid pixel circuits arranged along the second direction. The first peripheral power line is disposed on the substrate and located in a border region, the border region being located on at least one side of the second display area; the first peripheral power line extends at least along the first direction and is connected to the first power transmission network; the data lines connected to the plurality of invalid pixel circuits arranged along the second direction are connected to the first power transmission network.

[0011] In some exemplary embodiments, the display substrate further includes: a plurality of first power lines disposed on the substrate and located in the second display area, wherein at least one of the plurality of first power lines is connected to a plurality of invalid pixel circuits arranged along the second direction. Data lines connected to the plurality of invalid pixel circuits arranged along the second direction are connected to the first peripheral power lines through the first power lines connected to the plurality of invalid pixel circuits.

[0012] In some exemplary embodiments, the first peripheral power line includes: a first peripheral trace and a second peripheral trace that are interconnected; the second peripheral trace is located on the side of the first peripheral trace away from the substrate; the first peripheral trace and the first power transmission network are integrally formed; the second peripheral trace and the plurality of first power lines are integrally formed.

[0013] In some exemplary embodiments, the plurality of data lines are located on the side of the plurality of first power lines away from the substrate, and the plurality of first power lines are located on the side of the first power transmission network away from the substrate.

[0014] In some exemplary embodiments, in a direction perpendicular to the display substrate, the second display area includes: a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate; the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate. The first power transmission network is located on the first source / drain metal layer; the plurality of first power lines are located on the second source / drain metal layer; and the plurality of data lines are located on the third source / drain metal layer.

[0015] In some exemplary embodiments, in the first direction, n first-type pixel circuits are arranged every a second pixel circuits, where a and n are both integers greater than 0, and a is greater than n.

[0016] In some exemplary implementations, a is 4 and n is 1.

[0017] In some exemplary embodiments, the plurality of first region light-emitting elements includes: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light. At least one of the plurality of first pixel circuits is connected to two adjacent first light-emitting elements emitting the first color light; at least one of the plurality of first pixel circuits is connected to one second light-emitting element emitting the second color light; and at least one of the plurality of first pixel circuits is connected to one third light-emitting element emitting the third color light.

[0018] In some exemplary embodiments, the plurality of second-region light-emitting elements include: a plurality of fourth light-emitting elements emitting a first color light, a plurality of fifth light-emitting elements emitting a second color light, and a plurality of sixth light-emitting elements emitting a third color light. At least one of the plurality of second pixel circuits is connected to two adjacent fourth light-emitting elements emitting the first color light; at least one of the plurality of second pixel circuits is connected to one fifth light-emitting element emitting the second color light; and at least one of the plurality of second pixel circuits is connected to one sixth light-emitting element emitting the third color light.

[0019] In some exemplary embodiments, the first color light is green light, the second color light is red light, and the third color light is blue light.

[0020] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0023] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0024] Figure 2 This is a schematic planar diagram showing the arrangement of light-emitting elements in a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 3 This is a schematic diagram showing the arrangement of pixel circuits in the second display area according to at least one embodiment of the present disclosure;

[0026] Figure 4 This is a schematic diagram showing the connection between the second pixel circuit of the second display area and the light-emitting element of the second region in at least one embodiment of the present disclosure;

[0027] Figure 5 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0028] Figure 6 This is a partial cross-sectional schematic diagram of the second display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 7AThis is a partial schematic diagram of the semiconductor layer and the first gate metal layer of the second display area according to at least one embodiment of the present disclosure;

[0030] Figure 7B This is a partial schematic diagram of the second gate metal layer of the second display area according to at least one embodiment of the present disclosure;

[0031] Figure 7C This is a partial schematic diagram of the first source / drain metal layer of the second display area according to at least one embodiment of the present disclosure;

[0032] Figure 7D for Figure 7C A schematic diagram of the first source / drain metal layer in the diagram;

[0033] Figure 7E This is a schematic diagram of the second source / drain metal layer of the second display area according to at least one embodiment of the present disclosure;

[0034] Figure 7F This is a schematic diagram of the third source / drain metal layer of the second display area in at least one embodiment of the present disclosure;

[0035] Figure 8A This is a partial schematic diagram showing the boundary between the second display area and the border area of ​​at least one embodiment of the present disclosure;

[0036] Figure 8B for Figure 8A A schematic diagram of the first source / drain metal layer in the diagram;

[0037] Figure 8C for Figure 8A A schematic diagram of the second source / drain metal layer in the diagram;

[0038] Figure 8D for Figure 8A A schematic diagram of the third source / drain metal layer in the diagram;

[0039] Figure 9 This is a schematic diagram of another arrangement of the pixel circuit of the second display area according to at least one embodiment of the present disclosure;

[0040] Figure 10 This is a schematic diagram of another arrangement of the pixel circuit of the second display area according to at least one embodiment of the present disclosure;

[0041] Figure 11 This is a schematic diagram of another arrangement of the pixel circuit of the second display area according to at least one embodiment of the present disclosure;

[0042] Figure 12 This is a schematic diagram of another arrangement of the pixel circuit of the second display area according to at least one embodiment of the present disclosure;

[0043] Figure 13 This is a schematic diagram of another arrangement of the pixel circuit of the second display area according to at least one embodiment of the present disclosure;

[0044] Figure 14 This is a schematic plan view of another arrangement of light-emitting elements in a display substrate according to at least one embodiment of the present disclosure;

[0045] Figure 15 This is a schematic diagram of another arrangement of the pixel circuit of the second display area according to at least one embodiment of the present disclosure;

[0046] Figure 16 This is a schematic plan view of another arrangement of light-emitting elements in a display substrate according to at least one embodiment of the present disclosure;

[0047] Figure 17 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0048] The embodiments of this application will now be described in detail with reference to the accompanying drawings. This application describes multiple embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0049] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0050] Furthermore, in describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0051] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0052] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly defined.

[0053] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the meaning of the above terms in this application according to the circumstances.

[0054] In this application, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0055] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0056] In this application, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this application, the channel region refers to the region through which current primarily flows.

[0057] In this application, the first electrode can be the drain and the second electrode can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this application, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control electrode.

[0058] In this application, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0059] In this application, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0060] In this application, "light transmittance" refers to the ability of light to pass through a medium, which is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0061] In this application, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this application, "roughly the same" means that the values ​​differ by no more than 10%.

[0062] In this application, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this application, "A extends along direction B" refers to "the main part of A extends along direction B."

[0063] With the continuous development of display technology, cameras are typically installed on display devices to meet the needs of photography or facial recognition. To maximize screen-to-body ratio, technologies such as notch displays, waterdrop displays, and in-display punch-hole displays have emerged. These technologies reduce the area occupied by the camera by creating a hole in a portion of the display area and placing the camera below the hole, thereby increasing the screen-to-body ratio. However, these technologies require removing part of the display area, resulting in some areas of the screen being undisplayed, thus preventing further improvement in screen-to-body ratio. To avoid punching holes in the display area and to make a true full-screen display possible while ensuring the practicality of the display substrate, the under-display camera area typically employs either an external pixel circuitry method or an internal pixel circuitry method. The external pixel circuitry method involves placing the pixel circuitry connected to the light-emitting element in the under-display camera area within the normal display area, improving the light transmittance of the under-display camera area by arranging the light-emitting element and pixel circuitry separately. Since the under-display camera area does not have pixel circuitry, this area has no light-shielding layer other than the anode of the light-emitting element, achieving high light transmittance.

[0064] The inventors of this application observed that the normal display area near the under-display camera area exhibits a dimming phenomenon, particularly noticeable in low grayscale display scenarios. Further analysis revealed that because the under-display camera area uses an external pixel circuitry, with these external circuits positioned in the transition zone near the camera area, the voltage of the first power signal in the normal display area outside the transition zone is more uniform than that within the transition zone. This results in the transition zone having lower display brightness than the normal display area outside the transition zone, causing the transition zone to appear dim.

[0065] This embodiment provides a display substrate and a display device that can improve the uniformity of display brightness in the normal display area.

[0066] This embodiment provides a display substrate, including: a first display area and a second display area located at least one side of the first display area; the second display area includes: a first sub-display area located at least one side of the first display area and a second sub-display area located at least one side of the first sub-display area. The display substrate includes: a substrate, a plurality of first-area light-emitting elements, a plurality of second-area light-emitting elements, a plurality of first-type pixel circuits, a plurality of second-type pixel circuits, and a first power transmission network. The plurality of first-area light-emitting elements are disposed on the substrate and located in the first display area. The plurality of second-area light-emitting elements, the plurality of first-type pixel circuits, and the plurality of second-type pixel circuits are disposed on the substrate and located in the second display area; the plurality of second-type pixel circuits and the plurality of first-type pixel circuits are spaced apart along a first direction; the plurality of first-type pixel circuits include: a plurality of first-type pixel circuits located in the first sub-display area and a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits include: a plurality of first invalid pixel circuits located in the first sub-display area and a plurality of second invalid pixel circuits located in the second sub-display area. At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first region light-emitting elements via at least one conductive connection line, and at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second region light-emitting elements. A first power transmission network is disposed on the substrate and located in the second display area. The first power transmission network includes a plurality of first transmission lines extending along a first direction and a plurality of second transmission lines extending along a second direction. The first direction intersects the second direction; for example, the first direction may be perpendicular to the second direction. In the first sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of first invalid pixel circuits arranged along the second direction, and their orthographic projections onto the substrate overlap. In the second sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of second invalid pixel circuits arranged along the second direction, and their orthographic projections onto the substrate overlap. For example, the orthographic projection of the second transmission line in the first sub-display area onto the substrate may be located within the orthographic projection range of the plurality of first invalid pixel circuits arranged along the second direction onto the substrate, and the orthographic projection of the second transmission line in the second sub-display area onto the substrate may be located within the orthographic projection range of the plurality of second invalid pixel circuits arranged along the second direction onto the substrate.

[0067] The display substrate provided in this embodiment arranges the second transmission lines of the first power transmission network in the area where multiple first invalid pixel circuits are located in the first sub-display area, and arranges the second transmission lines of the first power transmission network in the area where multiple second invalid pixel circuits are located in the second sub-display area. This ensures that the first power transmission network is formed in both the first and second sub-display areas, thereby reducing the voltage difference of the first power signal between the first and second sub-display areas and improving the dark display situation in the first sub-display area.

[0068] In some exemplary embodiments, at least one of the plurality of invalid pixel circuits is connected to a plurality of invalid pixel connection electrodes located on the same conductive layer, and at least a portion of the invalid pixel connection electrodes connected to the plurality of invalid pixel circuits arranged sequentially along the second direction are connected to form a second transmission line. This example utilizes the area where the invalid pixel circuits are located to form the second transmission line, which can ensure that a first power transmission network for transmitting the first power signal is formed in the first sub-display area and the second sub-display area, improving the uniformity of the transmission of the first power signal within the second display area.

[0069] In some exemplary embodiments, a plurality of first invalid pixel circuit groups and a plurality of first pixel circuit groups are disposed within the first sub-display area. Each first invalid pixel circuit group includes a plurality of first invalid pixel circuits arranged sequentially along a second direction, and each first pixel circuit group includes a plurality of first pixel circuits arranged sequentially along the second direction. At least one of the plurality of first invalid pixel circuit groups is located on the side of the plurality of first pixel circuit groups closest to the first display area. For example, a first pixel circuit group is a first pixel circuit column, and a first invalid pixel circuit group is a first invalid pixel circuit column.

[0070] In some examples, multiple first pixel circuit groups and multiple first invalid pixel circuit groups within a first sub-display area are sequentially numbered in a first direction and along a direction away from the first display area; the numbering of at least some of the multiple first invalid pixel circuit groups conforms to an arithmetic sequence relationship, or the numbering of at least some of the multiple first pixel circuit groups conforms to an arithmetic sequence relationship. For example, the numbering of all the first invalid pixel circuit groups within the first sub-display area conforms to an arithmetic sequence relationship, or the numbering of all the first pixel circuit groups conforms to an arithmetic sequence relationship. For example, the number of each first pixel circuit group is even, and the number of each first invalid pixel circuit group is odd; or, the numbering of each first invalid pixel circuit group is even, and the numbering of each first pixel circuit group is odd; or, the numbering of the multiple first invalid pixel circuit groups conforms to the following relationship: 1 + (i-1) × 3, where i is an integer greater than 0. The arrangement of the first invalid pixel circuit and the first pixel circuit in this example can ensure the arrangement of the second transmission line of the first power transmission network in the first sub-display area, thereby reducing the voltage drop of the first power signal in the first sub-display area, improving the transmission uniformity of the first power signal in the second display area, and thus improving the display dimming situation in the first sub-display area.

[0071] The following examples illustrate the solution of this embodiment.

[0072] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, the display substrate may include a display area AA and a border area BB surrounding the display area AA. For example, the border area BB may include a first border area B1, a second border area B2, a third border area B3, and a fourth border area B4 located around the display area AA. The first border area B1 and the second border area B2 may be located on opposite sides of the display area AA along a second direction D2, and the third border area B3 and the fourth border area B4 may be located on opposite sides of the display area AA along a first direction D1. The first direction D1 intersects the second direction D2; for example, the first direction D1 may be perpendicular to the second direction D2. In some examples, the first border area B1 may be the upper border of the display substrate, the second border area B2 may be the lower border of the display substrate, the third border area B3 may be the left border of the display substrate, and the fourth border area B4 may be the right border of the display substrate.

[0073] In some examples, the display area AA may include a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the first display area A1 may be located at the top center of the display area AA, and the second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located at other positions such as the upper left or upper right corner of the display area AA, and the second display area A2 may surround at least one side of the first display area A1.

[0074] In some examples, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be other shapes such as rectangle, semicircle, pentagon, etc.

[0075] In some examples, the first display area A1 can be a light-transmitting display area, or it can also be called an under-display camera (FDC) area, configured for image display and light transmission; the second display area A2 can be called a normal display area, configured for image display. For example, the orthographic projection of a sensor (such as a camera, infrared sensor, etc.) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, such as... Figure 1 As shown, the first display area A1 can be circular, and the size of the sensor's orthographic projection on the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the sensor's orthographic projection on the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1.

[0076] In some examples, such as Figure 1 As shown, the pixel density of the first display area A1 can be less than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 can be equal to the pixel density of the second display area A2. In some examples, the ratio of the resolution of the first display area A1 to the resolution of the second display area A2 can be approximately 0.8 to 1.2. Alternatively, the resolution of the second display area A2 can be approximately the same as the resolution of the first display area A1. This embodiment is not limited in this respect.

[0077] In some examples, the display substrate may include at least: a plurality of first-area light-emitting elements 31 located in the first display area A1, a plurality of second-area light-emitting elements 32 located in the second display area A2, and a plurality of pixel circuits. The plurality of pixel circuits located in the second display area A2 may include: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits 42. The plurality of first-type pixel circuits may include: a plurality of first-type pixel circuits 41 and a plurality of invalid pixel circuits.

[0078] In some examples, at least one of the plurality of first pixel circuits 41 can be electrically connected to at least one of the plurality of first region light-emitting elements 31 via conductive connection lines 51. The first pixel circuit 41 can be configured to provide a driving signal to the connected first region light-emitting element 31 to drive the corresponding first region light-emitting element 31 to emit light. For example, the plurality of first pixel circuits 41 and the plurality of first region light-emitting elements 31 can have a one-to-one driving relationship or a one-to-many driving relationship. Since the first region light-emitting elements 31 and the first pixel circuits 41 are located in different regions, the orthographic projection of at least one first pixel circuit 41 onto the substrate and the orthographic projection of at least one first region light-emitting element 31 onto the substrate may not overlap.

[0079] In some examples, at least one of the plurality of second pixel circuits 42 may be electrically connected to at least one of the plurality of second region light-emitting elements 32, and the orthographic projection of at least one second pixel circuit 42 onto the substrate and the orthographic projection of at least one second region light-emitting element 32 onto the substrate may at least partially overlap. The second pixel circuit 42 may be configured to provide a driving signal to the connected second region light-emitting element 32 to drive the corresponding second region light-emitting element 32 to emit light. For example, the plurality of second pixel circuits 42 and the plurality of second region light-emitting elements 32 may have a one-to-one driving relationship or a one-to-many driving relationship.

[0080] Figure 2 This is a schematic planar diagram showing the arrangement of light-emitting elements in a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 1 and Figure 2As shown, the first display area A1 of the display substrate may include a plurality of first-area light-emitting elements 31, which may include: a plurality of first-area light-emitting elements 31a and 31d emitting a first color light, a plurality of second-area light-emitting elements 31b emitting a second color light, and a plurality of third-area light-emitting elements 31c emitting a third color light. The second display area A2 of the display substrate may include a plurality of second-area light-emitting elements 32, which may include: a plurality of fourth-area light-emitting elements 32a and 32d emitting a first color light, a plurality of fifth-area light-emitting elements 32b emitting a second color light, and a plurality of sixth-area light-emitting elements 32c emitting a third color light. In some examples, the first color light may be green light, the second color light may be red light, and the third color light may be blue light. However, this embodiment is not limited to this.

[0081] In some examples, a pixel unit of the first display area A1 may include four first region light-emitting elements (e.g., two first light-emitting elements 31a and 31d, one second light-emitting element 31b, and one third light-emitting element 31c). The two first light-emitting elements 31a and 31d, the one second light-emitting element 31b, and the one third light-emitting element 31c may be arranged in a diamond shape to form an RGBG pixel arrangement. For example, the second light-emitting element 31b and the third light-emitting element 31c may be arranged alternately in the same row along the first direction D1 and alternately in the same column along the second direction D2; the first light-emitting elements 31a and 31d may be arranged sequentially in the same row along the first direction D1 and sequentially in the same column along the second direction D2. The row containing the second light-emitting element 31b and the third light-emitting element 31c is alternately arranged with the row containing the first light-emitting elements 31a and 31d, and the column containing the second light-emitting element 31b and the third light-emitting element 31c is alternately arranged with the column containing the first light-emitting elements 31a and 31d. The arrangement of the fourth light-emitting elements 32a and 32d, the fifth light-emitting element 32b and the sixth light-emitting element 32c in the second display area A2 can be the same as the arrangement of the first light-emitting elements 31a and 31d, the second light-emitting element 31b and the third light-emitting element 31c in the first display area A1, so it will not be described again here.

[0082] In some examples, two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 in the first display area A1 can be interconnected. For example, the anodes of two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 can be interconnected. In this example, the first pixel circuit in the second display area A2 and the first light-emitting element in the first display area A1 can have a one-to-two driving relationship; in other words, one first pixel circuit in the second display area A2 can be configured to drive two first light-emitting elements (e.g., one first light-emitting element 31a and one first light-emitting element 31d) in the first display area A1. The first pixel circuit in the second display area A2 and the second light-emitting element 31b in the first display area A1 can have a one-to-one driving relationship, and the first pixel circuit in the second display area A2 and the third light-emitting element 31c in the first display area A1 can have a one-to-one driving relationship. The second pixel circuit in the second display area A2 and the second region light-emitting element can have a one-to-one driving relationship.

[0083] In some examples, each light-emitting element in the display area may include an anode, an organic light-emitting layer, and a cathode stacked sequentially. In this example, the light-emitting area of ​​the light-emitting element refers to the overlapping area of ​​the anode, organic light-emitting layer, and cathode of the light-emitting element, that is, the connection area between the anode and the organic light-emitting layer and cathode exposed by the pixel opening of the pixel definition layer.

[0084] In some examples, the area of ​​the light-emitting region of a single first-region light-emitting element 31 can be smaller than the area of ​​the light-emitting region of a single second-region light-emitting element 32 emitting light of the same color. Specifically, the area of ​​the light-emitting region of the first light-emitting element 31a (or 31d) can be smaller than the area of ​​the light-emitting region of the fourth light-emitting element 32a (or 32d). The area of ​​the light-emitting region of the second light-emitting element 31b can be smaller than the area of ​​the light-emitting region of the fifth light-emitting element 32b. The area of ​​the light-emitting region of the third light-emitting element 31c can be smaller than the area of ​​the light-emitting region of the sixth light-emitting element 32c. For example, the orthographic projection of a single second-region light-emitting element 32 onto the substrate can be quadrilateral or pentagonal, and the orthographic projection of a single first-region light-emitting element 31 onto the substrate can be circular or elliptical. This example, by reducing the area of ​​the light-emitting region of the first-region light-emitting element, can improve the light transmittance of the first display area and improve diffraction.

[0085] Figure 3 This is a schematic diagram of the pixel circuit layout of the second display area according to at least one embodiment of the present disclosure. Figure 4 This is a schematic diagram showing the connection between the second pixel circuit of the second display area and the light-emitting element of the second region in at least one embodiment of the present disclosure.

[0086] In some examples, such as Figure 1 and Figure 3As shown, the second display area A2 of the display substrate may include: a first sub-display area (also referred to as a transition area) A21 and a second sub-display area (also referred to as a non-transition area) A22. The first sub-display area A21 may be located on at least one side outside the first display area A1 (e.g., one side; or, both sides; or, all around, i.e., including the top and bottom sides and both sides). The first sub-display area A21 may be connected to the first display area A1, and the second sub-display area A22 may be located on at least one side of the first sub-display area A21, for example, it may surround the first sub-display area A21.

[0087] In some examples, the multiple pixel circuits of the second display area include: multiple first pixel circuits 41 located in the first sub-display area A21, multiple first invalid pixel circuits 43a located in the first sub-display area A21, multiple second invalid pixel circuits 43b located in the second sub-display area A22, and multiple second pixel circuits 42 located in the second display area A2.

[0088] In some examples, multiple first pixel circuits 41 in the first sub-display area A21 can be spaced apart between multiple second pixel circuits 42, and multiple first invalid pixel circuits 43a can be spaced apart between multiple second pixel circuits 42; similarly, multiple second invalid pixel circuits 43b in the second sub-display area A22 can be spaced apart between multiple second pixel circuits 42. For example, multiple second pixel circuits 42 can be arranged between two adjacent first pixel circuits 41 in the first direction D1, between two adjacent first invalid pixel circuits 43a in the first direction D1, and between two adjacent second invalid pixel circuits 43b in the first direction D1. This example, by providing multiple invalid pixel circuits (including multiple first invalid pixel circuits 43a and multiple second invalid pixel circuits 43b) in the second display area A2, can improve the uniformity of components in multiple film layers during the etching process. For example, the invalid pixel circuits can have a structure substantially the same as the first pixel circuits in their row or column, except that they are not electrically connected to any light-emitting element.

[0089] In some examples, at least one first pixel circuit 41 within the first sub-display area A21 can be electrically connected to at least one first area light-emitting element 31 via conductive connecting lines 51, and is configured to drive the at least one first area light-emitting element 31 to emit light. For example, two adjacent first area light-emitting elements 31 emitting a first color light (e.g., green G) within the first display area A1 can be driven by the same first pixel circuit 41, a single first area light-emitting element 31 emitting a second color light (e.g., red R) within the first display area A1 can be driven by one first pixel circuit 41, and a single first area light-emitting element 31 emitting a third color light (e.g., blue B) within the first display area A1 can be driven by one first pixel circuit 41. In some examples, the first pixel circuit driving the first area light-emitting element 31 emitting the first color light can be located on the side of the first pixel circuit driving the first area light-emitting elements 31 emitting the second and third color lights closer to the first display area A1. In some examples, the conductive connecting lines 51 can be made of a transparent conductive material to improve the light transmittance of the display substrate. For example, multiple conductive connecting lines 51 can be arranged within at least one transparent conductive layer.

[0090] In some examples, such as Figure 4 As shown, a second pixel circuit 42 within the second display area A2 can be connected to the anode (e.g., anode 320a, 320b, 320c, or 320d) of a second area light-emitting element 32. The orthographic projection of the anode of the second area light-emitting element 32 onto the substrate and the orthographic projection of the connected second pixel circuit 42 onto the substrate can partially overlap.

[0091] In some examples, since the second display area A2 is provided with not only a second pixel circuit 42 electrically connected to the second area light-emitting element 32, but also a first pixel circuit 41 electrically connected to the first area light-emitting element 31, the number of pixel circuits in the second display area A2 is greater than the number of second area light-emitting elements 32. In some examples, the area for setting the newly added pixel circuit (i.e., the first type of pixel circuit, including the first pixel circuit 41, the first invalid pixel circuit 43a, and the second invalid pixel circuit 43b) can be obtained by reducing the size of the second pixel circuit 42 in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the second area light-emitting element in the first direction D1.

[0092] In this example, the multiple pixel circuits within the second display area A2 can be arranged in an array along the first direction D1 and the second direction D2. The original column of 'a' pixel circuits can be compressed along the first direction D1, thereby adding space for one more pixel circuit column. The space occupied by the original 'a' pixel circuit columns and the compressed 'a+1' pixel circuit columns can be the same. Here, 'a' can be an integer greater than 1. In some examples, 'a' can be equal to 4. That is, along the first direction D1, every four second pixel circuit columns can be arranged with one first pixel circuit column or one invalid pixel circuit column. However, this embodiment is not limited to this. For example, 'a' can be equal to 2 or 3.

[0093] In other examples, the original b-pixel circuit rows can be compressed along the second direction D2 to add space for one more pixel circuit row, and the space occupied by the original b-pixel circuit rows and the compressed b+1-pixel circuit rows is the same. Here, b can be an integer greater than 1. Alternatively, the area for setting the new pixel circuit can be obtained by reducing the size of the second pixel circuit along the first direction D1 and the second direction D2.

[0094] In this example, a pixel circuit group can be a pixel circuit column. A pixel circuit row can include multiple pixel circuits arranged sequentially along a first direction D1, and the multiple pixel circuits in a pixel circuit row can all be connected to the same gate line. A pixel circuit column can include multiple pixel circuits arranged sequentially along a second direction D2.

[0095] In some examples, within the second display area A2, multiple second pixel circuit columns 420, multiple first pixel circuit columns 410, and multiple invalid pixel circuit columns (e.g., multiple first invalid pixel circuit columns 430a and multiple second invalid pixel circuit columns 430b) can be arranged at intervals along a first direction D1. Each second pixel circuit column 420 includes multiple second pixel circuits 42 arranged sequentially along a second direction D2; each first pixel circuit column 410 includes multiple first pixel circuits 41 arranged sequentially along the second direction D2; each first invalid pixel circuit column 430a includes multiple first invalid pixel circuits 43a arranged sequentially along the second direction D2; and each second invalid pixel circuit column 430b includes multiple second invalid pixel circuits 43b arranged sequentially along the second direction D2. For example, a first pixel circuit column 410, a first invalid pixel circuit column 430a, or a second invalid pixel circuit column 430b can be arranged with four second pixel circuit columns 420 spaced apart. Within the first sub-display area A21, multiple first invalid pixel circuit columns 430a, multiple first pixel circuit columns 410, and multiple second pixel circuit columns 420 can be arranged at intervals.

[0096] In some examples, such as Figure 3As shown, within the first sub-display area A21, along a first direction D1 away from the first display area A1, multiple first pixel circuit columns 410 and multiple first invalid pixel circuit columns 430a inserted within multiple second pixel circuit columns 420 can be numbered. The numbering of the multiple first invalid pixel circuit columns 430a can conform to an arithmetic sequence relationship. For example, among the multiple first pixel circuit columns 410 and multiple first invalid pixel circuit columns 430a within the first sub-display area A21, the numbering of the multiple first invalid pixel circuit columns 430a can satisfy the following relationship: 1 + (i-1) × 3, where i is an integer greater than 0. For instance, along the first direction D1 away from the first display area A1, columns 1, 4, and 7 inserted within the multiple second pixel circuit columns 420 are all first invalid pixel circuit columns 430a, while columns 2, 3, 5, and 6 inserted within the multiple second pixel circuit columns 420 are all first pixel circuit columns 410. Within the second sub-display area A22, the multiple pixel circuits inserted within the multiple second pixel circuit columns 420 are all second invalid pixel circuit columns 430b.

[0097] In some examples, the second display area A2 may be provided with a first power transmission network, which may include multiple first transmission lines extending along a first direction D1 and multiple second transmission lines extending along a second direction D2. Multiple first invalid pixel circuit columns 430a in the first sub-display area A21 may be connected to multiple second transmission lines, and multiple second invalid pixel circuit columns 430b in the second sub-display area A22 may be connected to multiple second transmission lines. For example, one first invalid pixel circuit column 430a is connected to one second transmission line, and one second invalid pixel circuit column 430b is connected to one second transmission line. In the first sub-display area A21, the orthographic projection of the second transmission line onto the substrate overlaps with the orthographic projection of the connected first invalid pixel circuit column 430a onto the substrate; in the second sub-display area A22, the orthographic projection of the second transmission line onto the substrate overlaps with the orthographic projection of the connected second invalid pixel circuit column 430b onto the substrate. For example, in the first sub-display area A21, the orthographic projection of the second transmission line onto the substrate may be located within the orthographic projection range of the connected first invalid pixel circuit column 430a onto the substrate; in the second sub-display area A22, the orthographic projection of the second transmission line onto the substrate may be located within the orthographic projection range of the connected second invalid pixel circuit column 430b onto the substrate.

[0098] In this example, a second transmission line is set up in the first sub-display area A21 using at least one first invalid pixel circuit array 430a, and a second transmission line is set up in the second sub-display area A22 using at least one second invalid pixel circuit array 430b, so that the second display area forms a first power transmission network. This can reduce the voltage difference of the first power signal between the first sub-display area and the second sub-display area, improve the uniformity of the transmission of the first power signal in the second display area, and thus improve the display dimming phenomenon in the first sub-display area.

[0099] Figure 5 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. In some examples, such as... Figure 5 As shown, the pixel circuit in this example may include a first transistor (also referred to as a first reset transistor) T1, a second transistor (also referred to as a threshold compensation transistor) T2, a third transistor (also referred to as a drive transistor) T3, a fourth transistor (also referred to as a data write transistor) T4, a fifth transistor (also referred to as a first light-emitting control transistor) T5, a sixth transistor (also referred to as a second light-emitting control transistor) T6, a seventh transistor (also referred to as a second reset transistor) T7, and a storage capacitor Cst. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0100] In some examples, such as Figure 5 As shown, the display substrate may include: a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 may be configured to provide a constant first power signal VDD to the pixel circuit, and the second power line PL2 may be configured to provide a constant second power signal VSS to the cathode of the light-emitting element EL, wherein the first power signal VDD is greater than the second power signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, the second reset control line RST2 electrically connected to the pixel circuit in the k-th row and the first reset control line RST1 electrically connected to the pixel circuit in the (k+1)-th row can be a single integrated structure. Here, n is an integer greater than 0. This reduces the number of signal lines on the display substrate, enabling a narrow bezel design.

[0101] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between the first power supply signal VDD and the second power supply signal VSS, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0102] In some examples, such as Figure 5 As shown, the third transistor T3 is electrically connected to the light-emitting element EL, and outputs a drive current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first power signal VDD, and second power signal VSS. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GL, the second terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first terminal of the second transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power line PL1, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The gates of the first transistor T1 and the third transistor T3 are electrically connected, and the third transistor T3 is configured to reset its gate. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL, and the seventh transistor T7 is configured to reset its anode. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0103] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0104] The following is about Figure 5 The working process of the pixel circuit is illustrated below. Figure 5 The pixel circuit shown is illustrated using P-type transistors as an example. In some examples, the operation of the pixel circuit during a single frame display period may include a first stage, a second stage, and a third stage.

[0105] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the light-emitting element EL does not emit light.

[0106] The second stage is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is a low-level signal, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high-level signals. The data line DL outputs the data signal DATA. During this stage, since the first electrode of the storage capacitor Cst is low, the third transistor T3 is turned on. The low-level scan signal SCAN turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage Vdata output by the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of the light-emitting element EL. This initializes (resets) the anode of the light-emitting element EL, clearing its internal pre-stored voltage and completing the initialization process, ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first transistor T1 to turn off. The light emission control signal EM provided by the light emission control line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0107] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control line EML is low-level, the fifth transistor T5 and the sixth transistor T6 are turned on. The first power supply signal VDD output by the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0108] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0109] I = K × (Vgs - Vth) 2=K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0110] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first power signal output by the first power line PL1.

[0111] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3.

[0112] Figure 6 This is a partial cross-sectional schematic diagram of the second display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 6 The diagram illustrates the structure of a second light-emitting element and a second pixel circuit in a second display area. In this example, the multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit can all be low-temperature polycrystalline silicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OTFTs). In other examples, the multiple transistors in the pixel circuit can be both LPS and OTFTs.

[0113] In some examples, such as Figure 6 As shown, in a direction perpendicular to the display substrate, the second display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 11, a conductive connection layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 11 of the second display area may include at least: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of invalid pixel circuits, each pixel circuit including a plurality of transistors and at least one capacitor. The light-emitting structure layer 13 of the second display area may include at least: a plurality of second-region light-emitting elements.

[0114] In some examples, Figure 6The diagram illustrates a second pixel circuit comprising a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 11 of the second display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first and second gate metal layers; an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer 104 and a first planarization layer 105 may be disposed between the first and second source / drain metal layers; a second planarization layer 106 may be disposed between the second and third source / drain metal layers; and a third planarization layer 107 may be disposed on the side of the third source / drain metal layer away from the substrate 10. In this embodiment, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 can be inorganic insulating layers, while the first planarization layer 105, the second planarization layer 106, and the third planarization layer 107 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer. In other examples, the circuit structure layer may omit the third source / drain metal layer, or the circuit structure layer may include a fourth source / drain metal layer located on the side of the third source / drain metal layer away from the substrate.

[0115] In some examples, such as Figure 6 As shown, the conductive connection layer 12 may include a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer sequentially disposed along the direction of the substrate 10. A fourth planarization layer 108 may be disposed between the first and second conductive connection layers, a fifth planarization layer 109 may be disposed between the second and third conductive connection layers, and a sixth planarization layer 110 may be disposed on the side of the third conductive connection layer away from the substrate 10. The fourth planarization layer 108, the fifth planarization layer 109, and the sixth planarization layer 110 may be organic insulating layers. In some examples, the first, second, and third conductive connection layers may be made of transparent conductive materials, such as indium tin oxide (ITO).

[0116] In some examples, such as Figure 6As shown, the semiconductor layer of the second display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 10 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 104 and the first planarization layer 105. The third source-drain metal layer may include at least a second transition electrode 232, which can be connected to the first transition electrode 231 through a fourth pixel via formed by the second planarization layer 106. The first conductive connection layer may include at least a third transition electrode 233, which can be connected to the second transition electrode 232 through a fifth pixel via formed by the third planarization layer 107. The second conductive connection layer may include at least a fourth transition electrode 234, which can be connected to the third transition electrode 233 through a sixth pixel via formed by the fourth planarization layer 108. The third conductive connection layer may include at least a fifth transition electrode 235, which can be connected to the fourth transition electrode 234 through a seventh pixel via formed by the fifth planarization layer 109. In some examples, the orthographic projection of the fifth pixel via, the sixth pixel via, and the seventh pixel via onto the substrate can be rectangular or circular.For example, the orthographic projections of the seventh pixel via and the fifth pixel via on the substrate may coincide, while the orthographic projections of the sixth pixel via and the seventh pixel via on the substrate may not coincide. This example can achieve the electrical connection between the pixel circuit and the light-emitting element through a second source / drain metal layer, a third source / drain metal layer, and three conductive connection layers. However, this embodiment is not limited to this. In other examples, the number of conductive connection layers may be one, two, or more.

[0117] In some examples, the orthographic projections of the third adapter electrode 233, the fourth adapter electrode 234, and the fifth adapter electrode 235 onto the substrate can be rectangular. The orthographic projections of the third adapter electrode 233, the fourth adapter electrode 234, and the fifth adapter electrode 235 onto the substrate can overlap and can partially overlap with the orthographic projection of the second adapter electrode 232 onto the substrate.

[0118] In some examples, such as Figure 6 As shown, the light-emitting structure layer 13 of the display area may include: a pixel definition layer 304 and multiple light-emitting elements (e.g., multiple second-area light-emitting elements located in the second display area A2 and multiple first-area light-emitting elements located in the first display area A1). For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode. For example, the first electrode 301 of the second-area light-emitting element located in the second display area A2 may be disposed on the fifth planarization layer 110 and electrically connected to the fifth transition electrode 235 through an eighth pixel via formed in the fifth planarization layer 110. The pixel definition layer 304 is disposed on the first electrode 301 and the fifth planarization layer 110. The pixel definition layer 304 may have multiple pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of the corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer can also be provided on the side of the pixel definition layer 304 away from the substrate 10, and the isolation pillar layer can include multiple isolation pillars (PS).

[0119] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0120] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0121] In some examples, such as Figure 6 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 1401, a second encapsulation layer 1402, and a third encapsulation layer 1403 stacked together. The first encapsulation layer 1401 and the third encapsulation layer 1403 may be made of inorganic materials, while the second encapsulation layer 1402 may be made of organic materials. The second encapsulation layer 1402 may be disposed between the first encapsulation layer 1401 and the third encapsulation layer 1403 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0122] The circuit structure layer of the second display area is illustrated below with an example. Figures 7A to 7FThe diagram illustrates two rows (e.g., row k and row k+1) and five columns (e.g., columns f to f+4) of pixel circuits in the first sub-display area of ​​the second display area. Columns f, f+1, f+2, and f+3 are all second pixel circuit columns, and column f+4 can be a first invalid pixel circuit column. Here, f and k are both integers greater than 0. For example, the equivalent circuit diagram of the second pixel circuit can be as follows: Figure 5 As shown, it may include a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, a sixth transistor T26, a seventh transistor T27, and a storage capacitor C1; the first invalid pixel circuit may include: a first transistor T31, a second transistor T32, a third transistor T33, a fourth transistor T34, a fifth transistor T35, a sixth transistor T36, a seventh transistor T37, and a storage capacitor C2.

[0123] Figure 7A This is a partial schematic diagram of the semiconductor layer and the first gate metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 7A As shown, the semiconductor layer of the second display area may include: an active layer of multiple transistors of multiple second pixel circuits (e.g., an active layer including first transistor T21 to seventh transistor T27), and an active layer of multiple transistors of multiple first invalid pixel circuits (e.g., an active layer including first transistor T31 to seventh transistor T37). The active layers of the first transistors T21 to seventh transistor T27 of a single second pixel circuit may be an interconnected integral structure, and the active layers of the first transistors T31 to seventh transistor T37 of a single first invalid pixel circuit may be an interconnected integral structure.

[0124] In some examples, such as Figure 7A As shown, the first gate metal layer of the second display area may include: gates of multiple transistors of multiple second pixel circuits (e.g., gates of first transistor T21 to seventh transistor T27), gates of multiple transistors of the first invalid pixel circuit (e.g., gates of first transistor T31 to seventh transistor T37), multiple scan lines (e.g., scan lines GL(k), GL(k+1)), multiple first reset control lines (e.g., first reset control lines RST1(k), RST1(k+1), RST1(k+2)), and multiple light emission control lines (e.g., light emission control lines EML(k), EML(k+1)). The multiple scan lines, multiple first reset control lines, and multiple light emission control lines may all extend along the first direction D1, for example, they may be zigzag lines extending along the first direction D1.

[0125] In some examples, such as Figure 7AAs shown, the first reset control line RST1(k+1) connected to the pixel circuit of row k+1 can be used as the second reset control line connected to the pixel circuit of row k. The scan line GL(k) and the gates of the second transistor T22 and the fourth transistor T24 of the second pixel circuit located in row k, as well as the gates of the second transistor T32 and the fourth transistor T34 of the first invalid pixel circuit, can be an integrated structure interconnected. The first reset control line RST1(k) and the gates of the first transistor T21 and the first transistor T31 of the second pixel circuit located in row k can be an integrated structure interconnected. The light emission control line EML(k) and the gates of the fifth transistor T25 and the sixth transistor T26 of the second pixel circuit located in row k, as well as the gates of the fifth transistor T35 and the sixth transistor T36 of the first invalid pixel circuit, can be an integrated structure interconnected. The gate of the third transistor T23 of the second pixel circuit can simultaneously serve as the first electrode of the storage capacitor of the second pixel circuit, and the gate of the third transistor T33 of the first invalid pixel circuit can simultaneously serve as the first electrode of the storage capacitor of the first invalid pixel circuit.

[0126] Figure 7B This is a partial schematic diagram of the second gate metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 7B As shown, the second gate metal layer of the second display area may include: multiple first initial signal lines (e.g., including first initial signal lines INIT1(k), INIT1(k+1), INIT1(k+2)), multiple second initial signal lines (e.g., including second initial signal lines INIT2(k), INIT2(k-1), INIT2(k+1)), the second electrode of the storage capacitor C1 of multiple second pixel circuits, and the second electrode of the storage capacitor C2 of multiple first invalid pixel circuits. The second electrode plates of the storage capacitor C1 of multiple second pixel circuits located in the same row and the second electrode plates of the storage capacitor C2 of multiple first invalid pixel circuits can be an integral structure interconnected. The multiple first initial signal lines and the multiple second initial signal lines can extend along the first direction D1, for example, they can be zigzag lines extending along the first direction D1.

[0127] Figure 7C This is a partial schematic diagram of the first source / drain metal layer of the second display area according to at least one embodiment of the present disclosure. Figure 7D for Figure 7C A schematic diagram of the first source / drain metal layer. In some examples, such as... Figure 7C and Figure 7DAs shown, the first source-drain metal layer of the second display area may include: multiple pixel connection electrodes (e.g., including the first pixel connection electrode 401 to the sixth pixel connection electrode 406), multiple invalid pixel connection electrodes (e.g., including the first invalid pixel connection electrode 411 to the sixth invalid pixel connection electrode 416), multiple first transmission lines 551, and multiple auxiliary routing segments 54.

[0128] In some examples, the first transmission line 551 may be located between two adjacent rows of pixel circuits (e.g., row k and row (k+1) pixel circuits) and extend along a first direction D1. Multiple auxiliary trace segments 54 may be spaced apart along and extend along the first direction D1, and may be located between two adjacent rows of pixel circuits (e.g., row (k+1) and row (k+2) pixel circuits). Along a second direction D2, the first transmission line 551 and the multiple auxiliary trace segments 54 may be spaced apart. This example uses multiple auxiliary trace segments 54 to facilitate electrostatic discharge within the second display area.

[0129] In some examples, the active layer of the first transistor T21 in the second pixel circuit located in row k can be connected to the first initial signal line INIT1(k) through the first pixel connection electrode 401; the gate of the third transistor T23 can be connected to the active layer of the second transistor T22 through the second pixel connection electrode 402; the active layer of the fourth transistor T24 can be connected to the fourth pixel connection electrode 404; the active layer of the fifth transistor T25 can be connected to the second electrode of the storage capacitor C1 through the third pixel connection electrode 403; the active layer of the sixth transistor T26 can be connected to the fifth pixel connection electrode 405; and the active layer of the seventh transistor T27 can be connected to the second initial signal line INIT2(k) through the sixth pixel connection electrode 406.

[0130] In some examples, the active layer of the first transistor T31 in the first invalid pixel circuit located in row k can be connected to the first initial signal line INIT1(k) through the first invalid pixel connection electrode 411; the gate of the third transistor T33 can be connected to the active layer of the second transistor T32 through the second invalid pixel connection electrode 412; the active layer of the fourth transistor T34 can be connected to the fourth invalid pixel connection electrode 414; the active layer of the fifth transistor T35 can be connected to the second electrode of the storage capacitor C2 through the third invalid pixel connection electrode 413; the active layer of the sixth transistor T36 can be connected to the fifth invalid pixel connection electrode 415; and the active layer of the seventh transistor T37 can be connected to the second initial signal line INIT2(k) through the sixth invalid pixel connection electrode 416.

[0131] In some examples, the orthographic projections of the first pixel connection electrode 401 and the first invalid pixel connection electrode 411 onto the substrate can be approximately rectangular rings. The orthographic projections of the second pixel connection electrode 402 and the second invalid pixel connection electrode 412 onto the substrate can be approximately zigzag lines extending along the second direction D2. The orthographic projections of the third pixel connection electrode 403 and the third invalid pixel connection electrode 413 onto the substrate can be approximately stripes extending along the second direction D2. The orthographic projections of the fourth pixel connection electrode 404 and the fourth invalid pixel connection electrode 414 onto the substrate can be approximately rectangular. The orthographic projections of the fifth pixel connection electrode 405 and the fifth invalid pixel connection electrode 415 onto the substrate can be approximately rectangular. The orthographic projections of the sixth pixel connection electrode 406 and the sixth invalid pixel connection electrode 416 onto the substrate can be approximately dumbbell shapes extending along the second direction D2. This example, by setting the shapes of the multiple invalid pixel connection electrodes to be approximately the same as the shapes of the multiple pixel connection electrodes, can help improve the uniformity of the first source / drain metal layer during the etching process.

[0132] In some examples, the first invalid pixel connection electrode 411, the second invalid pixel connection electrode 412, and the third invalid pixel connection electrode 413 can be connected sequentially. Multiple invalid pixel connection electrodes (e.g., including the first invalid pixel connection electrode 411, the second invalid pixel connection electrode 412, and the third invalid pixel connection electrode 413) of multiple first invalid pixel circuits arranged along the second direction D2 can be connected sequentially to form a second transmission line 552. The second transmission line 552 is connected to the first transmission line 551 to form a first power transmission network 55 located within the first sub-display area. Within the second sub-display area, the structure of the second invalid pixel circuit is similar to that of the first invalid pixel circuit, and multiple invalid pixel connection electrodes connected to the second invalid pixel circuit can be connected to form a second transmission line to form the first power transmission network 55 within the second sub-display area.

[0133] Figure 7E This is a schematic diagram of the second source / drain metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 7EAs shown, the second source / drain metal layer of the second display area may include: multiple first power lines (e.g., first power lines PL1(f) to PL1(f+4)) and multiple transition electrodes (e.g., first transition electrode 231, sixth transition electrode 236, seventh transition electrode 237, and eighth transition electrode 238). The multiple first power lines may extend along the second direction D2, for example, they may be zigzag lines extending along the second direction D2. For example, the first power line PL1(f+3) may be connected to the third pixel connection electrode 403 to achieve connection with the second electrode of the active layer of the fifth transistor and the storage capacitor of the second pixel circuit; the first power line PL1(f+4) may be connected to the third inactive pixel connection electrode 413 to achieve connection with the second transmission line 552 of the first power transmission network 55.

[0134] In some examples, the sixth transition electrode 236 can be connected to the fourth pixel connection electrode 404 to achieve an active layer connection with the fourth transistor of the second pixel circuit. The seventh transition electrode 237 can be connected to the fourth invalid pixel connection electrode 414 to achieve an active layer connection with the fourth transistor of the first invalid pixel circuit. The first transition electrode 231 can be connected to the fifth pixel connection electrode 405 to achieve an active layer connection with the sixth transistor of the second pixel circuit. The eighth transition electrode 238 can be connected to the fifth invalid pixel connection electrode 415 to achieve an active layer connection with the sixth transistor of the first invalid pixel circuit.

[0135] Figure 7F This is a schematic diagram of the third source / drain metal layer of the second display area according to at least one embodiment of this disclosure. In some examples, such as... Figure 7F As shown, the third source / drain metal layer of the second display area may include: multiple second power lines PL2, multiple data lines (e.g., data lines DL(f) to DL(f+4)), and multiple transition electrodes (e.g., second transition electrode 232 and ninth transition electrode 239). The multiple second power lines PL2 and multiple data lines may extend along the second direction D2 and be spaced apart along the first direction D1. The second power lines PL2 may be configured to connect to the cathode of the light-emitting element in the second region. For example, the data line DL(f+3) may be connected to the sixth transition electrode 236 to achieve electrical connection with the second pixel circuit and be configured to provide a data signal to the second pixel circuit. The data line DL(f+4) may be connected to the seventh transition electrode 237 to achieve connection with the first invalid pixel circuit. Since the first invalid pixel circuit is not used to drive the light-emitting element, the data line connected to the first invalid pixel circuit (e.g., data line DL(f+4)) may be configured to receive the first power signal to further improve the uniformity of the transmission of the first power signal in the second display area.

[0136] In some examples, the second transition electrode 232 can be connected to the first transition electrode 231 to achieve an electrical connection with the second pixel circuit. The ninth transition electrode 239 can be connected to the eighth transition electrode 238 to achieve a connection with the first invalid pixel circuit. In this example, the second transition electrode 232 can be connected to the anode of the second region light-emitting element to achieve an electrical connection between the second pixel circuit and the second region light-emitting element; the ninth transition electrode 239 is not connected to either the second region light-emitting element or the first region light-emitting element.

[0137] Figure 8A This is a partial schematic diagram of the boundary between the second display area and the border area, which is at least one embodiment of this disclosure. Figure 8A This diagram illustrates the boundary between the second display area A2 and the first border area B1. Figure 8A The structure of the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer is illustrated as an example, while the structure of the other film layers is omitted. Figure 8A The diagram illustrates a portion of the film layer of the pixel circuit in the two rows and nine columns (e.g., column f to column f+8) within the second display area A2. Figure 8B for Figure 8A A schematic diagram of the first source / drain metal layer in the image. Figure 8C for Figure 8A A schematic diagram of the second source / drain metal layer. Figure 8D for Figure 8A A schematic diagram of the third source / drain metal layer.

[0138] In some examples, such as Figures 8A to 8D As shown, the first border region B1 may be provided with a first peripheral power line 61 and a second peripheral power line 62. The first peripheral power line 61 and the second peripheral power line 62 may extend at least along a first direction D1. The second peripheral power line 62 may be located on the side of the first peripheral power line 61 away from the second display area A2. The second peripheral power line 62 may be located in the first source / drain metal layer. The first peripheral power line 61 may include: a first peripheral trace 611 and a second peripheral trace 612 interconnected. The second peripheral trace 612 may be located in the second source / drain metal layer, and the first peripheral trace 611 may be located in the first source / drain metal layer. For example, the orthographic projection of the second peripheral trace 612 onto the substrate may cover the orthographic projection of the first peripheral trace 611 onto the substrate.

[0139] In some examples, such as Figure 8B As shown, the second transmission line 552 of the first power transmission network 55 located in the first source / drain metal layer can extend to the first border region B1 and connect with the first peripheral trace 611 of the first peripheral power line 61. For example, the first power transmission network 55 and the first peripheral trace 611 are an integral structure.

[0140] In some examples, such as Figure 8C As shown, the pixel circuit in column f+4 is a first invalid pixel circuit column, and the pixel circuits in columns f to f+3 and columns f+5 to f+8 are all second pixel circuit columns. The first power line PL1(f+4) connected to the first invalid pixel circuit column and the first power lines connected to the multiple second pixel circuit columns can extend to the first border area B1 and are all connected to the second peripheral trace 612 of the first peripheral power line 61. For example, the second peripheral trace 612 and the multiple first power lines can be an integral structure.

[0141] In some examples, such as Figure 8A and Figure 8D As shown, the second power lines PL2 connected to the multiple second pixel circuit columns can extend to the first border region B1 and are electrically connected to the second peripheral power lines 62 located in the second source-drain metal layer. The second power lines PL2(f+4) and data lines DL(f+4) connected to the first invalid pixel circuit column (e.g., the f+4th pixel circuit) are interconnected as a single structure and extend to the first border region B1, connecting to the first power line PL1(f+4) located in the second source-drain metal layer, thereby achieving electrical connection with the first peripheral power lines 61.

[0142] In this example, the invalid pixel connection electrodes connected to the first invalid pixel circuit column form a first transmission line in the first sub-display area, ensuring the formation of a first power transmission network in the first sub-display area. Furthermore, the data lines connected to the first invalid pixel circuit column are connected to the first peripheral power line and the first power line, further improving the uniformity of the first power signal transmission. The structure of the second invalid pixel circuit in the second sub-display area is similar to that of the first invalid pixel circuit in the first sub-display area, and therefore will not be described further here.

[0143] Figure 9 This is a schematic diagram illustrating another arrangement of the pixel circuitry in the second display area according to at least one embodiment of this disclosure. In some examples, such as Figure 9As shown, within the first sub-display area A21, along a first direction D1 away from the first display area A1, the multiple first pixel circuit columns 410 and multiple first invalid pixel circuit columns 430a interposed within the multiple second pixel circuit columns 420 are numbered. The numbering of the multiple first invalid pixel circuit columns 430a can conform to an arithmetic sequence relationship. For example, in the multiple first pixel circuit columns 410 and multiple first invalid pixel circuit columns 430a within the first sub-display area A21, the numbering of the multiple first pixel circuit columns 410 satisfies the following relationship: 1 + (i-1) × 3, where i is an integer greater than 0. For example, columns 1, 4, and 7 inserted within the second pixel circuit columns 420 are all first pixel circuit columns 410, and columns 2, 3, 5, and 6 inserted within the second pixel circuit columns 420 are all first invalid pixel circuit columns 430a. Further descriptions of the display substrate in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0144] Figure 10 This is a schematic diagram illustrating another arrangement of the pixel circuitry in the second display area according to at least one embodiment of this disclosure. In some examples, such as Figure 10 As shown, within the first sub-display area A21, along a first direction D1 away from the first display area A1, the multiple first pixel circuit columns 410 and multiple first invalid pixel circuit columns 430a interposed within the multiple second pixel circuit columns 420 are numbered. The numbering of the multiple first invalid pixel circuit columns 430a can conform to an arithmetic sequence. For example, the numbers of the multiple first invalid pixel circuit columns 430a are odd, and the numbers of the multiple first pixel circuit columns 410 are even. For instance, columns 1, 3, and 5 inserted within the second pixel circuit columns 420 are all first invalid pixel circuit columns 430a, and columns 2, 4, and 6 inserted within the second pixel circuit columns 420 are all first pixel circuit columns 410. Further descriptions of the display substrate in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0145] Figure 11 This is a schematic diagram illustrating another arrangement of the pixel circuitry in the second display area according to at least one embodiment of this disclosure. In some examples, such as Figure 11As shown, within the first sub-display area A21, along a first direction D1 away from the first display area A1, the multiple first pixel circuit columns 410 and multiple first invalid pixel circuit columns 430a interposed within the multiple second pixel circuit columns 420 are numbered. The numbering of the multiple first invalid pixel circuit columns 430a can conform to an arithmetic sequence. For example, the numbers of the multiple first invalid pixel circuit columns 430a are even numbers, and the numbers of the multiple first pixel circuit columns 410 are odd numbers. For instance, columns 1, 3, and 5 inserted within the second pixel circuit columns 420 are all first pixel circuit columns 410, and columns 2, 4, and 6 inserted within the second pixel circuit columns 420 are all first invalid pixel circuit columns 430a. Further descriptions of the display substrate in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0146] Figure 12 This is a schematic diagram illustrating another arrangement of the pixel circuitry in the second display area according to at least one embodiment of this disclosure. In some examples, such as Figure 12 As shown, within the first sub-display area A21, multiple first invalid pixel circuit columns 430a are located on the side of the multiple first pixel circuit columns 410 closest to the first display area A1. For example, a dozen or more first invalid pixel circuit columns 430a can be arranged on the side of the multiple first pixel circuit columns 410 closest to the first display area A1. By centrally arranging the multiple first pixel circuit columns 410, the ratio between the maximum and minimum lengths of the conductive connection lines can be reduced. Further descriptions of the display substrate in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0147] Figure 13 This is a schematic diagram illustrating another arrangement of the pixel circuitry in the second display area according to at least one embodiment of this disclosure. In some examples, such as Figure 13 As shown, within the first sub-display area A21, two first invalid pixel circuit columns 430a and four first pixel circuit columns 410 can be arranged at intervals. Two first invalid pixel circuit columns 430a are provided every four first pixel circuit columns 410, and four second pixel circuit columns 420 are provided between adjacent first pixel circuit columns 410, between adjacent first invalid pixel circuit columns 430a, and between adjacent first pixel circuit columns 410 and first invalid pixel circuit columns 430a. Further descriptions of the display substrate in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0148] In other examples, the arrangement of the first invalid pixel circuit column and the first pixel circuit column in the first sub-display area of ​​the above embodiments can be combined with each other. For example, multiple first invalid pixel circuit columns can be arranged in the first sub-display area close to the first display area, and multiple first invalid pixel circuit columns and multiple first pixel circuit columns in the remaining area of ​​the first sub-display area can be arranged alternately, for example, arranged at intervals that conform to an arithmetic progression relationship.

[0149] Figure 14 This is a schematic planar view of another arrangement of light-emitting elements in a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 14 As shown, two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 in the first display area A1 can be interconnected. For example, the anodes of two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 can be interconnected. Similarly, two adjacent fourth light-emitting elements 32a and 32d arranged along the first direction D1 in the second display area A2 can be interconnected. For example, the anodes of two adjacent fourth light-emitting elements 32a and 32d arranged along the first direction D1 can be interconnected.

[0150] In this example, the first pixel circuit in the second display area A2 and the first light-emitting element in the first display area A1 can have a one-to-two driving relationship, and the second pixel circuit in the second display area A2 and the fourth light-emitting element can have a one-to-two driving relationship. In other words, one first pixel circuit in the second display area A2 can be configured to drive two first light-emitting elements in the first display area A1 (e.g., one first light-emitting element 31a and one first light-emitting element 31d), and one second pixel circuit in the second display area A2 can be configured to drive two fourth light-emitting elements in the second display area A2 (e.g., one fourth light-emitting element 32a and one fourth light-emitting element 32d). Further descriptions of the display substrate in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0151] Figure 15 This is a schematic diagram illustrating another arrangement of the pixel circuitry in the second display area according to at least one embodiment of this disclosure. In some examples, based on... Figure 14 The driving relationship between the pixel circuit and the light-emitting element is shown as follows: Figure 15 As shown, in the first sub-display area A21 of the second display area, in the first direction D1, two first type pixel circuit columns can be arranged every three second pixel circuit columns 420; in the second sub-display area A22, in the first direction D1, two second invalid pixel circuit columns 430b can be arranged every three second pixel circuit columns 420.

[0152] In some examples, such as Figure 15As shown, the two first-type pixel circuit columns arranged within the first sub-display area A21, spaced three times apart by the second pixel circuit columns 420, include the following two combinations. The first combination consists of two first pixel circuit columns 410 arranged along the first direction D1; the second combination consists of a first invalid pixel circuit column 430a and a first pixel circuit column 410 arranged along the first direction D1 away from the first display area A1. The first combination and the second combination are arranged alternately along the first direction D1. In other examples, the arrangement of the first combination and the second combination can satisfy the aforementioned arithmetic sequence relationship. In other examples, the two first-type pixel circuit columns arranged within the first sub-display area A21 at intervals of three second pixel circuit columns 420 include the following three combinations: the first combination consists of two first pixel circuit columns 410 arranged along the first direction D1; the second combination consists of a first invalid pixel circuit column 430a and a first pixel circuit column 410 arranged along the first direction D1 away from the first display area A1; the third combination consists of two first invalid pixel circuit columns 430a arranged along the first direction D1; the first, second, and third combinations can be arranged alternately along the first direction D1. This embodiment is not limited in this respect. Further descriptions of the display substrate in this example can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0153] Figure 16 This is a schematic planar view of another arrangement of light-emitting elements in a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 16 As shown, two adjacent first light-emitting elements 31a and 31d arranged along the second direction D2 in the first display area A1 can be connected to each other; two adjacent second light-emitting elements 31b arranged diagonally in the first display area A1 can be connected to each other; and two adjacent third light-emitting elements 31c arranged diagonally in the first display area A1 can be connected to each other.

[0154] In this example, the first pixel circuit in the second display area A2 and the first light-emitting element in the first display area A1 can have a one-to-two driving relationship, the first pixel circuit in the second display area A2 and the second light-emitting element in the first display area A1 can have a one-to-two driving relationship, and the first pixel circuit in the second display area A2 and the third light-emitting element in the first display area A1 can have a one-to-two driving relationship. Based on the driving relationship between the pixel circuit and the light-emitting element in this example, compared with the previous embodiment, the number of first pixel circuit columns in the second display area can be reduced, which is beneficial to reduce the length of the conductive connection lines and improve the display defects in the first display area caused by the length of the conductive connection lines. The arrangement of the first pixel circuit columns and the first invalid pixel circuit columns in this example can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0155] Figure 17This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 17 As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may at least partially overlap with a first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 may be located within the range of the first display area A1. In some examples, the sensor 92 may be a camera or an infrared sensor.

[0156] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following products: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following products: microdisplay, VR device or AR device containing a microdisplay, etc.

[0157] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0158] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate; a plurality of first area light emitting elements disposed on the substrate and located in the first display area; a plurality of second area light emitting elements, a plurality of first type pixel circuits and a plurality of second pixel circuits disposed on the substrate and located in the second display area; the plurality of second pixel circuits and the plurality of first type pixel circuits are arranged in a first direction; the plurality of first type pixel circuits comprises a plurality of first pixel circuits located in the first sub-display area and a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits comprises a plurality of first invalid pixel circuits located in the first sub-display area and a plurality of second invalid pixel circuits located in the second sub-display area; at least one first pixel circuit in the plurality of first pixel circuits is connected to at least one first area light emitting element in the plurality of first area light emitting elements through at least one conductive connection line, and at least one second pixel circuit in the plurality of second pixel circuits is connected to at least one second area light emitting element in the plurality of second area light emitting elements; a first power transmission network disposed on the substrate and located in the second display area, the first power transmission network comprises a plurality of first transmission lines extending in a first direction and a plurality of second transmission lines extending in a second direction; the first direction intersects the second direction; in the first sub-display area, at least one second transmission line in the plurality of second transmission lines is connected to a plurality of first invalid pixel circuits arranged in the second direction and there is an overlap in the orthographic projection of the substrate; in the second sub-display area, at least one second transmission line in the plurality of second transmission lines is connected to a plurality of second invalid pixel circuits arranged in the second direction and there is an overlap in the orthographic projection of the substrate. At least one invalid pixel circuit in the plurality of invalid pixel circuits is connected to a plurality of invalid pixel connection electrodes in the same conductive layer, and at least some invalid pixel connection electrodes in the plurality of invalid pixel connection electrodes connected by a plurality of invalid pixel circuits arranged in the second direction are connected to form a second transmission line. The first sub-display area is provided with a plurality of first invalid pixel circuit groups and a plurality of first pixel circuit groups, each first invalid pixel circuit group comprises a plurality of first invalid pixel circuits arranged in the second direction in sequence, and each first pixel circuit group comprises a plurality of first pixel circuits arranged in the second direction in sequence; 2. The display substrate of claim 1, wherein, At least one first invalid pixel circuit group in the plurality of first invalid pixel circuit groups is located on one side of at least one first pixel circuit group in the plurality of first pixel circuit groups close to the first display area.

3. The display substrate of claim 1, wherein, In the first direction and in the direction away from the first display area, the plurality of first pixel circuit groups and the plurality of first invalid pixel circuit groups in the first sub-display area are sequentially numbered. ​ 4. The display substrate of claim 3, wherein, ​ The numbers of at least some of the first invalid pixel circuit groups in the plurality of first invalid pixel circuit groups satisfy an arithmetic progression relationship. Alternatively, the numbers of at least some of the first pixel circuit groups in the plurality of first pixel circuit groups satisfy an arithmetic progression relationship.

5. The display substrate of claim 4, wherein, The number of each first pixel circuit group is even, and the number of each first invalid pixel circuit group is odd; or the number of each first invalid pixel circuit group is even, and the number of each first pixel circuit group is odd; or the numbers of the plurality of first invalid pixel circuit groups satisfy the following relationship: 1 + (i-1)×3, i is an integer greater than 0. 6.The display substrate of claim 1, wherein, The display substrate further comprises: a plurality of data lines disposed on the substrate and located in the second display area; at least one data line in the plurality of data lines is connected to the plurality of invalid pixel circuits arranged along the second direction; a first peripheral power line disposed on the substrate and located in a frame area, the frame area being located on at least one side of the second display area, the first peripheral power line extending at least along the first direction and being connected to the first power transmission network; the data line connected to the plurality of invalid pixel circuits arranged along the second direction is connected to the first power transmission network. 7.The display substrate of claim 6, wherein, The display substrate further comprises: a plurality of first power lines disposed on the substrate and located in the second display area, at least one first power line in the plurality of first power lines being connected to the plurality of invalid pixel circuits arranged along the second direction; the data line connected to the plurality of invalid pixel circuits arranged along the second direction is connected to the first peripheral power line through the first power line connected to the plurality of invalid pixel circuits. 8.The display substrate of claim 7, wherein, The first peripheral power line comprises a first peripheral trace and a second peripheral trace connected to each other; the second peripheral trace is located on the side of the first peripheral trace away from the substrate; the first peripheral trace and the first power transmission network are in an integrated structure; and the second peripheral trace and the plurality of first power lines are in an integrated structure. 9.The display substrate of claim 7, wherein, The plurality of data lines are located on the side of the plurality of first power lines away from the substrate, and the plurality of first power lines are located on the side of the first power transmission network away from the substrate. 10.The display substrate of claim 9, wherein, In a direction perpendicular to the display substrate, the second display area comprises a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on the side of the first source-drain metal layer away from the substrate, and the third source-drain metal layer is located on the side of the second source-drain metal layer away from the substrate; the first power transmission network is located on the first source-drain metal layer; the plurality of first power lines are located on the second source-drain metal layer; the plurality of data lines are located on the third source-drain metal layer.

11. The display substrate according to any one of claims 1 to 10, characterized in that, In the first direction, n first-type pixel circuits are arranged every a second pixel circuits, where a and n are both integers greater than 0, and a is greater than n. 12.The display substrate of claim 11, wherein, a is 4, and n is 1. 13.The display substrate of claim 1, wherein, The plurality of first regions of light emitting elements comprise: a plurality of first light emitting elements emitting first color light, a plurality of second light emitting elements emitting second color light, and a plurality of third light emitting elements emitting third color light. At least one of the first pixel circuits is connected with two adjacent first light emitting elements emitting first color light; at least one of the first pixel circuits is connected with one second light emitting element emitting second color light; and at least one of the first pixel circuits is connected with one third light emitting element emitting third color light. 14.The display substrate of claim 13, wherein, The plurality of second region light emitting elements comprises a plurality of fourth light emitting elements emitting first color light, a plurality of fifth light emitting elements emitting second color light, and a plurality of sixth light emitting elements emitting third color light. At least one of the second pixel circuits is connected with two adjacent fourth light emitting elements emitting first color light; at least one of the second pixel circuits is connected with one fifth light emitting element emitting second color light; and at least one of the second pixel circuits is connected with one sixth light emitting element emitting third color light.

15. The display substrate according to claim 13 or 14, characterized in that, The first color light is green light, the second color light is red light, and the third color light is blue light.

16. A display device comprising: A display substrate comprising any one of the display substrates of claims 1-15.

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