Display device, method of manufacturing the same, and electronic device including the same

Abstract

The invention provides a display device, a method of manufacturing the display device, and an electronic device including the display device. The display device includes a substrate defining an emission area and a non-emission area surrounding the emission area; a bank structure on the substrate in the emission region and including a tip protruding toward the non-emission region; an anode contact hole penetrating the bank structure; an anode on the bank structure and electrically connected to a transistor on the substrate through an anode contact hole; a pixel defining layer on the anode; and a light emitting layer on the pixel defining layer, in which the light emitting layer is spaced apart from the anode in a portion overlapping the anode contact hole in a plan view, and the pixel defining layer is between the light emitting layer and the anode, and the light emitting layer contacts the anode in a portion not overlapping the anode contact hole in the plan view.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2024-0119842, filed on September 4, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a display device and a method for manufacturing a display device. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are used in various electronic devices, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel display devices such as liquid crystal displays, field emission displays, and organic light-emitting diode (OLED) displays. Among these flat panel display devices, light-emitting display devices include light-emitting elements that enable each pixel of the display panel to emit its own light. Therefore, light-emitting display devices can display images without a backlight unit that provides light to the display panel. Summary of the Invention

[0005] This disclosure provides a display device capable of providing high-resolution images and a method for manufacturing the display device.

[0006] Another aspect of this disclosure is to resolve short circuits between the anode and the cathode.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of the disclosure.

[0008] In this embodiment of the disclosure, the display device includes: a substrate defining an emitting region and a non-emitting region surrounding the emitting region; a dam structure located on the substrate in the emitting region and including a tip projecting toward the non-emitting region; an anode contact hole penetrating the dam structure; an anode located on the dam structure and electrically connected to a transistor located on the substrate through the anode contact hole; a pixel defining layer located on the anode; and a light-emitting layer located on the pixel defining layer, wherein the light-emitting layer is spaced apart from the anode in a portion overlapping with the anode contact hole in a plan view, and the pixel defining layer is between the light-emitting layer and the anode, and the light-emitting layer contacts the anode in a portion not overlapping with the anode contact hole in a plan view.

[0009] In an implementation, the embankment structure may include: a first embankment layer; a second embankment layer located on the first embankment layer; and a third embankment layer having a tip that protrudes significantly beyond the first side surface of the second embankment layer facing the non-emission region toward the non-emission region.

[0010] In this implementation, the second and third dike layers may surround the anode contact hole.

[0011] In an implementation, the shape of the side surface of the dam structure facing the anode contact hole can be different from the shape of the side surface of the dam structure facing the non-emission area.

[0012] In one embodiment, the second side surface of the second dam layer facing the anode contact hole can be aligned with the third side surface of the third dam layer facing the anode contact hole.

[0013] In an implementation, the pixel defining layer may include: a first pixel defining layer located between the dam structure and the anode; a second pixel defining layer covering the edge of the anode and overlapping with the emitting region to define a first opening; and a third pixel defining layer overlapping with the anode contact hole and located between the light-emitting layer and the anode.

[0014] In one embodiment, the second opening may be defined between the third pixel defining layer and the second pixel defining layer in a direction parallel to the main surface of the substrate.

[0015] In one embodiment, the light-emitting layer may contact the anode in the portion of the planar view that overlaps with the second opening.

[0016] In one embodiment, the first pixel defining layer and the second pixel defining layer may overlap with the tip of the third dam layer in a direction perpendicular to the main surface of the substrate.

[0017] In an implementation, the second pixel defining layer and the third pixel defining layer may comprise the same material.

[0018] In an embodiment, the display device may further include: a first cathode located on the light-emitting layer; a first auxiliary electrode located on the first cathode and in contact with a first side surface of the second diaphragm layer; and a first element inorganic layer located on the first auxiliary electrode.

[0019] In one embodiment, the first cathode may not contact the first side surface of the second dam layer, and may be electrically connected to the second dam layer via the first auxiliary electrode.

[0020] In one embodiment, the first auxiliary electrode may be spaced apart from the first dam layer in a direction perpendicular to the main surface of the substrate, and the cavity is between the first auxiliary electrode and the first dam layer.

[0021] In an embodiment, the display device may further include: a second cathode, spaced apart from the first cathode in a portion overlapping with the non-emission region; a second auxiliary electrode, located on the second cathode and spaced apart from the first auxiliary electrode; and a second element inorganic layer, located on the second auxiliary electrode and spaced apart from the first element inorganic layer, wherein the first auxiliary electrode and the second auxiliary electrode may be electrically connected.

[0022] In an embodiment, the display device may further include: a connection electrode located between the substrate and the dam structure and electrically connected to the transistor; and a via layer covering the connection electrode, wherein an anode contact hole penetrates the via layer and the anode is electrically connected to the transistor through the connection electrode.

[0023] In one embodiment, the second pixel defining layer may include an inorganic material, and the third pixel defining layer may include an organic material.

[0024] In one embodiment, a method of manufacturing a display device includes: forming a dam structure having an undercut shape on a substrate in an emission region; forming an anode contact hole that penetrates the dam structure and exposes a connection electrode; forming an anode located on the dam structure and contacting the connection electrode through the anode contact hole; and forming a pixel defining layer on the anode, and forming a light-emitting layer and a cathode on the pixel defining layer, wherein the anode and the light-emitting layer are separated by the pixel defining layer in the portion overlapping with the anode contact hole.

[0025] In an embodiment, the dam structure may include a first dam layer, a second dam layer, and a third dam layer, the second dam layer and the third dam layer comprising different metallic materials from each other, and the anode contact hole is formed by simultaneously removing a portion of each of the first dam layer, the second dam layer, and the third dam layer during the formation of the anode contact hole.

[0026] In this implementation, the light-emitting layer and the cathode can be formed by deposition and etching processes without the need for a fine metal mask.

[0027] In one embodiment, the electronic device includes: at least one display device, including a substrate defining an emitting region and a non-emitting region; a display device housing housing therein housing the at least one display device; and an optical component for amplifying an image displayed by the at least one display device or converting an optical path, wherein the at least one display device further includes: a dam structure located on the substrate in the emitting region and including a tip projecting toward the non-emitting region; an anode contact hole penetrating the dam structure; an anode located on the dam structure and electrically connected to a transistor located on the substrate through the anode contact hole; a pixel defining layer located on the anode; and a light-emitting layer located on the pixel defining layer, wherein the light-emitting layer is spaced apart from the anode in a portion overlapping with the anode contact hole in a plan view, and the pixel defining layer is between the light-emitting layer and the anode, and the light-emitting layer contacts the anode in a portion not overlapping with the anode contact hole in a plan view. Attached Figure Description

[0028] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view of a head-mounted electronic device according to an embodiment; Figure 2 yes Figure 1 An exploded perspective view of an example of a head-mounted electronic device; Figure 3 This is a perspective view of a head-mounted electronic device according to an embodiment; Figure 4 This is a perspective view of the display device according to the embodiment; Figure 5 This is a cross-sectional view of the display device according to an embodiment; Figure 6 This is a plan view of the display layer of the display device according to the embodiment; Figure 7 It is shown Figure 6 A layout diagram showing the arrangement of multiple pixels in the display area; Figure 8 It is shown Figure 6 Another example and layout diagram of the arrangement of multiple pixels in the display area; Figure 9 It is along Figure 7 A cross-sectional view of an example of the display layer, taken by line A1-A1'; Figure 10 Is with Figure 9 An enlarged cross-sectional view of the display element layer overlapping the first emission region in the image; Figure 11 It is along Figure 7 A cross-sectional view of an example of the display layer, taken by line A3-A3'; Figure 12 Is with Figure 11 An enlarged cross-sectional view of the display element layer overlapping the first emission region in the image; Figure 13 yes Figure 12 An enlarged sectional view of the region "T" in the image; Figure 14 It is along Figure 7 Another embodiment and cross-sectional view of the display panel, cut off by line A3-A3'; Figure 15 Is with Figure 14 An enlarged cross-sectional view of the display element layer overlapping the first emission region in the image; Figures 16 to 25 The manufacturing process is shown sequentially. Figure 11 A cross-sectional view of the method for displaying the element layer; Figure 26 This is a block diagram of an electronic device according to one embodiment of the present disclosure; and Figure 27 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0029] The invention will be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout.

[0030] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element.

[0031] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a (a),” “an,” and “the” are intended to include the plural forms, including “at least one.” Thus, reference to “a” followed by “the” in the appended claims includes one element and multiple elements. For example, “a single element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as a limiting “a (a)” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “comprises” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It should be understood that, in addition to the orientations depicted in the drawings, relative terms are intended to include different orientations of the device. For example, if the device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, the term “down” can include both “down” and “up” orientations depending on the specific orientation of the drawing. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the term “below” or “under” can include both above and below orientations.

[0034] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement under discussion and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). Terms such as “about” may mean within one or more standard deviations, or, for example, within ±30%, ±20%, ±10%, ±5% of the stated value.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and shall not be interpreted in an idealized or overly formalized sense unless expressly so defined herein.

[0036] Embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments. Thus, variations in shape as a result of, for example, manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but are to include, for example, deviations in shape due to manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0037] In the following description, the embodiments will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 This is a perspective view of the head-mounted electronic device 1 according to the embodiment. Figure 2 yes Figure 1 An exploded perspective view of an example of a head-mounted electronic device 1.

[0039] refer to Figure 1 and Figure 2 The electronic device 1 according to the embodiment can be a head-mounted electronic device, and therefore can also be referred to as head-mounted electronic device 1. The head-mounted electronic device 1 includes a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head mounting strap 140, a first display device 10_1, a second display device 10_2, a middle frame 160, a first optical component 151, a second optical component 152, a control circuit board 170, and a connector.

[0040] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Each of the first display device 10_1 and the second display device 10_2 is associated with a reference. Figure 4 The described display devices 10 are substantially the same. Therefore, the descriptions of the first display device 10_1 and the second display device 10_2 will be based on reference. Figure 4 The given description will replace it.

[0041] The first optical component 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical component 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical component 151 and the second optical component 152 may include at least one convex lens.

[0042] The intermediate frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and can also be disposed between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 supports and fixes the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0043] The control circuit board 170 can be disposed between the intermediate frame 160 and the display device housing 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 170 can convert image sources received from the outside into digital image data, and transmit the digital image data to the first display device 10_1 and the second display device 10_2 via connectors.

[0044] The control circuit board 170 can transmit digital image data corresponding to a left image optimized for the user's left eye to the first display device 10_1, and transmit digital image data corresponding to a right image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 can transmit the same digital image data to both the first display device 10_1 and the second display device 10_2.

[0045] The display device housing 110 houses a first display device 10_1, a second display device 10_2, a middle frame 160, a first optical component 151, a second optical component 152, a control circuit board 170, and a connector. A housing cover 120 is positioned to cover the opening surface of the display device housing 110. The housing cover 120 may include a first eyepiece 131 for the user's left eye and a second eyepiece 132 for the user's right eye. Although the first eyepiece 131 and the second eyepiece 132 are... Figure 1 and Figure 2 The first eyepiece 131 and the second eyepiece 132 are set separately, but the implementation method described in this specification is not limited to this. In another embodiment, the first eyepiece 131 and the second eyepiece 132 can also be combined into one.

[0046] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical component 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical component 152. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 151 through the first eyepiece 131, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 152 through the second eyepiece 132.

[0047] The head-mounted strap 140 secures the display device housing 110 to the user's head, such that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are held in place over the user's left and right eyes, respectively. When the display device housing 110 is made lightweight and small, the head-mounted electronic device 1 may include, for example... Figure 3 The eyeglasses frame shown is not the head-mounted strap 140.

[0048] In addition, the head-mounted electronic device 1 may also include a battery for supplying power, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0049] Figure 3 This is a perspective view of the head-mounted electronic device 1_1 according to the embodiment.

[0050] refer to Figure 3 According to the embodiment, the head-mounted electronic device 1_1 may be an electronic device in which the display device housing 120_1 is implemented in the form of lightweight and small eyeglasses. The head-mounted electronic device 1_1 according to the embodiment may include a display device 10_3, a left lens 311, a right lens 312, a support frame 350, eyeglass frame temples 341 and 342, an optical component 320, an optical path conversion component 330, and a display device housing 120_1.

[0051] Figure 3 The display device 10_3 shown is referenced Figure 4 The display device 10 described is essentially the same.

[0052] The display device housing 120_1 can accommodate the display device 10_3, the optical component 320, and the optical path conversion component 330. The image displayed on the display device 10_3 can be magnified by the optical component 320, its optical path can be converted by the optical path conversion component 330, and then provided to the user's right eye through the right lens 312. Therefore, the user can view an augmented reality image—a combination of a virtual image displayed on the display device 10_3 and a real image viewed through the right lens 312—through their right eye.

[0053] Despite Figure 3 The display device housing 120_1 is located at the right end of the support frame 350, but the embodiments described herein are not limited to this. In another example, the display device housing 120_1 may also be located at the left end of the support frame 350. In this case, the image displayed on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 120_1 may be located at both the left and right ends of the support frame 350. In this case, the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0054] Figure 4 This is a perspective view of the display device 10 according to the embodiment.

[0055] refer to Figure 4 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit in televisions, laptops, monitors, billboards, or Internet of Things (IoT) devices. As another example, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, and head-mounted displays.

[0056] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having a short side in the first direction DR1 and a long side in the second direction DR2. Each corner where the short side extending in the first direction DR1 intersects the long side extending in the second direction DR2 may be rounded to have a predetermined curvature or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0057] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0058] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DDA containing pixels of the displayed image and a non-display area NDA located around the display area DDA.

[0059] The display area DDA can emit light from multiple emission regions or multiple openings, as will be described later. For example, the display panel 100 may include pixel circuitry containing switching elements, a pixel defining layer defining emission regions or openings, and self-emissive elements. For example, the self-emissive element may include, but is not limited to, at least one of an organic light-emitting diode (OLED) containing an organic light-emitting layer, a quantum dot OLED containing a quantum dot emitting layer, an inorganic OLED containing inorganic semiconductors, and a micro-LED. The following figures illustrate the case where the self-emissive element is an organic light-emitting diode.

[0060] The non-display area NDA can be the area outside the display area DDA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100.

[0061] The sub-region SBA can extend from one side of the main region MA. The sub-region SBA can include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may house the display driver 200 and pad units connected to the circuit board 300. In some embodiments, the sub-region SBA may be omitted, and the display driver 200 and pad units may be located in the non-display area NDA.

[0062] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can be formed as an integrated circuit and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be located in a sub-region SBA and can overlap with the main region MA in the thickness direction by bending the sub-region SBA. As another example, the display driver 200 can be mounted on a circuit board 300.

[0063] The circuit board 300 can be attached to the pad units of the display panel 100 using an anisotropic conductive film. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0064] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be connected to the touch sensor layer TSL (see [link]). Figure 5 () for sensing and driving touch on display device 10.

[0065] Figure 5 This is a cross-sectional view of the display device 10 according to the embodiment.

[0066] refer to Figure 5 The display panel 100 may include a display layer DPL, a touch sensor layer TSL, and a color filter layer CFL. The display layer DPL may include a substrate SUB, a transistor layer TFTL, a display element layer EML, and a thin film encapsulation layer TFEL.

[0067] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate capable of being bent, folded, rolled, etc. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but the implementation is not limited thereto. In another embodiment, the substrate SUB can include a glass material or a metallic material. The main surface of the substrate SUB can be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0068] The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL can be located in the portion overlapping with the display area DDA, the non-display area NDA, and the sub-region SBA. The transistor layer TFTL may include multiple transistor TFTs (see [link to documentation]). Figure 9 ).

[0069] The display element layer (EML) may be located on the transistor layer (TFTL). The display element layer (EML) may be located in the portion overlapping with the display area (DDA). The display element layer (EML) may include, but is not limited to, at least one of organic light-emitting diodes (OLEDs) containing an organic light-emitting layer, quantum dot light-emitting diodes (LEDs) containing a quantum dot light-emitting layer, inorganic light-emitting diodes (LEDs) containing inorganic semiconductors, and micro LEDs.

[0070] A thin-film encapsulation layer (TFEL) may be located on the display element layer (EML). The TFEL may be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The TFEL may cover the top and side surfaces of the display element layer (EML) and protect it from external oxygen and moisture. The TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the display element layer (EML). In some embodiments, the TFEL may be omitted.

[0071] The touch sensor layer (TSL) can be located on the thin-film encapsulation layer (TFEL). The touch sensor layer (TSL) can be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The touch sensor layer (TSL) can sense the user's touch using mutual capacitance or self-capacitance. In some embodiments, the touch sensor layer (TSL) can be omitted.

[0072] The color filter layer (CFL) can be located on the touch sensor layer (TSL). The CFL can be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The CFL absorbs a portion of the light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the CFL prevents color distortion caused by the reflection of external light.

[0073] Since the color filter layer CFL is directly disposed on the touch sensor layer TSL, the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small. According to an embodiment, the color filter layer CFL can be omitted.

[0074] like Figure 5 As shown, the portion of the display panel 100 that overlaps with the sub-region SBA can be bent. When this portion of the display panel 100 is bent, the display driver 200, the circuit board 300, and the touch driver 400 can overlap with the main region MA on the third-party DR3.

[0075] When this portion of the display panel 100 is bent, the bending protection layer BPL can protect the structure located below it and overlapping with the sub-region SBA from bending stress.

[0076] Figure 6 This is a plan view of the display layer DPL of the display device 10 according to an embodiment. As used herein, "plan view" is a view of the display device 10 in the thickness direction (third direction DR3).

[0077] refer to Figure 6 The display layer DPL can include multiple pixels PX, multiple power lines VL connected to the pixels PX, multiple scan lines SL, multiple emission control lines EDL, and multiple data lines DL in the part that overlaps with the display area DDA.

[0078] Scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects with the first direction DR1. Scan lines SL can be arranged along the second direction DR2. Scan lines SL can sequentially supply scan signals to pixels PX.

[0079] The transmit control lines EDL can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The transmit control lines EDL can be arranged along the second direction DR2. The transmit control lines EDL can sequentially supply transmit signals to the pixel PX.

[0080] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to pixels PX. The data voltage determines the individual brightness of each pixel PX.

[0081] The power line VL may include a main power line VL1 and a sub-power line VL2. At least one of a first power voltage (high potential voltage) and a second power voltage (low potential voltage) can be transmitted to the sub-power line VL2 through the main power line VL1, which overlaps with the non-display area NDA. The main power line VL1 and the sub-power line VL2 can be collectively referred to as power line VL.

[0082] The non-display area NDA may surround the display area DDA. The non-display area NDA may include a scan driver 211 and a transmit control driver 213.

[0083] The scan driver 211 can be located outside the display area DDA or on the non-display area NDA. The scan driver 211 may include multiple drive transistors that generate gate signals based on gate control signals.

[0084] The transmit control driver 213 can be located on the other side of the display area DDA or on the other side of the non-display area NDA. The transmit control driver 213 may include multiple transmit control transistors that generate transmit signals based on transmit control signals.

[0085] The display layer DPL included in the embodiment may include a display driver 200 and a plurality of pad electrodes PD in the portion overlapping with the sub-region SBA. The pad electrodes PD may be spaced apart from each other in the first direction DR1 and may be connected to different lines respectively.

[0086] Figure 7 It is shown Figure 6 A layout diagram showing the arrangement of multiple pixels PX in the display area DDA.

[0087] refer to Figure 7 Each of the pixels PX in the embodiment may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 located in the portion overlapping with the display area DDA. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be spaced apart from each other.

[0088] The display panel 100 of the embodiment may include a non-emitting region NLA and an emitting region EA located in the portion overlapping with the pixel PX. The emitting region EA may be the portion from which the pixel PX emits light, and the non-emitting region NLA may be the portion from which it does not emit light.

[0089] The emission region EA may include a first emission region EA1, which is the emission region of the first sub-pixel SP1; a second emission region EA2, which is the emission region of the second sub-pixel SP2; and a third emission region EA3, which is the emission region of the third sub-pixel SP3.

[0090] In some embodiments, the emission region EA may have a quadrilateral planar shape (e.g., a strip structure). When the emission region EA has a strip structure, the first emission region EA1 and the second emission region EA2, as well as the first emission region EA1 and the third emission region EA3, may be adjacent to each other in a first direction DR1, and the second emission region EA2 and the third emission region EA3 may be adjacent to each other in a second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other. However, the embodiments are not limited to this, and in another embodiment, the emission region EA may also have a planar shape other than a quadrilateral shape, such as a hexagon, other polygons, a circle, an ellipse, or an irregular shape.

[0091] The first emission region EA1, the second emission region EA2, and the third emission region EA3 in this embodiment can emit light of different colors. For example, the first emission region EA1 can emit red light, the second emission region EA2 can emit green light, and the third emission region EA3 can emit blue light. However, the embodiment is not limited to this. According to the embodiment, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can also emit light of the same color.

[0092] The non-emitting region NLA may include a first non-emitting region NLA1 and a second non-emitting region NLA2. The first non-emitting region NLA1 may surround each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3, and may prevent color mixing of light emitted from each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3.

[0093] The second non-emissive region NLA2 may be surrounded by the emitting region EA. The second non-emissive region NLA2 may be located in the portion overlapping with the anode contact holes ACTH of the display panel 100. The placement of each anode contact hole ACTH may vary within the emitting region EA.

[0094] Figure 8 It is shown Figure 6 Another example and layout diagram of the arrangement of multiple pixels PX in the display area DDA.

[0095] refer to Figure 8The launch area EA can be configured as a pen tile with a diamond arrangement. ® The structure can be configured as a hexagonal structure with a hexagonal arrangement.

[0096] In some implementations, when the launch area EA has a PenTile ® In the case of a hexagonal or rectangular structure, each of the pixels PX may have a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4, and the emission region EA may include a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, a third emission region EA3 as the emission region of the third sub-pixel SP3, and a fourth emission region EA4 as the emission region of the fourth sub-pixel SP4.

[0097] In some implementations, when the launch area EA has a PenTile ® In the case of a hexagonal or rectangular structure, the first transmitting region EA1 and the third transmitting region EA3 can be adjacent to each other in the first direction DR1, and the second transmitting region EA2 and the fourth transmitting region EA4 can be adjacent to each other in the second direction DR2. Furthermore, the first transmitting region EA1 and the second transmitting region EA2 can be adjacent to each other in the first oblique direction DD1, and the second transmitting region EA2 and the third transmitting region EA3 can be adjacent to each other in the second oblique direction DD2. Additionally, the first transmitting region EA1 and the fourth transmitting region EA4 can be adjacent to each other in the second oblique direction DD2, and the third transmitting region EA3 and the fourth transmitting region EA4 can be adjacent to each other in the first oblique direction DD1. The first oblique direction DD1 can be the direction between the first direction DR1 and the second direction DR2 and is inclined at a 45-degree angle relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 can be a direction orthogonal to the first oblique direction DD1.

[0098] The non-emitting region NLA may include a first non-emitting region NLA1 and a second non-emitting region NLA2. The second non-emitting region NLA2 may be located in the portion overlapping with the anode contact hole ACTH. Redundant descriptions will be omitted.

[0099] Figure 9 It is along Figure 7 The example cross-sectional view of the display layer DPL, cut by line A1-A1'. Figure 9 The cross-sectional structure of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, which do not overlap with the anode contact hole ACTH, is shown in the portion that overlaps with the display area DDA of the display panel 100.

[0100] refer to Figure 9 The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a transistor TFT, a gate insulating layer GI, a first insulating layer ILD1, a capacitor electrode CPE, a second insulating layer ILD2, a first connection electrode CNE1, a first via layer VIA1, a second connection electrode CNE2, and a second via layer VIA2.

[0101] The first buffer layer BF1 may be located on the substrate SUB. The first buffer layer BF1 may include an inorganic layer that can prevent air or moisture penetration. For example, the first buffer layer BF1 may include multiple inorganic layers stacked alternately.

[0102] The bottom metal layer BML may be located on the first buffer layer BF1. Each of the bottom metal layers BML may include a conductive metal and may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0103] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic layer that can prevent the penetration of air or moisture. For example, the second buffer layer BF2 may include multiple inorganic layers stacked alternately.

[0104] The transistor TFT can be disposed on the second buffer layer BF2, and can be respectively formed into pixel circuits connected to multiple pixels. For example, each of the transistor TFTs can be a driving transistor or a switching transistor of the pixel circuit.

[0105] Each transistor TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE. The active layer ACT may be located on a second buffer layer BF2. The active layer ACT may overlap with the gate electrode GE on a third-direction DR3 and may be insulated from the gate electrode GE by a gate insulating layer GI. In a portion of the active layer ACT, the material of the active layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0106] The gate insulating layer GI can be located on the active layer ACT. The gate insulating layer GI can cover the active layer ACT and the second buffer layer BF2, and can insulate the active layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0107] The gate electrode GE may be located on the gate insulating layer GI. In a planar view, the gate electrode GE may overlap with the active layer ACT, with the gate insulating layer GI interposed between them. The gate electrode GE may include a conductive metal, and may each be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0108] The first insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second insulating layer ILD2.

[0109] The capacitor electrode CPE can be located on the first insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE on the third-direction DR3. The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0110] The second insulating layer ILD2 may cover the capacitor electrode CPE and the first insulating layer ILD1. The second insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second insulating layer ILD2 may be connected to the contact hole of the first insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0111] The first connection electrode CNE1 can be located on the second insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 can be inserted into a contact hole formed in the first insulating layer ILD1, the second insulating layer ILD2 and the gate insulating layer GI to contact the drain electrode DE of the transistor TFT.

[0112] The first via layer VIA1 may cover the first connecting electrode CNE1 and the second insulating layer ILD2. The first via layer VIA1 may planarize the structure beneath it. The first via layer VIA1 may include contact holes through which the second connecting electrode CNE2 passes.

[0113] The first through-hole layer VIA1 may include an organic insulating material. For example, the first through-hole layer VIA1 may include acrylic resin, polyimide, polyamide, benzocyclobutene, phenolic resin, or the like.

[0114] The second connecting electrode CNE2 may be located on the first via layer VIA1. The second connecting electrode CNE2 may be inserted into a contact hole formed in the first via layer VIA1 to contact the first connecting electrode CNE1. The second connecting electrode CNE2 may electrically connect the first connecting electrode CNE1 to the anode AE. The second via layer VIA2 may cover the second connecting electrode CNE2 and the first via layer VIA1.

[0115] The second through-pore layer VIA2 may include organic materials. For example, the second through-pore layer VIA2 may include acrylic resin, polyimide, polyamide, benzocyclobutene, phenolic resin, or the like.

[0116] Figure 10 Is with Figure 9 An enlarged cross-sectional view of the display element layer EML overlapping the first emission region EA1 in the image.

[0117] refer to Figure 9 and Figure 10 In this embodiment, the display element layer (EML) can be disposed on the transistor layer (TFTL). The display element layer (EML) may include a dam structure (BN), a pixel defining layer (PDL), a light-emitting element (LE), and an inorganic element layer (IO).

[0118] The dam structure BN of the embodiment can be disposed on the second through-hole layer VIA2 in the portion overlapping with the emission region EA. The dam structure BN may include a first dam layer BN1, a second dam layer BN2, and a third dam layer BN3. The first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 can be sequentially stacked on the third-direction DR3.

[0119] In this embodiment, the first dam layer BN1 can be located on the second perforated layer VIA2. The first dam layer BN1 can cover the entire surface of the second perforated layer VIA2.

[0120] The first diaphragm layer BN1 may include an etch-resistant conductive metal. For example, the first diaphragm layer BN1 may be titanium (Ti). The first diaphragm layer BN1 can assist in applying a low potential voltage to the cathode CE.

[0121] In this embodiment, the second dam layer BN2 can be located on the first dam layer BN1 to contact the first dam layer BN1. The second dam layer BN2 can be electrically connected to the first dam layer BN1. The second dam layer BN2 can assist in electrically connecting the first dam layer BN1 to the cathode CE. The second dam layer BN2 (which can be formed as multiple sheets of second dam layer BN2) can be located in the portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, and can be spaced apart from each other.

[0122] The second dam layer BN2 may include a metal with high electrical conductivity. For example, the second dam layer BN2 may include aluminum (Al).

[0123] In some embodiments, the second dam layer BN2 may include a first side surface 2c. The first side surface 2c of the second dam layer BN2 may be the surface facing the first non-emissive region NLA1.

[0124] In some embodiments, each of the first side surfaces 2c of the second dam layer BN2 can be divided into a first portion 2ca and a second portion 2cb based on its contact area. The first portion 2ca may be the portion that contacts the first auxiliary electrode AX1, and the second portion 2cb may be the portion that does not contact the first auxiliary electrode AX1. According to an embodiment, the second portion 2cb may contact the organic encapsulation layer TFE1, but the embodiment is not limited thereto. The third dam layer BN3 (which may be formed as multiple sheets of the third dam layer BN3) may be located in the portions that overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3, and may be spaced apart from each other.

[0125] In this embodiment, the third diaphragm layer BN3 can be located on the second diaphragm layer BN2. The third diaphragm layer BN3 can include a conductive metal with etch resistance. For example, the third diaphragm layer BN3 can be titanium (Ti).

[0126] The third dam layer BN3 may have a pointed tip that protrudes significantly more from the first side surface 2c of the second dam layer BN2 toward the first non-emitting region NLA1. In the process of manufacturing the display device 10, the third dam layer BN3 may have a lower etch rate than the second dam layer BN2. Therefore, the third dam layer BN3 may have a pointed tip that protrudes significantly more from the second dam layer BN2 in the first direction DR1. Thus, the first side surface 2c of the second dam layer BN2 and the pointed tip of the third dam layer BN3 may form an undercut. In other words, the dam structure BN of the embodiment may have an overhang structure.

[0127] Because the embankment structure BN in this embodiment includes a pointed tip (TIP) protruding toward the first non-emitting region NLA1, the light-emitting layer EL and the cathode CE can be formed on the embankment structure BN without using a fine metal mask during the manufacturing process of the display device 10. In other words, the light-emitting layer EL and the cathode CE overlapping the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 can be separated by the pointed tip (TIP) of the embankment structure BN. The manufacturing process will be described later.

[0128] In some implementations, the height of the second embankment layer BN2 may be higher than the height of the first embankment layer BN1 and the height of the third embankment layer BN3.

[0129] In this implementation, the pixel-defining layer PDL can be located on the embankment structure BN in the portion that overlaps with the emission region EA.

[0130] The pixel-defining layer (PDL) may include a first pixel-defining layer (PDL1) and a second pixel-defining layer (PDL2) stacked sequentially. The first pixel-defining layer (PDL1) and the second pixel-defining layer (PDL2) may be stacked sequentially on a third-direction DR3.

[0131] In this embodiment, the first pixel defining layer PDL1 can be located on the third dam layer BN3. The first pixel defining layer PDL1 can overlap with the tip TIP of the third dam layer BN3 on the third-direction DR3.

[0132] The first pixel limiting layer PDL1 can insulate the dam structure BN from the anode AE. Therefore, the first pixel limiting layer PDL1 can solve the short circuit between the dam structure BN and the anode AE, and also solve the driving failure of the light-emitting element LE.

[0133] The first pixel defining layer PDL1 may include an inorganic insulating material. For example, the first pixel defining layer PDL1 may include at least one of silicon nitride, silicon oxide, and silicon oxide nitride.

[0134] In this embodiment, the second pixel defining layer PDL2 can be located on the first pixel defining layer PDL1. The second pixel defining layer PDL2 can define the first opening OP1 and can expose the anode AE ​​in the portion overlapping with the first opening OP1 in a planar view. In other words, the second pixel defining layer PDL2 can surround the first opening OP1 and cover the edge of the anode AE. The second pixel defining layer PDL2 can overlap with the tip TIP of the third embankment layer BN3 on the third-direction DR3.

[0135] The second pixel defining layer PDL2 may include an inorganic insulating material. For example, the second pixel defining layer PDL2 may include at least one of silicon nitride, silicon oxide, and silicon oxide nitride.

[0136] In this embodiment, the light-emitting element LE can be located on the pixel defining layer PDL. The light-emitting element LE can overlap with the embankment structure BN on the third-direction DR3. In the display device 10 of this embodiment, since the light-emitting element LE is formed on the embankment structure BN, a high-resolution display device with a relatively narrow gap between the light-emitting elements LE can be realized.

[0137] The light-emitting element LE may include a first light-emitting element LE1 disposed in a first emission region EA1, a second light-emitting element LE2 disposed in a second emission region EA2, and a third light-emitting element LE3 disposed in a third emission region EA3. The first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may be spaced apart from each other.

[0138] The first light-emitting element LE1 may include a first anode AE1, a first light-emitting layer EL1, a first cathode CE1, and a first auxiliary electrode AX1. The second light-emitting element LE2 may include a second anode AE2, a second light-emitting layer EL2, a second cathode CE2, and a second auxiliary electrode AX2. The third light-emitting element LE3 may include a third anode AE3, a third light-emitting layer EL3, a third cathode CE3, and a third auxiliary electrode AX3.

[0139] The first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 can emit light of different colors. For example, the first light-emitting element LE1 can emit red light, the second light-emitting element LE2 can emit green light, and the third light-emitting element LE3 can emit blue light.

[0140] In this embodiment, the anode AE ​​can be located on the first pixel definition layer PDL1. The anode AE ​​can include a first anode AE1, a second anode AE2, and a third anode AE3. The first anode AE1 can be located in the portion overlapping with the first emission region EA1, the second anode AE2 can be located in the portion overlapping with the second emission region EA2, and the third anode AE3 can be located in the portion overlapping with the third emission region EA3.

[0141] The anode AE ​​can have a stacked structure of layers of materials with high work functions, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and reflective material layers such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), or mixtures thereof. For example, the anode AE ​​can have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, or ITO / Ag / ITO.

[0142] In this embodiment, the light-emitting layer EL can be located on the anode AE. The light-emitting layer EL can be an organic light-emitting layer made of organic material and can be formed on the anode AE ​​by a deposition process. The light-emitting layer EL can contact the anode AE ​​in the portion overlapping with the first opening OP1 in the planar view and can cover the entire second pixel defining layer PDL2.

[0143] The light-emitting layer EL may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3. The first light-emitting layer EL1 may be located in the portion overlapping with the first emission region EA1, the second light-emitting layer EL2 may be located in the portion overlapping with the second emission region EA2, and the third light-emitting layer EL3 may be located in the portion overlapping with the third emission region EA3.

[0144] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can emit light of different colors. For example, the first light-emitting layer EL1 can emit red light, the second light-emitting layer EL2 can emit green light, and the third light-emitting layer EL3 can emit blue light. However, the implementation is not limited to this.

[0145] In this embodiment, the cathode CE can be located on the light-emitting layer EL. The cathode CE can cover the entire light-emitting layer EL.

[0146] The cathode CE may include a transparent conductive material to transmit light generated from the light-emitting layer EL. For example, the cathode CE may include a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The cathode CE may also include a transparent metal oxide layer disposed on a material layer with a low work function.

[0147] The cathode CE may include a first cathode CE1, a second cathode CE2, and a third cathode CE3. The first cathode CE1 may be located in the portion overlapping with the first emission region EA1, the second cathode CE2 may be located in the portion overlapping with the second emission region EA2, and the third cathode CE3 may be located in the portion overlapping with the third emission region EA3.

[0148] The first cathode CE1, the second cathode CE2, and the third cathode CE3 can be spaced apart from each other. The first cathode CE1, the second cathode CE2, and the third cathode CE3 do not need to be directly connected, but can be electrically connected through the auxiliary electrode AX and the dam structure BN.

[0149] In this embodiment, the auxiliary electrode AX can be located on the cathode CE. The auxiliary electrode AX can cover the entire cathode CE.

[0150] The auxiliary electrode AX may include a transparent conductive material (TCO). For example, the auxiliary electrode AX may include indium zinc oxide (IZO).

[0151] The auxiliary electrode AX may include a first auxiliary electrode AX1, a second auxiliary electrode AX2, and a third auxiliary electrode AX3. The first auxiliary electrode AX1 may be located in the portion overlapping with the first emission region EA1, the second auxiliary electrode AX2 may be located in the portion overlapping with the second emission region EA2, and the third auxiliary electrode AX3 may be located in the portion overlapping with the third emission region EA3.

[0152] The first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3 can be spaced apart from each other. The first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3 do not need to be directly connected, but can be electrically connected through the dike structure BN. Specifically, each auxiliary electrode AX (e.g., the first auxiliary electrode AX1) can cover the entire tip TIP of the third dike layer BN3 and can contact the first side surface 2c of the second dike layer BN2. Therefore, the first auxiliary electrode AX1, the second auxiliary electrode AX2, and the third auxiliary electrode AX3 can be electrically connected to each other through the second dike layer BN2 and the first dike layer BN1.

[0153] Each auxiliary electrode AX (e.g., a first auxiliary electrode AX1) may be spaced apart from the first dam layer BN1 on the third-direction DR3. In other words, each auxiliary electrode AX may be spaced apart from the first dam layer BN1 on the third-direction DR3, with a cavity between them. The cavity formed between the auxiliary electrode AX and the first dam layer BN1 may be a portion in which the material forming the light-emitting layer EL and the material forming the cathode CE are temporarily positioned during the manufacturing process and then removed.

[0154] Since the display device 10 of the embodiment includes the cavity described above, it can be seen that in the process of manufacturing the display device 10, the light-emitting layer EL and the cathode CE are formed by deposition and etching processes without the use of a mask.

[0155] In this embodiment, the inorganic layer IO can be located on the light-emitting element LE. The inorganic layer IO can completely cover the light-emitting element LE and prevent oxygen or moisture from penetrating into the light-emitting element LE. The inorganic layer IO does not need to contact the dike structure BN.

[0156] The inorganic layer IO of a component may include an inorganic insulating material. For example, the inorganic layer IO of a component may include any one of silicon nitride, silicon oxide, and silicon oxide nitride.

[0157] The inorganic layer IO may include a first inorganic layer IO1, a second inorganic layer IO2, and a third inorganic layer IO3. The first inorganic layer IO1 may be disposed on a first light-emitting element LE1 in a first emission region EA1, the second inorganic layer IO2 may be disposed on a second light-emitting element LE2 in a second emission region EA2, and the third inorganic layer IO3 may be located on a third light-emitting element LE3 in a third emission region EA3. The first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3 may be spaced apart from each other in the portion overlapping with the non-emission region NLA.

[0158] In the accompanying drawings, the first element inorganic layer IO1, the second element inorganic layer IO2, and the third element inorganic layer IO3 appear to be formed on the same layer. However, in the process of manufacturing the display device 10, the first element inorganic layer IO1 can be formed after the first light-emitting element LE1, the second element inorganic layer IO2 can be formed after the second light-emitting element LE2, and the third element inorganic layer IO3 can be formed after the third light-emitting element LE3.

[0159] Each element inorganic layer IO (e.g., the first element inorganic layer IO1) may be spaced apart from the first embankment layer BN1 on the third-direction DR3, with a cavity between them. Redundant descriptions will be omitted.

[0160] The thin-film encapsulation layer TFEL in this embodiment can be located on the display element layer EML. The thin-film encapsulation layer TFEL may include an organic encapsulation layer TFE1 and an inorganic encapsulation layer TFE3.

[0161] In this embodiment, the organic encapsulation layer TFE1 can be located on the inorganic layer IO of the component. For example, the organic encapsulation layer TFE1 can contact and cover the entirety of the first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3.

[0162] The organic encapsulation layer TFE1 can planarize the steps formed according to the contour of the underlying structure. Furthermore, the organic encapsulation layer TFE1 can fill the cavity formed between the first embankment layer BN1 and the inorganic layer IO in the portion overlapping with the emitter region EA. According to an embodiment, the organic encapsulation layer TFE1 can be omitted.

[0163] The organic encapsulation layer TFE1 may include polymer-based materials. For example, the organic encapsulation layer TFE1 may include acrylic resin, silicone resin, epoxy resin, silicone acrylic resin, polyimide, polyethylene, etc.

[0164] In this embodiment, the inorganic encapsulation layer TFE3 can be located on top of the organic encapsulation layer TFE1. The inorganic encapsulation layer TFE3 can protect the underlying structure from moisture and oxygen. According to this embodiment, the inorganic encapsulation layer TFE3 can be omitted.

[0165] The inorganic encapsulation layer TFE3 may include inorganic insulating materials. For example, the inorganic encapsulation layer TFE3 may include any one of silicon nitride, silicon oxide, and silicon oxide nitride.

[0166] Figure 11 It is along Figure 7 The example cross-sectional view of the display layer DPL is taken by line A3-A3'. Figure 12 Is with Figure 11An enlarged cross-sectional view of the display element layer EML overlapping the first emission region EA1 in the image. Figure 11 The cross-sectional structure of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 overlapping with the anode contact hole ACTH of the display device 10 is shown. Common descriptions will be omitted below, and the structure of the display element layer EML overlapping with the anode contact hole ACTH will be described below.

[0167] refer to Figure 11 and Figure 12 In this embodiment, the anode contact hole ACTH can be defined to overlap with the second non-emitting region NLA2. Specifically, the anode contact hole ACTH can be located in the portion overlapping with the first opening OP1 defined by the second pixel defining layer PDL2. The anode contact hole ACTH can penetrate the second via layer VIA2. Therefore, the second connection electrode CNE2 overlapping with the anode contact hole ACTH can be exposed. The anode contact hole ACTH can assist in the electrical connection of the anode AE ​​of the display element layer EML to the transistor TFT of the transistor layer TFTL.

[0168] A portion of the dam structure BN included in the display element layer EML can be penetrated by the anode contact hole ACTH. Specifically, the portion of the first dam layer BN1 that overlaps with the first opening OP1 in the plan view can be penetrated by the anode contact hole ACTH, and the first dam layer BN1 can surround the anode contact hole ACTH. Furthermore, the portion of the second dam layer BN2 that overlaps with the first opening OP1 in the plan view can be penetrated by the anode contact hole ACTH, and the second dam layer BN2 can surround the anode contact hole ACTH. Additionally, the portion of the third dam layer BN3 that overlaps with the first opening OP1 in the plan view can be penetrated by the anode contact hole ACTH, and the third dam layer BN3 can surround the anode contact hole ACTH.

[0169] For example, if the anode contact hole ACTH is spaced apart from and formed separately from the dam structure BN in an area that does not overlap with the dam structure BN, the display device 10 may require a separate anode contact hole area, which may make it difficult to achieve high resolution.

[0170] In the display device 10 of this embodiment, since the anode contact hole ACTH is formed as a through-bar structure BN, the anode AE ​​and the transistor TFT can be electrically connected without a separate anode contact hole area. Therefore, the display device 10 of this embodiment can be applied to high-resolution electronic devices.

[0171] In some embodiments, the shapes of the dam structure BN facing the first non-emissive region NLA1 and the dam structure BN facing the anode contact hole ACTH can differ from each other. For example, the dam structure BN facing the first non-emissive region NLA1 can have a shape in which the tip TIP of the third dam layer BN3 protrudes significantly beyond the first side surface 2c of the second dam layer BN2. Conversely, the side surface 3d of the third dam layer BN3 facing the anode contact hole ACTH can be aligned with the second side surface 2d of the second dam layer BN2. This can be caused by simultaneously etching the second dam layer BN2 and the third dam layer BN3 to form the anode contact hole ACTH during the manufacturing process of the display device 10. The manufacturing process will be described later.

[0172] The first pixel defining layer PDL1, included in the display element layer EML, can cover the anode contact hole ACTH along its shape in the portion overlapping with the anode contact hole ACTH. The first pixel defining layer PDL1 can expose the second connection electrode CNE2 in the portion overlapping with the anode contact hole ACTH.

[0173] In some implementations, the first pixel defining layer PDL1 may contact and cover the second side surface 2d of the second dam layer BN2 and the side surface 3d of the third dam layer BN3.

[0174] As described above, the first pixel defining layer PDL1 can insulate the dam structure BN from the anode AE. Therefore, the dam structure BN can be spaced apart from the anode AE ​​on the third-direction DR3 in the portion overlapping with the anode AE, and the first pixel defining layer PDL1 is interposed between them.

[0175] Figure 13 yes Figure 12 An enlarged sectional view of the area "T" in the diagram.

[0176] refer to Figures 11 to 13 On the third-direction DR3, the first thickness H11 of the first pixel defining layer PDL1 that does not overlap with the anode contact hole ACTH of the embodiment can be greater than the second thickness H12 of the first pixel defining layer PDL1 that overlaps with the anode contact hole ACTH. This can be caused by a reduction in the step coverage characteristics of the deposited material, depending on the degree of recess of each anode contact hole ACTH on the third-direction DR3 or by the cone angle formed by each anode contact hole ACTH. For example, the second thickness H12 can be 30% or less of the first thickness H11. The aforementioned thicknesses can have the same meaning as height and / or width.

[0177] The anode AE ​​included in the display element layer EML can cover the anode contact hole ACTH along its shape in the portion overlapping with it. The anode AE ​​can contact the second connection electrode CNE2 in the portion overlapping with the anode contact hole ACTH. Therefore, the anode AE ​​can be electrically connected to the second connection electrode CNE2. As described above, the anode AE ​​can be electrically connected to the transistor TFT via the second connection electrode CNE2.

[0178] In some embodiments, the anode AE ​​may cover the second side surface 2d of the second dam layer BN2 and the side surface 3d of the third dam layer BN3 in the portion overlapping with the anode contact hole ACTH.

[0179] In an implementation, on the third-direction DR3, the first thickness H21 of each anode AE ​​(e.g., the first anode AE1) that does not overlap with the anode contact hole ACTH can be greater than the second thickness H22 of the anode AE ​​(e.g., the first anode AE1) that overlaps with the anode contact hole ACTH. For example, the second thickness H22 can be 30% or less of the first thickness H21. Other redundant descriptions will be omitted.

[0180] The third pixel defining layer PDL3, included in the display element layer EML, can be located in the portion overlapping with the emission region EA. Each second opening OP2 can be defined between the third pixel defining layer PDL3 and the second pixel defining layer PDL2 adjacent to the third pixel defining layer PDL3. Therefore, the anode AE ​​can be exposed in the portion overlapping with each second opening OP2, and can contact the light emitting layer EL on the third-direction DR3 in the portion overlapping with each second opening OP2.

[0181] The third pixel defining layer PDL3 can cover the anode contact hole ACTH along its shape in the portion overlapping with the anode contact hole ACTH. The third pixel defining layer PDL3 can contact and cover the entire anode AE ​​in the portion overlapping with the anode contact hole ACTH. The third pixel defining layer PDL3 can insulate the anode AE ​​from the cathode CE in the portion overlapping with the anode contact hole ACTH.

[0182] For example, if small particles form on the anode AE ​​in the portion overlapping with the anode contact hole ACTH, a short circuit may occur between the anode AE ​​and the cathode CE because the light-emitting layer EL and the cathode CE are formed to cover the small particles along their shape. Therefore, this could lead to a driving failure of the light-emitting element LE.

[0183] In the display device 10 of the embodiment, since the third pixel limiting layer PDL3 is provided between the anode AE ​​and the cathode CE in the portion overlapping with the anode contact hole ACTH, the short circuit between the anode AE ​​and the cathode CE and the driving failure of the light-emitting element LE can be solved.

[0184] In some implementations, the third pixel defining layer PDL3 may include the same material as the second pixel defining layer PDL2.

[0185] The light-emitting layer EL included in the display element layer EML can be located on the second pixel limiting layer PDL2 and the third pixel limiting layer PDL3, and can cover the entire second pixel limiting layer PDL2 and the third pixel limiting layer PDL3.

[0186] The emitting layer EL can cover the anode contact hole ACTH along its shape in the portion overlapping with it. The emitting layer EL can also cover the entire anode AE ​​in the portion overlapping with the anode contact hole ACTH. However, the emitting layer EL can be spaced apart from the anode AE ​​in the portion overlapping with the anode contact hole ACTH, with the third pixel defining layer PDL3 interposed between them, and can contact the anode AE ​​in the portion not overlapping with the anode contact hole ACTH.

[0187] Therefore, the light-emitting layer EL may not emit light in the portion that overlaps with the anode contact hole ACTH or the third pixel defining layer PDL3, and the portion that overlaps with the anode contact hole ACTH or the third pixel defining layer PDL3 may be defined as the second non-emitting region NLA2.

[0188] In some embodiments, on the third-direction DR3, the first thickness H31 of each light-emitting layer EL that does not overlap with the anode contact hole ACTH can be greater than the second thickness H32 of the light-emitting layer EL that overlaps with the anode contact hole ACTH. For example, the second thickness H32 can be 30% or less of the first thickness H31. Redundant descriptions will be omitted.

[0189] The cathode CE, included in the display element layer EML, can be located on the light-emitting layer EL. The cathode CE can cover the entire second pixel defining layer PDL2 and the third pixel defining layer PDL3. The cathode CE can cover the third pixel defining layer PDL3 along its shape in the portion overlapping with the anode contact hole ACTH. In the manufacturing process, the cathode CE can have a higher step coverage characteristic than the process for forming the light-emitting layer EL. Therefore, the cathode CE can contact and cover the entire light-emitting layer EL in the portion overlapping with the anode contact hole ACTH.

[0190] As described above, since the display device 10 of the embodiment includes a third pixel defining layer PDL3, the short circuit between the anode AE ​​and the cathode CE can be resolved during the process.

[0191] The auxiliary electrode AX included in the display element layer EML can be located on the light-emitting layer EL. The auxiliary electrode AX can cover the entire second pixel defining layer PDL2 and the third pixel defining layer PDL3. The auxiliary electrode AX can cover the third pixel defining layer PDL3 along its shape in the portion overlapping with the anode contact hole ACTH. The auxiliary electrode AX can cover the entire cathode CE in the portion overlapping with the anode contact hole ACTH. Other redundant descriptions will be omitted.

[0192] Figure 14 It is along Figure 7 Another embodiment and cross-sectional view of the display panel 100, taken by line A3-A3'. Figure 15 Is with Figure 14 An enlarged cross-sectional view of the display element layer EML overlapping the first emission region EA1 in the image.

[0193] refer to Figure 14 and Figure 15 The display element layer EML of the display device 10s may have a different shape than the display element layer EML of the display device 10, because the third pixel defining layer PDL3 includes organic material. A description of the common structure of the display device 10 and the display device 10s will be omitted, and the differences will be described below.

[0194] The third pixel defining layer PDL3 included in the display device 10s may be located in the portion overlapping with the emission region EA. The third pixel defining layer PDL3 may define each second opening OP2 together with the adjacent second pixel defining layer PDL2. The anode AE ​​may be exposed in the portion overlapping with each second opening OP2 and may contact the light emitting layer EL in the portion overlapping with each second opening OP2.

[0195] The third pixel defining layer PDL3 included in the display device 10s can cover the entire anode AE ​​in the portion overlapping with the anode contact hole ACTH. Furthermore, the third pixel defining layer PDL3 can flatten the step formed by the anode AE ​​in the portion overlapping with the anode contact hole ACTH.

[0196] The third pixel defining layer PDL3 included in the display device 10s may include an organic material. For example, the third pixel defining layer PDL3 may include a photosensitive material such as a polyamide resin, a polyimide resin, an acrylic resin, an epoxy resin, or a phenolic resin.

[0197] In the process of manufacturing the display device 10s, the third pixel definition layer PDL3 can be formed by a separate process after the second pixel definition layer PDL2 is formed.

[0198] In the display device 10s of the embodiment, since the third pixel defining layer PDL3 is formed between the anode AE ​​and the cathode CE in the portion overlapping with the anode contact hole ACTH, the short circuit between the anode AE ​​and the cathode CE can be resolved, and thus the driving failure of the light-emitting element LE can be resolved. Other redundant descriptions will be omitted.

[0199] The light-emitting layer EL included in the display device 10s can cover the entire anode AE ​​in the portion that overlaps with the anode contact hole ACTH. However, the light-emitting layer EL can be spaced apart from the anode AE ​​by a third pixel defining layer PDL3 interposed between them in the portion that overlaps with the anode contact hole ACTH, and can contact the anode AE ​​in the portion that does not overlap with the anode contact hole ACTH.

[0200] Therefore, the luminescent layer EL can be non-luminescent in the portion overlapping with the anode contact hole ACTH, and the portion overlapping with the anode contact hole ACTH can be defined as the second non-emitting region NLA2.

[0201] The cathode CE included in the display device 10s may be located on the second pixel defining layer PDL2 and the third pixel defining layer PDL3. The cathode CE may cover the entire second pixel defining layer PDL2 and the third pixel defining layer PDL3.

[0202] The auxiliary electrode AX included in the display device 10s can be located on the second pixel defining layer PDL2 and the third pixel defining layer PDL3. The auxiliary electrode AX can cover the entire second pixel defining layer PDL2 and the third pixel defining layer PDL3. Other redundant descriptions will be omitted.

[0203] Figures 16 to 25 The manufacturing process is shown sequentially. Figure 11 A cross-sectional view of the method for fabricating the display element layer EML. The process for fabricating the display element layer EML that overlaps with the anode contact hole ACTH will now be described in the order of formation of each layer.

[0204] refer to Figure 16 and Figure 17 A dam structure BN is formed on the second via layer VIA2 covering the second connecting electrode CNE2. The dam structure BN may cover the entire second via layer VIA2 and may include a first dam layer BN1, a second dam layer BN2 and a third dam layer BN3 stacked sequentially.

[0205] In the current process, the second dam layer BN2 and the third dam layer BN3 can be made of different materials. For example, the third dam layer BN3 can be made of a material that has greater etching resistance than the second dam layer BN2 in the same etching process. Redundant descriptions will be omitted.

[0206] Next, after forming multiple photoresist PRs on the third diaphragm layer BN3, the photoresist PRs are used as a mask to perform the first etching process. For example, the first etching process can be performed as a dry etching process.

[0207] In the current process, the dam structure BN that does not overlap with the photoresist PR can be removed. Therefore, the anode contact hole ACTH can be formed. The side surfaces of the second via layer VIA2, the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 facing the anode contact hole ACTH can be positioned aligned with each other. In the current process, the second connecting electrode CNE2 can be exposed in the portion overlapping with the anode contact hole ACTH. The angle formed by each second connecting electrode CNE2 and each anode contact hole ACTH can vary depending on the implementation.

[0208] Next, refer to Figure 18 A first pixel defining layer PDL1 is formed on the third dam layer BN3. In the current process, the first pixel defining layer PDL1 can cover the entire side surface of the second via layer VIA2, the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 facing the anode contact hole ACTH.

[0209] In the current process, the first pixel defining layer PDL1 can expose the second connection electrode CNE2 in the portion overlapping with the anode contact hole ACTH. For example, the first pixel defining layer PDL1 can be formed to cover the second connection electrode CNE2, and the portion of the first pixel defining layer PDL1 overlapping with the second connection electrode CNE2 can then be removed by a subsequent etching process. Alternatively, a mask can be used to form the first pixel defining layer PDL1 to expose the portion overlapping with the second connection electrode CNE2.

[0210] In the current process, on the third-direction DR3, the second thickness H12 of the first pixel defining layer PDL1 overlapping with the anode contact hole ACTH (see...) Figure 13 The thickness H11 of the first pixel-defining layer PDL1, which does not overlap with the anode contact hole ACTH, can be smaller than the first thickness H11 (see...). Figure 13 This can be caused by a change in the step coverage characteristics of the process for forming the first pixel-defining layer PDL1 based on the contour formed by the anode contact hole ACTH. (The above is in...) Figure 13 Other descriptions are provided and therefore will be omitted.

[0211] Next, an anode AE ​​is formed on the first pixel defining layer PDL1. Multiple anode AEs can be formed, and the multiple anode AEs can contact the second connecting electrode CNE2 in the portion overlapping with the anode contact hole ACTH.

[0212] The anode AE ​​may include a first anode AE1, a second anode AE2, and a third anode AE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be spaced apart from each other.

[0213] Next, a second pixel-defining layer PDL2 is formed to cover the anode AE. The second pixel-defining layer PDL2 can be formed on the entire surface and can cover the first pixel-defining layer PDL1 and the anode AE ​​along the contour formed by the first pixel-defining layer PDL1 and the anode AE.

[0214] In the current process, on the third-direction DR3, the second thickness H22 of the anode AE ​​overlapping with the anode contact hole ACTH (see...) Figure 13 The thickness H21 of the anode AE, which does not overlap with the anode contact hole ACTH, can be less than the first thickness H21 (see [reference]). Figure 13 This can be caused by changes in the step coverage characteristics of the process used to form the anode AE ​​based on the profile formed by the anode contact hole ACTH. (The above is in...) Figure 13 Other descriptions are provided and therefore will be omitted.

[0215] refer to Figures 19 to 22 Multiple photoresist PRs are formed on the second pixel defining layer PDL2. In the current process, the photoresist PRs can be formed to overlap with the edge of the anode AE ​​and the anode contact hole ACTH.

[0216] Next, a second etching process is performed using photoresist (PR) as a mask. For example, the second etching process can be performed as a dry etching process.

[0217] In the current process, the portions of the pixel-defining layer PDL, the second barrier layer BN2, and the third barrier layer BN3 that do not overlap with the photoresist PR can be removed. Therefore, the pixel-defining layer PDL can be formed as a first pixel-defining layer PDL1, a second pixel-defining layer PDL2, and a third pixel-defining layer PDL3.

[0218] As described above, the first pixel defining layer PDL1 prevents the dam structure BN and the anode AE ​​from contacting each other. Furthermore, the second pixel defining layer PDL2 defines a first opening OP1 that overlaps with the emission region EA and can surround the edge of the anode AE. Additionally, the third pixel defining layer PDL3 can be located in the portion overlapping with the anode contact hole ACTH and can define each second opening OP2 together with the adjacent second pixel defining layer PDL2. The anode AE ​​can be exposed in the portion overlapping each second opening OP2.

[0219] In the current process, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 can be formed by a single process. Therefore, the display device 10 of the embodiment can be easily manufactured.

[0220] Next, after forming multiple photoresist layers (PRs) to cover the entire second pixel definition layer (PDL2) and the third pixel definition layer (PDL3), a third etching process is performed. For example, the third etching process can be performed as a wet etching process.

[0221] In current processes, the second and third diaphragm layers BN2 and BN3, comprising different metallic materials, can have different etching rates. Specifically, in the same etching process, the third diaphragm layer BN3 can have higher etching resistance than the second diaphragm layer BN2. In other words, the second diaphragm layer BN2 can comprise a material with a higher etching rate than the third diaphragm layer BN3 in the same etching process. Therefore, the third diaphragm layer BN3 can comprise a tip TIP that protrudes significantly beyond the first side surface 2c of the second diaphragm layer BN2 in the first direction DR1.

[0222] In the current process, the first pixel-defining layer PDL1 and the second pixel-defining layer PDL2 can overlap with the tip TIP of the third embankment layer BN3 on the third-direction DR3.

[0223] Next, refer to Figures 23 to 25 The first light-emitting layer EL1, the first cathode CE1 and the first auxiliary electrode AX1 are deposited on the first anode AE1 to form the first light-emitting element LE1.

[0224] In the current process, the formation of the first light-emitting layer EL1 can be performed using a thermal deposition process. In the current process, the material forming the first light-emitting layer EL1 can be formed not only on the first anode AE1, but also on the second anode AE2, the third anode AE3, and the first diaphragm layer BN1.

[0225] In the display device 10 of the embodiment, since the third diaphragm layer BN3 includes a pointed tip, the material of the first light-emitting layer EL1 formed on the first anode AE1 can be spaced apart from the materials of the first light-emitting layer EL1 formed on the second anode AE2, the third anode AE3, and the first diaphragm layer BN1. In other words, in the display device 10, since the third diaphragm layer BN3 includes a pointed tip, the light-emitting layers EL that are spaced apart from each other can be formed on the first anode AE1, the second anode AE2, and the third anode AE3 respectively without using a fine metal mask.

[0226] In current processes, the formation of the first cathode CE1 can be performed using either thermal deposition or sputtering. The process for forming the first cathode CE1 can exhibit higher step coverage characteristics than the process for forming the first light-emitting layer EL1. Therefore, the first cathode CE1 can completely cover the first light-emitting layer EL1.

[0227] In the current process, the material forming the first cathode CE1 can be formed not only on the first anode AE1, but also on the second anode AE2, the third anode AE3 and the first dam layer BN1.

[0228] In the display device 10 of this embodiment, since the third diaphragm layer BN3 includes a tip, the material of the first cathode CE1 formed on the first anode AE1 can be spaced apart from the materials of the second anode AE2, the third anode AE3, and the first diaphragm layer BN1. In other words, in the display device 10, since the third diaphragm layer BN3 includes a tip, the cathodes CE, which are spaced apart from each other, can be formed on the first anode AE1, the second anode AE2, and the third anode AE3 respectively without using a fine metal mask.

[0229] In the current process, the first auxiliary electrode AX1 can be formed by sputtering. The process of forming the first auxiliary electrode AX1 can have higher step coverage characteristics than the process of forming the first cathode CE1. Therefore, the first auxiliary electrode AX1 can cover the entire first cathode CE1.

[0230] In the current process, the material forming the first auxiliary electrode AX1 can be formed not only on the first anode AE1, but also on the second anode AE2, the third anode AE3 and the first dam layer BN1.

[0231] In the display device 10 of this embodiment, since the third dam layer BN3 includes a tip, the material of the first auxiliary electrode AX1 formed on the first anode AE1 can be spaced apart from the materials of the second anode AE2, the third anode AE3, and the first dam layer BN1. In other words, in the display device 10, since the third dam layer BN3 includes a tip, the auxiliary electrodes AX1 spaced apart from each other can be formed on the first anode AE1, the second anode AE2, and the third anode AE3 respectively without using a fine metal mask.

[0232] Next, an inorganic layer IO is formed on the first auxiliary electrode AX1. The inorganic layer IO can cover the underlying structure with a uniform thickness along the contour of the underlying structure.

[0233] Next, photoresist PR is formed in the portion overlapping with the first anode AE1 and in the area surrounding the first anode AE1, and the photoresist PR is used as a mask to perform the fourth etching process.

[0234] In the current process, the materials forming the first light-emitting layer EL1, the first cathode CE1, the first auxiliary electrode AX1, and the element inorganic layer IO in the portion that does not overlap with the photoresist PR can all be removed in one step. Through this process, the second anode AE2 and the third anode AE3 can be exposed again, and the material forming the element inorganic layer IO can be formed as the first element inorganic layer IO1.

[0235] In the current process, since the display device 10 of the embodiment includes a third pixel defining layer PDL3 in the portion overlapping with the anode contact hole ACTH, the short circuit between the anode AE ​​and the cathode CE can be resolved. Redundant descriptions will be omitted.

[0236] In the current process, the cavity can be formed on the third-direction DR3 between the first element inorganic layer IO1 and the first dam layer BN1. In other words, the cavity can be formed on the third-direction DR3 between the first auxiliary electrode AX1 and the first dam layer BN1. The cavity can be formed by removing the material temporarily positioned on the first dam layer BN1 to form the first light-emitting layer EL1 and the material to form the first cathode CE1.

[0237] In the current process, the first auxiliary electrode AX1 can contact and cover the first side surface 2c of the second dam layer BN2. Therefore, the first cathode CE1 can be electrically connected to the second dam layer BN2 through the first auxiliary electrode AX1. As described above, the second dam layer BN2 can be electrically connected to the first dam layer BN1.

[0238] Next, the same process is repeated to form the second light-emitting layer EL2, the second cathode CE2, and the second auxiliary electrode AX2 on the second anode AE2. Thus, the second light-emitting element LE2 and the second element inorganic layer IO2 are formed. Furthermore, the third light-emitting layer EL3, the third cathode CE3, and the third auxiliary electrode AX3 are formed on the third anode AE3 to form the third light-emitting element LE3 and the third element inorganic layer IO3. Therefore, it is possible to form... Figure 11 The EML layer of the display element is shown overlapping with the ACTH anode contact hole. Redundant descriptions will be omitted.

[0239] The display device according to one embodiment of the present disclosure can be applied to various electronic devices. The electronic device according to one embodiment of the present disclosure includes the display device described above, and may also include modules or devices with additional functions in addition to the display device.

[0240] Figure 26 This is a block diagram of an electronic device 1 according to one embodiment of the present disclosure.

[0241] refer to Figure 26 An electronic device 1 according to one embodiment of the present disclosure may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0242] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0243] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0244] The power module 14 may include a power supply module such as a power adapter or battery, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0245] At least one of the components of an electronic device 1 according to one embodiment of the present disclosure may be included in a display device 10 according to an embodiment of the present disclosure. Furthermore, some modules that are functionally included in a single module may be included in the display device 10, while other modules may be disposed separately from the display device 10. For example, the display device 10 may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed as other devices within the electronic device 1 besides the display device 10.

[0246] Figure 27 This is a schematic diagram of an electronic device 1 according to various embodiments of the present disclosure.

[0247] refer to Figure 27 The various electronic devices 1 of the display device 10 according to the embodiments of the present disclosure may include not only image display electronic devices such as smartphones 1_1a, tablet PCs (personal computers) 1_1b, laptop computers 1_1c, televisions 1_1d and desktop monitors 1_1e, but also wearable electronic devices including display modules 11, such as smart glasses 1_2a, head-mounted displays 1_2b and smartwatches 1_2c, as well as in-vehicle electronic devices 1_3 including display modules 11, such as CID (central information display) and interior mirror displays arranged on the dashboard and center console of a car.

[0248] According to the display device and the method of manufacturing the display device according to the embodiment, high-resolution images can be provided and short circuits between the anode and cathode can be resolved.

[0249] However, the effects of this disclosure are not limited to those set forth herein. The above and other effects of this disclosure will become more apparent to those skilled in the art upon reference to the claims.

[0250] This invention should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0251] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the invention without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device comprising: a substrate defining an emission area and a non-emission area surrounding the emission area; a bank structure on the substrate in the emission area and including a tip projecting toward the non-emission area; an anode contact hole penetrating the bank structure; an anode on the bank structure and electrically connected to a transistor on the substrate through the anode contact hole; a pixel-defining layer on the anode; and a light-emitting layer on the pixel-defining layer, wherein the light-emitting layer is spaced apart from the anode in a plan view in a portion overlapping the anode contact hole, the pixel-defining layer is between the light-emitting layer and the anode, and the light-emitting layer contacts the anode in the plan view in a portion not overlapping the anode contact hole. the bank structure includes:

2. The display device according to claim 1, wherein a first bank layer; a second bank layer on the first bank layer; and a third bank layer having the tip, the tip projecting more toward the non-emission area than a first side surface of the second bank layer facing the non-emission area. the second bank layer and the third bank layer surround the anode contact hole.

3. The display device according to claim 2, wherein a shape of a side surface of the bank structure facing the anode contact hole is different from a shape of a side surface of the bank structure facing the non-emission area.

4. The display device according to claim 3, wherein a second side surface of the second bank layer facing the anode contact hole is aligned with a third side surface of the third bank layer facing the anode contact hole.

5. The display device of claim 4, wherein, the pixel-defining layer includes:

6. The display device according to claim 2, wherein a first pixel-defining layer between the bank structure and the anode; a second pixel-defining layer covering an edge of the anode and overlapping the emission area to define a first opening; and a third pixel-defining layer overlapping the anode contact hole and between the light-emitting layer and the anode. a second opening is defined between the third pixel-defining layer and the second pixel-defining layer in a direction parallel to a major surface of the substrate.

7. The display device of claim 6, wherein, the light-emitting layer contacts the anode in the plan view in a portion overlapping the second opening.

8. The display device of claim 7, wherein, the first pixel-defining layer and the second pixel-defining layer overlap the tip of the third bank layer in a direction perpendicular to the major surface of the substrate.

9. The display device of claim 6, wherein, the second pixel-defining layer and the third pixel-defining layer include the same material.

10. The display device according to claim 6, wherein 11. The display device according to claim 2, further comprising: a first cathode on the light-emitting layer; a first auxiliary electrode on the first cathode and contacting the first side surface of the second bank layer; and a first element inorganic layer on the first auxiliary electrode. the first cathode does not contact the first side surface of the second bank layer, and is electrically connected to the second bank layer through the first auxiliary electrode. the first auxiliary electrode is spaced apart from the first bank layer in a direction perpendicular to a major surface of the substrate, and a cavity is between the first auxiliary electrode and the first bank layer.

12. The display device of claim 11, wherein, 14. The display device according to claim 11, further comprising:

13. The display device of claim 11, wherein, a second cathode spaced apart from the first cathode in a portion overlapping the non-emission area; ​ ​ a second auxiliary electrode located over the second cathode and spaced apart from the first auxiliary electrode; and a second element inorganic layer located over the second auxiliary electrode and spaced apart from the first element inorganic layer, wherein the first auxiliary electrode and the second auxiliary electrode are electrically connected.

15. The display device according to claim 1, further comprising: a connection electrode located between the substrate and the bank structure and electrically connected to the transistor; and a via layer covering the connection electrode, wherein the anode contact hole penetrates the via layer, and the anode is electrically connected to the transistor through the connection electrode.

16. The display device of claim 6, wherein, The second pixel-defining layer includes an inorganic material, and the third pixel-defining layer includes an organic material.

17. A method of manufacturing a display device, the method comprising: forming a bank structure having an undercut shape over a substrate in an emission region; forming an anode contact hole that penetrates the bank structure and exposes a connection electrode; forming an anode located over the bank structure and contacting the connection electrode through the anode contact hole; and forming a pixel-defining layer over the anode, and forming a light-emitting layer and a cathode over the pixel-defining layer, wherein the anode and the light-emitting layer are separated by the pixel-defining layer in a portion overlapping the anode contact hole.

18. The method of claim 17, wherein, The bank structure includes a first bank layer, a second bank layer, and a third bank layer, the second bank layer and the third bank layer include different metal materials from each other, and in forming the anode contact hole, the anode contact hole is formed by simultaneously removing a portion of each of the first bank layer, the second bank layer, and the third bank layer.

19. The method of claim 18, wherein, In forming the light-emitting layer and the cathode, the light-emitting layer and the cathode are formed by a deposition process and an etching process without a fine metal mask.

20. An electronic device comprising: at least one display device including a substrate defining an emission region and a non-emission region; a display device housing accommodating the at least one display device therein; and an optical member configured to magnify an image displayed by the at least one display device or to convert an optical path, wherein the at least one display device further comprises: a bank structure located over the substrate in the emission region and including a tip projecting toward the non-emission region; an anode contact hole penetrating the bank structure; an anode located over the bank structure and electrically connected to a transistor located on the substrate through the anode contact hole; a pixel-defining layer located over the anode; and a light-emitting layer located over the pixel-defining layer, wherein the light-emitting layer is spaced apart from the anode in a portion overlapping the anode contact hole in a plan view, the pixel-defining layer is between the light-emitting layer and the anode, and the light-emitting layer contacts the anode in a portion not overlapping the anode contact hole in the plan view.

Images