Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes a substrate including a display area and a peripheral area adjacent to the display area; a first electrode disposed on the substrate in the display area; an auxiliary electrode disposed on the substrate in the display area and spaced apart from the first electrode; a pixel defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the auxiliary electrode; a spacer disposed on the pixel defining layer and separating the electrode layer into second electrodes spaced apart from each other in the display area; and an organic film pattern disposed between the pixel defining layer and the spacer in the display area and the peripheral area, and overlapping with at least a portion of the spacer in a plan view in the display area and the peripheral area.

Description

Technical Field

[0001] This disclosure generally relates to display devices that provide visual information and electronic devices that include display devices. Background Technology

[0002] With the development of information technology, the importance of display devices, which serve as the connection medium between users and information, has become increasingly apparent. For example, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), plasma display panels (PDPs), or quantum dot displays is increasing.

[0003] The display device includes light-emitting elements and pixel driving circuitry for driving the light-emitting elements. The light-emitting element may include a pixel electrode, an intermediate layer disposed on the pixel electrode, and a counter electrode disposed on the intermediate layer. The intermediate layer may be provided commonly for multiple light-emitting elements. In this case, when current is supplied to one light-emitting element, a problem may arise where the current is also supplied to other adjacent light-emitting elements through the intermediate layer commonly provided for multiple light-emitting elements, leading to a degradation of the color purity of the display device. To solve this problem, the display device may further include a separator that separates (or disconnects) the intermediate layer. Summary of the Invention

[0004] The embodiments provide a display device in which the phenomenon of scratching (i.e., pressing) of the mask used in the process of forming the light-emitting element is suppressed.

[0005] The embodiments provide an electronic device including a display device.

[0006] A display device according to embodiments of the present disclosure may include: a substrate including a display area and a peripheral area adjacent to the display area; a first electrode disposed in the display area and on the substrate; an auxiliary electrode disposed in the display area and on the substrate, and spaced apart from the first electrode; a pixel defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the auxiliary electrode; a separator disposed on the pixel defining layer and separating the electrode layer into a plurality of second electrodes spaced apart from each other in the display area; and an organic film pattern disposed between the pixel defining layer and the separator in the display area and the peripheral area, and overlapping at least a portion of the separator in a plan view in the display area and the peripheral area.

[0007] In an embodiment, the separator may include: a first portion that overlaps with the organic film pattern in a plan view; and a second portion that is spaced apart from the first portion and does not overlap with the organic film pattern in a plan view.

[0008] In one embodiment, the horizontal height of the upper surface of the first part of the separator may be higher than the horizontal height of the upper surface of the second part of the separator.

[0009] In one embodiment, the first portion of the separator may be covered with an organic film pattern in the display area. A first side surface of the first portion of the separator and a second side surface opposite to the first side surface may contact the pixel defining layer in the display area.

[0010] In an embodiment, the separator may include: a first extension extending in a first direction; a second extension extending in a second direction intersecting the first direction; and an intersection portion where the first and second extensions intersect. The organic film pattern may overlap with the intersection portion of the separator in a planar view.

[0011] In the embodiments, the organic film pattern and pixel defining layer may include different materials.

[0012] In one embodiment, the cross-sectional shape of a portion of the separator may be asymmetrical in the peripheral region.

[0013] In one embodiment, in the peripheral region, the organic film pattern may overlap with the first side surface of that portion of the separator in a plan view.

[0014] In one embodiment, the first side surface of this portion of the separator may contact the organic film pattern in the peripheral area. The second side surface of this portion of the separator, opposite to the first side surface, may contact the pixel defining layer in the peripheral area.

[0015] In one embodiment, the display device may further include a connecting pattern disposed on the auxiliary electrode and the pixel defining layer, and electrically connected to the auxiliary electrode. In a plan view, the separator may overlap with the connecting pattern.

[0016] In one embodiment, a portion of the connecting pattern may be arranged in the display area along the outline of the pixel-defining layer and the organic film pattern.

[0017] In this embodiment, the connecting pattern can be arranged in the peripheral area, on the pixel defining layer. The cross-sectional shape of a portion of the separator may be asymmetrical in the peripheral area. A first side surface of this portion of the separator may contact the organic film pattern in the peripheral area. A second side surface of this portion of the separator, opposite to the first side surface, may contact the connecting pattern in the peripheral area.

[0018] In one embodiment, in the peripheral region, the organic film pattern may overlap with the entire region of the separator in a planar view.

[0019] In an embodiment, the display area may include a first emitting area to a third emitting area from which light is emitted, and in a plan view, a separator may surround at least a portion of each of the first to third emitting areas.

[0020] A display device according to embodiments of the present disclosure may include: a substrate including a display area and a peripheral area adjacent to the display area; a first electrode disposed in the display area and on the substrate; an auxiliary electrode disposed in the peripheral area and on the substrate; a pixel defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the auxiliary electrode; a separator disposed on the pixel defining layer and separating the electrode layer into a second electrode disposed in the display area and a dummy electrode electrically connected to the auxiliary electrode and disposed in the peripheral area; a connection pattern disposed between the pixel defining layer and the separator and electrically connecting the second electrode and the dummy electrode; and an organic film pattern disposed between the pixel defining layer and the connection pattern and overlapping at least a portion of the separator in a plan view.

[0021] In an embodiment, the separator may include: a first portion that overlaps with the organic film pattern in a plan view; and a second portion that is spaced apart from the first portion and does not overlap with the organic film pattern in a plan view.

[0022] In one embodiment, the horizontal height of the upper surface of the first part of the separator may be higher than the horizontal height of the upper surface of the second part of the separator.

[0023] In one embodiment, the first side surface of the separator and the second side surface opposite to the first side surface can contact the connecting pattern.

[0024] In one embodiment, a portion of the connecting pattern may be arranged along the contours of the pixel-defining layer and the organic film pattern.

[0025] In an embodiment, in a plan view, each of the second electrode and the dummy electrode can contact the connection pattern in an area overlapping with the separator.

[0026] In one embodiment, the display device may further include an auxiliary connection electrode disposed in the peripheral area, on the auxiliary electrode, and electrically connected to the auxiliary electrode. The auxiliary connection electrode may contact a dummy electrode in the peripheral area.

[0027] A display device according to embodiments of the present disclosure may include: a substrate including a display area and a peripheral area adjacent to the display area; a pixel driving circuit disposed on the substrate and including transistors; a first electrode disposed in the display area and on the substrate; a connecting electrode disposed in the display area and on the substrate, spaced apart from the first electrode and electrically connected to the pixel driving circuit; a pixel defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the connecting electrode; a separator disposed on the pixel defining layer and separating the electrode layer into a plurality of second electrodes spaced apart from each other in the display area; and an organic film pattern disposed between the pixel defining layer and the separator in the display area and the peripheral area, and overlapping at least a portion of the separator in a plan view in the display area and the peripheral area.

[0028] In an embodiment, the separator may include: a first portion that overlaps with the organic film pattern in a plan view; and a second portion that is spaced apart from the first portion and does not overlap with the organic film pattern in a plan view.

[0029] In one embodiment, the horizontal height of the upper surface of the first part of the separator may be higher than the horizontal height of the upper surface of the second part of the separator.

[0030] In one embodiment, the first portion of the separator may be covered with an organic film pattern in the display area. A first side surface of the first portion of the separator and a second side surface opposite to the first side surface may contact the pixel defining layer in the display area.

[0031] In one embodiment, the separator may include: a first extension extending in a first direction; a second extension extending in a second direction intersecting the first direction; and an intersection portion where the first and second extensions intersect. In a plan view, the organic film pattern may overlap with the intersection portion of the separator.

[0032] In the embodiments, the organic film pattern and pixel defining layer may include different materials.

[0033] In one embodiment, the cross-sectional shape of a portion of the separator may be asymmetrical in the peripheral region.

[0034] In one embodiment, in the peripheral region, the organic film pattern may overlap with the first side surface of that portion of the separator in a plan view.

[0035] In one embodiment, the first side surface of this portion of the separator may contact the organic film pattern in the peripheral area. The second side surface of this portion of the separator, opposite to the first side surface, may contact the pixel defining layer in the peripheral area.

[0036] In an embodiment, the display device may further include: a connecting pattern disposed on the connecting electrode and the pixel defining layer, and electrically connected to the connecting electrode. In a plan view, the spacer may overlap with the connecting pattern.

[0037] In one embodiment, the connection pattern may expose at least a portion of the organic film pattern in the display area.

[0038] In this embodiment, the connecting pattern can be arranged in the peripheral area, on the pixel defining layer. The cross-sectional shape of a portion of the separator may be asymmetrical in the peripheral area. A first side surface of this portion of the separator may contact the organic film pattern in the peripheral area. A second side surface of this portion of the separator, opposite to the first side surface, may contact the connecting pattern in the peripheral area.

[0039] In one embodiment, in the peripheral region, the organic film pattern may overlap with the entire region of the separator in a planar view.

[0040] In an embodiment, the display area may include a first emitting area to a third emitting area from which it emits light, and in a plan view, the separator may completely surround each of the first to third emitting areas.

[0041] An electronic device according to embodiments of the present disclosure may include: a display device including pixels; and a processor that transmits image data signals and input control signals to the display device and is communicatively connected to the display device. The display device may include: a substrate including a display area and a peripheral area adjacent to the display area; a first electrode disposed in the display area and on the substrate; an auxiliary electrode disposed in the display area and on the substrate, and spaced apart from the first electrode; a pixel defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the auxiliary electrode; a separator disposed on the pixel defining layer and separating the electrode layer into a plurality of second electrodes spaced apart from each other in the display area; and an organic film pattern disposed between the pixel defining layer and the separator in the display area and the peripheral area, and overlapping at least a portion of the separator in a plan view in the display area and the peripheral area.

[0042] An electronic device according to embodiments of the present disclosure may include: a display device including pixels; and a processor that transmits image data signals and input control signals to the display device and is communicatively connected to the display device. The display device may include: a substrate including a display area and a peripheral area adjacent to the display area; a pixel driving circuit disposed on the substrate and including transistors; a first electrode disposed in the display area and on the substrate; a connecting electrode disposed in the display area and on the substrate, spaced apart from the first electrode and electrically connected to the pixel driving circuit; a pixel defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the connecting electrode; a separator disposed on the pixel defining layer and separating the electrode layer into a plurality of second electrodes spaced apart from each other in the display area; and an organic film pattern disposed between the pixel defining layer and the separator in the display area and the peripheral area, and overlapping at least a portion of the separator in a plan view in the display area and the peripheral area.

[0043] A display device according to embodiments of the present disclosure may include: a separator disposed in a display area on a pixel defining layer, and separating an electrode layer into a plurality of second electrodes spaced apart from each other; and an organic film pattern disposed between the pixel defining layer and the separator, and overlapping at least a portion of the separator in a planar view in the display area. The separator may include: a first portion overlapping the organic film pattern in a planar view; and a second portion spaced apart from the first portion and not overlapping the organic film pattern in a planar view.

[0044] The upper surface of the first part of the separator can be at a higher level than the upper surface of the second part of the separator. Accordingly, the mask used in the process of forming the light-emitting element (e.g., an intermediate layer) can contact the first part of the separator but not the second part. As a result, the phenomenon of mask pressing that may occur when the area of ​​the separator in contact with the mask is large can be suppressed.

[0045] An organic film pattern can be arranged in the peripheral region between the pixel defining layer and the separator, and can overlap with at least a portion of the separator in a planar view within the peripheral region. The cross-sectional shape of a portion of the separator can be asymmetrical in the peripheral region. For example, the first side surface of this portion of the separator that contacts the organic film pattern may not have a reverse tapered slope, and the second side surface opposite the first side surface that does not contact the organic film pattern may have a reverse tapered slope. Because the first side surface of the separator does not have a reverse tapered slope, the electrode layer in the peripheral region can be formed as an extended layer without being broken. Attached Figure Description

[0046] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0047] Figure 1A This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0048] Figure 1B This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0049] Figure 2 The illustration includes Figure 1A and Figure 1B A schematic diagram of the circuit structure of a pixel in a display device.

[0050] Figure 3 It is a diagram. Figure 1A and Figure 1B A floor plan of a portion of the display device area.

[0051] Figure 4 It is a diagram. Figure 3 An enlarged plan view of one of the unit emission regions in the unit emission region.

[0052] Figure 5 It is along Figure 4 A schematic cross-sectional view taken from line II-II'.

[0053] Figure 6 It is along Figure 1A A schematic cross-sectional view taken from line I-I'.

[0054] Figure 7 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0055] Figure 8 It is a diagram. Figure 7 A floor plan of a portion of the display device area.

[0056] Figure 9 It is a diagram. Figure 8 An enlarged plan view of one of the unit emission regions in the unit emission region.

[0057] Figure 10 It is along Figure 9 A schematic cross-sectional view taken from line IV-IV'.

[0058] Figure 11 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken from line III-III'.

[0059] Figure 12 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken from line III-III'.

[0060] Figure 13This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0061] Figure 14 It is a diagram. Figure 13 A schematic cross-sectional view of the display device.

[0062] Figure 15 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0063] Figure 16 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0064] Figure 17A The illustration includes Figure 16 A schematic diagram of an embodiment of the circuit structure of a pixel in a display device.

[0065] Figure 17B The illustration includes Figure 16 A schematic diagram of another embodiment of the circuit structure of a pixel in a display device.

[0066] Figure 18 It is a diagram. Figure 16 A floor plan of a portion of the display device area.

[0067] Figure 19 It is a diagram. Figure 18 An enlarged plan view of one of the unit emission regions in the unit emission region.

[0068] Figure 20 It is along Figure 19 A schematic cross-sectional view taken from line VI-VI'.

[0069] Figure 21 It is along Figure 16 A schematic cross-sectional view of the line V-V'.

[0070] Figure 22 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0071] Figure 23 It is a diagram. Figure 22 A floor plan of a portion of the display device area.

[0072] Figure 24 It is a diagram. Figure 23 An enlarged plan view of one of the unit emission regions in the unit emission region.

[0073] Figure 25 It is along Figure 24 A schematic cross-sectional view of line VIII-VIII'.

[0074] Figure 26It is according to the embodiment along Figure 22 A schematic cross-sectional view of line VII-VII'.

[0075] Figure 27 It is according to the embodiment along Figure 22 A schematic cross-sectional view of line VII-VII'.

[0076] Figure 28 This is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0077] Figure 29 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0078] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0079] Various modifications and forms may be made in this disclosure, and specific embodiments will be illustrated in the accompanying drawings and described in detail in the text. However, this is not intended to limit this disclosure to the specific forms disclosed, and it will be understood that all variations, equivalents, or substitutions falling within the spirit and scope of this disclosure should be included.

[0080] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items.

[0081] It will be understood that when an element is referred to as "connected" or "linked" to another element, it may be directly connected to or directly linked to that other element, or an intermediary element may be present. Conversely, when an element is referred to as "directly connected" or "directly linked" to another element, no intermediary element is present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection, with or without an intermediary element. Additionally, when an element is referred to as "in contact" or "in contact" with another element, the element may be in "electrical contact" or "physical contact" with the other element, or in "indirect contact" or "direct contact" with the other element. Other terms used to describe relationships between elements (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.) should be interpreted in a similar manner.

[0082] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. It will be further understood that, when used in this specification, the term “comprising” indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0083] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “down” to other elements will be oriented “up” to other elements. Thus, depending on the specific orientation of the figure, the term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “under” other elements will be oriented “above” other elements. Thus, the terms “below” or “under” can encompass both “up” and “down” orientations.

[0084] In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purposes of its meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purposes of its meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in combined or separate meanings and can be understood as equivalent to "and / or".

[0085] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation from that particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0086] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0087] In the following description, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0088] Figure 1A This is a plan view illustrating a display device according to an embodiment of the present disclosure. Figure 1B This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0089] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The display device and its various components or layers may have a thickness extending along a third direction that intersects or intersects the plane, for example, each of the first direction DR1 and the second direction DR2 may be perpendicular to the third direction.

[0090] refer to Figure 1A and Figure 1B The display device DD1 (or DD1a) can be a device activated by an electrical signal. For example, the display device DD1 can be a small display device used in small electronic devices such as smartphones, mobile phones, smartwatches, game consoles, or cameras. For example, the display device DD1a can be a medium to large display device used in medium to large electronic devices such as laptops, tablet computers, televisions, computer monitors, vehicle monitors, or external billboards. Figure 1A The illustration shows a display device DD1 as an embodiment of a small display device, and... Figure 1B The illustration shows a display device DD1a as an embodiment of a medium-to-large-sized display device.

[0091] The display device DD1 (or DD1a) may include a display area DA and a peripheral area NDA. The display area DA may be an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The peripheral area NDA may be disposed adjacent to the display area DA. For example, the peripheral area NDA may surround at least a portion of the display area DA. In embodiments, the peripheral area NDA may be an area where no image is displayed. However, this disclosure is not limited thereto, and an image may be displayed in at least a portion of the peripheral area NDA. For example, a light-emitting element that emits light may be arranged in at least a portion of the peripheral area NDA.

[0092] The display device DD1 (or DD1a) may include a substrate SUB, a pixel PX, a gate line GL, a data line DL, a data driver DDV, and a gate driver GDV.

[0093] The substrate SUB can serve as the base for the display device DD1 (or DD1a). In embodiments, the substrate SUB may include glass, quartz, silicon, or polymers, etc. These can be used individually or in combination with each other. The substrate SUB can have a single-layer structure or a multilayer structure comprising multiple layers of different materials stacked on top of each other.

[0094] Pixels (PX) can be arranged in the display area (DA) or on the substrate (SUB). Pixels (PX) can be electrically connected to gate lines (GL) and data lines (DL). For example, pixels (PX) can be arranged in a matrix in a first direction (DR1) and a second direction (DR2). Each pixel (PX) can include pixel driving circuitry and a light-emitting element. The light-emitting element can emit light. The light-emitting element can be an organic light-emitting diode (OLED) or an inorganic light-emitting diode (LED).

[0095] Each of the gate lines GL and each of the data lines DL can intersect each other. For example, each of the gate lines GL can extend substantially in a first direction DR1, and the gate lines GL can be arranged in a second direction DR2. Each of the data lines DL can extend substantially in the second direction DR2, and the data lines DL can be arranged in the first direction DR1. However, this disclosure is not limited thereto.

[0096] The data driver DDV can be disposed in the peripheral area NDA or on the substrate SUB. The data driver DDV generates a data voltage. The data driver DDV outputs the data voltage to the data line DL. The data voltage can be applied to the pixel PX through the data line DL.

[0097] In one embodiment, the data driver DDV may be mounted on the substrate SUB. However, this disclosure is not limited thereto, and in another embodiment, the data driver DDV may be arranged as a chip-on-film (COF) on a flexible film attached to the substrate SUB.

[0098] In an embodiment, Figure 1B The display device DD1a may include a plurality of data drivers DDV. For example, the data drivers DDV may be arranged on opposite sides of the display area DA in the second direction DR2. For example, the data drivers DDV may be arranged along each of the long sides of the display device DD1a. However, this disclosure is not limited thereto.

[0099] A gate driver (GDV) can be disposed in the peripheral region NDA, on the substrate SUB. The gate driver (GDV) can generate a gate signal. The gate driver (GDV) can output the gate signal to the gate line GL. The gate signal can be applied to the pixel PX through the gate line GL. In an embodiment, the gate driver (GDV) can be disposed on opposite sides of the display region DA in the first direction DR1. However, this disclosure is not limited thereto.

[0100] In the embodiment, the transmitter driver that generates the transmit control signal (not in...) Figure 1A and Figure 1B (As shown in the diagram) can be further arranged in the peripheral NDA. Transmission control signals can be transmitted via the transmission control line (not shown in the diagram). Figure 1A and Figure 1B (As shown in the middle illustration) is applied to pixel PX.

[0101] Figure 1A and Figure 1B The number or arrangement of data drivers (DDVs) and gate drivers (GDVs) shown in the diagram are merely examples, and this disclosure is not limited thereto.

[0102] although Figure 1A The illustration shows a display device DD1 having a substantially rectangular planar shape, the rectangular planar shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2, but this disclosure is not limited thereto. Although Figure 1B The illustration shows a display device DD1a having a generally rectangular planar shape, the rectangular planar shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but the present disclosure is not limited thereto. For example, according to embodiments, the planar shape of each of the display devices DD1 and DD1a can be varied.

[0103] The following description, together with the accompanying drawings, can be applied in essentially the same way. Figure 1A Display device DD1 and Figure 1B The display device is DD1a. Therefore, for ease of description, both display devices DD1 and DD1a will be referred to as display device DD1 below.

[0104] Figure 2 The illustration includes Figure 1A and Figure 1BA schematic diagram of the circuit structure of a pixel in a display device.

[0105] refer to Figure 2 Pixel PX may include a light-emitting element LD and a pixel driving circuit PC1 connected to the light-emitting element LD. In an embodiment, the pixel driving circuit PC1 may include first transistors to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and a first capacitor C1. However, this disclosure is not limited thereto, and some components of the pixel driving circuit PC1 may be omitted, and other components may be added. In other words, Figure 2 The circuit structure of the pixel PX illustrated in the figure (i.e., the number or arrangement of transistors, the number or arrangement of capacitors, etc.) is only an example and can be changed according to the example.

[0106] exist Figure 2 In the illustration, the first transistor T1, the third transistor T3, and the fourth transistor T4 are shown as n-type transistors, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are shown as p-type transistors. However, this disclosure is not limited thereto, and in another embodiment, some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be n-type transistors, and the others may be p-type transistors. For example, the first transistor T1 may be an n-type transistor, and the second to seventh transistors T2, T3, T4, T5, T6, and T7 may be p-type transistors.

[0107] When a pixel PX includes both n-type and p-type transistors, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, this disclosure is not limited thereto, and both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0108] The pixel driver circuit PC1 can be connected to the first to fourth gate lines GWL, GCL, GIL, and GBL, the data line DL, the first to fourth voltage lines VL1, VL2, VL3, and VL4, and the transmit control line ECL. The first gate line GWL transmits the first gate signal GW. The second gate line GCL transmits the second gate signal GC. The third gate line GIL transmits the third gate signal GI. The fourth gate line GBL transmits the fourth gate signal GB. The data line DL transmits the data voltage VDATA. The first voltage line VL1 transmits the first power voltage ELVDD, which has a relatively high voltage level. The second voltage line VL2 transmits the second power voltage ELVSS, which has a relatively low voltage level. The third voltage line VL3 transmits the gate initialization voltage VINT. The fourth voltage line VL4 transmits the anode initialization voltage VAINT.

[0109] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a second node N2. The second terminal of the first transistor T1 may be connected to a third node N3. The first transistor T1 can provide a drive current ID to the light-emitting element LD.

[0110] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 can receive a first gate signal GW via a first gate line GWL. The first terminal of the second transistor T2 can receive a data voltage VDATA via a data line DL. The second terminal of the second transistor T2 can be connected to a second node N2.

[0111] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, if the second transistor T2 is a p-type transistor, it can be turned off when the first gate signal GW has a positive voltage level, and it can be turned on when the first gate signal GW has a negative voltage level. If the second transistor T2 is an n-type transistor, it can be turned off when the first gate signal GW has a negative voltage level, and it can be turned on when the first gate signal GW has a positive voltage level. When the second transistor T2 is turned on, it can provide the data voltage VDATA to the second node N2.

[0112] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor T3 can receive the second gate signal GC through the second gate line GCL. The first terminal of the third transistor T3 can be connected to the first node N1. The second terminal of the third transistor T3 can be connected to the third node N3.

[0113] The third transistor T3 can be turned on or off in response to the second gate signal GC. For example, if the third transistor T3 is an n-type transistor, it can be turned off when the second gate signal GC has a negative voltage level, and it can be turned on when the second gate signal GC has a positive voltage level. If the third transistor T3 is a p-type transistor, it can be turned off when the second gate signal GC has a positive voltage level, and it can be turned on when the second gate signal GC has a negative voltage level. When the third transistor T3 is turned on, it can connect to the first transistor T1 diode. For example, the third transistor T3 can compensate for the threshold voltage of the first transistor T1.

[0114] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor T4 can receive the third gate signal GI via the third gate line GIL. The first terminal of the fourth transistor T4 can receive the gate initialization voltage VINT via the third voltage line VL3. The second terminal of the fourth transistor T4 can be connected to the first node N1.

[0115] The fourth transistor T4 can be turned on or off in response to the third gate signal GI. For example, if the fourth transistor T4 is an n-type transistor, it can be turned off when the third gate signal GI has a negative voltage level, and it can be turned on when the third gate signal GI has a positive voltage level. If the fourth transistor T4 is a p-type transistor, it can be turned off when the third gate signal GI has a positive voltage level, and it can be turned on when the third gate signal GI has a negative voltage level. When the fourth transistor T4 is turned on, it can provide the gate initialization voltage VINT to the first node N1. Accordingly, the fourth transistor T4 can initialize the voltage at the gate terminal of the first transistor T1.

[0116] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fifth transistor T5 can receive a transmit control signal EM via the transmit control line ECL. The first terminal of the fifth transistor T5 can receive a first power voltage ELVDD via the first voltage line VL1. The second terminal of the fifth transistor T5 can be connected to the second node N2.

[0117] The fifth transistor T5 can be turned on or off in response to the transmit control signal EM. For example, if the fifth transistor T5 is a p-type transistor, it can be turned off when the transmit control signal EM has a positive voltage level, and it can be turned on when the transmit control signal EM has a negative voltage level. If the fifth transistor T5 is an n-type transistor, it can be turned off when the transmit control signal EM has a negative voltage level, and it can be turned on when the transmit control signal EM has a positive voltage level. When the fifth transistor T5 is turned on, it can supply the first power voltage ELVDD to the first terminal of the first transistor T1.

[0118] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the sixth transistor T6 can receive a transmit control signal EM via the transmit control line ECL. The first terminal of the sixth transistor T6 can be connected to the third node N3. The second terminal of the sixth transistor T6 can be connected to the fourth node N4.

[0119] The sixth transistor T6 can be turned on or off in response to the transmit control signal EM. For example, if the sixth transistor T6 is a p-type transistor, it can be turned off when the transmit control signal EM has a positive voltage level, and it can be turned on when the transmit control signal EM has a negative voltage level. If the sixth transistor T6 is an n-type transistor, it can be turned off when the transmit control signal EM has a negative voltage level, and it can be turned on when the transmit control signal EM has a positive voltage level. When the sixth transistor T6 is turned on, it can provide the drive current ID to the light-emitting element LD.

[0120] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the seventh transistor T7 can receive the fourth gate signal GB via the fourth gate line GBL. The first terminal of the seventh transistor T7 can receive the anode initialization voltage VAINT via the fourth voltage line VL4. The second terminal of the seventh transistor T7 can be connected to the fourth node N4.

[0121] The seventh transistor T7 can be turned on or off in response to the fourth gate signal GB. For example, if the seventh transistor T7 is a p-type transistor, it can be turned off when the fourth gate signal GB has a positive voltage level, and it can be turned on when the fourth gate signal GB has a negative voltage level. If the seventh transistor T7 is an n-type transistor, it can be turned off when the fourth gate signal GB has a negative voltage level, and it can be turned on when the fourth gate signal GB has a positive voltage level. When the seventh transistor T7 is turned on, it can provide the anode initialization voltage VAINT to the fourth node N4. Accordingly, the seventh transistor T7 can initialize the voltage of the anode of the light-emitting element LD.

[0122] The first capacitor C1 may include a first terminal and a second terminal. The first terminal of the first capacitor C1 can receive a first power voltage ELVDD through a first voltage line VL1. The second terminal of the first capacitor C1 can be connected to a first node N1. When the second transistor T2 is turned off, the first capacitor C1 can maintain the voltage level of the gate terminal of the first transistor T1.

[0123] Although not illustrated, in another embodiment, the pixel driving circuit PC1 may further include a second capacitor. The second capacitor may include a first terminal supplied with a first electrical voltage ELVDD and a second terminal connected to the first terminal of the first transistor T1.

[0124] A light-emitting element (LD) may include an anode and a cathode. The anode of the LD may be connected to a fourth node N4. The cathode of the LD may receive a second power voltage ELVSS via a second voltage line VL2. The LD can produce light with a brightness corresponding to the drive current ID.

[0125] Figure 3 It is a diagram. Figure 1A and Figure 1B A floor plan of a portion of the display device area. Figure 4 It is a diagram. Figure 3 An enlarged plan view of one of the unit emission regions in the unit emission region. Figure 5 It is along Figure 4 A schematic cross-sectional view taken from line II-II'.

[0126] Specifically, Figure 3 The diagram schematically illustrates the four cell transmission areas UEA1 and UEA2 arranged in a two-row, two-column matrix. Figure 4 The diagram schematically illustrates an enlarged view of the first transmission area, UEA1, among the two transmission areas, UEA1 and UEA2. For ease of description, Figure 5 Some of the components shown in the diagram are in Figure 3 and Figure 4 The middle part is either omitted or emphasized.

[0127] refer to Figure 3 and Figure 4 The display device DD1 may include a first pixel driving circuit to a third pixel driving circuit PCa, PCb and PCc, a first light-emitting element to a third light-emitting element LDa, LDb and LDc, a first auxiliary connection electrode to a third auxiliary connection electrode CCEa, CCEb and CCEc, a separator SPR and a plurality of organic film patterns OGP.

[0128] Each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be referenced above. Figure 2 The pixel driving circuit PC1 described corresponds to this. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc may include at least one transistor and at least one capacitor. Figure 5 The diagram shows the first transistor TR1, the first capacitor CAP1, and the second capacitor CAP2.

[0129] Figure 5 The first transistor TR1 can be connected to the anode electrode (ACE, reference) Figure 5A transistor connected to the light-emitting element. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc is... Figure 2 In the case of pixel driving circuit PC1, the first transistor TR1 can be Figure 2 The sixth transistor, T6. Figure 5 The first capacitor CAP1 can be with Figure 2 The first capacitor C1 corresponds to, and Figure 5 The second capacitor CAP2 can be omitted. However, this disclosure is not limited thereto, and Figure 5 The second capacitor CAP2 can be connected with Figure 2 The first capacitor C1 corresponds to, and Figure 5 The first capacitor CAP1 can be omitted. (Refer to...) Figure 5 The first transistor TR1, the first capacitor CAP1, and the second capacitor CAP2 are described in more detail.

[0130] Figure 3 and Figure 4 The schematic diagram illustrates that the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc each have a rectangular shape and are arranged sequentially along the first direction DR1 in a plan view. However, this disclosure is not limited thereto, and the shape and arrangement of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be varied according to embodiments.

[0131] Each of the first to third light-emitting elements LDa, LDb, and LDc can be referenced above. Figure 2 The light-emitting element LD is described. For example, each of the first to third light-emitting elements LDa, LDb, and LDc may include a first electrode (E1, reference). Figure 5 ), and the intermediate layer (ML, reference) arranged on the first electrode Figure 5 ) and the electrode layer arranged on the intermediate layer (E2L, reference) Figure 5 In an embodiment, the first electrode can be used as... Figure 2 The anode, and the electrode layer can be used as Figure 2 The cathode.

[0132] In an embodiment, the electrode layer can be separated (or disconnected) by the separator SPR into a plurality of second electrodes. For example, the electrode layer can be separated (or disconnected) into a second electrode (E2, reference) of the first light-emitting element LTa. Figure 5 ), the second electrode of the second light-emitting element LDb and the second electrode of the third light-emitting element LDc.

[0133] The first to third light-emitting elements LDa, LDb, and LDc can be connected to the first to third pixel driving circuits PCa, PCb, and PCc, respectively. For example, the first light-emitting element LDa can be connected to the first pixel driving circuit PCa, the second light-emitting element LDb can be connected to the second pixel driving circuit PCb, and the third light-emitting element LDc can be connected to the third pixel driving circuit PCc. Accordingly, the first pixel driving circuit PCa and the first light-emitting element LDa can form a pixel, the second pixel driving circuit PCb and the second light-emitting element LDb can form a pixel, and the third pixel driving circuit PCc and the third light-emitting element LDc can form a pixel.

[0134] The first to third light-emitting elements LDa, LDb, and LDc can emit light of different colors. For example, the first light-emitting element LDa can emit red light, the second light-emitting element LDb can emit green light, and the third light-emitting element LDc can emit blue light. However, this disclosure is not limited thereto.

[0135] In an embodiment, such as Figure 3 As shown, the display device DD1 may include a first unit transmission area UEA1 and a second unit transmission area UEA2. The first unit transmission area UEA1 and the second unit transmission area UEA2 may be defined in a matrix form along a first direction DR1 and a second direction DR2. Although Figure 3 Only four unit emission areas are shown, but the entire display area (DA, see...) is also visible. Figure 1A and Figure 1B Multiple cell emission regions are defined in a matrix form along the first direction DR1 and the second direction DR2.

[0136] The first to third light-emitting elements LDa, LDb, and LDc that are adjacent to each other can be arranged in each of the first unit emission region UEA1 and the second unit emission region UEA2. For example, the first to third emission regions EAa, EAb, and EAc that are adjacent to each other can be defined in each of the first unit emission region UEA1 and the second unit emission region UEA2, and the first to third light-emitting elements LDa, LDb, and LDc can be arranged in the first to third emission regions EAa, EAb, and EAc, respectively.

[0137] The first to third emission regions EAa, EAb, and EAc can be defined by a pixel-limited layer (PDL, see reference below). Figure 5The pixel opening is defined by the first to third emission regions EAa, EAb, and EAc. For example, each of these regions can be a region that emits light from the light-emitting element. For example, the first light-emitting element LDa can be disposed in the first emission region EAa, and the first emission region EAa can be a region that emits light from the first light-emitting element LDa. The second light-emitting element LDb can be disposed in the second emission region EAb, and the second emission region EAb can be a region that emits light from the second light-emitting element LDb. The third light-emitting element LDc can be disposed in the third emission region EAc, and the third emission region EAc can be a region that emits light from the third light-emitting element LDc.

[0138] In the embodiments, the first unit emission area UEA1 and the second unit emission area UEA2 can be distinguished based on the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc). For example, for each first unit emission area UEA1, the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc) can be the same, and for each second unit emission area UEA2, the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc) can be the same.

[0139] In an embodiment, such as Figure 3 As shown, the first unit transmission area UEA1 and the second unit transmission area UEA2 can be arranged alternately along the first direction DR1 (i.e., the row direction) and the second direction DR2 (i.e., the column direction). However, this disclosure is not limited thereto, and the number of different unit transmission areas included in the display device DD1 or the arrangement relationship between the unit transmission areas can be varied according to embodiments.

[0140] Figure 3 and Figure 4 The illustration schematically depicts the first to third transmission regions EAa, EAb, and EAc arranged in an S-striped structure. However, this disclosure is not limited thereto, and the arrangement of the first to third transmission regions EAa, EAb, and EAc can be varied according to embodiments.

[0141] The separator SPR can be arranged in a plan view between the first to third transmission regions EAa, EAb, and EAc. For example, the separator SPR can be arranged in a plan view between the first transmission region EAa and the second transmission region EAb, between the second transmission region EAb and the third transmission region EAc, and between the first transmission region EAa and the third transmission region EAc. The separator SPR can surround at least a portion of each of the first to third transmission regions EAa, EAb, and EAc in a plan view. In an embodiment, as... Figure 3 and Figure 4 As shown, in a plan view, the separator SPR may surround a portion of each of the first to third transmission regions EAa, EAb, and EAc, and may not surround another portion of each of the first to third transmission regions EAa, EAb, and EAc. However, this disclosure is not limited thereto, and in another embodiment, the separator SPR may completely surround each of the first to third transmission regions EAa, EAb, and EAc in a plan view.

[0142] The separator SPR can place the electrode layer (E2L, reference) in the display area. Figure 5 The second electrode of the first light-emitting element LTa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc are separated (or disconnected). Accordingly, the second electrodes of the first light-emitting element LTa, the second light-emitting element LDb, and the third light-emitting element LDc can be spaced apart from each other.

[0143] In embodiments, the spacer SPR may comprise an organic insulating material. For example, the spacer SPR may comprise a photosensitive resin (e.g., a photoresist), but this disclosure is not limited thereto.

[0144] In the display area, the organic film pattern OGP can overlap with at least a portion of the spacer SPR in the plan view. In the plan view, the organic film pattern OGP can be arranged within a portion of the area where the spacer SPR is arranged. In other words, a portion of the spacer SPR (e.g., Figure 5 The first part of the separator SPR (SPP1) can overlap with the organic membrane pattern OGP in the plan view, and the other parts of the separator SPR (e.g., Figure 5 The second part (SPP2) of the separator SPR may not overlap with the organic membrane pattern OGP in the planar view. The organic membrane pattern OGP may include organic materials.

[0145] Organic membrane patterned OGPs can have various planar shapes. For example, such as... Figure 3As shown, each of the organic film patterns OGP can have at least one of the following planar shapes in the planar view: a triangular planar shape, a rectangular planar shape, a square planar shape, a cross-shaped planar shape, and a rhombus planar shape. However, this disclosure is not limited thereto, and the organic film patterns OGP can have the same planar shape as each other.

[0146] In the embodiments, the organic film patterns (OGPs) may have different sizes (or areas) from each other. However, this disclosure is not limited thereto, and the organic film patterns (OGPs) may have the same size from each other.

[0147] In an embodiment, the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a planar view. The intersection portion CRP of the separator SPR can be the portion where a first extension portion of the separator SPR extending in a first direction DR1 and a second extension portion of the separator SPR extending in a second direction DR2 intersect. For example, as Figure 3 As shown, the first organic film pattern OGP1 in the organic film pattern OGP can overlap with the intersection CRP of the separator SPR in a plan view. The intersection CRP of the separator SPR can provide a relatively large space for covering the organic film pattern OGP compared to the first and second extensions of the separator SPR. However, this disclosure is not limited thereto, and the organic film pattern OGP can overlap with the first and second extensions of the separator SPR in a plan view. For example, as... Figure 3 As shown, the second organic membrane pattern OGP2 in the organic membrane pattern OGP can overlap with the first extension portion or the second extension portion of the separator SPR in the plan view.

[0148] In an embodiment, the organic film pattern OGP can be arranged within the area where the separator SPR is arranged in a plan view, and the separator SPR can cover the organic film pattern OGP and contact the pixel defining layer (PDL, reference) in a cross-sectional view. Figure 5 However, this disclosure is not limited thereto. For example, such as Figure 3 As shown, some of the organic membrane patterns OGP can be arranged inside the area with spacers SPR in the plan view, and other organic membrane patterns OGP can overlap with both the area with spacers SPR and the area without spacers SPR in the plan view.

[0149] In the following text, it will be referred to as Figure 4Centered on the first unit emission region UEA1, this section describes in more detail the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third auxiliary connection electrodes CCEa, CCEb, and CCEc. The following description of the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third auxiliary connection electrodes CCEa, CCEb, and CCEc can be applied substantially equivalently to all unit emission regions.

[0150] As described above, the display device DD1 may include a first auxiliary connection electrode to a third auxiliary connection electrode CCEa, CCEb, and CCEc. The first auxiliary connection electrode CCEa can connect the first light-emitting element LDa and the auxiliary electrode (AUE, reference) Figure 5 Electrical connection. The second auxiliary connection electrode CCEb can electrically connect the second light-emitting element LDb and the auxiliary electrode. The third auxiliary connection electrode CCEc can electrically connect the third light-emitting element LDc and the auxiliary electrode. Second power voltage (ELVSS, reference) Figure 2 It can be applied to the auxiliary electrode.

[0151] The first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc may comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. Examples of conductive materials that can be used as the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing Al, alloys containing Ag, alloys containing Cu, alloys containing Mo, and aluminum nitride (Al). x N y ), Tungsten nitride (W x N y ), titanium nitride (Ti x N y ), Chromium nitride (Cr x N y ), tantalum nitride (Ta x N y ), Tin oxide (SnO) x Gallium oxide (GaO) x Indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO) xOr zinc alumina (AZO), etc. These can be used alone or in combination with each other. In an embodiment, the first auxiliary connection electrode to the third auxiliary connection electrode CCEa, CCEb and CCEc can have a multilayer structure in which multiple conductive layers are stacked on top of each other. Reference will be made below. Figure 5 Provide a detailed description.

[0152] The first auxiliary connection electrode CCEa may include a first auxiliary electrode connection portion CAa and a first light-emitting connection portion CNa.

[0153] The first auxiliary electrode connection portion CAa can be a connection of the first auxiliary connection electrode CCEa to the auxiliary electrode (AUE, reference). Figure 5 For example, the location of the first auxiliary electrode connection portion CAa can be such that it exposes the auxiliary electrode and penetrates the fifth insulating layer (IL5, reference). Figure 5 Contact holes (CNT, reference) Figure 5 The position corresponds to the location of ).

[0154] The first light-emitting connection portion CNa can be the second electrode (E2, reference) of the first auxiliary connection electrode CCEa connected to the first light-emitting element LDa. Figure 5 For example, the first light-emitting connection portion CNa can be the first auxiliary connection electrode CCEa covered by the sixth insulating layer (IL6, reference). Figure 5 ) and Pixel Confinement Layer (PDL, reference) Figure 5 The portion of the first light-emitting connection portion CNa is exposed to connect to the second electrode of the first light-emitting element LDa. Correspondingly, the position of the first light-emitting connection portion CNa can be such that it exposes the first auxiliary connection electrode CCEa and penetrates the pixel defining layer and the sixth insulating layer through a sub-opening (OP, reference OP). Figure 5 The position corresponds to the location of ).

[0155] The second electrode of the first light-emitting element LTa can be connected to the first auxiliary connection electrode CCEa. For example, the second electrode of the first light-emitting element LTa can contact the first auxiliary connection electrode CCEa. As a result, the second electrode of the first light-emitting element LTa can be electrically connected to the auxiliary electrode (AUE, reference) through the first auxiliary connection electrode CCEa. Figure 5 ).

[0156] In an embodiment, the first light-emitting connection portion CNa can be arranged at a position that does not overlap with the first emitting region EAa in a plan view. For example, the second electrode of the first light-emitting element LDa can contact the first auxiliary connection electrode CCEa at a position that does not overlap with the first emitting region EAa in a plan view. For example, in a plan view, the first light-emitting connection portion CNa can be arranged between the first emitting region EAa and the separator SPR. Accordingly, the second electrode and the auxiliary electrode of the first light-emitting element LDa can be electrically connected to each other through the first auxiliary connection electrode CCEa without reducing the size of the first emitting region EAa.

[0157] The second auxiliary connection electrode CCEb may include a second auxiliary electrode connection portion CAb and a second light-emitting connection portion CNb.

[0158] The second auxiliary electrode connection portion CAb can be the part of the second auxiliary connection electrode CCEb that connects to the auxiliary electrode. For example, the position of the second auxiliary electrode connection portion CAb can correspond to the position of the contact hole that exposes the auxiliary electrode and penetrates the fifth insulating layer.

[0159] The second light-emitting connection portion CNb can be the portion of the second auxiliary connection electrode CCEb that connects to the second electrode of the second light-emitting element LDb. For example, the second light-emitting connection portion CNb can be the portion of the second auxiliary connection electrode CCEb that is exposed by the sixth insulating layer and the pixel defining layer to connect to the second electrode of the second light-emitting element LDb. Accordingly, the position of the second light-emitting connection portion CNb can correspond to the position of the sub-opening that exposes the second auxiliary connection electrode CCEb and penetrates the pixel defining layer and the sixth insulating layer.

[0160] In an embodiment, the second auxiliary connection electrode CCEb may be spaced apart from the first auxiliary connection electrode CCEa in a plan view. In other words, the first auxiliary connection electrode CCEa and the second auxiliary connection electrode CCEb may be different electrodes from each other.

[0161] The second electrode of the second light-emitting element LDb can be connected to the second auxiliary connection electrode CCEb. For example, the second electrode of the second light-emitting element LDb can contact the second auxiliary connection electrode CCEb. As a result, the second electrode of the second light-emitting element LDb can be electrically connected to the auxiliary electrode through the second auxiliary connection electrode CCEb.

[0162] In an embodiment, the second light-emitting connection portion CNb can be arranged at a position that does not overlap with the second emitting region EAb in a plan view. For example, the second electrode of the second light-emitting element LDb can contact the second auxiliary connection electrode CCEb at a position that does not overlap with the second emitting region EAb in a plan view. For example, in a plan view, the second light-emitting connection portion CNb can be arranged between the second emitting region EAb and the separator SPR. Accordingly, the second electrode and the auxiliary electrode of the second light-emitting element LDb can be electrically connected to each other through the second auxiliary connection electrode CCEb without reducing the size of the second emitting region EAb.

[0163] The third auxiliary connection electrode CCEc may include a third auxiliary electrode connection portion CAc and a third light-emitting connection portion CNc.

[0164] The third auxiliary electrode connection portion CAc can be the part of the third auxiliary connection electrode CCEc that connects to the auxiliary electrode. For example, the position of the third auxiliary electrode connection portion CAc can correspond to the position of the contact hole that exposes the auxiliary electrode and penetrates the fifth insulating layer.

[0165] The third light-emitting connection portion CNc can be the portion of the third auxiliary connection electrode CCEc that connects to the second electrode of the third light-emitting element LDc. For example, the third light-emitting connection portion CNc can be the portion of the third auxiliary connection electrode CCEc that is exposed by the sixth insulating layer and the pixel defining layer to connect to the second electrode of the third light-emitting element LDc. Accordingly, the position of the third light-emitting connection portion CNc can correspond to the position of the sub-opening that exposes the third auxiliary connection electrode CCEc and penetrates the pixel defining layer and the sixth insulating layer.

[0166] In an embodiment, the third auxiliary connection electrode CCEc may be spaced apart from the first auxiliary connection electrode CCEa and the second auxiliary connection electrode CCEb in a plan view. In other words, the first auxiliary connection electrode CCEa, the second auxiliary connection electrode CCEb, and the third auxiliary connection electrode CCEc may be different electrodes from each other.

[0167] The second electrode of the third light-emitting element LDc can be connected to the third auxiliary connection electrode CCEc. For example, the second electrode of the third light-emitting element LDc can contact the third auxiliary connection electrode CCEc. As a result, the second electrode of the third light-emitting element LDc can be electrically connected to the auxiliary electrode through the third auxiliary connection electrode CCEc.

[0168] In an embodiment, the third light-emitting connection portion CNc can be arranged at a position that does not overlap with the third emitting region EAc in a plan view. For example, the second electrode of the third light-emitting element LDc can contact the third auxiliary connection electrode CCEc at a position that does not overlap with the third emitting region EAc in a plan view. For example, in a plan view, the third light-emitting connection portion CNc can be arranged between the third emitting region EAc and the separator SPR. Accordingly, the second electrode and the auxiliary electrode of the third light-emitting element LDc can be electrically connected to each other through the third auxiliary connection electrode CCEc without reducing the size of the third emitting region EAc.

[0169] like Figure 3 As shown, for each of the first unit transmitter regions UEA1, the shape or arrangement of each of the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, as well as the arrangement relationship between the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, can be the same. For each of the second unit transmitter regions UEA2, the shape or arrangement of each of the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, as well as the arrangement relationship between the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, can be the same.

[0170] In the following text, reference will be made to Figure 5 The cross-sectional structure of the display device DD1 is described in more detail with the first emission zone EAa as the center. The following description of the cross-sectional structure of the display device DD1 can be applied substantially equivalently to all emission zones.

[0171] Further reference Figure 5 The display device DD1 may include a substrate SUB, a first bottom conductive layer BML1, a second bottom conductive layer BML2, a first transistor TR1, a first capacitor CAP1, a second capacitor CAP2, an auxiliary electrode AUE, an anode connection electrode ACE, a first auxiliary connection electrode CCEa, first to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a first light-emitting element LDa, an organic film pattern OGP, a separator SPR, a first dummy layer DP1, a second dummy layer DP2 and an encapsulation layer ENC. The separator SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1.

[0172] The first transistor TR1 may include a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. The first capacitor CAP1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The second capacitor CAP2 may include a first capacitor electrode CPE1 and a third capacitor electrode CPE3. The first light-emitting element LDa may include a first electrode E1, an intermediate layer ML, and a second electrode E2.

[0173] As described above, the first transistor TR1, the first capacitor CAP1, and the second capacitor CAP2 may be components included in the first pixel driving circuit PCa.

[0174] The substrate SUB can serve as the base for the display device DD1. In embodiments, the substrate SUB may include glass, quartz, silicon, or polymers, etc. These can be used individually or in combination with each other. The substrate SUB can have a single-layer structure or a multi-layer structure comprising multiple layers of different materials stacked on top of each other.

[0175] The first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3 can be disposed on the substrate SUB. In an embodiment, the first bottom conductive layer BML1 and the second bottom conductive layer BML2 can withstand different electrical signals. The first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3 can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0176] The first insulating layer IL1 may cover the first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3, and may be disposed on the substrate SUB. The first insulating layer IL1 may prevent or reduce the diffusion of metal atoms or impurities from the substrate SUB to the first active pattern AP1. The first insulating layer IL1 may include an insulating material. Examples of insulating materials that can be used as the first insulating layer IL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0177] A first active pattern AP1 may be disposed on a first insulating layer IL1. In an embodiment, the first active pattern AP1 may overlap with a first bottom conductive layer BML1 in a plan view. The first active pattern AP1 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern AP1 may include a first contact region S1, a second contact region D1, and a first channel region CH1 between the first contact region S1 and the second contact region D1. The first contact region S1 and the second contact region D1 may have a higher conductivity than the first channel region CH1.

[0178] In an embodiment, the first active pattern AP1 may include an oxide semiconductor material. Examples of oxide semiconductor materials that can be used as the first active pattern AP1 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO), etc. These may be used alone or in combination with each other. However, this disclosure is not limited thereto, and in another embodiment, the first active pattern AP1 may include a silicon semiconductor material.

[0179] The second insulating layer IL2 may cover the first active pattern AP1 and may be disposed on the first insulating layer IL1. The second insulating layer IL2 may include an insulating material. For example, the second insulating layer IL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0180] The first gate electrode GE1 can be disposed on the second insulating layer IL2. In a planar view, the first gate electrode GE1 can overlap with the first channel region CH1 of the first active pattern AP1. The first gate electrode GE1 can comprise a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. Although not shown in the diagram... Figure 5 As illustrated in the figure, in an embodiment, the first gate electrode GE1 can contact the first bottom conductive layer BML1.

[0181] The first capacitor electrode CPE1 can be disposed on the second insulating layer IL2. The first capacitor electrode CPE1 can overlap with the third capacitor electrode CPE3 in a plan view. The first capacitor electrode CPE1 and the third capacitor electrode CPE3 can form a second capacitor CAP2. The first capacitor electrode CPE1 can include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide.

[0182] The third insulating layer IL3 may cover the first gate electrode GE1 and the first capacitor electrode CPE1, and may be disposed on the second insulating layer IL2. The third insulating layer IL3 may include an insulating material. For example, the third insulating layer IL3 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0183] The second capacitor electrode CPE2 can be disposed on the third insulating layer IL3. The second capacitor electrode CPE2 can overlap with the first capacitor electrode CPE1 in a planar view. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can form the first capacitor CAP1. The second capacitor electrode CPE2 can include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide.

[0184] The fourth insulating layer IL4 may cover the second capacitor electrode CPE2 and may be disposed on the third insulating layer IL3. The fourth insulating layer IL4 may include an insulating material. For example, the fourth insulating layer IL4 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0185] The first contact electrode SE1 and the second contact electrode DE1 can be disposed on the fourth insulating layer IL4. The first contact electrode SE1 can contact the first contact area S1 of the first active pattern AP1, and the second contact electrode DE1 can contact the second contact area D1 of the first active pattern AP1. The first contact electrode SE1 and the second contact electrode DE1 can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0186] In one embodiment, the second contact electrode DE1 may contact the first bottom conductive layer BML1. However, this disclosure is not limited thereto. For example, if the first gate electrode GE1 contacts the first bottom conductive layer BML1, the second contact electrode DE1 may not contact the first bottom conductive layer BML1.

[0187] Accordingly, a first transistor TR1 can be formed, comprising a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. As described above, the first transistor TR1 can be a transistor connected to a light-emitting element via an anode connection electrode ACE.

[0188] The auxiliary electrode AUE can be disposed in the display area DA on the substrate SUB. For example, the auxiliary electrode AUE can be disposed in the display area DA on the fourth insulating layer IL4. The auxiliary electrode AUE can contact the second bottom conductive layer BML2. The auxiliary electrode AUE can be spaced apart from the first electrode E1. Second power voltage (ELVSS, reference) Figure 2 An auxiliary electrode (AUE) can be applied to the auxiliary electrode. The auxiliary electrode (AUE) may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0189] The fifth insulating layer IL5 may cover the first contact electrode SE1, the second contact electrode DE1, and the auxiliary electrode AUE, and may be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 may include insulating materials. For example, the fifth insulating layer IL5 may include organic insulating materials. For example, the fifth insulating layer IL5 may include photoresist, polypropylene resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, or epoxy resin, etc. These can be used individually or in combination with each other.

[0190] The first auxiliary connection electrode CCEa can be disposed on the auxiliary electrode AUE. For example, the first auxiliary connection electrode CCEa can be disposed in the display area DA, on the fifth insulating layer IL5. As described above, the first auxiliary connection electrode CCEa can be electrically connected to the auxiliary electrode AUE. For example, the first auxiliary connection electrode CCEa can contact the auxiliary electrode AUE through a contact hole CNT penetrating the fifth insulating layer IL5. Accordingly, the position of the first auxiliary electrode connection portion CAa can correspond to the position of the contact hole CNT.

[0191] The first auxiliary connection electrode CCEa may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. In an embodiment, the first auxiliary connection electrode CCEa may have a multilayer structure in which multiple conductive layers are stacked on top of each other. For example, the first auxiliary connection electrode CCEa may include a first conductive layer CL1, a second conductive layer CL2, and a third conductive layer CL3 stacked sequentially.

[0192] In this embodiment, the first conductive layer CL1 may comprise a metal and / or a transparent conductive oxide. Examples of metals that can be used as the first conductive layer CL1 include titanium (Ti) or molybdenum (Mo). Examples of transparent conductive oxides that can be used as the first conductive layer CL1 include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (InO). x Materials used include indium gallium oxide (IGO) and zinc aluminum oxide (AZO). Compared to the second conductive layer CL2, the first conductive layer CL1 can have a relatively small thickness.

[0193] The second conductive layer CL2 and the first conductive layer CL1 can be made of different materials. For example, the second conductive layer CL2 and the first conductive layer CL1 can be made of different metals. For example, the second conductive layer CL2 can be made of aluminum (Al) or copper (Cu). The thickness of the second conductive layer CL2 can be greater than the thickness of the first conductive layer CL1.

[0194] The third conductive layer CL3 and the second conductive layer CL2 can be made of different materials. For example, the third conductive layer CL3 can include a metal and / or a transparent conductive oxide different from the second conductive layer CL2. Examples of metals that can be used as the third conductive layer CL3 include titanium (Ti) or molybdenum (Mo). Examples of transparent conductive oxides that can be used as the third conductive layer CL3 include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (InO). x Materials used include indium gallium oxide (IGO) or zinc aluminum oxide (AZO). The thickness of the third conductive layer CL3 can be less than the thickness of the second conductive layer CL2.

[0195] In some embodiments, the first conductive layer CL1 and the third conductive layer CL3 may comprise the same material. However, this disclosure is not limited thereto.

[0196] The side surface CL2-S of the second conductive layer CL2 may be recessed toward the center of the first auxiliary connection electrode CCEa compared to the side surfaces CL1-S of the first conductive layer CL1 and CL3-S of the third conductive layer CL3. In other words, the side surfaces CL1-S of the first conductive layer CL1 and CL3-S of the third conductive layer CL3 may protrude beyond the side surface CL2-S of the second conductive layer CL2. Accordingly, due to the protrusion of the third conductive layer CL3 beyond the second conductive layer CL2, the first auxiliary connection electrode CCEa may have a pointed structure. For example, when the second conductive layer CL2 is etched using an etching material with an etching rate higher than that for the first and third conductive layers CL1 and CL3, the first auxiliary connection electrode CCEa may be formed with a pointed structure.

[0197] exist Figure 5 In the illustration, the first auxiliary connection electrode CCEa is shown as having a three-layer structure in which the first to third conductive layers CL1, CL2, and CL3 are stacked. However, this disclosure is not limited thereto, and in another embodiment, the first auxiliary connection electrode CCEa may have a two-layer structure in which the second conductive layer CL2 and the third conductive layer CL3 are stacked. For example, the first conductive layer CL1 may be omitted.

[0198] The anode connection electrode ACE can be disposed on the fifth insulating layer IL5. The anode connection electrode ACE can contact the second contact electrode DE1 and the first electrode E1. Accordingly, the anode connection electrode ACE can electrically connect the first transistor TR1 and the first light-emitting element LDa. The anode connection electrode ACE can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0199] The sixth insulating layer IL6 may cover the anode connection electrode ACE and may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may partially cover the first auxiliary connection electrode CCEa and may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may define a first sub-opening SO1 that exposes at least a portion of the first auxiliary connection electrode CCEa. For example, the first sub-opening SO1 may expose the tip structure of the first auxiliary connection electrode CCEa. The sixth insulating layer IL6 may include an insulating material. For example, the sixth insulating layer IL6 may include an organic insulating material. For example, the sixth insulating layer IL6 may include photoresist, polypropylene resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, or epoxy resin, etc. These may be used alone or in combination with each other.

[0200] The first electrode E1 can be disposed in the display area DA, on the substrate SUB. For example, the first electrode E1 can be disposed on the sixth insulating layer IL6. The first electrode E1 can contact the anode connection electrode ACE. Accordingly, the first electrode E1 can be electrically connected to the first transistor TR1 through the anode connection electrode ACE. The first electrode E1 can include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. As described above, the first electrode E1 can be used as... Figure 2 The anode.

[0201] A pixel defining layer PDL can be disposed on a substrate SUB and can define a pixel opening that exposes the first electrode E1. For example, the pixel defining layer PDL can be disposed on a sixth insulating layer IL6 and the first electrode E1 and can define a pixel opening that exposes at least a portion of the first electrode E1. A first emitter region EAa can be defined by the pixel opening.

[0202] The pixel defining layer (PDL) can further define a second sub-opening (SO2) corresponding to a first sub-opening (SO1) of the sixth insulating layer (IL6). The second sub-opening (SO2) can overlap with the first sub-opening (SO1) in a plan view, and the first and second sub-openings (SO1 and SO2) can be spatially connected to each other. For example, the first and second sub-openings (SO1 and SO2) can be connected to define a sub-opening (OP), and the sub-opening (OP) can expose at least a portion of the first auxiliary connection electrode (CCEa). For example, the sub-opening (OP) can expose the tip structure of the first auxiliary connection electrode (CCEa).

[0203] The pixel defining layer (PDL) may include an insulating material. For example, the PDL may include an organic insulating material. For example, the PDL may include photoresist, polypropylene resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, or epoxy resin, etc. These can be used alone or in combination with each other. In embodiments, the PDL may further include inorganic or organic materials comprising a black light-shielding material.

[0204] An organic film pattern (OGP) can be disposed in the display area (DA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the display area (DA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, the upper surface of the organic film pattern (OGP) can be an upwardly convex curved surface.

[0205] Organic film patterning (OGP) can include organic materials. For example, organic film patterning OGP can include photoresists, polypropylene resins, polyimide resins, polyamide resins, silicone resins, acrylic resins, or epoxy resins. These can be used alone or in combination with each other. In embodiments, the organic film patterning OGP and the pixel defining layer (PDL) can include different materials.

[0206] The separator SPR can be arranged on the pixel definition layer (PDL). The width of the upper part of the separator SPR can be greater than the width of the lower part of the separator SPR. For example, the side surface of the separator SPR that connects the upper and lower surfaces of the separator SPR can have a reverse tapered slope. In other words, the separator SPR can have an inverted trapezoidal cross-sectional shape.

[0207] exist Figure 5 In the illustration, the side surface of the separator SPR is shown to have a single reverse tapering ramp. However, this disclosure is not limited thereto, and in another embodiment, the side surface of the separator SPR may have multiple reverse tapering ramps. For example, the separator SPR may have a double reverse tapering structure.

[0208] The separator SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1. The first portion SPP1 of the separator SPR may overlap with the organic film pattern OGP in a planar view, and the second portion SPP2 of the separator SPR may be spaced apart from the organic film pattern OGP in a planar view. In other words, the second portion SPP2 of the separator SPR may not overlap with the organic film pattern OGP in a planar view. In an embodiment, the first portion SPP1 of the separator SPR may contact the organic film pattern OGP and the pixel defining layer PDL, and may cover the organic film pattern OGP. In other words, the first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface may contact the pixel defining layer PDL in the display area DA. The first and second side surfaces of the first portion SPP1 of the separator SPR may have reverse tapered bevels, and the separator SPR can be easily separated (or disconnected) from the electrode layer E2L (or the second electrode E2).

[0209] Since the organic film pattern OGP is arranged between the pixel defining layer PDL and the first portion SPP1 of the separator SPR, the upper surface of the first portion SPP1 of the separator SPR can be an upwardly convex curved surface. In an embodiment, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Here, the horizontal height of the upper surface of the separator SPR can be the horizontal height of the highest part of the upper surface of the separator SPR.

[0210] An intermediate layer ML can be disposed on the first electrode E1 and the pixel defining layer PDL. A portion of the intermediate layer ML can be disposed in a pixel opening of the pixel defining layer PDL. In an embodiment, the intermediate layer ML may include a first functional layer comprising an organic material, a light-emitting layer disposed on the first functional layer and comprising a light-emitting material, and a second functional layer disposed on the light-emitting layer and comprising an organic material. For example, the first functional layer may include a hole injection layer or a hole transport layer, and the second functional layer may include an electron transport layer or an electron injection layer.

[0211] Shaded areas where the intermediate layer ML is difficult to deposit can exist around the separator SPR with a reverse tapered slope. Accordingly, the intermediate layer ML can be separated (or disconnected) by the separator SPR in and / or around the shaded areas. For example, the first and second functional layers included in the intermediate layer ML can be separated (or disconnected) by the separator SPR. Accordingly, current leakage to other light-emitting elements adjacent to the first light-emitting element LDa (e.g., the second light-emitting element LDb and the third light-emitting element LDc) can be reduced. For example, color mixing due to unnecessary emission from other light-emitting elements can be prevented.

[0212] The first dummy layer DP1 can be disposed on the separator SPR. Since the intermediate layer ML has a structure separated (or disconnected) by the separator SPR, the first dummy layer DP1 can be formed. For example, the first dummy layer DP1 and the intermediate layer ML can be formed in the same process. In an embodiment, the first dummy layer DP1 can be omitted.

[0213] The intermediate layer ML can also be separated (or disconnected) by the tip structure of the first auxiliary connection electrode CCEa. Because the intermediate layer ML is separated (or disconnected) by the tip structure of the first auxiliary connection electrode CCEa, at least a portion of the side surface CL2-S of the second conductive layer CL2 can be exposed. Accordingly, the second electrode E2 of the first light-emitting element LDa can contact the side surface CL2-S of the second conductive layer CL2.

[0214] Electrode layer E2L (e.g., Figure 5 The second electrode (E2) can be disposed on the intermediate layer ML. The electrode layer E2L can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. In an embodiment, the electrode layer E2L can have a single-layer structure. However, this disclosure is not limited thereto. In another embodiment, the electrode layer E2L can have a multilayer structure in which multiple conductive layers are stacked on top of each other. For example, the electrode layer E2L can have a two-layer structure, which includes a first sub-electrode layer comprising a metal and a second sub-electrode layer disposed on the first sub-electrode layer and comprising a transparent conductive oxide.

[0215] The shadowed areas where it is difficult to deposit the electrode layer E2L can exist around the separator SPR with a reverse tapered slope. Within and / or around the shadowed areas, the electrode layer E2L can be separated (or disconnected) by the separator SPR. For example, the electrode layer E2L can be separated (or disconnected) into the second electrode E2 of the first light-emitting element LTa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc.

[0216] The second electrode E2 of the first light-emitting element LDa can be connected to the first auxiliary connection electrode CCEa. For example, the second electrode E2 can contact the side surface CL2-S of the second conductive layer CL2. For example, if the deposition angle of the deposition process for forming the electrode layer E2L is greater than the deposition angle of the deposition process for forming the intermediate layer ML, the electrode layer E2L (e.g., the second electrode E2) can be formed to contact the side surface CL2-S of the second conductive layer CL2 while covering the intermediate layer ML that is disconnected by the tip structure. As a result, the second electrode E2 can be electrically connected to the auxiliary electrode AUE through the first auxiliary connection electrode CCEa. Accordingly, the second electrode E2 can receive a second power voltage (ELVSS, reference) from the auxiliary electrode AUE. Figure 2 ).

[0217] In an embodiment, the electrode layer E2L (specifically, the second electrode E2) can be separated (or disconnected) by the tip structure of the first auxiliary connection electrode CCEa. However, this disclosure is not limited thereto, and the electrode layer E2L (e.g., the second electrode E2) can be formed to extend without being disconnected by the tip structure.

[0218] The second dummy layer DP2 can be disposed on the separator SPR. For example, the second dummy layer DP2 can be disposed on the first dummy layer DP1. Since the electrode layer E2L has a structure that is separated (or disconnected) by the separator SPR, the second dummy layer DP2 can be formed. For example, the second dummy layer DP2 and the electrode layer E2L can be formed in the same process. In an embodiment, the second dummy layer DP2 can be omitted.

[0219] The encapsulation layer ENC can be disposed on the electrode layer E2L. The encapsulation layer ENC can completely cover the electrode layer E2L, the separator SPR, the first dummy layer DP1, and the second dummy layer DP2. In an embodiment, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1 containing inorganic insulating material, an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1 and containing organic insulating material, and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL and containing inorganic insulating material.

[0220] Although not in Figure 5 The diagram shows a touch sensing layer, but in an embodiment, the touch sensing layer may be disposed on the encapsulation layer ENC. For example, the touch sensing layer may include a plurality of touch electrode arrays for capacitively detecting a user's touch, touch pad portions, and a plurality of touch lines electrically connecting the touch pad portions and the touch electrode arrays. However, this disclosure is not limited thereto. In an embodiment, the touch sensing layer may be omitted.

[0221] According to an embodiment, the display device DD1 may include a second electrical voltage (ELVSS, reference) applied to it. Figure 2 The electrode layer E2L comprises an auxiliary electrode AUE and auxiliary connection electrodes CCEa, CCEb, and CCEc, each having a pointed structure and contacting the auxiliary electrode AUE. Because each of the auxiliary connection electrodes CCEa, CCEb, and CCEc has a pointed structure, the electrode layer E2L (e.g., a cathode) can be easily connected to the auxiliary connection electrodes CCEa, CCEb, and CCEc. The electrode layer E2L can be electrically connected to the auxiliary electrode AUE via the auxiliary connection electrodes CCEa, CCEb, and CCEc. Accordingly, the electrode layer E2L can receive a second electrical voltage from the auxiliary electrode AUE and can suppress voltage drop phenomena in the voltage supplied to the electrode layer E2L.

[0222] As described above, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Accordingly, the mask used in the process of forming the intermediate layer ML can contact the first portion SPP1 of the separator SPR, but can avoid contacting the second portion SPP2. In other words, the area of ​​the separator SPR in contact with the mask can be relatively reduced. As a result, the phenomenon of mask pressing that may occur when the area of ​​the separator SPR in contact with the mask is large can be suppressed.

[0223] Figure 6 It is along Figure 1A A schematic cross-sectional view taken from line I-I'.

[0224] refer to Figure 6 The display device DD1 according to an embodiment of this disclosure may include a substrate SUB, a second bottom conductive layer BML2, a first capacitor CAP1, a second capacitor CAP2, an auxiliary electrode AUE, an auxiliary connection electrode CCE, first to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, an intermediate layer ML, an electrode layer E2L, an organic film pattern OGP, a separator SPR, and an encapsulation layer ENC. In the following, references to the above are... Figure 5 Redundant descriptions of the structure of the display device DD1 may be omitted or summarized.

[0225] An organic film pattern (OGP) can be disposed in the peripheral area (NDA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the peripheral area (NDA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, the upper surface of the organic film pattern (OGP) can be an upwardly convex curved surface. The organic film pattern (OGP) can include an organic material. In an embodiment, the organic film pattern (OGP) and the pixel defining layer (PDL) can include different materials.

[0226] The separator SPR can be disposed on the pixel defining layer PDL. The separator SPR can contact the organic film pattern OGP and the pixel defining layer PDL in the peripheral region NDA. In an embodiment, the organic film pattern OGP can overlap with a portion of the separator SPR in a planar view in the peripheral region NDA. For example, the organic film pattern OGP can overlap with a portion of the separator SPR in a planar view in the peripheral region NDA. Since the upper surface of the organic film pattern OGP includes an upwardly convex curved surface, the upper surface of the separator SPR can also include an upwardly convex curved surface.

[0227] In an embodiment, such as Figure 6As shown, the cross-sectional shape of a portion of the separator SPR may be asymmetrical in the peripheral region NDA. For example, a first side surface of a portion of the separator SPR may contact the organic film pattern OGP in the peripheral region NDA, and a second side surface opposite to the first side surface may contact the pixel defining layer PDL without contacting the organic film pattern OGP. Accordingly, in the process of forming the separator SPR, the difference in characteristics between the organic film pattern OGP and the pixel defining layer PDL may lead to a difference in the degree of inclination of the first side surface and the second side surface.

[0228] The second side surface of the separator SPR can have a reverse tapered slope. Because the second side surface of the separator SPR has a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can have a separated (or disconnected) structure in the display area DA.

[0229] In contrast, the first side surface of the separator SPR may not have a reverse tapered slope. For example, by forming an organic film pattern OGP that overlaps with the first side surface of the separator SPR in a planar view within the peripheral region NDA, the first side surface of the separator SPR may not have a reverse tapered slope. Since the first side surface of the separator SPR does not have a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can be formed as extended layers without being broken within the peripheral region NDA.

[0230] Figure 7 This is a plan view illustrating a display device according to an embodiment of the present disclosure. Figure 8 It is a diagram. Figure 7 A floor plan of a portion of the display device area. Figure 9 It is a diagram. Figure 8 An enlarged plan view of one of the unit emission regions in the unit emission region. Figure 10 It is along Figure 9 A schematic cross-sectional view taken from line IV-IV'.

[0231] For example, Figure 8 The diagram schematically illustrates the four cell transmission areas UEA1 and UEA2 arranged in a two-row, two-column matrix. Figure 9 The diagram schematically illustrates an enlarged view of the first transmission area, UEA1, among the two transmission areas, UEA1 and UEA2. For ease of description, Figure 10 Some of the components shown in the diagram are in Figure 8 and Figure 9 The middle part is either omitted or emphasized.

[0232] refer to Figure 7 , Figure 8 , Figure 9 and Figure 10 The display device DD1-2 can be a device activated by an electrical signal. For example, such as... Figure 7 As shown, the display device DD1-2 can be a small display device used in small electronic devices such as smartphones, mobile phones, smartwatches, game consoles, or cameras. However, this disclosure is not limited thereto, and the display device DD1-2 can be a medium to large display device used in medium to large electronic devices such as laptop computers, tablet computers, televisions, computer monitors, vehicle monitors, or external billboards.

[0233] Reference above Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 and Figure 5 Compared to the described display device DD1, the display device DD1-2 may further include auxiliary connection electrodes (e.g., Figure 10 The first auxiliary connection electrode (CCEa) and the second electrode (e.g., Figure 10 The connection pattern of the second electrode E2) electrically connected (e.g., Figure 10 The first connection pattern (CNPa). See below for reference. Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 and Figure 5 The redundant description of the display device DD1 may be omitted or summarized.

[0234] like Figure 8 and Figure 9 As shown, the display device DD1-2 may include a first pixel driving circuit to a third pixel driving circuit PCa, PCb and PCc, a first light-emitting element to a third light-emitting element LDa, LDb and LDc, a first auxiliary connection electrode to a third auxiliary connection electrode CCEa, CCEb and CCEc, a first connection pattern to a third connection pattern CNPa, CNPb and CNPc, a separator SPR and a plurality of organic film patterns OGP.

[0235] Each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be referenced above. Figure 2 The pixel driving circuit PC1 described corresponds to this. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc may include at least one transistor and at least one capacitor. Figure 10 The diagram shows the first transistor TR1, the first capacitor CAP1, and the second capacitor CAP2.

[0236] Figure 10 The first transistor TR1 can be connected to the anode electrode (ACE, reference) Figure 10 The transistors connected to the light-emitting element. For example, in the first pixel driving circuit to the third pixel driving circuit, PCa, PCb, and PCc are... Figure 2 In the case of pixel driving circuit PC1, the first transistor TR1 can be Figure 2 The sixth transistor, T6.

[0237] Each of the first to third light-emitting elements LDa, LDb, and LDc can be referenced above. Figure 2 The light-emitting element LD is described. For example, each of the first to third light-emitting elements LDa, LDb, and LDc may include a first electrode (E1, reference). Figure 10 ), and the intermediate layer (ML, reference) arranged on the first electrode Figure 10 ) and the electrode layer arranged on the intermediate layer (E2L, reference) Figure 10 In an embodiment, the first electrode E1 can be used as... Figure 2 The anode, and the electrode layer E2L can be used as... Figure 2 The cathode.

[0238] In an embodiment, the electrode layer E2L can be separated (or disconnected) by the separator SPR into a plurality of second electrodes spaced apart from each other. For example, the electrode layer E2L can be separated (or disconnected) into the second electrode (E2, reference) of the first light-emitting element LTa. Figure 10 ), the second electrode of the second light-emitting element LDb and the second electrode of the third light-emitting element LDc.

[0239] The first to the third light-emitting elements LDa, LDb, and LDc can be connected to the first to the third pixel driving circuits PCa, PCb, and PCc, respectively. For example, the first light-emitting element LDa can be connected to the first pixel driving circuit PCa, the second light-emitting element LDb can be connected to the second pixel driving circuit PCb, and the third light-emitting element LDc can be connected to the third pixel driving circuit PCc.

[0240] The separator SPR can be arranged in a plan view between the first to third transmission regions EAa, EAb, and EAc. For example, the separator SPR can be arranged in a plan view between the first transmission region EAa and the second transmission region EAb, between the second transmission region EAb and the third transmission region EAc, and between the first transmission region EAa and the third transmission region EAc. The separator SPR can surround at least a portion of each of the first to third transmission regions EAa, EAb, and EAc in a plan view. In an embodiment, as... Figure 8 and Figure 9As shown in the diagram, in a plan view, the spacer SPR may surround a portion of each of the first to third emission regions EAa, EAb, and EAc, and may not surround another portion of each of the first to third emission regions EAa, EAb, and EAc. However, this disclosure is not limited thereto, and the spacer SPR may completely surround each of the first to third emission regions EAa, EAb, and EAc in a plan view. In embodiments, the spacer SPR may comprise an organic insulating material.

[0241] The separator SPR can separate (or disconnect) the electrode layer E2L in the display area DA into the second electrode E2 of the first light-emitting element LDa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc. Accordingly, the second electrodes E2 of the first light-emitting element LDa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc can be spaced apart from each other.

[0242] The organic membrane pattern (OGP) can overlap with at least a portion of the spacer segment (SPR) in a plan view. The organic membrane pattern (OGP) can be arranged within a portion of the area where the spacer segment (SPR) is arranged. In other words, a portion of the spacer segment (e.g., Figure 10 The first part of the separator SPR (SPP1) can overlap with the organic membrane pattern OGP in the plan view, and the other parts of the separator SPR (e.g., Figure 10 The second part (SPP2) of the separator SPR may not overlap with the organic membrane pattern OGP in the planar view. The organic membrane pattern OGP may include organic materials.

[0243] In an embodiment, the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a planar view. The intersection portion CRP of the separator SPR can be the portion where a first extension portion of the separator SPR extending in a first direction DR1 and a second extension portion of the separator SPR extending in a second direction DR2 intersect. For example, as Figure 8 As shown, the first organic film pattern OGP1 in the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a planar view. However, this disclosure is not limited to this, and the organic film pattern OGP can overlap with the first extension portion and the second extension portion of the separator SPR in a planar view. For example, as Figure 8 As shown, the second organic membrane pattern OGP2 in the organic membrane pattern OGP can overlap with the first extension portion or the second extension portion of the separator SPR in the plan view.

[0244] In an embodiment, the organic film pattern OGP can be arranged in the area where the spacer SPR is arranged in the plan view. However, this disclosure is not limited to this, and some of the organic film pattern OGPs can be arranged in the area where the spacer SPR is arranged in the plan view, while other organic film pattern OGPs can overlap with both the area where the spacer SPR is arranged and the area where the spacer SPR is not arranged in the plan view.

[0245] In the following text, it will be referred to as Figure 9 Centered on the first unit emission region UEA1, this section describes in more detail the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third auxiliary connection electrodes CCEa, CCEb, and CCEc. The following description of the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third auxiliary connection electrodes CCEa, CCEb, and CCEc can be applied substantially equivalently to all unit emission regions.

[0246] As described above, the display device DD1-2 may include a first auxiliary connection electrode to a third auxiliary connection electrode CCEa, CCEb, and CCEc, and a first connection pattern to a third connection pattern CNPa, CNPb, and CNPc. The first auxiliary connection electrode CCEa and the first connection pattern CNPa can connect the first light-emitting element LDa and the auxiliary electrode (AUE, reference) Figure 10 Electrical connection. The second auxiliary connection electrode CCEb and the second connection pattern CNPb can electrically connect the second light-emitting element LDb and the auxiliary electrode AUE. The third auxiliary connection electrode CCEc and the third connection pattern CNPc can electrically connect the third light-emitting element LDc and the auxiliary electrode AUE. Second power voltage (ELVSS, reference) Figure 2 It can be applied to the auxiliary electrode AUE.

[0247] The first auxiliary connection electrode to the third auxiliary connection electrode CCEa, CCEb and CCEc may comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides or transparent conductive oxides. In embodiments, the first auxiliary connection electrode to the third auxiliary connection electrode CCEa, CCEb and CCEc may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0248] In this embodiment, the first to third connection patterns CNPa, CNPb, and CNPc may comprise transparent conductive oxides. For example, the first to third connection patterns CNPa, CNPb, and CNPc may comprise indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), and indium oxide (InO). x ), Tin oxide (SnO) x Gallium oxide (GaO) x Materials such as zinc alumina (AZO) or zinc aluminum oxide can be used. These can be used alone or in combination with each other. However, this disclosure is not limited thereto, and in another embodiment, the first to third connection patterns CNPa, CNPb, and CNPc may include conductive materials such as metals, alloys, or conductive metal nitrides. In embodiments, the first to third connection patterns CNPa, CNPb, and CNPc may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0249] The first auxiliary connection electrode CCEa may include a first auxiliary electrode connection portion CAa and a first light-emitting connection portion CNa.

[0250] The first auxiliary electrode connection portion CAa can be the part of the first auxiliary connection electrode CCEa that connects to the auxiliary electrode AUE. For example, the location of the first auxiliary electrode connection portion CAa can be such that it exposes the auxiliary electrode AUE and penetrates the fifth insulating layer (IL5, reference). Figure 10 Contact holes (CNT, reference) Figure 10 The position corresponds to the location of ).

[0251] The first light-emitting connection portion CNa can be the portion of the first auxiliary connection electrode CCEa that is connected to the first connection pattern CNPa. For example, the first light-emitting connection portion CNa can be the portion of the first auxiliary connection electrode CCEa that is covered by the sixth insulating layer (IL6, reference). Figure 10 ) and Pixel Confinement Layer (PDL, reference) Figure 10 The portion of the first light-emitting connection portion CNa is exposed to connect to the first connection pattern CNa. Accordingly, the position of the first light-emitting connection portion CNa can be such that it exposes the first auxiliary connection electrode CCEa and penetrates the pixel defining layer PDL and the sixth insulating layer IL6 through a sub-opening (OP, reference) Figure 10 The positions of the first light-emitting connection portion CNa and the first emitting region EAa are corresponding. In the plan view, the first light-emitting connection portion CNa may not overlap with the first emitting region EAa. For example, in the plan view, the first light-emitting connection portion CNa may be arranged between the first emitting region EAa and the separator SPR.

[0252] The first connection pattern CNPa can be connected to the first auxiliary connection electrode CCEa. For example, the first connection pattern CNPa can contact the first light-emitting connection portion CNa of the first auxiliary connection electrode CCEa. However, this disclosure is not limited thereto, and the first connection pattern CNPa may not directly contact the first auxiliary connection electrode CCEa. For example, the first connection pattern CNPa can contact a capping layer (which contacts the first light-emitting connection portion CNa of the first auxiliary connection electrode CCEa), and can be electrically connected to the first light-emitting connection portion CNa of the first auxiliary connection electrode CCEa through the capping layer. The capping layer may include a conductive material. For example, the capping layer and the first electrode E1 can be formed substantially simultaneously and can include the same material.

[0253] The first connection pattern CNPa may not overlap with the first emitter region EAa in the plan view. In an embodiment, the first connection pattern CNPa may surround at least a portion of the first emitter region EAa in the plan view. For example, as... Figure 9 As shown, the first connection pattern CNPa may surround a portion of the first emitter region EAa in a plan view, but may not surround other portions of the first emitter region EAa. However, this disclosure is not limited thereto. In another embodiment, the first connection pattern CNPa may completely surround the first emitter region EAa in a plan view, and the first connection pattern CNPa may have a closed-loop shape completely surrounding the first emitter region EAa in a plan view.

[0254] The second electrode E2 of the first light-emitting element LTa can be connected to the first connection pattern CNPa. For example, the second electrode E2 of the first light-emitting element LTa can contact the first connection pattern CNPa. Accordingly, the first connection pattern CNPa can electrically connect the first auxiliary connection electrode CCEa and the second electrode E2 of the first light-emitting element LTa. As a result, the second electrode E2 of the first light-emitting element LTa can be electrically connected to the auxiliary electrode AUE through the first auxiliary connection electrode CCEa and the first connection pattern CNPa.

[0255] In an embodiment, the second electrode E2 of the first light-emitting element LTa and the first connection pattern CNPa can be in contact with each other at a position in the plan view that does not overlap with the first emitting region EAa. Accordingly, the second electrode E2 of the first light-emitting element LTa can be electrically connected to the auxiliary electrode AUE through the first connection pattern CNPa and the first auxiliary connection electrode CCEa without reducing the size of the first emitting region EAa.

[0256] The second auxiliary connection electrode CCEb may include a second auxiliary electrode connection portion CAb and a second light-emitting connection portion CNb.

[0257] The second auxiliary electrode connection portion CAb can be the part of the second auxiliary connection electrode CCEb that connects to the auxiliary electrode AUE. For example, the position of the second auxiliary electrode connection portion CAb can correspond to the position of the contact hole that exposes the auxiliary electrode AUE and penetrates the fifth insulating layer IL5.

[0258] The second light-emitting connection portion CNb can be the portion of the second auxiliary connection electrode CCEb that connects to the second connection pattern CNPb. For example, the second light-emitting connection portion CNb can be the portion of the second auxiliary connection electrode CCEb exposed by the sixth insulating layer IL6 and the pixel defining layer PDL for connection to the second connection pattern CNPb. Accordingly, the position of the second light-emitting connection portion CNb can correspond to the position of the sub-opening that exposes the second auxiliary connection electrode CCEb and penetrates the pixel defining layer PDL and the sixth insulating layer IL6. In a plan view, the second light-emitting connection portion CNb may not overlap with the second emitting region EAb. For example, in a plan view, the second light-emitting connection portion CNb can be arranged between the second emitting region EAb and the separator SPR.

[0259] In an embodiment, the second auxiliary connection electrode CCEb may be spaced apart from the first auxiliary connection electrode CCEa in a plan view. In other words, the first auxiliary connection electrode CCEa and the second auxiliary connection electrode CCEb may be different electrodes from each other.

[0260] The second connection pattern CNPb can be connected to the second auxiliary connection electrode CCEb. For example, the second connection pattern CNPb can contact the second light-emitting connection portion CNb of the second auxiliary connection electrode CCEb. However, this disclosure is not limited thereto, and the second connection pattern CNPb may not directly contact the second auxiliary connection electrode CCEb. For example, the second connection pattern CNPb can contact a capping layer (which contacts the second light-emitting connection portion CNb of the second auxiliary connection electrode CCEb), and can be electrically connected to the second light-emitting connection portion CNb of the second auxiliary connection electrode CCEb through the capping layer. The capping layer may include a conductive material. For example, the capping layer and the first electrode E1 can be formed substantially simultaneously and can include the same material.

[0261] The second connection pattern CNPb may not overlap with the second emission region EAb in a planar view. In an embodiment, the second connection pattern CNPb may surround at least a portion of the second emission region EAb in a planar view. For example, as... Figure 9 As shown, the second connection pattern CNPb may surround a portion of the second emitter region EAb, and may not surround another portion of the second emitter region EAb. However, this disclosure is not limited thereto, and in another embodiment, the second connection pattern CNPb may have a closed-loop shape that completely surrounds the second emitter region EAb in a plan view.

[0262] In an embodiment, the second connection pattern CNPb can be connected to the first connection pattern CNPa. For example, although not in Figure 8 As illustrated in the diagram, the connecting patterns can be arranged in the area between the separator SPR and the first connecting pattern CNPa and the second connecting pattern CNPb, and the first connecting pattern CNPa and the second connecting pattern CNPb can be connected to each other. However, this disclosure is not limited thereto. In another embodiment, the second connecting pattern CNPb can be spaced apart from the first connecting pattern CNPa. In other words, the first connecting pattern CNPa and the second connecting pattern CNPb can be different patterns from each other.

[0263] The second electrode of the second light-emitting element LDb can be connected to the second connection pattern CNPb. For example, the second electrode of the second light-emitting element LDb can contact the second connection pattern CNPb. Accordingly, the second connection pattern CNPb can electrically connect the second auxiliary connection electrode CCEb and the second electrode of the second light-emitting element LDb. As a result, the second electrode of the second light-emitting element LDb can be electrically connected to the auxiliary electrode AUE through the second auxiliary connection electrode CCEb and the second connection pattern CNPb.

[0264] In an embodiment, the second electrode of the second light-emitting element LDb and the second connection pattern CNPb can be in contact with each other at a position in the plan view that does not overlap with the second emitting region EAb. Accordingly, the second electrode of the second light-emitting element LDb can be electrically connected to the auxiliary electrode AUE through the second connection pattern CNPb and the second auxiliary connection electrode CCEb without reducing the size of the second emitting region EAb.

[0265] The third auxiliary connection electrode CCEc may include a third auxiliary electrode connection portion CAc and a third light-emitting connection portion CNc.

[0266] The third auxiliary electrode connection portion CAc can be the part of the third auxiliary connection electrode CCEc that connects to the auxiliary electrode AUE. For example, the position of the third auxiliary electrode connection portion CAc can correspond to the position of the contact hole that exposes the auxiliary electrode AUE and penetrates the fifth insulating layer IL5.

[0267] The third light-emitting connection portion CNc can be the portion of the third auxiliary connection electrode CCEc that connects to the third connection pattern CNPc. For example, the third light-emitting connection portion CNc can be the portion of the third auxiliary connection electrode CCEc exposed by the sixth insulating layer IL6 and the pixel defining layer PDL for connection to the third connection pattern CNPc. Accordingly, the position of the third light-emitting connection portion CNc can correspond to the position of the sub-opening that exposes the third auxiliary connection electrode CCEc and penetrates the pixel defining layer PDL and the sixth insulating layer IL6. In a plan view, the third light-emitting connection portion CNc may not overlap with the third emitting region EAc. For example, in a plan view, the third light-emitting connection portion CNc can be arranged between the third emitting region EAc and the separator SPR.

[0268] In an embodiment, the third auxiliary connection electrode CCEc may be spaced apart from the first auxiliary connection electrode CCEa and the second auxiliary connection electrode CCEb in a plan view. In other words, the first auxiliary connection electrode CCEa, the second auxiliary connection electrode CCEb, and the third auxiliary connection electrode CCEc may be different electrodes from each other.

[0269] The third connection pattern CNPc can be connected to the third auxiliary connection electrode CCEc. For example, the third connection pattern CNPc can contact the third light-emitting connection portion CNc of the third auxiliary connection electrode CCEc. However, this disclosure is not limited thereto, and the third connection pattern CNPc may not directly contact the third auxiliary connection electrode CCEc. For example, the third connection pattern CNPc can contact the capping layer (which contacts the third light-emitting connection portion CNc of the third auxiliary connection electrode CCEc), and can be electrically connected to the third light-emitting connection portion CNc of the third auxiliary connection electrode CCEc through the capping layer. The capping layer may include a conductive material. For example, the capping layer and the first electrode E1 can be formed substantially simultaneously and can include the same material.

[0270] The third connection pattern CNPc may not overlap with the third emission region EAc in a planar view. In an embodiment, the third connection pattern CNPc may surround at least a portion of the third emission region EAc in a planar view. For example, as... Figure 9 As shown, the third connection pattern CNPc may surround a portion of the third emitter region EAc, and may not surround another portion of the third emitter region EAc. However, this disclosure is not limited thereto, and in another embodiment, the third connection pattern CNPc may have a closed-loop shape that completely surrounds the third emitter region EAc in a plan view.

[0271] In an embodiment, the third connection pattern CNPc can be connected to the first connection pattern CNPa and / or the second connection pattern CNPb. For example, although not in Figure 8As illustrated in the diagram, the connecting patterns can be arranged in the area between the separator SPR and the first connecting pattern CNPa and the third connecting pattern CNPc, and / or between the second connecting pattern CNPb and the third connecting pattern CNPc, and the third connecting pattern CNPc can be connected to the first connecting pattern CNPa and / or the second connecting pattern CNPb. However, this disclosure is not limited thereto. In another embodiment, the third connecting pattern CNPc can be spaced apart from the first connecting pattern CNPa and the second connecting pattern CNPb. In other words, the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc can be different patterns from each other.

[0272] The second electrode of the third light-emitting element LDc can be connected to the third connection pattern CNPc. For example, the second electrode of the third light-emitting element LDc can contact the third connection pattern CNPc. Accordingly, the third connection pattern CNPc can electrically connect the third auxiliary connection electrode CCEc and the second electrode of the third light-emitting element LDc. As a result, the second electrode of the third light-emitting element LDc can be electrically connected to the auxiliary electrode AUE through the third auxiliary connection electrode CCEc and the third connection pattern CNPc.

[0273] In an embodiment, the second electrode of the third light-emitting element LDc and the third connection pattern CNPc can be in contact with each other at a position in the plan view that does not overlap with the third emitting region EAc. Accordingly, the second electrode of the third light-emitting element LDc can be electrically connected to the auxiliary electrode AUE through the third connection pattern CNPc and the third auxiliary connection electrode CCEc without reducing the size of the third emitting region EAc.

[0274] like Figure 8 As shown, for each of the first unit transmitter regions UEA1, the shape or arrangement of each of the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, as well as the arrangement relationship between the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, can be the same. For each of the second unit transmitter regions UEA2, the shape or arrangement of each of the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, as well as the arrangement relationship between the first auxiliary connection electrodes to the third auxiliary connection electrodes CCEa, CCEb, and CCEc, can be the same.

[0275] For each first unit transmission area UEA1, the shape or arrangement of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the arrangement relationship between the first to third connection patterns CNPa, CNPb, and CNPc, can be the same. For each second unit transmission area UEA2, the shape or arrangement of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the arrangement relationship between the first to third connection patterns CNPa, CNPb, and CNPc, can be the same.

[0276] As described above, the display device DD1-2 may include a separator SPR. The separator SPR may overlap with the first to third connection patterns CNPa, CNPb, and CNPc in a plan view. For example, the separator SPR may cover a portion of each of the first to third connection patterns CNPa, CNPb, and CNPc. For example, at least a portion of the separator SPR may extend along the edge of each of the first to third connection patterns CNPa, CNPb, and CNPc in a plan view. Accordingly, the area where the second electrodes of the first to third light-emitting elements LDa, LDb, and LDc contact the first to third connection patterns CNPa, CNPb, and CNPc may be adjacent to or overlap with the area where the separator SPR is disposed in a plan view.

[0277] In the following text, the cross-sectional structure of the display device DD1-2 will be described in more detail with the first emission zone EAa as the focus. The following description of the cross-sectional structure of the display device DD1-2 can be applied substantially equivalently to all emission zones.

[0278] like Figure 10 As shown, the display device DD1-2 may include a substrate SUB, a first bottom conductive layer BML1, a second bottom conductive layer BML2, a first transistor TR1, a first capacitor CAP1, a second capacitor CAP2, an auxiliary electrode AUE, an anode connection electrode ACE, a first auxiliary connection electrode CCEa, first to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a first light-emitting element LDA, an organic film pattern OGP, a first connection pattern CNPa, a separator SPR, a first dummy layer DP1, a second dummy layer DP2, and an encapsulation layer ENC. The first light-emitting element LDA may include a first electrode E1, an intermediate layer ML, and a second electrode E2. In the following text, the above references... Figure 5 The redundant description of the display device DD1 may be omitted or summarized.

[0279] The auxiliary electrode AUE can be disposed in the display area DA, on the fourth insulating layer IL4. The auxiliary electrode AUE can contact the second bottom conductive layer BML2. The auxiliary electrode AUE can be spaced apart from the first electrode E1. Second power voltage (ELVSS, reference) Figure 2 It can be applied to the auxiliary electrode AUE.

[0280] The first auxiliary connection electrode CCEa can be disposed in the display area DA on the fifth insulating layer IL5. As described above, the first auxiliary connection electrode CCEa can be connected to the auxiliary electrode AUE. For example, the first auxiliary connection electrode CCEa can contact the auxiliary electrode AUE through a contact hole CNT penetrating the fifth insulating layer IL5. Accordingly, the position of the first auxiliary electrode connection portion CAa can correspond to the position of the contact hole CNT. In an embodiment, the first auxiliary connection electrode CCEa can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0281] The anode connection electrode ACE can be disposed on the fifth insulating layer IL5. The anode connection electrode ACE can contact the second contact electrode DE1 and the first electrode E1. Accordingly, the anode connection electrode ACE can electrically connect the first transistor TR1 and the first light-emitting element LDa.

[0282] The sixth insulating layer IL6 may cover the anode connection electrode ACE and may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may partially cover the first auxiliary connection electrode CCEa and may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may define a first sub-opening SO1 that exposes at least a portion of the first auxiliary connection electrode CCEa.

[0283] The first electrode E1 can be disposed on the sixth insulating layer IL6. The first electrode E1 can contact the anode connection electrode ACE. Accordingly, the first electrode E1 can be electrically connected to the first transistor TR1 through the anode connection electrode ACE.

[0284] A pixel defining layer (PDL) may be disposed on a sixth insulating layer (IL6) and a first electrode (E1). The PDL may define a pixel opening that exposes at least a portion of the first electrode (E1). A first emitter region (EAa) may be defined by the pixel opening.

[0285] The pixel-defining layer PDL can further define a second sub-opening SO2 corresponding to a first sub-opening SO1 of the sixth insulating layer IL6. The second sub-opening SO2 can overlap with the first sub-opening SO1 in a plan view, and the first and second sub-openings SO1 and SO2 can be spatially connected to each other. For example, the first and second sub-openings SO1 and SO2 can be connected to define a sub-opening OP. The sub-opening OP can expose at least a portion of the first auxiliary connection electrode CCEa.

[0286] An organic film pattern (OGP) can be disposed in the display area (DA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the display area (DA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, the upper surface of the organic film pattern (OGP) can be an upwardly convex curved surface. The organic film pattern (OGP) can include an organic material. In an embodiment, the organic film pattern (OGP) and the pixel defining layer (PDL) can include different materials.

[0287] The first connection pattern CNPa can be disposed on the first auxiliary connection electrode CCEa, the sixth insulating layer IL6, and the pixel defining layer PDL. As described above, the first connection pattern CNPa can be connected to the first auxiliary connection electrode CCEa. The first connection pattern CNPa can be connected to the first auxiliary connection electrode CCEa through a sub-opening OP that penetrates the sixth insulating layer IL6 and the pixel defining layer PDL. Accordingly, the position of the first light-emitting connection portion CNa can correspond to the position of the sub-opening OP.

[0288] In one embodiment, the first connection pattern CNPa may include a transparent conductive oxide. However, this disclosure is not limited thereto, and in another embodiment, the first connection pattern CNPa may include a conductive material such as a metal, alloy, conductive metal oxide, or conductive metal nitride. In another embodiment, the first connection pattern CNPa may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0289] In one embodiment, a portion of the first connection pattern CNPa may be arranged along the contours of the pixel defining layer PDL and the organic film pattern OGP, and this portion of the first connection pattern CNPa may cover the organic film pattern OGP. However, this disclosure is not limited thereto, and in another embodiment, the first connection pattern CNPa may expose at least a portion of the upper surface of the organic film pattern OGP.

[0290] In an embodiment, the first connection pattern CNPa can be arranged along the contour of the pixel defining layer PDL, and the organic film pattern OGP can be arranged on the first connection pattern CNPa. The first portion SPP1 of the separator SPR can contact and cover the organic film pattern OGP, and the first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface can contact the first connection pattern CNPa.

[0291] The separator SPR can be arranged on the pixel-defining layer PDL and the first connection pattern CNPa. The separator SPR can overlap with the first connection pattern CNPa in the planar view. For example, the separator SPR can cover a portion of the first connection pattern CNPa.

[0292] The side surface of the separator SPR that connects the upper and lower surfaces of the separator SPR may have a reverse tapering slope. In other words, at least a portion of the cross-section of the separator SPR may be an inverted trapezoid.

[0293] In an embodiment, such as Figure 10 As shown, the side surface of the separator SPR can have multiple reverse tapered ramps. For example, the separator SPR can have a double reverse tapered structure. Accordingly, it is easier to separate (or disconnect) the separator SPR from the electrode layer E2L.

[0294] The separator SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1. The first portion SPP1 of the separator SPR may overlap with the organic membrane pattern OGP in a planar view, and the second portion SPP2 of the separator SPR may be spaced apart from the organic membrane pattern OGP in a planar view. In other words, the second portion SPP2 of the separator SPR may not overlap with the organic membrane pattern OGP in a planar view. In an embodiment, the first portion SPP1 of the separator SPR may cover a portion of the first connection pattern CNPa, and the first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface may contact the first connection pattern CNPa.

[0295] Since the organic film pattern OGP is arranged between the pixel defining layer PDL and the first portion SPP1 of the separator SPR, the upper surface of the first portion SPP1 of the separator SPR can have an upwardly convex curved surface. In an embodiment, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Accordingly, the mask used in the process of forming the intermediate layer ML can contact the first portion SPP1 of the separator SPR, but can not contact the second portion SPP2 of the separator SPR. As a result, the phenomenon of mask pressing that may occur when the area of ​​the separator SPR in contact with the mask is large can be suppressed.

[0296] The intermediate layer ML can be disposed on the first electrode E1, the pixel defining layer PDL, and the first connection pattern CNPa. A portion of the intermediate layer ML can be disposed in the pixel opening of the pixel defining layer PDL.

[0297] The shadowed area where the intermediate layer ML is difficult to deposit can exist around the separator SPR with a reverse tapered slope. Accordingly, the intermediate layer ML can be separated (or disconnected) by the separator SPR in and / or around the shadowed area. When the intermediate layer ML is separated (or disconnected), a portion of the first connection pattern CNPa can be exposed at a location adjacent to or overlapping with the separator SPR. Accordingly, the second electrode E2 of the first light-emitting element LDa can contact the first connection pattern CNPa.

[0298] Electrode layer E2L can be disposed on intermediate layer ML. In one embodiment, electrode layer E2L can have a single-layer structure. However, this disclosure is not limited thereto, and in another embodiment, electrode layer E2L can have a multilayer structure in which multiple conductive layers are stacked on top of each other. For example, electrode layer E2L can have a two-layer structure comprising a first sub-electrode layer containing metal and a second sub-electrode layer disposed on the first sub-electrode layer and comprising a transparent conductive oxide.

[0299] The shadowed areas where it is difficult to deposit the electrode layer E2L can exist around the separator SPR with a reverse tapered slope. Within and / or around the shadowed areas, the electrode layer E2L can be separated (or disconnected) by the separator SPR. For example, the electrode layer E2L can be separated (or disconnected) into the second electrode E2 of the first light-emitting element LTa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc. For example, the second electrodes E2 of the first light-emitting element LTa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc can be electrically independent of each other.

[0300] like Figure 10As shown, electrode layer E2L (e.g., second electrode E2) can contact the first connection pattern CNPa. For example, the second electrode E2 can contact the first connection pattern CNPa at a location adjacent to or overlapping with the separator SPR. In other words, electrode layer E2L (e.g., second electrode E2) can contact the first connection pattern CNPa in the area overlapping with the separator SPR in the planar view. For example, if the deposition angle of the deposition process used to form electrode layer E2L is greater than the deposition angle of the deposition process used to form intermediate layer ML, electrode layer E2L (e.g., second electrode E2) can be formed to cover the side of the disconnected intermediate layer ML and contact the first connection pattern CNPa. As a result, the second electrode E2 can be electrically connected to the auxiliary electrode AUE through the first connection pattern CNPa and the first auxiliary connection electrode CCEa. Accordingly, the second electrode E2 can receive a second power voltage (ELVSS, reference) from the auxiliary electrode AUE. Figure 2 ).

[0301] The encapsulation layer ENC can be disposed on the electrode layer E2L. The encapsulation layer ENC can completely cover the electrode layer E2L, the connection patterns CNPa, CNPb and CNPc, the separator SPR, the first dummy layer DP1 and the second dummy layer DP2.

[0302] According to an embodiment, the display device DD1-2 may include auxiliary connection electrodes CCEa, CCEb, and CCEc, connection patterns CNPa, CNPb, and CNPc, and a separator SPR. Accordingly, the electrode layer E2L (e.g., a cathode) can be easily electrically connected to the auxiliary electrode AUE via the auxiliary connection electrodes CCEa, CCEb, and CCEc and the connection patterns CNPa, CNPb, and CNPc. Accordingly, the electrode layer E2L can receive a second power voltage (ELVSS, reference 'AUE') from the auxiliary electrode AUE. Figure 2 It can also suppress the voltage drop phenomenon of the voltage supplied to the electrode layer E2L.

[0303] Figure 11 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken from line III-III'. Figure 12 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken from line III-III'.

[0304] refer to Figure 11 and Figure 12The display device DD1-2 according to an embodiment of the present disclosure may include a substrate SUB, a second bottom conductive layer BML2, a first capacitor CAP1, a second capacitor CAP2, an auxiliary electrode AUE, an auxiliary connection electrode CCE, a first insulating layer to a sixth insulating layer IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a connection pattern CNP, an intermediate layer ML, an electrode layer E2L, an organic film pattern OGP, a separator SPR and an encapsulation layer ENC.

[0305] An organic film pattern (OGP) can be disposed in the peripheral area (NDA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the peripheral area (NDA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, as... Figure 11 As shown, the upper surface of the organic film pattern OGP can be an upwardly convex curved surface. However, this disclosure is not limited thereto, and in another embodiment, as... Figure 12 As shown, the organic membrane patterned OGP can have a substantially flat upper surface. The organic membrane patterned OGP can include organic materials.

[0306] The connection pattern CNP can be arranged in the peripheral area NDA and on the pixel-defining layer PDL. In an embodiment, as shown... Figure 11 As shown, the connection pattern CNP can be spaced apart from the organic film pattern OGP in the peripheral region NDA and can contact the upper surface of the pixel defining layer PDL. However, this disclosure is not limited thereto, and in another embodiment, as Figure 12 As shown, the connecting pattern CNP can be arranged on the organic film pattern OGP and can contact the upper surface of the organic film pattern OGP.

[0307] The separator SPR can be disposed on the pixel-defining layer PDL. The separator SPR can contact the organic film pattern OGP and the connecting pattern CNP in the peripheral region NDA. In an embodiment, as... Figure 11 As shown, in the peripheral region NDA, the organic film pattern OGP may overlap with a portion of the separator SPR in a planar view. For example, in the peripheral region NDA, the organic film pattern OGP may overlap with a first side surface of the separator SPR in a planar view. If the upper surface of the organic film pattern OGP includes an upwardly convex curved surface, the upper surface of the separator SPR may also include an upwardly convex curved surface. However, this disclosure is not limited thereto. In embodiments, as... Figure 12 As shown, in the peripheral region NDA, the organic membrane pattern OGP can overlap with the entire separator SPR in a planar view. When the organic membrane pattern OGP has a substantially flat upper surface, the separator SPR can also have a substantially flat upper surface.

[0308] In an embodiment, such as Figure 11 and Figure 12 As shown, the cross-sectional shape of a portion of the separator SPR may be asymmetrical in the peripheral region NDA. For example, the first side surface of this portion of the separator SPR may contact the organic film pattern OGP in the peripheral region NDA, and the second side surface opposite to the first side surface may contact the connecting pattern CNP. Therefore, in the process of forming the separator SPR, the difference in the characteristics between the organic film pattern OGP and the connecting pattern CNP may lead to a difference in the degree of inclination of the first side surface and the second side surface.

[0309] The second side surface of the separator SPR can have a reverse tapered slope. For example, the second side surface of the separator SPR can have multiple reverse tapered slopes. Because the second side surface of the separator SPR has a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can be separated (or disconnected) in the display area DA.

[0310] In contrast, the first side surface of the separator SPR may not have a reverse tapered slope.

[0311] like Figure 11 As shown, by forming an organic film pattern OGP in the peripheral region NDA that overlaps with the first side surface of the separator SPR in the plan view, the first side surface of the separator SPR may not have a reverse tapered slope.

[0312] like Figure 12 As shown, when the first side surface of the separator SPR contacts the organic film pattern OGP having a substantially flat upper surface, the first side surface of the separator SPR may not have a reverse tapered slope. The organic film pattern OGP and the pixel defining layer PDL may comprise different materials. For example, the organic film pattern OGP may comprise a polystyrene-based resin and / or a polyimide-based resin. However, this disclosure is not limited thereto.

[0313] Since the first side surface of the separator SPR does not have a reverse tapering slope, the intermediate layer ML and the electrode layer E2L can be formed as an extension in the peripheral region NDA without being broken.

[0314] Figure 13 This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present disclosure. For example, Figure 13 The cross-sectional structure of the display device DD1-3 is schematically illustrated with the emission area EA, which is included in the display area DA, as the center. The following description of the cross-sectional structure of the display device DD1-3 can be applied substantially equivalently to all emission areas.

[0315] refer to Figure 13The display device DD1-3 according to embodiments of the present disclosure may include a substrate SUB, a first bottom conductive layer BML1, a second bottom conductive layer BML2, a first transistor TR1, a first capacitor CAP1, a second capacitor CAP2, an auxiliary electrode AUE, an anode connection electrode ACE, an auxiliary connection electrode CCE, a first insulating layer to a sixth insulating layer IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a light-emitting element LD, an organic film pattern OGP, a connection pattern CNP', a separator SPR, a first dummy layer DP1, a second dummy layer DP2 and an encapsulation layer ENC. The light-emitting element LD may include a first electrode E1, an intermediate layer ML and a second electrode E2.

[0316] Reference above Figures 7 to 12 Compared to the described display device DD1-2, the display device DD1-3 may include a connection pattern CNP' that contacts the auxiliary connection electrode CCE in the area overlapping with the separator SPR in a plan view. In other words, the light-emitting connection portion CN of the contact connection pattern CNP' of the auxiliary connection electrode CCE may overlap with the separator SPR in a plan view. In the following text, the above references... Figures 7 to 12 The redundant description of the display device DD1-2 may be omitted or summarized.

[0317] The auxiliary electrode AUE can be disposed on the fourth insulating layer IL4. The auxiliary electrode AUE can contact the second bottom conductive layer BML2. The auxiliary electrode AUE can be spaced apart from the first electrode E1. Second power voltage (ELVSS, reference) Figure 2 It can be applied to the auxiliary electrode AUE.

[0318] The auxiliary connection electrode CCE can be disposed on the fifth insulating layer IL5. The auxiliary connection electrode CCE can be connected to the auxiliary electrode AUE. For example, the auxiliary connection electrode CCE can contact the auxiliary electrode AUE through a first contact hole CNT1 penetrating the fifth insulating layer IL5. Accordingly, the position of the auxiliary electrode connection portion CA can correspond to the position of the first contact hole CNT1. In an embodiment, the auxiliary connection electrode CCE can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0319] The sixth insulating layer IL6 can cover the anode connection electrode ACE and the auxiliary connection electrode CCE, and can be arranged on the fifth insulating layer IL5.

[0320] A pixel defining layer (PDL) may be disposed on a sixth insulating layer (IL6) and a first electrode (E1). The PDL may define a pixel opening that exposes at least a portion of the first electrode (E1). An emitter region (EA) may be defined by the pixel opening.

[0321] An organic film pattern (OGP) can be disposed in the display area (DA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the display area (DA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, the upper surface of the organic film pattern (OGP) can be an upwardly convex curved surface. In an embodiment, the organic film pattern (OGP) and the pixel defining layer (PDL) can include different materials.

[0322] The connection pattern CNP' can be arranged on the pixel defining layer PDL. The connection pattern CNP' can be connected to the auxiliary connection electrode CCE. For example, the connection pattern CNP' can be connected to the auxiliary connection electrode CCE through the second contact hole CNT2 that penetrates the sixth insulating layer IL6 and the pixel defining layer PDL. Accordingly, the position of the light-emitting connection portion CN can correspond to the position of the second contact hole CNT2.

[0323] In one embodiment, the connection pattern CNP' may include a transparent conductive oxide. However, this disclosure is not limited thereto, and in another embodiment, the connection pattern CNP' may include a conductive material such as a metal, alloy, conductive metal oxide, or conductive metal nitride.

[0324] In an embodiment, the connection pattern CNP' may be arranged along the contours of the pixel defining layer PDL and the organic film pattern OGP, and the connection pattern CNP' may cover the organic film pattern OGP. However, this disclosure is not limited thereto.

[0325] In this embodiment, the organic membrane pattern OGP can be disposed on the connecting pattern CNP'. The first portion SPP1 of the separator SPR can contact and cover the organic membrane pattern OGP. The first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface can contact the connecting pattern CNP'.

[0326] The separator SPR can be arranged on the pixel-defined layer PDL and the connection pattern CNP'. The separator SPR can overlap with the connection pattern CNP' in the planar view. For example, the separator SPR can cover a portion of the connection pattern CNP'.

[0327] The side surface of the separator SPR that connects the upper and lower surfaces of the separator SPR may have a reverse tapering slope. In an embodiment, such as Figure 13 As shown, the side surface of the separator SPR can have multiple reverse tapered ramps. For example, the separator SPR can have a double reverse tapered structure. Accordingly, it is easier to separate (or disconnect) the separator SPR from the electrode layer E2L.

[0328] The separator SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1. The first portion SPP1 of the separator SPR may overlap with the organic membrane pattern OGP in a planar view, and the second portion SPP2 of the separator SPR may be spaced apart from the organic membrane pattern OGP in a planar view. In other words, the second portion SPP2 of the separator SPR may not overlap with the organic membrane pattern OGP in a planar view. In an embodiment, the first portion SPP1 of the separator SPR may cover a portion of the connecting pattern CNP', and the first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface may contact the connecting pattern CNP'.

[0329] Since the organic film pattern OGP is arranged between the pixel defining layer PDL and the first portion SPP1 of the separator SPR, the upper surface of the first portion SPP1 of the separator SPR can be an upwardly convex curved surface. In an embodiment, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Accordingly, the mask used in the process of forming the intermediate layer ML can contact the first portion SPP1 of the separator SPR, but can not contact the second portion SPP2 of the separator SPR. As a result, the phenomenon of mask pressing that may occur when the area of ​​the separator SPR in contact with the mask is large can be suppressed.

[0330] In an embodiment, the connection pattern CNP' can contact the auxiliary connection electrode CCE in the area overlapping with the separator SPR in the planar view. In other words, the light-emitting connection portion CN can overlap with the separator SPR in the planar view. (Refer to the above...) Figure 10 In the described display device DD1-2, the first light-emitting connection portion CNa is spaced apart from the separator SPR in the plan view, while in the reference... Figure 13 In the described display device DD1-3, the light-emitting connection portion CN can overlap with the separator SPR in the plan view. For example, the area for contacting the auxiliary connection electrode CCE and the connection pattern CNP' is not required. Accordingly, the constraints on the design of the emission area due to the connection pattern CNP' can be reduced. As a result, the degree of freedom in the design of the emission area can be increased, and the size of the emission area (i.e., the aperture ratio) can be further increased.

[0331] Electrode layer E2L can be disposed on intermediate layer ML. Shaded areas where electrode layer E2L is difficult to deposit can exist around separator SPR with reverse taper slope. In and / or around the shaded areas, electrode layer E2L can be separated (or disconnected) by separator SPR.

[0332] Electrode layer E2L (e.g., second electrode E2) can contact connection pattern CNP'. For example, electrode layer E2L (e.g., second electrode E2) can contact connection pattern CNP' at a location adjacent to or overlapping with separator SPR. In other words, electrode layer E2L (e.g., second electrode E2) can contact connection pattern CNP' in the area overlapping with separator SPR in the plan view. Electrode layer E2L (e.g., second electrode E2) can be formed to cover the side of the disconnected intermediate layer ML and contact connection pattern CNP'. As a result, second electrode E2 can be electrically connected to auxiliary electrode AUE through connection pattern CNP' and auxiliary connection electrode CCE. Accordingly, second electrode E2 can receive a second power voltage (ELVSS, reference) from auxiliary electrode AUE. Figure 2 ).

[0333] Figure 14 It is a diagram. Figure 13 A schematic cross-sectional view of a display device. For example, Figure 14 The cross-sectional structure of the display device DD1-3 in the peripheral area NDA adjacent to the display area DA is schematically illustrated.

[0334] refer to Figure 14 The display device DD1-3 according to embodiments of the present disclosure may include a substrate SUB, a first bottom conductive layer BML1, a first transistor TR1, an anode connection electrode ACE, first to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a light-emitting element LD, a connection pattern CNP', an electrode layer E2L, an organic film pattern OGP, a separator SPR, and an encapsulation layer ENC. The electrode layer E2L may include a second electrode E2. The light-emitting element LD may include a first electrode E1, an intermediate layer ML, and a second electrode E2.

[0335] The cross-sectional structure of the display device DD1-3 in the peripheral region NDA can be compared with the above reference. Figure 11 and Figure 12 The cross-sectional structure of the described display device DD1-2 in the peripheral region NDA is basically the same.

[0336] In an embodiment, such as Figure 11 and Figure 14As shown, the organic film pattern OGP can be disposed in the peripheral region NDA between the pixel defining layer PDL and the separator SPR, and the upper surface of the organic film pattern OGP can be an upwardly convex curved surface. The connecting pattern CNP' can be spaced apart from the organic film pattern OGP in the peripheral region NDA and can contact the upper surface of the pixel defining layer PDL. The separator SPR can be disposed in the peripheral region NDA on the pixel defining layer PDL, and the organic film pattern OGP can overlap a portion of the separator SPR in a planar view. For example, in the peripheral region NDA, the organic film pattern OGP can overlap with a first side surface of the separator SPR in a planar view. Since the upper surface of the organic film pattern OGP is an upwardly convex curved surface, the upper surface of the separator SPR can also be an upwardly convex curved surface. However, this disclosure is not limited thereto.

[0337] In an embodiment, such as Figure 12 As shown, the organic film pattern OGP can have a substantially flat upper surface in the peripheral region NDA. The connecting pattern CNP' can be disposed on the organic film pattern OGP and can contact the upper surface of the organic film pattern OGP. The separator SPR can be disposed in the peripheral region NDA, on the pixel defining layer PDL, and the organic film pattern OGP can overlap with the entire separator SPR in the planar view. Because the organic film pattern OGP has a substantially flat upper surface, the separator SPR can also have a substantially flat upper surface.

[0338] The cross-sectional shape of a portion of the separator SPR can be asymmetrical within the peripheral region NDA. For example, the first side surface of this portion of the separator SPR may contact the organic film pattern OGP within the peripheral region NDA, and the second side surface opposite the first side surface may contact the connecting pattern CNP'. Therefore, during the process of forming the separator SPR, the difference in characteristics between the organic film pattern OGP and the connecting pattern CNP' can lead to a difference in the degree of inclination between the first and second side surfaces.

[0339] The second side surface of the separator SPR can have a reverse tapered slope. For example, the second side surface of the separator SPR can have multiple reverse tapered slopes. Because the second side surface of the separator SPR has a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can be separated (or disconnected) in the display area DA.

[0340] In contrast, the first side surface of the separator SPR may not have a reverse tapered slope. Because the first side surface of the separator SPR does not have a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can be formed as an extension in the peripheral region NDA without being broken.

[0341] Figure 15This is a schematic cross-sectional view illustrating a display device according to an embodiment of the present disclosure. For example, Figure 15 The cross-sectional structure of the display device DD2 is schematically illustrated with the peripheral area NDA adjacent to the display area DA as the center.

[0342] refer to Figure 15 According to embodiments of the present disclosure, the display device DD2 may include a substrate SUB, a first bottom conductive layer BML1, a second bottom conductive layer BML2, a first transistor TR1, a first capacitor CAP1, a second capacitor CAP2, an auxiliary electrode AUE', an anode connection electrode ACE, an auxiliary connection electrode CCE', a first insulating layer to a sixth insulating layer IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a light-emitting element LD, an organic film pattern OGP, a connection pattern CNP", a separator SPR, a first dummy layer DP1, an electrode layer E2L, a second dummy layer DP2 and an encapsulation layer ENC. The electrode layer E2L may include a second electrode E2 and a dummy electrode DME spaced apart from the second electrode E2. The light-emitting element LD may include a first electrode E1, an intermediate layer ML and a second electrode E2.

[0343] Reference above Figures 7 to 10 Unlike the described display devices DD1-2, display device DD2 may include an auxiliary electrode AUE' and an auxiliary connection electrode CCE' arranged in the peripheral region NDA, and may further include a dummy electrode DME in the peripheral region NDA that contacts the auxiliary connection electrode CCE'. In the following text, the above references... Figures 7 to 10 The redundant description of the display device DD1-2 may be omitted or summarized.

[0344] The auxiliary electrode AUE' can be disposed in the peripheral region NDA on the substrate SUB. For example, the auxiliary electrode AUE' can be disposed in the peripheral region NDA on the fourth insulating layer IL4. The auxiliary electrode AUE' can contact the second bottom conductive layer BML2. The auxiliary electrode AUE' can be spaced apart from the first electrode E1. Second power voltage (ELVSS, reference) Figure 2 It can be applied to the auxiliary electrode AUE'.

[0345] An auxiliary connection electrode CCE' can be disposed on the auxiliary electrode AUE'. For example, the auxiliary connection electrode CCE' can be disposed in the peripheral region NDA, on the fifth insulating layer IL5. The auxiliary connection electrode CCE' can be electrically connected to the auxiliary electrode AUE'. For example, the auxiliary connection electrode CCE' can contact the auxiliary electrode AUE' through a contact hole CNT penetrating the fifth insulating layer IL5. Accordingly, the position of the auxiliary electrode connection portion CA can correspond to the position of the contact hole CNT. In an embodiment, the auxiliary connection electrode CCE' can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0346] The sixth insulating layer IL6 may partially cover the auxiliary connection electrode CCE' and may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may define a first sub-opening SO1' that exposes at least a portion of the auxiliary connection electrode CCE'.

[0347] A pixel defining layer (PDL) can be disposed on a substrate (SUB) and can define a pixel opening that exposes the first electrode (E1). For example, the pixel defining layer (PDL) can be disposed on a sixth insulating layer (IL6) and the first electrode (E1) and can define a pixel opening that exposes at least a portion of the first electrode (E1). The emitter region (EA) can be defined by the pixel opening.

[0348] The pixel-defining layer (PDL) can further define a second sub-opening (SO2') corresponding to the first sub-opening (SO1') of the sixth insulating layer (IL6). The second sub-opening (SO2') can overlap with the first sub-opening (SO1') in a plan view, and the first and second sub-openings (SO1' and SO2') can be spatially connected to each other. For example, the first and second sub-openings (SO1' and SO2') can be connected to define a sub-opening (OP'). The sub-opening (OP') can expose at least a portion of the auxiliary connection electrode (CCE') in the peripheral region (NDA).

[0349] An organic film pattern OGP can be disposed in the peripheral area NDA and on the pixel defining layer PDL. Although not shown, the organic film pattern OGP can be disposed in the display area DA and on the pixel defining layer PDL. The organic film pattern OGP can be disposed between the pixel defining layer PDL and the separator SPR. In an embodiment, the upper surface of the organic film pattern OGP can be an upwardly convex curved surface. The organic film pattern OGP can include an organic material.

[0350] The connection pattern "CNP" can be disposed on the pixel defining layer PDL. For example, the connection pattern "CNP" can be disposed between the pixel defining layer PDL and the separator SPR. The connection pattern "CNP" can be electrically connected to the auxiliary connection electrode CCE' via the dummy electrode DME described below. In an embodiment, the connection pattern "CNP" can be disposed along the contour of the pixel defining layer PDL and the organic film pattern OGP, and the connection pattern "CNP" can cover the organic film pattern OGP. However, this disclosure is not limited thereto. In an embodiment, the organic film pattern OGP can be disposed on the connection pattern "CNP". The first portion SPP1 of the separator SPR can contact the organic film pattern OGP and can cover the organic film pattern OGP. The first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface can contact the connection pattern "CNP".

[0351] The separator SPR can be arranged on the pixel-defined layer PDL and the connection pattern CNP". The separator SPR can overlap with the connection pattern CNP" in the planar view. For example, the separator SPR can cover a portion of the connection pattern CNP".

[0352] The side surface of the separator SPR that connects the upper and lower surfaces of the separator SPR may have a reverse tapering slope. In other words, at least a portion of the cross-section of the separator SPR may be an inverted trapezoid. In an embodiment, such as Figure 15 As shown, the side surface of the separator SPR can have multiple reverse tapered ramps.

[0353] In an embodiment, such as Figure 15 As shown, the cross-sectional shape of the separator SPR can be symmetrical in the peripheral region NDA. For example, the first side surface of the separator SPR and the second side surface opposite to the first side surface can both contact the connecting pattern CNP in the peripheral region NDA. Both the first and second side surfaces of the separator SPR can have multiple reverse tapered slopes. Because the first and second side surfaces of the separator SPR have multiple reverse tapered slopes, the intermediate layer ML and the electrode layer E2L can be separated (or disconnected) in the display region DA and the peripheral region NDA.

[0354] The separator SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1. The first portion SPP1 of the separator SPR may overlap with the organic film pattern OGP in a plan view, and the second portion SPP2 of the separator SPR may be spaced apart from the organic film pattern OGP in a plan view. In other words, the second portion SPP2 of the separator SPR may not overlap with the organic film pattern OGP in a plan view. In an embodiment, the first portion SPP1 of the separator SPR may cover a portion of the connecting pattern CNP, and the first side surface of the first portion SPP1 of the separator SPR and the second side surface opposite to the first side surface may contact the connecting pattern CNP.

[0355] Since the organic film pattern OGP is arranged between the pixel defining layer PDL and the first portion SPP1 of the separator SPR, the upper surface of the first portion SPP1 of the separator SPR can be an upwardly convex curved surface. In an embodiment, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Accordingly, the mask used in the process of forming the intermediate layer ML can contact the first portion SPP1 of the separator SPR, but can not contact the second portion SPP2 of the separator SPR. As a result, the phenomenon of mask pressing that may occur when the area of ​​the separator SPR in contact with the mask is large can be suppressed.

[0356] The intermediate layer ML can be disposed on the first electrode E1, the pixel defining layer PDL, and the connection pattern CNP". A portion of the intermediate layer ML can be disposed in the pixel opening of the pixel defining layer PDL.

[0357] Shaded areas where the intermediate layer ML is difficult to deposit can exist around the separator SPR with a reverse tapered slope. Accordingly, the intermediate layer ML can be separated (or disconnected) by the separator SPR in and / or around the shaded area. With the intermediate layer ML separated (or disconnected), a portion of the connection pattern CNP can be exposed at a location adjacent to or overlapping with the separator SPR. Accordingly, the second electrode E2 and the dummy electrode DME of the light-emitting element LD can contact the connection pattern CNP.

[0358] The electrode layer E2L can be disposed on the auxiliary connection electrode CCE', the pixel defining layer PDL, and the intermediate layer ML. In an embodiment, the electrode layer E2L can have a single-layer structure. However, this disclosure is not limited thereto, and in another embodiment, the electrode layer E2L can have a multilayer structure in which multiple conductive layers are stacked on top of each other. For example, the electrode layer E2L can have a two-layer structure, which includes a first sub-electrode layer comprising a metal and a second sub-electrode layer disposed on the first sub-electrode layer and comprising a transparent conductive oxide.

[0359] Shaded areas where electrode layer E2L is difficult to deposit can exist around a separator SPR with a reverse tapered slope. In and / or around the shaded areas, electrode layer E2L can be separated (or disconnected) by the separator SPR. For example, electrode layer E2L can be separated (or disconnected) into a second electrode E2 disposed in display area DA and a dummy electrode DME disposed in peripheral area NDA.

[0360] The dummy electrode DME can be connected to the auxiliary connection electrode CCE'. For example, the dummy electrode DME can contact the auxiliary connection electrode CCE' in the peripheral region NDA. Accordingly, the dummy electrode DME can be electrically connected to the auxiliary electrode AUE' through the auxiliary connection electrode CCE'.

[0361] like Figure 15 As shown, the second electrode E2 can contact the connection pattern CNP. For example, the second electrode E2 can contact the connection pattern CNP at a position adjacent to or overlapping with the first side surface of the separator SPR that is adjacent to the display area DA. In other words, the second electrode E2 can contact the connection pattern CNP in the area that overlaps with the first side surface of the separator SPR in the plan view.

[0362] The dummy electrode DME can be connected to the connection pattern CNP. For example, the dummy electrode DME can contact the connection pattern CNP at a position adjacent to or overlapping with the second side surface of the separator SPR, which is opposite to the first side surface. In other words, the dummy electrode DME can contact the connection pattern CNP in the area overlapping with the second side surface of the separator SPR in the plan view.

[0363] For example, if the deposition angle of the deposition process used to form the electrode layer E2L is greater than the deposition angle of the deposition process used to form the intermediate layer ML, the second electrode E2 and the dummy electrode DME can be formed to cover the side of the disconnected intermediate layer ML and contact the connection pattern CNP". As a result, the second electrode E2 can be electrically connected to the auxiliary electrode AUE' through the connection pattern CNP", the dummy electrode DME, and the auxiliary connection electrode CCE'. Accordingly, the second electrode E2 can receive a second power voltage (ELVSS, reference) from the auxiliary electrode AUE'. Figure 2 ).

[0364] According to an embodiment, in the display device DD2, the second electrode E2 (e.g., cathode) can be easily electrically connected to the auxiliary electrode AUE' arranged in the peripheral area NDA via the connection pattern CNP', the dummy electrode DME, and the auxiliary connection electrode CCE'. For example, the auxiliary electrode AUE' and the auxiliary connection electrode CCE' used to provide the second power voltage may not be arranged in the display area DA. As a result, the design freedom of the display area DA (e.g., the emitting area EA) can be increased, and the size (i.e., aperture ratio) of the emitting area can be further increased.

[0365] Figure 16 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0366] refer to Figure 16 The display device DD3 can be a device activated by an electrical signal. For example, such as... Figure 16 As shown, the display device DD3 can be a small display device used in small electronic devices such as smartphones, mobile phones, smartwatches, game consoles, or cameras. However, this disclosure is not limited thereto, and in another embodiment, the display device DD3 can be a medium to large-sized display device used in medium to large-sized electronic devices such as laptops, tablet PCs, televisions, computer monitors, vehicle monitors, or external billboards. Hereinafter, the above references... Figure 1A and Figure 1B Redundant descriptions of the display device DD1 (or DD1a) may be omitted or summarized.

[0367] The display device DD3 may include a display area DA and a peripheral area NDA. The display area DA may be an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The peripheral area NDA may be disposed adjacent to the display area DA. For example, the peripheral area NDA may surround at least a portion of the display area DA. In an embodiment, the peripheral area NDA may be an area where no image is displayed.

[0368] The display device DD3 may include a substrate SUB, a pixel PX, a gate line GL, a data line DL, a data driver DDV, and a gate driver GDV.

[0369] Pixels PX can be arranged in the display area DA and on the substrate SUB. Pixels PX can be electrically connected to gate lines GL and data lines DL. For example, pixels PX can be arranged in a matrix in a first direction DR1 and a second direction DR2. Each of the pixels PX can include pixel driving circuitry and a light-emitting element.

[0370] The data driver DDV can be disposed in the peripheral area NDA or on the substrate SUB. The data driver DDV generates a data voltage. The data driver DDV outputs the data voltage to the data line DL. The data voltage can be applied to the pixel PX through the data line DL.

[0371] The gate driver (GDV) can be disposed in the peripheral region NDA or on the substrate SUB. The gate driver (GDV) generates a gate signal. The gate driver (GDV) outputs the gate signal to the gate line GL. The gate signal can be applied to the pixel PX through the gate line GL.

[0372] In an embodiment, although not illustrated, the transmit driver that generates the transmit control signal may be further arranged in the peripheral region NDA. The transmit control signal can be applied to pixel PX via the transmit control line.

[0373] Figure 17A The illustration includes Figure 16 A schematic diagram of an embodiment of the circuit structure of a pixel in a display device.

[0374] refer to Figure 17A In one embodiment, pixel PX may include a light-emitting element LD and a pixel driving circuit PC2 connected to the light-emitting element LD. In another embodiment, pixel driving circuit PC2 may include a first transistor T1, a second transistor T2, and a first capacitor C1. Figure 17A In the diagram, both the first transistor T1 and the second transistor T2 are illustrated as n-type transistors. However, this disclosure is not limited thereto, and some of the transistors in the first transistor T1 and the second transistor T2 may be n-type transistors, while others may be p-type transistors. For example, the first transistor T1 may be an n-type transistor, and the second transistor T2 may be a p-type transistor.

[0375] When a pixel PX includes both n-type and p-type transistors, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, this disclosure is not limited thereto, and in another embodiment, both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0376] The pixel driving circuit PC2 can be connected to the first gate line GWL, the data line DL, the first voltage line VL1, and the second voltage line VL2. The first gate line GWL can transmit the first gate signal GW. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit a first power voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power voltage ELVSS with a relatively low voltage level.

[0377] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. In an embodiment, the first terminal of the first transistor T1 may be the source, and the second terminal of the first transistor T1 may be the drain. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a second node N2. The second terminal of the first transistor T1 may be connected to a third node N3. The second terminal of the first transistor T1 may be connected to a light-emitting element LD. The first transistor T1 can control the drive current ID supplied to the light-emitting element LD.

[0378] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the second transistor T2 may be the source, and the second terminal of the second transistor T2 may be the drain. However, this disclosure is not limited thereto, and in another embodiment, the first terminal of the second transistor T2 may be the drain, and the second terminal of the second transistor T2 may be the source. The gate terminal of the second transistor T2 may receive a first gate signal GW via a first gate line GWL. The first terminal of the second transistor T2 may receive a data voltage VDATA via a data line DL. The second terminal of the second transistor T2 may be connected to a first node N1.

[0379] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, if the second transistor T2 is an n-type transistor, it can be turned off when the first gate signal GW has a negative voltage level, and it can be turned on when the first gate signal GW has a positive voltage level. If the second transistor T2 is a p-type transistor, it can be turned off when the first gate signal GW has a positive voltage level, and it can be turned on when the first gate signal GW has a negative voltage level. While the second transistor T2 is turned on, it can provide the data voltage VDATA to the first node N1. Accordingly, the second transistor T2 can drive the first transistor T1.

[0380] The first capacitor C1 may include a first terminal and a second terminal. The first terminal of the first capacitor C1 may be connected to a first node N1. The second terminal of the first capacitor C1 may be connected to a second node N2. Current may be charged into or discharged from the first capacitor C1 according to the data voltage VDATA transmitted to the first node N1.

[0381] A light-emitting element (LD) may include an anode and a cathode. The anode of the LD may be connected to a first voltage line VL1. The cathode of the LD may be connected to a third node N3. For example, the cathode of the LD may be connected to the second terminal of a first transistor T1.

[0382] Figure 17B The illustration includes Figure 16 A schematic diagram of another embodiment of the circuit structure of a pixel in a display device.

[0383] Reference above Figure 17A Compared to the embodiment of the circuit structure of the described pixel PX, the following reference... Figure 17B The pixel driving circuit PC2' of the described embodiment of the pixel PX circuit structure may further include third to sixth transistors T3, T4, T5 and T6, and a second capacitor C2. Therefore, redundant descriptions of some components can be omitted or simplified.

[0384] refer to Figure 17B In an embodiment, pixel PX may include a light-emitting element LD and a pixel driving circuit PC2' connected to the light-emitting element LD. In an embodiment, pixel driving circuit PC2' may include first transistors to sixth transistors T1', T2, T3, T4, T5, and T6, a first capacitor C1, and a second capacitor C2. Figure 17B In the illustration, all of the first to sixth transistors T1', T2, T3, T4, T5, and T6 are shown as n-type transistors. However, this disclosure is not limited thereto, and in another embodiment, some of the first to sixth transistors T1', T2, T3, T4, T5, and T6 may be n-type transistors, and the others may be p-type transistors. For example, the first transistor T1' may be an n-type transistor, some of the second to sixth transistors T2, T3, T4, T5, and T6 may be n-type transistors, and the others may be p-type transistors.

[0385] When a pixel PX includes both n-type and p-type transistors, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, this disclosure is not limited thereto, and both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0386] The pixel driving circuit PC2' can be connected to the first to third gate lines GWL, GCL, and GRL, the data line DL, the first to fourth voltage lines VL1, VL2, VL3, and VL4, the first transmit control line ECL1, and the second transmit control line ECL2. The first gate line GWL can transmit the first gate signal GW. The second gate line GCL can transmit the second gate signal GC. The third gate line GRL can transmit the third gate signal GR. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit a first power voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power voltage ELVSS with a relatively low voltage level. The third voltage line VL3 can transmit the cathode initialization voltage Vcint. The fourth voltage line VL4 can transmit the reference voltage Vref. The reference voltage Vref can have a voltage level lower than the first power voltage ELVDD.

[0387] Apart from Figure 17B The first terminal of the first transistor T1' is connected to the second voltage line VL2 through the sixth transistor T6 and Figure 17B The second terminal of the first transistor T1' is connected to the light-emitting element LD via the fifth transistor T5. Figure 17B The first transistor T1' can be referenced above. Figure 17A The first transistor T1 described is essentially the same. Therefore, redundant descriptions can be omitted or simplified. For example, the first transistor T1' of the pixel driving circuit PC2' can be connected to the light-emitting element LD through the fifth transistor T5, and the driving current ID supplied to the light-emitting element LD through the fifth transistor T5 can be controlled.

[0388] Figure 17B The second transistor T2 can be referenced above. Figure 17A The second transistor T2 described is essentially the same. Accordingly, Figure 17A The description of the second transistor T2 can be applied in essentially the same way. Figure 17B The second transistor T2. For example, when the second transistor T2 is turned on, the second transistor T2 can drive the first transistor T1'.

[0389] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the third transistor T3 may be the source, and the second terminal of the third transistor T3 may be the drain. However, this disclosure is not limited thereto, and in another embodiment, the first terminal of the third transistor T3 may be the drain, and the second terminal of the third transistor T3 may be the source. The gate terminal of the third transistor T3 may receive a second gate signal GC through a second gate line GCL. The first terminal of the third transistor T3 may be connected to a third node N3. The second terminal of the third transistor T3 may receive a cathode initialization voltage Vcint through a third voltage line VL3.

[0390] The third transistor T3 can be turned on or off in response to the second gate signal GC. For example, when the third transistor T3 is an n-type transistor, it can be turned off when the second gate signal GC has a negative voltage level, and it can be turned on when the second gate signal GC has a positive voltage level. When the third transistor T3 is a p-type transistor, it can be turned off when the second gate signal GC has a positive voltage level, and it can be turned on when the second gate signal GC has a negative voltage level. When the third transistor T3 is turned on, it can provide the cathode initialization voltage Vcint to the third node N3. For example, it can provide the cathode initialization voltage Vcint to the cathode of the light-emitting element LD to initialize the cathode voltage. The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the fourth transistor T4 may be the source, and the second terminal may be the drain. However, this disclosure is not limited thereto, and in another embodiment, the first terminal of the fourth transistor T4 may be the drain, and the second terminal may be the source.

[0391] The gate terminal of the fourth transistor T4 can receive the third gate signal GR through the third gate line GRL. The first terminal of the fourth transistor T4 can be connected to the first node N1. The second terminal of the fourth transistor T4 can receive the reference voltage Vref through the fourth voltage line VL4.

[0392] The fourth transistor T4 can be turned on or off in response to the third gate signal GR. For example, if the fourth transistor T4 is an n-type transistor, it can be turned off when the third gate signal GR has a negative voltage level, and it can be turned on when the third gate signal GR has a positive voltage level. If the fourth transistor T4 is a p-type transistor, it can be turned off when the third gate signal GR has a positive voltage level, and it can be turned on when the third gate signal GR has a negative voltage level. When the fourth transistor T4 is turned on, it can provide the reference voltage Vref to the first node N1.

[0393] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the fifth transistor T5 may be the source, and the second terminal of the fifth transistor T5 may be the drain. However, this disclosure is not limited thereto, and in another embodiment, the first terminal of the fifth transistor T5 may be the drain, and the second terminal of the fifth transistor T5 may be the source. The gate terminal of the fifth transistor T5 may receive a first transmit control signal EM1 via a first transmit control line ECL1. The first terminal of the fifth transistor T5 may be connected to the second terminal of the first transistor T1'. The second terminal of the fifth transistor T5 may be connected to a third node N3. The second terminal of the fifth transistor T5 may be connected to a light-emitting element LD.

[0394] The fifth transistor T5 can be turned on or off in response to the first transmit control signal EM1. For example, if the fifth transistor T5 is an n-type transistor, it can be turned off when the first transmit control signal EM1 has a negative voltage level, and it can be turned on when the first transmit control signal EM1 has a positive voltage level. If the fifth transistor T5 is a p-type transistor, it can be turned off when the first transmit control signal EM1 has a positive voltage level, and it can be turned on when the first transmit control signal EM1 has a negative voltage level. When the fifth transistor T5 is turned on, it can electrically connect the first transistor T1' and the light-emitting element LD. For example, the fifth transistor T5 can electrically connect the second terminal of the first transistor T1' and the cathode of the light-emitting element LD in response to the first transmit control signal EM1.

[0395] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the sixth transistor T6 may be the source, and the second terminal of the sixth transistor T6 may be the drain. However, this disclosure is not limited thereto, and in another embodiment, the first terminal of the sixth transistor T6 may be the drain, and the second terminal of the sixth transistor T6 may be the source. The gate terminal of the sixth transistor T6 may receive a second transmit control signal EM2 via a second transmit control line ECL2. The first terminal of the sixth transistor T6 may receive a second power supply voltage ELVSS via a second voltage line VL2. The second terminal of the sixth transistor T6 may be connected to a second node N2.

[0396] The sixth transistor T6 can be turned on or off in response to the second transmit control signal EM2. For example, if the sixth transistor T6 is an n-type transistor, it can be turned off when the second transmit control signal EM2 has a negative voltage level, and it can be turned on when the second transmit control signal EM2 has a positive voltage level. If the sixth transistor T6 is a p-type transistor, it can be turned off when the second transmit control signal EM2 has a positive voltage level, and it can be turned on when the second transmit control signal EM2 has a negative voltage level. When the sixth transistor T6 is turned on, it can supply the second power voltage ELVSS to the second node N2.

[0397] although Figure 17B The illustration shows that the fifth transistor T5 and the sixth transistor T6 are driven independently by different transmit control signals, but this disclosure is not limited thereto. In another embodiment, the first transmit control signal EM1 and the second transmit control signal EM2 can be provided as a substantially single transmit control signal, the fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on or off, and the first transmit control line ECL1 and the second transmit control line ECL2 can be provided as a substantially single transmit control line.

[0398] Figure 17B The first capacitor C1 can be referenced above. Figure 17A The first capacitor C1 described is essentially the same. Accordingly, Figure 17A The description of the first capacitor C1 can be applied in essentially the same way. Figure 17B The first capacitor C1. For example, based on the data voltage VDATA transmitted to the first node N1, current can be charged into or discharged from the first capacitor C1.

[0399] The second capacitor C2 may include a first terminal and a second terminal. The first terminal of the second capacitor C2 may be connected to the second node N2. The second terminal of the second capacitor C2 may be connected to the second voltage line VL2. For example, the second capacitor C2 may be connected in series with the first capacitor C1. The data voltage VDATA may be transmitted to the first node N1 and may be divided due to the series connection between the first capacitor C1 and the second capacitor C2, so that the divided data voltage VDATA may be transmitted to the second node N2. Since the first transistor T1' generates a drive current ID based on the voltage of the first node N1 and the voltage of the second node N2, the data range can be extended.

[0400] In addition to the cathode being connected to the first terminal of the third transistor T3 and to the second terminal of the first transistor T1' via the fifth transistor T5, Figure 17B The light-emitting element LD can be compared with the above reference. Figure 17A The light-emitting elements (LDs) described are essentially the same. Therefore, redundant descriptions can be omitted or simplified. For example, the cathode of the LD can be connected to the second terminal of the first transistor T1' via the fifth transistor T5. The cathode of the LD can receive the cathode initialization voltage Vcint via the third transistor T3.

[0401] like Figure 17A and Figure 17B As shown, according to an embodiment, the anode of the light-emitting element LD can receive a first power voltage ELVDD through a first voltage line VL1, and the cathode of the light-emitting element LD can be connected to the second terminal of the first transistor T1 (or T1'). For example, the potential of the cathode of the light-emitting element LD can be controlled by electrically connecting it to the first transistor T1 (or T1').

[0402] Since the first voltage line VL1 provides a first power voltage ELVDD with a relatively high voltage level and the second voltage line VL2 provides a second power voltage ELVSS with a relatively low voltage level, the second terminal of the first transistor T1 (or T1') can be the drain when the first transistor T1 (or T1') is an n-type transistor. According to an embodiment, the cathode of the light-emitting element LD can be connected to the drain of the first transistor T1 (or T1').

[0403] When the first transistor T1 (or T1') is an n-type transistor, if the anode of the light-emitting element LD is connected to the source of the first transistor T1 (or T1'), the source voltage of the first transistor T1 (or T1') may shift due to the degradation of the light-emitting element LD, and the gate-source voltage (Vgs) of the first transistor T1 (or T1') may change. As a result, the range of variation of the drive current ID may increase, image retention defects may occur, and the lifespan of the display device may be shortened.

[0404] According to an embodiment, the anode of the light-emitting element LD can receive a first power voltage ELVDD, and the cathode of the light-emitting element LD can be connected to the drain of the first transistor T1 (or T1'). Accordingly, even if the light-emitting element LD deteriorates, the gate-source voltage (Vgs) of the first transistor T1 (or T1') can remain unchanged. Consequently, the range of variation in the drive current ID due to the deterioration of the light-emitting element LD can be reduced. Therefore, the image retention defects of the display device DD3 that depend on the increase in usage time can be reduced, and the lifespan of the display device DD3 can be improved.

[0405] Figure 17A and Figure 17B The circuit structure of the pixel PX illustrated in the figure (e.g., the number or arrangement of transistors, the number or arrangement of capacitors) is merely an example, and various changes may be made according to the embodiment.

[0406] Figure 18 It is a diagram. Figure 16 A floor plan of a portion of the display device area. Figure 19 It is a diagram. Figure 18 An enlarged plan view of one of the unit emission regions in the unit emission region. Figure 20 It is along Figure 19 A schematic cross-sectional view taken from line VI-VI'.

[0407] For example, Figure 18 The diagram schematically illustrates the four cell transmission areas UEA1 and UEA2 arranged in a two-row, two-column matrix. Figure 19 The diagram schematically illustrates an enlarged view of the first transmission area, UEA1, among the two transmission areas, UEA1 and UEA2. For ease of description, Figure 20 Some of the components shown in the diagram are in Figure 18 and Figure 19 The text is either omitted or emphasized. For example, in... Figure 18 In the middle, the following was omitted. Figure 19 The second electrodes E2a, E2b, and E2c are shown in the diagram.

[0408] refer to Figure 18 and Figure 19 The display device DD3 may include a first pixel driving circuit to a third pixel driving circuit PCa, PCb and PCc, a first light-emitting element to a third light-emitting element LDa, LDb and LDc, a first connecting electrode to a third connecting electrode CEa, CEb and CEc, a separator SPR and a plurality of organic film patterns OGP.

[0409] Each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be referenced above. Figure 17A and Figure 17B At least one of the described pixel driving circuits PC2 and PC2' corresponds to each other. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb and PCc may include at least one transistor and at least one capacitor. Figure 20 The diagram shows the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2.

[0410] Figure 20 The first transistor TR1 can be a transistor connected to the light-emitting element via a connection electrode. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc is... Figure 17A In the case of pixel driving circuit PC2, the first transistor TR1 can be Figure 17A The first transistor T1, and the second transistor TR2 can be Figure 17A The second transistor T2. Each of the first to third pixel driving circuits PCa, PCb, and PCc is... Figure 17B In the case of pixel driving circuit PC2', the first transistor TR1 can be Figure 17B The fifth transistor T5, and the second transistor TR2 can be Figure 17B One of the first transistor T1', the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6.

[0411] In an embodiment, Figure 20 The first capacitor CAP1 can be with Figure 17A and Figure 17B The first capacitor C1 corresponds to, and Figure 20 The second capacitor CAP2 can be connected with Figure 17B The second capacitor C2 corresponds to this. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb and PCc is... Figure 17A In the case of the pixel driving circuit PC2, the second capacitor CAP2 can be omitted. However, this disclosure is not limited thereto, and in embodiments, Figure 20 The first capacitor CAP1 can be with Figure 17B The second capacitor C2 corresponds to, and Figure 20 The second capacitor CAP2 can be connected with Figure 17A and Figure 17B The first capacitor C1 corresponds to this. Each of the first to third pixel driving circuits PCa, PCb, and PCc is... Figure 17AIn the case of the pixel driving circuit PC2, the first capacitor CAP1 can be omitted. The following will refer to... Figure 20 The first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 are described in more detail.

[0412] Figure 18 and Figure 19 The schematic illustration shows that the first pixel driving circuit to the third pixel driving circuits PCa, PCb and PCc each have a rectangular shape in a plan view and are arranged sequentially along the first direction DR1. However, this disclosure is not limited thereto, and the shape and arrangement of the first pixel driving circuit to the third pixel driving circuits PCa, PCb and PCc can be varied according to embodiments.

[0413] Each of the first to third light-emitting elements LDa, LDb, and LDc can be referenced above. Figure 17A and Figure 17B The light-emitting element LD is described. For example, the first to third light-emitting elements LDa, LDb, and LDc may include a first electrode (E1, reference). Figure 20 ), and the intermediate layer (ML, reference) arranged on the first electrode Figure 20 ) and the electrode layer E2L arranged on the intermediate layer (reference) Figure 20 In an embodiment, the first electrode can be used as... Figure 17A and Figure 17B The anode, and the electrode layer E2L can be used as... Figure 17A and Figure 17B The cathode.

[0414] In an embodiment, the electrode layer E2L can be separated (or disconnected) by the separator SPR into a plurality of second electrodes E2a, E2b, and E2c spaced apart from each other. For example, the electrode layer E2L can be separated (or disconnected) into the second electrode E2a of the first light-emitting element LDa, the second electrode E2b of the second light-emitting element LDb, and the second electrode E2c of the third light-emitting element LDc. This will be described in more detail below.

[0415] The first to third light-emitting elements LDa, LDb, and LDc can be connected to the first to third pixel driving circuits PCa, PCb, and PCc, respectively. For example, the first light-emitting element LDa can be connected to the first pixel driving circuit PCa, the second light-emitting element LDb can be connected to the second pixel driving circuit PCb, and the third light-emitting element LDc can be connected to the third pixel driving circuit PCc. Accordingly, the first pixel driving circuit PCa and the first light-emitting element LDa can form a pixel, the second pixel driving circuit PCb and the second light-emitting element LDb can form a pixel, and the third pixel driving circuit PCc and the third light-emitting element LDc can form a pixel.

[0416] The first to third light-emitting elements LDa, LDb, and LDc can emit light of different colors. For example, the first light-emitting element LDa can emit red light, the second light-emitting element LDb can emit green light, and the third light-emitting element LDc can emit blue light. However, this disclosure is not limited thereto.

[0417] In an embodiment, such as Figure 18 As shown, the display device DD3 may include a first unit transmission area UEA1 and a second unit transmission area UEA2. The first unit transmission area UEA1 and the second unit transmission area UEA2 may be arranged in a matrix on a first direction DR1 and a second direction DR2. Although Figure 18 Only four unit emission areas are illustrated, but this disclosure is not limited to this, and multiple unit emission areas may be present throughout the entire display area (DA, see reference). Figure 16 The elements are arranged in a matrix along the first direction DR1 and the second direction DR2.

[0418] The first to third light-emitting elements LDa, LDb, and LDc that are adjacent to each other can be arranged in each of the first unit emission region UEA1 and the second unit emission region UEA2. For example, the first to third emission regions EAa, EAb, and EAc that are adjacent to each other can be defined in each of the first unit emission region UEA1 and the second unit emission region UEA2, and the first to third light-emitting elements LDa, LDb, and LDc can be arranged in the first to third emission regions EAa, EAb, and EAc, respectively.

[0419] The first to third emission regions EAa, EAb, and EAC can be defined by a pixel-limited layer (PDL, see below) as described below. Figure 20The pixel opening is defined by the first to third emission regions EAa, EAb, and EAc. For example, each of these regions can be a region that emits light from the light-emitting element. For example, the first light-emitting element LDa can be disposed in the first emission region EAa, and the first emission region EAa can be a region that emits light from the first light-emitting element LDa. The second light-emitting element LDb can be disposed in the second emission region EAb, and the second emission region EAb can be a region that emits light from the second light-emitting element LDb. The third light-emitting element LDc can be disposed in the third emission region EAc, and the third emission region EAc can be a region that emits light from the third light-emitting element LDc.

[0420] In the embodiments, the first unit emission area UEA1 and the second unit emission area UEA2 can be distinguished based on the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc). For example, for each first unit emission area UEA1, the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc) can be the same, and for each second unit emission area UEA2, the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc) can be the same.

[0421] In an embodiment, such as Figure 18 As shown, the first unit transmission area UEA1 and the second unit transmission area UEA2 can be arranged alternately along the first direction DR1 (i.e., the row direction) and the second direction DR2 (i.e., the column direction). However, this disclosure is not limited thereto, and the number of different unit transmission areas included in the display device DD3 or the arrangement relationship between the unit transmission areas can be varied according to embodiments.

[0422] Figure 18 and Figure 19 The illustration schematically depicts the first to third transmission regions EAa, EAb, and EAc arranged in an S-striped structure. However, this disclosure is not limited thereto, and the arrangement of the first to third transmission regions EAa, EAb, and EAc can be varied according to embodiments.

[0423] The spacer splitter (SPR) can be arranged in a plan view between the first to third transmission regions EAa, EAb, and EAc. For example, the spacer splitter SPR can be arranged in a plan view between the first transmission region EAa and the second transmission region EAb, between the second transmission region EAb and the third transmission region EAc, and between the first transmission region EAa and the third transmission region EAc. In an embodiment, the spacer splitter SPR can completely surround each of the first to third transmission regions EAa, EAb, and EAc in a plan view.

[0424] In embodiments, the spacer SPR may comprise an organic insulating material. For example, the spacer SPR may comprise a photosensitive resin (e.g., a photoresist), but this disclosure is not limited thereto.

[0425] The separator SPR can separate (or disconnect) the electrode layer E2L in the display area into the second electrode E2a of the first light-emitting element LTa, the second electrode E2b of the second light-emitting element LDb, and the second electrode E2c of the third light-emitting element LDc. Accordingly, the second electrodes E2a, E2b, and E2c can be spaced apart from each other. The second electrodes E2a, E2b, and E2c can be electrically independent of each other.

[0426] The organic membrane pattern (OGP) can overlap with at least a portion of the spacer segment (SPR) in a plan view. The organic membrane pattern (OGP) can be arranged within a portion of the area where the spacer segment (SPR) is arranged. In other words, a portion of the spacer segment (e.g., Figure 20 The first part of the separator SPR (SPP1) can overlap with the organic membrane pattern OGP in the plan view, and the other part of the separator SPR (e.g., Figure 20 The second part (SPP2) of the separator SPR may not overlap with the organic membrane pattern OGP in the planar view. The organic membrane pattern OGP may include organic materials.

[0427] In the embodiments, the organic film pattern (OGP) can have various planar shapes. For example, such as Figure 18 As shown, each of the organic film patterns OGP can have at least one of the following planar shapes in the planar view: a triangular planar shape, a rectangular planar shape, a square planar shape, a cross-shaped planar shape, or a rhombus planar shape. However, this disclosure is not limited thereto, and the organic film patterns OGP can have the same planar shape as each other.

[0428] In the embodiments, the organic film patterns (OGPs) may have different sizes (or areas) from each other. However, this disclosure is not limited thereto, and the organic film patterns (OGPs) may have the same size from each other.

[0429] In an embodiment, the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a planar view. Here, the intersection portion CRP of the separator SPR can be the portion where a first extension portion of the separator SPR extending in a first direction DR1 and a second extension portion of the separator SPR extending in a second direction DR2 intersect. For example, as... Figure 18 As shown, the first organic film pattern OGP1 in the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a plan view. Compared to the first extension portion and the second extension portion of the separator SPR, the intersection portion CRP of the separator SPR can provide a relatively large space for covering the organic film pattern OGP. However, this disclosure is not limited thereto, and in another embodiment, the organic film pattern OGP can overlap with the first extension portion and the second extension portion of the separator SPR in a plan view. For example, as Figure 18 As shown, the second organic membrane pattern OGP2 in the organic membrane pattern OGP can overlap with the first extension portion or the second extension portion of the separator SPR in the plan view.

[0430] In an embodiment, the organic film pattern OGP can be arranged in the area where the separator SPR is arranged in the plan view, and the separator SPR can cover the organic film pattern OGP and contact the pixel defining layer (PDL, reference) in the plan view. Figure 20 However, this disclosure is not limited thereto. For example, such as Figure 18 As shown, some of the organic membrane patterns OGP can be arranged in the area with spacers SPR in the plan view, and other organic membrane patterns OGP can overlap with both the area with spacers SPR and the area without spacers SPR in the plan view.

[0431] In the following text, it will be referred to as Figure 19 Centered on the first unit emission region UEA1, this section describes in more detail the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third pixel driving circuits PCa, PCb, and PCc. The following description of the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third pixel driving circuits PCa, PCb, and PCc can be applied substantially equivalently to all unit emission regions.

[0432] As described above, the display device DD3 may include a first connecting electrode to a third connecting electrode CEa, CEb, and CEc. The first connecting electrode CEa can electrically connect a first light-emitting element LDa and a first pixel driving circuit PCa. The second connecting electrode CEb can electrically connect a second light-emitting element LDb and a second pixel driving circuit PCb. The third connecting electrode CEc can electrically connect a third light-emitting element LDc and a third pixel driving circuit PCc.

[0433] The first to third connecting electrodes CEa, CEb, and CEc may comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. In embodiments, the first to third connecting electrodes CEa, CEb, and CEc may have a multilayer structure in which multiple conductive layers are stacked on top of each other. Reference will be made below. Figure 20 Provide a detailed description.

[0434] The first connecting electrode CEa may include a first circuit connecting portion CPa and a first light-emitting connecting portion CNa.

[0435] The first circuit connection portion CPa can be the part of the first connection electrode CEa that is connected to the first pixel driving circuit PCa. For example, the first circuit connection portion CPa can be the first transistor (TR1, reference) of the first connection electrode CEa that is connected to the first pixel driving circuit PCa. Figure 20 The location of the first circuit connection portion CPa can correspond to the location of the first transistor of the first pixel driving circuit PCa. For example, the location of the first circuit connection portion CPa can be such that the first transistor of the first pixel driving circuit PCa is exposed and penetrates the fifth insulating layer (IL5, reference IL5). Figure 20 Contact holes (CNT, reference) Figure 20 The position corresponds to the location of ).

[0436] The first light-emitting connection portion CNa can be the portion of the first connecting electrode CEa that connects to the second electrode E2a of the first light-emitting element LDa. For example, the first light-emitting connection portion CNa can be the portion of the first connecting electrode CEa that is covered by the sixth insulating layer (IL6, reference). Figure 20 ) and Pixel Confinement Layer (PDL, reference) Figure 20 The portion of the first light-emitting connection portion CNa is exposed to connect to the second electrode E2a. Correspondingly, the position of the first light-emitting connection portion CNa can be the same as the sub-opening (OP, reference) that exposes the first connection electrode CEa and penetrates the pixel defining layer and the sixth insulating layer. Figure 20 The position corresponds to the location of ).

[0437] The second electrode E2a of the first light-emitting element LDa can be connected to the first connecting electrode CEa. For example, the second electrode E2a of the first light-emitting element LDa can contact the first connecting electrode CEa. As a result, the second electrode E2a of the first light-emitting element LDa can be electrically connected to the first pixel driving circuit PCa through the first connecting electrode CEa.

[0438] In an embodiment, the first light-emitting connection portion CNa can be arranged at a position that does not overlap with the first emitting region EAa in a plan view. For example, in a plan view, the first light-emitting connection portion CNa can be arranged between the first emitting region EAa and the separator SPR. For example, the second electrode E2a of the first light-emitting element LDa can have a protruding portion extending from the first emitting region EAa to a position that does not overlap with the first emitting region EAa in a plan view, and the second electrode E2a of the first light-emitting element LDa can contact the first connection electrode CEa at a position that does not overlap with the first emitting region EAa. Accordingly, the second electrode E2a of the first light-emitting element LDa and the first pixel driving circuit PCa can be electrically connected to each other through the first connection electrode CEa without reducing the size of the first emitting region EAa.

[0439] The second connecting electrode CEb may include a second circuit connecting portion CPb and a second light-emitting connecting portion CNb.

[0440] The second circuit connection portion CPb can be the part of the second connection electrode CEb that connects to the second pixel driving circuit PCb. For example, the second circuit connection portion CPb can be the first transistor (TR1, reference) of the second connection electrode CEb that connects to the second pixel driving circuit PCb. Figure 20 The location of the second circuit connection portion CPb can correspond to the location of the first transistor of the second pixel driving circuit PCb. For example, the location of the second circuit connection portion CPb can be such that it exposes the first transistor of the second pixel driving circuit PCb and penetrates the fifth insulating layer (IL5, reference IL5). Figure 20 The positions of the contact holes correspond to those of the contacts.

[0441] The second light-emitting connection portion CNb can be the portion of the second connection electrode CEb that connects to the second electrode E2b of the second light-emitting element LDb. For example, the second light-emitting connection portion CNb can be the portion of the second connection electrode CEb that is covered by the sixth insulating layer (IL6, reference). Figure 20 ) and Pixel Confinement Layer (PDL, reference) Figure 20 The portion exposed for connection to the second electrode E2b. Accordingly, the position of the second light-emitting connection portion CNb can correspond to the position of the sub-opening that exposes the second connection electrode CEb and penetrates the pixel defining layer and the sixth insulating layer.

[0442] In an embodiment, the second connecting electrode CEb may be spaced apart from the first connecting electrode CEa in a plan view. In other words, the first connecting electrode CEa and the second connecting electrode CEb may be different electrodes from each other.

[0443] The second electrode E2b of the second light-emitting element LDb can be connected to the second connection electrode CEb. For example, the second electrode E2b of the second light-emitting element LDb can contact the second connection electrode CEb. As a result, the second electrode E2b of the second light-emitting element LDb can be electrically connected to the second pixel driving circuit PCb through the second connection electrode CEb.

[0444] In an embodiment, the second light-emitting connection portion CNb can be arranged at a position that does not overlap with the second emitting region EAb in a plan view. For example, in a plan view, the second light-emitting connection portion CNb can be arranged between the second emitting region EAb and the separator SPR. For example, the second electrode E2b of the second light-emitting element LDb can have a protruding portion extending from the second emitting region EAb to a position that does not overlap with the second emitting region EAb in a plan view, and the second electrode E2b of the second light-emitting element LDb can contact the second connection electrode CEb at a position that does not overlap with the second emitting region EAb. Accordingly, the second electrode E2b of the second light-emitting element LDb and the second pixel driving circuit PCb can be electrically connected to each other via the second connection electrode CEb without reducing the size of the second emitting region EAb.

[0445] The third connecting electrode CEc may include a third circuit connecting portion CPC and a third light-emitting connecting portion CNc.

[0446] The third circuit connection portion CPc can be the part of the third connection electrode CEc that connects to the third pixel driving circuit PCc. For example, the third circuit connection portion CPc can be the first transistor (TR1, reference) of the third connection electrode CEc that connects to the third pixel driving circuit PCc. Figure 20 The third circuit connection portion CPC can be positioned to correspond to the position of the first transistor in the third pixel driving circuit PCc. Specifically, the position of the third circuit connection portion CPC can be such that it exposes the first transistor of the third pixel driving circuit PCc and penetrates the fifth insulating layer (IL5, reference IL5). Figure 20 The positions of the contact holes correspond to those of the contacts.

[0447] The third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that connects to the second electrode E2c of the third light-emitting element LDc. For example, the third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that is covered by the sixth insulating layer (IL6, reference). Figure 20 ) and Pixel Confinement Layer (PDL, reference) Figure 20The portion exposed for connection to the second electrode E2c. Accordingly, the position of the third light-emitting connection portion CNc can correspond to the position of the sub-opening that exposes the third connection electrode CEc and penetrates the pixel defining layer and the sixth insulating layer.

[0448] In an embodiment, the third connecting electrode CEc may be spaced apart from the first connecting electrode CEa and the second connecting electrode CEb in a plan view. In other words, the first connecting electrode CEa, the second connecting electrode CEb, and the third connecting electrode CEc may be different electrodes from each other.

[0449] The second electrode E2c of the third light-emitting element LDc can be connected to the third connecting electrode CEc. For example, the second electrode E2c of the third light-emitting element LDc can contact the third connecting electrode CEc. As a result, the second electrode E2c of the third light-emitting element LDc can be electrically connected to the third pixel driving circuit PCc through the third connecting electrode CEc.

[0450] In an embodiment, the third light-emitting connection portion CNc can be arranged at a position that does not overlap with the third emitting region EAc in a plan view. For example, in a plan view, the third light-emitting connection portion CNc can be arranged between the third emitting region EAc and the separator SPR. For example, the second electrode E2c of the third light-emitting element LDc can have a protruding portion extending from the third emitting region EAc to a position that does not overlap with the third emitting region EAc in a plan view, and the second electrode E2c of the third light-emitting element LDc can contact the third connecting electrode CEc at a position that does not overlap with the third emitting region EAc. Accordingly, the second electrode E2c of the third light-emitting element LDc and the third pixel driving circuit PCc can be electrically connected to each other through the third connecting electrode CEc without reducing the size of the third emitting region EAc.

[0451] According to an embodiment, the second electrodes E2a, E2b, and E2c can contact the first to third connecting electrodes CEa, CEb, and CEc respectively at positions in the plan view where the second electrodes E2a, E2b, and E2c do not overlap with the first to third transmitting regions EAa, EAb, and EAc respectively. Correspondingly, the second electrodes E2a, E2b, and E2c can contact the first to third connecting electrodes CEa, CEb, and CEc respectively without reducing the size of each of the first to third transmitting regions EAa, EAb, and EAc.

[0452] According to an embodiment, the second electrodes E2a, E2b, and E2c can be electrically connected to the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc respectively via the first connecting electrode to the third connecting electrode CEa, CEb, and CEc. Accordingly, the design limitations on each of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc due to the position, shape, and size of the first to third emitting regions EAa, EAb, and EAc can be reduced. For example, even if at least some of the first circuit connection portions to the third circuit connection portions CPa, CPb, and CPc overlap with the first to third emitting regions EAa, EAb, and EAc in a plan view, the second electrodes E2a, E2b, and E2c can still be easily electrically connected to the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc respectively via the first connecting electrode to the third connecting electrode CEa, CEb, and CEc. Accordingly, the shape or arrangement of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc can be designed independently of the position, shape, and size of the first to third emission regions EAa, EAb, and EAc. Consequently, the design freedom of each of the first to third pixel driving circuits PCa, PCb, and PCc can be increased.

[0453] In this embodiment, regardless of the position, shape, and size of the first to third emitter regions EAa, EAb, and EAc, the first to third pixel driving circuits PCa, PCb, and PCc can all be designed to be identical to each other. As described above, the position of the first circuit connection portion CPa can correspond to the position of the first transistor of the first pixel driving circuit PCa, the position of the second circuit connection portion CPb can correspond to the position of the first transistor of the second pixel driving circuit PCb, and the position of the third circuit connection portion CPc can correspond to the position of the first transistor of the third pixel driving circuit PCc. Accordingly, when the first to third pixel driving circuits PCa, PCb, and PCc are formed to have substantially the same size and arranged along the first direction DR1, the positions of the first circuit connection portion CPa, the second circuit connection portion CPb, and the third circuit connection portion CPc can be arranged along the first direction DR1.

[0454] like Figure 18As shown, for each first unit transmitter region UEA1, the shape or arrangement of the first to third connecting electrodes CEa, CEb, and CEc, as well as the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same. For each second unit transmitter region UEA2, the shape or arrangement of each of the first to third connecting electrodes CEa, CEb, and CEc, as well as the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same.

[0455] As described above, the display device DD3 may include a separator SPR. The electrode layer E2L may be separated (or disconnected) by the separator SPR into second electrodes E2a, E2b, and E2c. For example, the second electrode E2a of the first light-emitting element LDa, the second electrode E2b of the second light-emitting element LDb, and the second electrode E2c of the third light-emitting element LDc may be electrically independent of each other through the separator SPR.

[0456] The separator SPR can define first opening regions to third opening regions OA1, OA2, and OA3, respectively, corresponding to the second electrodes E2a, E2b, and E2c. For example, the separator SPR can have a grid structure surrounding the second electrodes E2a, E2b, and E2c in a plan view. The second electrode E2a of the first light-emitting element LDa can be arranged in the first opening region OA1 of the separator SPR, the second electrode E2b of the second light-emitting element LDb can be arranged in the second opening region OA2 of the separator SPR, and the second electrode E2c of the third light-emitting element LDc can be arranged in the third opening region OA3 of the separator SPR.

[0457] In an embodiment, in a plan view, the shape of the first opening region OA1 can be substantially the same as the shape of the second electrode E2a of the first light-emitting element LDa, the shape of the second opening region OA2 can be substantially the same as the shape of the second electrode E2b of the second light-emitting element LDb, and the shape of the third opening region OA3 can be substantially the same as the shape of the second electrode E2c of the third light-emitting element LDc.

[0458] Further references will be made below. Figure 20 The cross-sectional structure of the display device DD3 is described in more detail with the first emission zone EAa as the center. The following description of the cross-sectional structure of the display device DD3 can be applied substantially equivalently to all emission zones. (Refer to the above...) Figure 5 Redundant descriptions of the cross-sectional structure of the display device DD1 may be omitted or summarized.

[0459] Further reference Figure 20The display device DD3 may include a substrate SUB, a first bottom conductive layer BML1, a second bottom conductive layer BML2, a first transistor TR1, a second transistor TR2, a first capacitor CAP1, a second capacitor CAP2, a first connecting electrode CEa, first insulating layers to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a first light-emitting element LDA, an organic film pattern OGP, a separator SPR, a first dummy layer DP1, a second dummy layer DP2 and an encapsulation layer ENC. The separator SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1.

[0460] The first transistor TR1 may include a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. The second transistor TR2 may include a second active pattern AP2, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. The first capacitor CAP1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The second capacitor CAP2 may include a first capacitor electrode CPE1 and a third capacitor electrode CPE3. The first light-emitting element LDa may include a first electrode E1, an intermediate layer ML, and a second electrode E2a.

[0461] As described above, the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 may be components included in the first pixel driving circuit PCa.

[0462] The first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3 can be disposed on the substrate SUB. Each of the first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide.

[0463] The first insulating layer IL1 can cover the first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3, and can be disposed on the substrate SUB. The first insulating layer IL1 can prevent or reduce the diffusion of metal atoms or impurities from the substrate SUB to the first active pattern AP1 and / or the second active pattern AP2.

[0464] A first active pattern AP1 may be disposed on a first insulating layer IL1. In an embodiment, the first active pattern AP1 may overlap with a first bottom conductive layer BML1. The first active pattern AP1 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern AP1 may include a first contact region S1, a second contact region D1, and a first channel region CH1 between the first contact region S1 and the second contact region D1.

[0465] The second active pattern AP2 may be disposed on the first insulating layer IL1. In an embodiment, the second active pattern AP2 may overlap with the second bottom conductive layer BML2. The second active pattern AP2 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The second active pattern AP2 may include a third contact region S2, a fourth contact region D2, and a second channel region CH2 between the third contact region S2 and the fourth contact region D2.

[0466] In this embodiment, the first active pattern AP1 and the second active pattern AP2 may include an oxide semiconductor material. However, this disclosure is not limited thereto, and the first active pattern AP1 and the second active pattern AP2 may include different materials. For example, one of the first active pattern AP1 and the second active pattern AP2 may include an oxide semiconductor material, and the other of the first active pattern AP1 and the second active pattern AP2 may include a silicon semiconductor material.

[0467] Figure 20 The illustration schematically shows a first active pattern AP1 and a second active pattern AP2 arranged in the same layer. However, this disclosure is not limited thereto, and in another embodiment, the first active pattern AP1 and the second active pattern AP2 may be arranged in different layers.

[0468] The second insulating layer IL2 can cover the first active pattern AP1 and the second active pattern AP2, and can be arranged on the first insulating layer IL1.

[0469] The first gate electrode GE1 may be disposed on the second insulating layer IL2. In a plan view, the first gate electrode GE1 may overlap with the first channel region CH1 of the first active pattern AP1. The first gate electrode GE1 may comprise a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. Although not illustrated, in an embodiment, the first gate electrode GE1 may contact the first bottom conductive layer BML1.

[0470] The second gate electrode GE2 may be disposed on the second insulating layer IL2. In a plan view, the second gate electrode GE2 may overlap with the second channel region CH2 of the second active pattern AP2. The second gate electrode GE2 may comprise a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. Although not illustrated, in an embodiment, the second gate electrode GE2 may contact the second bottom conductive layer BML2.

[0471] The third insulating layer IL3 can cover the first gate electrode GE1, the second gate electrode GE2 and the first capacitor electrode CPE1, and can be arranged on the second insulating layer IL2.

[0472] The fourth insulating layer IL4 can cover the second capacitor electrode CPE2 and can be arranged on the third insulating layer IL3.

[0473] The first to fourth contact electrodes SE1, DE1, SE2, and DE2 can be disposed on the fourth insulating layer IL4. The first contact electrode SE1 can contact the first contact area S1 of the first active pattern AP1, and the second contact electrode DE1 can contact the second contact area D1 of the first active pattern AP1. The third contact electrode SE2 can contact the third contact area S2 of the second active pattern AP2, and the fourth contact electrode DE2 can contact the fourth contact area D2 of the second active pattern AP2. The first to fourth contact electrodes SE1, DE1, SE2, and DE2 can comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0474] In an embodiment, the first contact electrode SE1 may contact the first bottom conductive layer BML1, and the third contact electrode SE2 may contact the second bottom conductive layer BML2. However, this disclosure is not limited thereto. For example, if the first gate electrode GE1 contacts the first bottom conductive layer BML1, the first contact electrode SE1 may not contact the first bottom conductive layer BML1. If the second gate electrode GE2 contacts the second bottom conductive layer BML2, the third contact electrode SE2 may not contact the second bottom conductive layer BML2.

[0475] Accordingly, a first transistor TR1 can be formed, comprising a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. As described above, the first transistor TR1 can be a transistor connected to the light-emitting element via a connection electrode. For example, in the first pixel driving circuit PCa, it is... Figure 17A In the case of pixel driving circuit PC2, the first transistor TR1 can be Figure 17A The first transistor T1. In the first pixel drive circuit PCa is... Figure 17BIn the case of pixel driving circuit PC2', the first transistor TR1 can be Figure 17B The fifth transistor, T5.

[0476] A second transistor TR2 can be formed, comprising a second active pattern AP2, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. For example, in the first pixel driving circuit PCa... Figure 17A In the case of pixel driving circuit PC2, the second transistor TR2 can be Figure 17A The second transistor T2. In the first pixel drive circuit PCa is... Figure 17B In the case of pixel driving circuit PC2', the second transistor TR2 can be Figure 17B One of the first to fourth transistors T1', T2, T3 and T4, and the sixth transistor T6.

[0477] The fifth insulating layer IL5 can cover the first contact electrode to the fourth contact electrode SE1, DE1, SE2 and DE2, and can be arranged on the fourth insulating layer IL4.

[0478] The first connection electrode CEa can be disposed in the display area DA on the substrate SUB. For example, the first connection electrode CEa can be disposed in the display area DA on the fifth insulating layer IL5. The first connection electrode CEa can be spaced apart from the first electrode E1. As described above, the first connection electrode CEa can be connected to the first transistor TR1. For example, the first connection electrode CEa can contact the first transistor TR1 through a contact hole CNT penetrating the fifth insulating layer IL5. Accordingly, the position of the first circuit connection portion CPa can correspond to the position of the contact hole CNT.

[0479] The first connecting electrode CEa may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. In an embodiment, the first connecting electrode CEa may have a multilayer structure in which multiple conductive layers are stacked on top of each other. For example, the first connecting electrode CEa may include a first conductive layer CL1, a second conductive layer CL2, and a third conductive layer CL3 stacked sequentially.

[0480] In this embodiment, the first conductive layer CL1 may comprise a metal and / or a transparent conductive oxide. Examples of metals that can be used as the first conductive layer CL1 include titanium (Ti) or molybdenum (Mo). Examples of transparent conductive oxides that can be used as the first conductive layer CL1 include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (InO). x Materials used include indium gallium oxide (IGO) or zinc aluminum oxide (AZO). The first conductive layer CL1 can have a thinner thickness than the second conductive layer CL2.

[0481] The second conductive layer CL2 and the first conductive layer CL1 can be made of different materials. For example, the second conductive layer CL2 and the first conductive layer CL1 can be made of different metals. For example, the second conductive layer CL2 can be made of aluminum (Al) or copper (Cu). The second conductive layer CL2 can have a greater thickness than the first conductive layer CL1.

[0482] The third conductive layer CL3 and the second conductive layer CL2 can be made of different materials. For example, the third conductive layer CL3 can include a metal and / or a transparent conductive oxide different from the second conductive layer CL2. Examples of metals that can be used as the third conductive layer CL3 include titanium (Ti) or molybdenum (Mo). Examples of transparent conductive oxides that can be used as the third conductive layer CL3 include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (InO). x Materials used include indium gallium oxide (IGO) or zinc aluminum oxide (AZO). The third conductive layer CL3 can have a thinner thickness than the second conductive layer CL2.

[0483] In some embodiments, the first conductive layer CL1 and the third conductive layer CL3 may comprise the same material. However, this disclosure is not limited thereto.

[0484] The side surface CL2-S of the second conductive layer CL2 is recessed towards the center of the first connecting electrode CEa compared to the side surfaces CL1-S of the first conductive layer CL1 and CL3-S of the third conductive layer CL3. In other words, the side surfaces CL1-S of the first conductive layer CL1 and CL3-S of the third conductive layer CL3 can protrude outward compared to the side surface CL2-S of the second conductive layer CL2. Accordingly, the first connecting electrode CEa can have a pointed structure due to the protruding portion of the third conductive layer CL3 compared to the second conductive layer CL2. For example, when the second conductive layer CL2 is etched using an etching material with an etching rate higher than that for the first and third conductive layers CL1 and CL3, the first connecting electrode CEa can be formed with a pointed structure.

[0485] exist Figure 20 In the illustration, the first connecting electrode CEa is shown as having a three-layer structure in which first conductive layers to third conductive layers CL1, CL2, and CL3 are stacked. However, this disclosure is not limited thereto, and in another embodiment, the first connecting electrode CEa may have a two-layer structure in which second conductive layer CL2 and third conductive layer CL3 are stacked. In another embodiment, the first conductive layer CL1 may be omitted.

[0486] The sixth insulating layer IL6 may partially cover the first connecting electrode CEa and may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may define a first sub-opening SO1 that exposes at least a portion of the first connecting electrode CEa. For example, the first sub-opening SO1 may expose the tip structure of the first connecting electrode CEa.

[0487] The first electrode E1 can be disposed in the display area DA on the substrate SUB. For example, the first electrode E1 can be disposed in the display area DA on the sixth insulating layer IL6. The first electrode E1 can include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. As described above, the first electrode E1 can be used as... Figure 17A and Figure 17B The anode.

[0488] A pixel defining layer PDL can be disposed on a substrate SUB and can define a pixel opening that exposes the first electrode E1. For example, the pixel defining layer PDL can be disposed on a sixth insulating layer IL6 and the first electrode E1 and can define a pixel opening that exposes at least a portion of the first electrode E1. A first emitter region EAa can be defined by the pixel opening.

[0489] The pixel defining layer PDL can further define a second sub-opening SO2 corresponding to a first sub-opening SO1 of the sixth insulating layer IL6. The second sub-opening SO2 can overlap with the first sub-opening SO1 in a plan view, and the first and second sub-openings SO1 and SO2 can be spatially connected to each other. For example, the first and second sub-openings SO1 and SO2 can be connected to define a sub-opening OP, and the sub-opening OP can expose at least a portion of the first connecting electrode CEa. For example, the sub-opening OP can expose the tip structure of the first connecting electrode CEa.

[0490] An organic film pattern (OGP) can be disposed in the display area (DA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the display area (DA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, the upper surface of the organic film pattern (OGP) can be an upwardly convex curved surface. The organic film pattern (OGP) can include an organic material. In an embodiment, the organic film pattern (OGP) and the pixel defining layer (PDL) can include different materials.

[0491] The separator SPR can be arranged on the pixel-defining layer (PDL). The side surface of the separator SPR connecting the upper and lower surfaces of the separator SPR can have a reverse tapered slope. In other words, the separator SPR can have an inverted trapezoidal cross-sectional shape.

[0492] exist Figure 20In the illustration, the side surface of the separator SPR is shown to have a single reverse tapering ramp. However, this disclosure is not limited thereto, and in another embodiment, the side surface of the separator SPR may have multiple reverse tapering ramps. For example, the separator SPR may have a double reverse tapering structure.

[0493] The spacer SPR may include a first portion SPP1 and a second portion SPP2 spaced apart from the first portion SPP1. The first portion SPP1 of the spacer SPR may overlap with the organic membrane pattern OGP in a planar view, and the second portion SPP2 of the spacer SPR may be spaced apart from the organic membrane pattern OGP in a planar view. In other words, the second portion SPP2 of the spacer SPR may not overlap with the organic membrane pattern OGP in a planar view.

[0494] Since the organic film pattern OGP is arranged between the pixel defining layer PDL and the first portion SPP1 of the separator SPR, the upper surface of the first portion SPP1 of the separator SPR can be an upwardly convex curved surface. In an embodiment, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Here, the horizontal height of the upper surface of the separator SPR can be the horizontal height of the highest part of the upper surface of the separator SPR.

[0495] An intermediate layer ML can be disposed on the first electrode E1 and the pixel defining layer PDL. A portion of the intermediate layer ML can be disposed in a pixel opening of the pixel defining layer PDL. In an embodiment, the intermediate layer ML may include a first functional layer comprising an organic material, a light-emitting layer disposed on the first functional layer and comprising a light-emitting material, and a second functional layer disposed on the light-emitting layer and comprising an organic material. For example, the first functional layer may include a hole injection layer or a hole transport layer, and the second functional layer may include an electron transport layer or an electron injection layer.

[0496] Shaded areas where intermediate layer ML is difficult to deposit can exist around separator SPRs with reverse tapering slopes. Accordingly, intermediate layer ML can be separated (or broken) by separator SPRs in and / or around shaded areas.

[0497] The intermediate layer ML can also be separated (or disconnected) by the tip structure of the first connecting electrode CEa. Since the intermediate layer ML is separated (or disconnected) by the tip structure of the first connecting electrode CEa, at least a portion of the side surface CL2-S of the second conductive layer CL2 can be exposed. Accordingly, the second electrode E2a of the first light-emitting element LDa can contact the side surface CL2-S of the second conductive layer CL2.

[0498] The first dummy layer DP1 can be arranged on the separator SPR. Since the intermediate layer ML is separated (or disconnected) by the separator SPR, the first dummy layer DP1 can be formed. For example, the first dummy layer DP1 and the intermediate layer ML can be formed in the same process. In an embodiment, the first dummy layer DP1 can be omitted.

[0499] Electrode layers E2L (i.e., second electrodes E2a, E2b, and E2c) can be disposed on the intermediate layer ML. In an embodiment, electrode layers E2L (i.e., second electrodes E2a, E2b, and E2c) can have a single-layer structure. However, this disclosure is not limited thereto, and in another embodiment, electrode layers E2L (i.e., second electrodes E2a, E2b, and E2c) can have a multilayer structure in which multiple conductive layers are stacked on top of each other. For example, electrode layers E2L (i.e., second electrodes E2a, E2b, and E2c) can have a two-layer structure comprising a first sub-electrode layer containing metal and a second sub-electrode layer disposed on the first sub-electrode layer and comprising a transparent conductive oxide.

[0500] Shaded areas where electrode layer E2L is difficult to deposit can exist around a separator SPR with a reverse tapered slope. Within and / or around these shaded areas, the electrode layer E2L can be separated (or disconnected) by the separator SPR. For example, as... Figure 19 As shown, the electrode layer E2L can be separated (or disconnected) into a second electrode E2a of the first light-emitting element LDa arranged in the first opening region OA1 of the separator SPR, a second electrode E2b of the second light-emitting element LDb arranged in the second opening region OA2 of the separator SPR, and a second electrode E2c of the third light-emitting element LDc arranged in the third opening region OA3 of the separator SPR. For example, the second electrodes E2a, E2b, and E2c can be electrically independent of each other.

[0501] like Figure 20 As shown, the electrode layer E2L (e.g., the second electrode E2a) can be electrically connected to the first connecting electrode CEa. Specifically, the electrode layer E2L (e.g., the second electrode E2a) can contact the side surface CL2-S of the second conductive layer CL2. For example, if the deposition angle of the deposition process used to form the electrode layer E2L is greater than the deposition angle of the deposition process used to form the intermediate layer ML, the electrode layer E2L (e.g., the second electrode E2a) can be formed to contact the side surface CL2-S of the second conductive layer CL2 while covering the intermediate layer ML that is disconnected by the tip structure. As a result, the second electrode E2a can be electrically connected to the first transistor TR1 through the first connecting electrode CEa.

[0502] In one embodiment, the electrode layer E2L (e.g., the second electrode E2a) may be separated (or disconnected) by the tip structure of the first connecting electrode CEa. However, this disclosure is not limited thereto, and in another embodiment, the electrode layer E2L (e.g., the second electrode E2a) may be formed to extend without being disconnected by the tip structure.

[0503] The second dummy layer DP2 can be disposed on the separator SPR. For example, the second dummy layer DP2 can be disposed on the first dummy layer DP1. Since the electrode layer E2L is separated (or disconnected) by the separator SPR, the second dummy layer DP2 can be formed. For example, the second dummy layer DP2 and the electrode layer E2L can be formed in the same process. In an embodiment, the second dummy layer DP2 can be omitted.

[0504] The encapsulation layer ENC can be disposed on the electrode layer E2L. The encapsulation layer ENC can completely cover the electrode layer E2L, the separator SPR, the first dummy layer DP1, and the second dummy layer DP2. In an embodiment, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1 containing inorganic insulating material, an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1 and containing organic insulating material, and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL and containing inorganic insulating material.

[0505] According to an embodiment, the display device DD3 may include connecting electrodes CEa, CEb, and CEc, and a separator SPR. Accordingly, the electrode layer E2L (e.g., cathode) disposed on the first electrode E1 (e.g., anode) can be readily electrically connected to the pixel driving circuits PCa, PCb, and PCc. For example, the electrode layer E2L disposed on the first electrode E1 can be connected to the driving transistors (e.g., [missing information]) of each of the pixel driving circuits PCa, PCb, and PCc via the connecting electrodes CEa, CEb, and CEc. Figure 17A and Figure 17B The drain of the first transistor T1 (or T1') is used. Accordingly, even with degradation of the light-emitting element, the gate-source voltage (Vgs) of the driving transistor remains unchanged. Consequently, the range of driving current variation due to light-emitting element degradation can be reduced. Therefore, the image retention defects of the display device DD3 that depend on increased usage time can be reduced, and the lifespan of the display device DD3 can be improved.

[0506] As described above, the horizontal height of the upper surface of the first portion SPP1 of the separator SPR can be higher than the horizontal height of the upper surface of the second portion SPP2 of the separator SPR. Accordingly, the mask used in the process of forming the intermediate layer ML can contact the first portion SPP1 of the separator SPR, but can avoid contacting the second portion SPP2. In other words, the area of ​​the separator SPR in contact with the mask can be relatively reduced. As a result, the phenomenon of mask pressing that may occur when the area of ​​the separator SPR in contact with the mask is large can be suppressed.

[0507] Figure 21 It is along Figure 16 A schematic cross-sectional view of the line V-V'.

[0508] refer to Figure 21 The display device DD3 according to embodiments of the present disclosure may include a substrate SUB, a first bottom conductive layer BML1, a first transistor TR1, a first capacitor CAP1, a second capacitor CAP2, a first connecting electrode CEa, first insulating layers to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, an intermediate layer ML, an electrode layer E2L, an organic film pattern OGP, a separator SPR, and an encapsulation layer ENC. In the following, references above... Figure 20 Redundant descriptions of the cross-sectional structure of the display device DD3 may be omitted or summarized.

[0509] An organic film pattern (OGP) can be disposed in the peripheral area (NDA) and on the pixel defining layer (PDL). For example, the organic film pattern (OGP) can be disposed in the peripheral area (NDA) between the pixel defining layer (PDL) and the separator (SPR). In an embodiment, the upper surface of the organic film pattern (OGP) can be an upwardly convex curved surface. The organic film pattern (OGP) can include an organic material. In an embodiment, the organic film pattern (OGP) and the pixel defining layer (PDL) can include different materials.

[0510] The separator SPR can be disposed on the pixel defining layer PDL. The separator SPR can contact the organic film pattern OGP and the pixel defining layer PDL in the peripheral region NDA. In an embodiment, in the peripheral region NDA, the organic film pattern OGP can overlap with a portion of the separator SPR in a planar view. For example, in the peripheral region NDA, the organic film pattern OGP can overlap with a first side surface of the separator SPR in a planar view. Since the upper surface of the organic film pattern OGP includes an upwardly convex curved surface, the upper surface of the separator SPR can also be an upwardly convex curved surface.

[0511] In an embodiment, such as Figure 21As shown, the cross-sectional shape of a portion of the separator SPR can be asymmetrical in the peripheral region NDA. For example, a first side surface of a portion of the separator SPR may contact the organic film pattern OGP in the peripheral region NDA, and a second side surface opposite to the first side surface may contact the pixel defining layer PDL without contacting the organic film pattern OGP. Accordingly, in the process of forming the separator SPR, the difference in the characteristics between the organic film pattern OGP and the pixel defining layer PDL can lead to a difference in the degree of inclination of the first side surface and the second side surface.

[0512] The second side surface of the separator SPR can have a reverse tapered slope. Because the second side surface of the separator SPR has a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can be separated (or disconnected) in the display area DA.

[0513] In contrast, the first side surface of the separator SPR may not have a reverse tapered slope. For example, by forming an organic film pattern OGP that overlaps with the first side surface of the separator SPR in a planar view within the peripheral region NDA, the first side surface of the separator SPR may not have a reverse tapered slope. Since the first side surface of the separator SPR does not have a reverse tapered slope, the intermediate layer ML and the electrode layer E2L can be formed as extended layers without being broken within the peripheral region NDA.

[0514] Figure 22 This is a plan view illustrating a display device according to an embodiment of the present disclosure. Figure 23 It is a diagram. Figure 22 A floor plan of a portion of the display device area. Figure 24 It is a diagram. Figure 23 An enlarged plan view of one of the unit emission regions in the unit emission region. Figure 25 It is along Figure 24 A schematic cross-sectional view of line VIII-VIII'.

[0515] For example, Figure 23 The diagram schematically illustrates the four cell transmission areas UEA1 and UEA2 arranged in a two-row, two-column matrix. Figure 24 The diagram schematically illustrates an enlarged view of the first transmission area, UEA1, among the two transmission areas, UEA1 and UEA2. For ease of description, Figure 25 Some of the components shown in the diagram are in Figure 23 and Figure 24 The text is either omitted or emphasized. For example, in... Figure 23 In the middle, the following was omitted. Figure 24 The second electrodes E2a, E2b, and E2c are shown in the diagram.

[0516] refer to Figure 22 , Figure 23, Figure 24 and Figure 25 The display device DD3-2 can be a device activated by an electrical signal. For example, such as... Figure 22 As shown, the display device DD3-2 can be a small display device used in small electronic devices such as smartphones, mobile phones, smartwatches, game consoles, or cameras. However, this disclosure is not limited thereto, and in another embodiment, the display device DD3-2 can be a medium-to-large display device used in medium-to-large electronic devices such as laptop computers, tablet computers, televisions, computer monitors, vehicle monitors, or external billboards.

[0517] Reference above Figure 16 , Figure 17A , Figure 17B , Figure 18 , Figure 19 and Figure 20 Compared to the described display device DD3, the display device DD3-2 may further include connecting electrodes (e.g., Figure 25 The first connecting electrode CEa) and the second electrode (e.g., Figure 25 The connection pattern of the second electrode E2a) electrically connected (e.g., Figure 25 The first connection pattern (CNPa). See below for reference. Figure 16 , Figure 17A , Figure 17B , Figure 18 , Figure 19 and Figure 20 The redundant description of the display device DD3 can be omitted or summarized.

[0518] like Figure 23 and Figure 24 As shown, the display device DD3-2 may include a first pixel driving circuit to a third pixel driving circuit PCa, PCb and PCc, a first light-emitting element to a third light-emitting element LDa, LDb and LDc, a first connecting electrode to a third connecting electrode CEa, CEb and CEc, a first connecting pattern to a third connecting pattern CNPa, CNPb and CNPc, a separator SPR and a plurality of organic film patterns OGP.

[0519] Each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be referenced above. Figure 17A and Figure 17B The pixel driving circuits PC2 and PC2' described correspond to one of them. For example, each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb and PCc may include at least one transistor and at least one capacitor. Figure 25 The diagram shows the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2.

[0520] Figure 25 The first transistor TR1 can be a transistor connected to the light-emitting element via connecting electrodes and connecting patterns. For example, in the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc, Figure 17A In the case of pixel driving circuit PC2, the first transistor TR1 can be Figure 17A The first transistor T1. PCa, PCb, and PCc in the first pixel driving circuit to the third pixel driving circuit are... Figure 17B In the case of pixel driving circuit PC2', the first transistor TR1 can be Figure 17B The fifth transistor, T5.

[0521] Each of the first to third light-emitting elements LDa, LDb, and LDc can be referenced above. Figure 17A and Figure 17B The light-emitting element LD is described. For example, each of the first to third light-emitting elements LDa, LDb, and LDc may include a first electrode (E1, reference). Figure 25 ), and the intermediate layer (ML, reference) arranged on the first electrode Figure 25 The first electrode is disposed on an intermediate layer and an electrode layer E2L. In an embodiment, the first electrode can be used as... Figure 17A and Figure 17B The anode, and the electrode layer E2L can be used as... Figure 17A and Figure 17B The cathode.

[0522] In an embodiment, the electrode layer E2L can be separated (or disconnected) by the separator SPR into a plurality of second electrodes E2a, E2b, and E2c spaced apart from each other. For example, the electrode layer E2L can be separated (or disconnected) into the second electrode E2a of the first light-emitting element LDa, the second electrode E2b of the second light-emitting element LDb, and the second electrode E2c of the third light-emitting element LDc.

[0523] The first to the third light-emitting elements LDa, LDb, and LDc can be connected to the first to the third pixel driving circuits PCa, PCb, and PCc, respectively. For example, the first light-emitting element LDa can be connected to the first pixel driving circuit PCa, the second light-emitting element LDb can be connected to the second pixel driving circuit PCb, and the third light-emitting element LDc can be connected to the third pixel driving circuit PCc.

[0524] The spacer splitter (SPR) can be arranged in a plan view between the first to third emission regions EAa, EAb, and EAc. For example, the spacer splitter SPR can be arranged in a plan view between the first emission region EAa and the second emission region EAb, between the second emission region EAb and the third emission region EAc, and between the first emission region EAa and the third emission region EAc. In an embodiment, the spacer splitter SPR can completely surround each of the first to third emission regions EAa, EAb, and EAc in a plan view. In an embodiment, the spacer splitter SPR may include an organic insulating material.

[0525] The separator SPR can separate (or disconnect) the electrode layer E2L in the display area DA into the second electrode E2a of the first light-emitting element LDa, the second electrode E2b of the second light-emitting element LDb, and the second electrode E2c of the third light-emitting element LDc. Accordingly, the second electrodes E2a, E2b, and E2c can be spaced apart from each other. The second electrodes E2a, E2b, and E2c can be electrically independent of each other.

[0526] The organic membrane pattern (OGP) can overlap with at least a portion of the spacer segment (SPR) in a plan view. The organic membrane pattern (OGP) can be arranged within a portion of the area where the spacer segment (SPR) is arranged. In other words, a portion of the spacer segment (e.g., Figure 25 The first part of the separator SPR (SPP1) can overlap with the organic membrane pattern OGP in the plan view, and the other part of the separator SPR (e.g., Figure 25 The second part (SPP2) of the separator SPR may not overlap with the organic membrane pattern OGP in the planar view. The organic membrane pattern OGP may include organic materials.

[0527] In an embodiment, the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a planar view. The intersection portion CRP of the separator SPR can be the portion where a first extension portion of the separator SPR extending in a first direction DR1 and a second extension portion of the separator SPR extending in a second direction DR2 intersect. For example, as Figure 23 As shown, the first organic film pattern OGP1 in the organic film pattern OGP can overlap with the intersection portion CRP of the separator SPR in a planar view. However, this disclosure is not limited thereto, and in another embodiment, the organic film pattern OGP can overlap with the first extension portion and the second extension portion of the separator SPR in a planar view. For example, as Figure 23 As shown, the second organic membrane pattern OGP2 in the organic membrane pattern OGP can overlap with the first extension portion or the second extension portion of the separator SPR in the plan view.

[0528] In one embodiment, the organic film pattern OGP can be arranged in the area where the spacer SPR is arranged in the plan view. However, this disclosure is not limited thereto, and in another embodiment, some of the organic film pattern OGPs can be arranged inside the area where the spacer SPR is arranged in the plan view, and other organic film pattern OGPs can overlap with both the area where the spacer SPR is arranged and the area where the spacer SPR is not arranged in the plan view.

[0529] In the following text, it will be referred to as Figure 24 Centered on the first unit emission region UEA1, this section describes in more detail the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third pixel driving circuits PCa, PCb, and PCc. The following description of the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third pixel driving circuits PCa, PCb, and PCc can be applied substantially equivalently to all unit emission regions.

[0530] As described above, the display device DD3-2 may include first connecting electrodes to third connecting electrodes CEa, CEb, and CEc, and first connecting patterns to third connecting patterns CNPa, CNPb, and CNPc. The first connecting electrode CEa and the first connecting pattern CNPa can electrically connect a first light-emitting element LDa and a first pixel driving circuit PCa. The second connecting electrode CEb and the second connecting pattern CNPb can electrically connect a second light-emitting element LDb and a second pixel driving circuit PCb. The third connecting electrode CEc and the third connecting pattern CNPc can electrically connect a third light-emitting element LDc and a third pixel driving circuit PCc.

[0531] The first to third connecting electrodes CEa, CEb, and CEc may comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. In embodiments, the first to third connecting electrodes CEa, CEb, and CEc may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0532] In this embodiment, the first to third connection patterns CNPa, CNPb, and CNPc may comprise transparent conductive oxides. For example, the first to third connection patterns CNPa, CNPb, and CNPc may comprise indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), and indium oxide (InO). x ), Tin oxide (SnO) x Gallium oxide (GaO) xMaterials such as zinc alumina (AZO) or zinc aluminum oxide can be used. These can be used alone or in combination with each other. However, this disclosure is not limited thereto, and in another embodiment, the first to third connection patterns CNPa, CNPb, and CNPc may include conductive materials such as metals, alloys, or conductive metal nitrides. In embodiments, the first to third connection patterns CNPa, CNPb, and CNPc may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked on top of each other.

[0533] The first connecting electrode CEa may include a first circuit connecting portion CPa and a first light-emitting connecting portion CNa.

[0534] The first circuit connection portion CPa can be the part of the first connection electrode CEa that is connected to the first pixel driving circuit PCa. For example, the location of the first circuit connection portion CPa can be related to the first transistor (TR1, reference) that exposes the first pixel driving circuit PCa. Figure 25 And penetrates the fifth insulating layer (IL5, reference) Figure 25 Contact holes (CNT, reference) Figure 25 The position corresponds to the location of ).

[0535] The first light-emitting connection portion CNa can be the portion of the first connection electrode CEa that is connected to the first connection pattern CNPa. For example, the first light-emitting connection portion CNa can be the portion of the first connection electrode CEa that is covered by a sixth insulating layer (IL6, reference). Figure 25 ) and Pixel Confinement Layer (PDL, reference) Figure 25 The portion of the first light-emitting connection portion CNa is exposed to connect to the first connection pattern CNa. Accordingly, the position of the first light-emitting connection portion CNa can be such that it exposes the first connection electrode CEa and penetrates the pixel defining layer PDL and the sixth insulating layer IL6 through a sub-opening (OP, reference) Figure 25 The positions of the first light-emitting connection portion CNa and the first emitting region EAa are corresponding. In the plan view, the first light-emitting connection portion CNa may not overlap with the first emitting region EAa. For example, in the plan view, the first light-emitting connection portion CNa may be arranged between the first emitting region EAa and the separator SPR.

[0536] The first connection pattern CNPa can be connected to the first connection electrode CEa. For example, the first connection pattern CNPa can contact the first light-emitting connection portion CNa of the first connection electrode CEa. However, this disclosure is not limited thereto, and in another embodiment, the first connection pattern CNPa may not directly contact the first connection electrode CEa. For example, the first connection pattern CNPa can contact a capping layer (which contacts the first light-emitting connection portion CNa of the first connection electrode CEa), and can be electrically connected to the first light-emitting connection portion CNa of the first connection electrode CEa through the capping layer. The capping layer may include a conductive material. For example, the capping layer and the first electrode E1 can be formed substantially simultaneously and can include the same material.

[0537] The first connection pattern CNPa may not overlap with the first emitter region EAa in a planar view. In an embodiment, the first connection pattern CNPa may surround at least a portion of the first emitter region EAa in a planar view. For example, the first connection pattern CNPa may have a closed-loop shape that completely surrounds the first emitter region EAa in a planar view. However, this disclosure is not limited thereto.

[0538] The second electrode E2a of the first light-emitting element LDa can be connected to the first connection pattern CNPa. For example, the second electrode E2a of the first light-emitting element LDa can contact the first connection pattern CNPa. Accordingly, the first connection pattern CNPa can electrically connect the first connection electrode CEa and the second electrode E2a of the first light-emitting element LDa. As a result, the second electrode E2a of the first light-emitting element LDa can be electrically connected to the first pixel driving circuit PCa through the first connection electrode CEa and the first connection pattern CNPa.

[0539] In an embodiment, in a planar view, the outline of the area where the second electrode E2a of the first light-emitting element LDa and the first connecting pattern CNPa contact each other can be substantially the same as or similar to the outline of the edge of the first connecting pattern CNPa. For example, if the first connecting pattern CNPa has a closed-loop shape that completely surrounds the first emitting region EAa in the planar view, the area where the second electrode E2a of the first light-emitting element LDa and the first connecting pattern CNPa contact each other can also have a closed-loop shape in the planar view. For example, the second electrode E2a of the first light-emitting element LDa and the first connecting pattern CNPa can contact each other at a position that does not overlap with the first emitting region EAa in the planar view. Accordingly, the second electrode E2a of the first light-emitting element LDa and the first pixel driving circuit PCa can be electrically connected to each other through the first connecting pattern CNPa and the first connecting electrode CEa without reducing the size of the first emitting region EAa.

[0540] The second connecting electrode CEb may include a second circuit connecting portion CPb and a second light-emitting connecting portion CNb.

[0541] The second circuit connection portion CPb can be the part of the second connection electrode CEb that connects to the second pixel driving circuit PCb. For example, the location of the second circuit connection portion CPb can correspond to the location of the contact hole that exposes the first transistor of the second pixel driving circuit PCb and penetrates the fifth insulating layer IL5.

[0542] The second light-emitting connection portion CNb can be the portion of the second connection electrode CEb that connects to the second connection pattern CNPb. For example, the second light-emitting connection portion CNb can be the portion of the second connection electrode CEb exposed by the sixth insulating layer IL6 and the pixel defining layer PDL for connection to the second connection pattern CNPb. Accordingly, the position of the second light-emitting connection portion CNb can correspond to the position of the sub-opening that exposes the second connection electrode CEb and penetrates the pixel defining layer PDL and the sixth insulating layer IL6. In a plan view, the second light-emitting connection portion CNb may not overlap with the second emitting region EAb. For example, in a plan view, the second light-emitting connection portion CNb can be arranged between the second emitting region EAb and the separator SPR.

[0543] In an embodiment, the second connecting electrode CEb may be spaced apart from the first connecting electrode CEa in a plan view. In other words, the first connecting electrode CEa and the second connecting electrode CEb may be different electrodes from each other.

[0544] The second connection pattern CNPb can be connected to the second connection electrode CEb. For example, the second connection pattern CNPb can contact the second light-emitting connection portion CNb of the second connection electrode CEb. However, this disclosure is not limited thereto, and in another embodiment, the second connection pattern CNPb may not directly contact the second connection electrode CEb. For example, the second connection pattern CNPb can contact a capping layer (which contacts the second light-emitting connection portion CNb of the second connection electrode CEb), and can be electrically connected to the second light-emitting connection portion CNb of the second connection electrode CEb through the capping layer. The capping layer may include a conductive material. For example, the capping layer and the first electrode E1 can be formed substantially simultaneously and can include the same material.

[0545] The second connection pattern CNPb may not overlap with the second emitter region EAb in a planar view. In an embodiment, the second connection pattern CNPb may surround at least a portion of the second emitter region EAb in a planar view. For example, the second connection pattern CNPb may have a closed-loop shape that completely surrounds the second emitter region EAb in a planar view. However, this disclosure is not limited thereto.

[0546] In an embodiment, the second connection pattern CNPb may be spaced apart from the first connection pattern CNPa. In other words, the first connection pattern CNPa and the second connection pattern CNPb may be different patterns from each other.

[0547] The second electrode E2b of the second light-emitting element LDb can be connected to the second connection pattern CNPb. For example, the second electrode E2b of the second light-emitting element LDb can contact the second connection pattern CNPb. Accordingly, the second connection pattern CNPb can electrically connect the second connection electrode CEb and the second electrode E2b of the second light-emitting element LDb. As a result, the second electrode E2b of the second light-emitting element LDb can be electrically connected to the second pixel driving circuit PCb through the second connection electrode CEb and the second connection pattern CNPb.

[0548] In an embodiment, in a planar view, the outline of the area where the second electrode E2b of the second light-emitting element LDb and the second connecting pattern CNPb contact each other can be substantially the same as or similar to the outline of the edge of the second connecting pattern CNPb. For example, when the second connecting pattern CNPb has a closed-loop shape that completely surrounds the second emitting region EAb in the planar view, the area where the second electrode E2b of the second light-emitting element LDb and the second connecting pattern CNPb contact each other can also have a closed-loop shape in the planar view. For example, the second electrode E2b of the second light-emitting element LDb and the second connecting pattern CNPb can contact each other at a location in the planar view that does not overlap with the second emitting region EAb. Accordingly, the second electrode E2b of the second light-emitting element LDb and the second pixel driving circuit PCb can be electrically connected to each other via the second connecting pattern CNPb and the second connecting electrode CEb without reducing the size of the second emitting region EAb.

[0549] The third connecting electrode CEc may include a third circuit connecting portion CPC and a third light-emitting connecting portion CNc.

[0550] The third circuit connection portion CPc can be the part of the third connection electrode CEc that connects to the third pixel driving circuit PCc. For example, the location of the third circuit connection portion CPc can correspond to the location of the contact hole that exposes the first transistor of the third pixel driving circuit PCc and penetrates the fifth insulating layer IL5.

[0551] The third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that connects to the third connection pattern CNPc. For example, the third light-emitting connection portion CNc can be the portion of the third connection electrode CEc exposed by the sixth insulating layer IL6 and the pixel defining layer PDL for connection to the third connection pattern CNPc. Accordingly, the position of the third light-emitting connection portion CNc can correspond to the position of the sub-opening that exposes the third connection electrode CEc and penetrates the pixel defining layer PDL and the sixth insulating layer IL6. In a plan view, the third light-emitting connection portion CNc may not overlap with the third emitting region EAc. For example, in a plan view, the third light-emitting connection portion CNc can be arranged between the third emitting region EAc and the separator SPR.

[0552] In an embodiment, the third connecting electrode CEc may be spaced apart from the first connecting electrode CEa and the second connecting electrode CEb in a plan view. In other words, the first connecting electrode CEa, the second connecting electrode CEb, and the third connecting electrode CEc may be different electrodes from each other.

[0553] The third connection pattern CNPc can be connected to the third connection electrode CEc. For example, the third connection pattern CNPc can contact the third light-emitting connection portion CNc of the third connection electrode CEc. However, this disclosure is not limited thereto, and in another embodiment, the third connection pattern CNPc may not directly contact the third connection electrode CEc. For example, the third connection pattern CNPc can contact a capping layer (which contacts the third light-emitting connection portion CNc of the third connection electrode CEc), and can be electrically connected to the third light-emitting connection portion CNc of the third connection electrode CEc through the capping layer. The capping layer may include a conductive material. For example, the capping layer and the first electrode E1 can be formed substantially simultaneously and can include the same material.

[0554] The third connection pattern CNPc may not overlap with the third emitter region EAc in a planar view. In an embodiment, the third connection pattern CNPc may surround at least a portion of the third emitter region EAc in a planar view. For example, the third connection pattern CNPc may have a closed-loop shape that completely surrounds the third emitter region EAc in a planar view. However, this disclosure is not limited thereto.

[0555] In an embodiment, the third connection pattern CNPc may be spaced apart from the first connection pattern CNPa and the second connection pattern CNPb. In other words, the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may be different patterns from each other.

[0556] The second electrode E2c of the third light-emitting element LDc can be connected to the third connection pattern CNPc. For example, the second electrode E2c of the third light-emitting element LDc can contact the third connection pattern CNPc. Accordingly, the third connection pattern CNPc can electrically connect the third connection electrode CEc and the second electrode E2c of the third light-emitting element LDc. As a result, the second electrode E2c of the third light-emitting element LDc can be electrically connected to the third pixel driving circuit PCc through the third connection electrode CEc and the third connection pattern CNPc.

[0557] In an embodiment, in a planar view, the outline of the area where the second electrode E2c of the third light-emitting element LDc and the third connecting pattern CNPc contact each other can be substantially the same as or similar to the outline of the edge of the third connecting pattern CNPc. For example, if the third connecting pattern CNPc has a closed-loop shape that completely surrounds the third emitting region EAc in the planar view, the area where the second electrode E2c of the third light-emitting element LDc and the third connecting pattern CNPc contact each other can also have a closed-loop shape in the planar view. For example, the second electrode E2c of the third light-emitting element LDc and the third connecting pattern CNPc can contact each other at a position that does not overlap with the third emitting region EAc in the planar view. Accordingly, the second electrode E2c of the third light-emitting element LDc and the third pixel driving circuit PCc can be electrically connected to each other through the third connecting pattern CNPc and the third connecting electrode CEc without reducing the size of the third emitting region EAc.

[0558] According to an embodiment, the second electrodes E2a, E2b, and E2c can respectively contact the first to third connection patterns CNPa, CNPb, and CNPc at positions in the planar view where they do not overlap with the first to third emission regions EAa, EAb, and EAc, respectively. Correspondingly, the second electrodes E2a, E2b, and E2c can contact the first to third connection patterns CNPa, CNPb, and CNPc, respectively, without reducing the size of each of the first to third emission regions EAa, EAb, and EAc.

[0559] According to an embodiment, the second electrodes E2a, E2b, and E2c can be electrically connected to the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc respectively via the first connecting electrode to the third connecting electrode CEa, CEb, and CEc and the first connecting pattern to the third connecting pattern CNPa, CNPb, and CNPc. Accordingly, the design limitations on each of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc due to the position, shape, and size of the first to third emitting regions EAa, EAb, and EAc can be reduced. For example, even if at least some of the first circuit connection portions to the third circuit connection portions CPa, CPb, and CPc overlap with the first to third emitting regions EAa, EAb, and EAc, the second electrodes E2a, E2b, and E2c can still be easily electrically connected to the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc respectively via the first connecting electrode to the third connecting electrode CEa, CEb, and CEc and the first connecting pattern to the third connecting pattern CNPa, CNPb, and CNPc. Accordingly, the shape or arrangement of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc can be designed independently of the position, shape, and size of the first to third emission regions EAa, EAb, and EAc. Consequently, the design freedom of each of the first to third pixel driving circuits PCa, PCb, and PCc can be increased.

[0560] like Figure 23 As shown, for each first unit transmitter region UEA1, the shape or arrangement of the first to third connecting electrodes CEa, CEb, and CEc, as well as the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same. For each second unit transmitter region UEA2, the shape or arrangement of each of the first to third connecting electrodes CEa, CEb, and CEc, as well as the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same.

[0561] For each first unit transmission area UEA1, the shape or arrangement of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the arrangement relationship between the first to third connection patterns CNPa, CNPb, and CNPc, can be the same. For each second unit transmission area UEA2, the shape or arrangement of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the arrangement relationship between the first to third connection patterns CNPa, CNPb, and CNPc, can be the same.

[0562] As described above, the display device DD3-2 may include a separator SPR. The separator SPR may be disposed on the pixel defining layer PDL and the first to third connection patterns CNPa, CNPb, and CNPc. In a plan view, the separator SPR may overlap with the first to third connection patterns CNPa, CNPb, and CNPc. For example, the separator SPR may cover a portion of each of the first to third connection patterns CNPa, CNPb, and CNPc. For example, at least a portion of the separator SPR may extend along the edge of each of the first to third connection patterns CNPa, CNPb, and CNPc. Accordingly, the areas of the second electrodes E2a, E2b, and E2c that contact each other with the first to third connection patterns CNPa, CNPb, and CNPc may be adjacent to or overlap with the separator SPR in a plan view.

[0563] The separator SPR can define first opening regions to third opening regions OA1, OA2, and OA3, respectively, corresponding to the second electrodes E2a, E2b, and E2c. For example, the separator SPR can have a grid structure surrounding the second electrodes E2a, E2b, and E2c in a plan view. In an embodiment, in a plan view, the shape of the first opening region OA1 can be substantially the same as the shape of the second electrode E2a of the first light-emitting element LDa, the shape of the second opening region OA2 can be substantially the same as the shape of the second electrode E2b of the second light-emitting element LDb, and the shape of the third opening region OA3 can be substantially the same as the shape of the second electrode E2c of the third light-emitting element LDc.

[0564] The first to third opening regions OA1, OA2, and OA3 of the separator SPR can correspond to the first to third connecting patterns CNPa, CNPb, and CNPc, respectively. For example, in a plan view, the first connecting pattern CNPa can overlap with the first opening region...

Claims

1. A display device comprising: a substrate including a display region and a peripheral region adjacent to the display region; a first electrode arranged on the substrate in the display region; an auxiliary electrode arranged on the substrate in the display region and spaced apart from the first electrode; a pixel-defining layer arranged on the substrate and defining an opening exposing the first electrode; an electrode layer arranged on the first electrode and electrically connected to the auxiliary electrode; a partition arranged on the pixel-defining layer and separating the electrode layer into a plurality of second electrodes spaced apart from each other in the display region; and an organic film pattern arranged between the pixel-defining layer and the partition in the display region and the peripheral region and overlapping at least a portion of the partition in a plan view in the display region and the peripheral region. the partition includes:

2. The display device according to claim 1, wherein a first portion overlapping the organic film pattern in the plan view; and a second portion spaced apart from the first portion and not overlapping the organic film pattern in the plan view. a horizontal level of an upper surface of the first portion of the partition is higher than a horizontal level of an upper surface of the second portion of the partition.

3. The display device of claim 2, wherein, 4. The display device according to claim 2, wherein the first portion of the partition covers the organic film pattern in the display region, and a first side surface of the first portion of the partition and a second side surface opposite to the first side surface contact the pixel-defining layer in the display region.

5. The display device according to claim 1, wherein the partition includes: a first extension portion extending in a first direction; a second extension portion extending in a second direction intersecting the first direction; and an intersection portion at which the first extension portion and the second extension portion intersect, and the organic film pattern overlaps the intersection portion of the partition in the plan view. the organic film pattern and the pixel-defining layer include different materials.

6. The display device according to claim 1, wherein a cross-sectional shape of a portion of the partition is asymmetric in the peripheral region.

7. The display device according to claim 1, wherein in the peripheral region, the organic film pattern overlaps a first side surface of the portion of the partition in the plan view.

8. The display device of claim 7, wherein, 9. The display device according to claim 8, wherein the first side surface of the portion of the partition contacts the organic film pattern in the peripheral region, and a second side surface of the portion of the partition opposite to the first side surface contacts the pixel-defining layer in the peripheral region.

10. The display device according to claim 1, further comprising: a connection pattern arranged on the auxiliary electrode and the pixel-defining layer and electrically connected to the auxiliary electrode, wherein the partition overlaps the connection pattern in the plan view. a portion of the connection pattern is arranged along contours of the pixel-defining layer and the organic film pattern in the display region.

11. The display device of claim 10, wherein, 12. The display device according to claim 10, wherein the connection pattern is arranged on the pixel-defining layer in the peripheral region, ​ a cross-sectional shape of a portion of the partition is asymmetric in the peripheral region, a first side surface of the portion of the partition contacts the organic film pattern in the peripheral region, and a second side surface of the portion of the partition, opposite the first side surface, contacts the connection pattern in the peripheral region.

13. The display device of claim 12, wherein, In the peripheral region, the organic film pattern overlaps an entire area of the partition in the plan view.

14. The display device according to claim 1, wherein the display area includes a first emission area to a third emission area from which light is emitted, and in the plan view, the partition surrounds at least a portion of each of the first emission area to the third emission area.

15. A display device comprising: a substrate including a display area and a peripheral area adjacent to the display area; a first electrode disposed on the substrate in the display area; an auxiliary electrode disposed on the substrate in the peripheral area; a pixel-defining layer disposed on the substrate and defining an opening exposing the first electrode; an electrode layer disposed on the first electrode and electrically connected to the auxiliary electrode; a partition disposed on the pixel-defining layer and separating the electrode layer into a second electrode disposed in the display area and a dummy electrode electrically connected to the auxiliary electrode and disposed in the peripheral area; a connection pattern disposed between the pixel-defining layer and the partition and electrically connecting the second electrode and the dummy electrode; and an organic film pattern disposed between the pixel-defining layer and the connection pattern and overlapping at least a portion of the partition in a plan view. the partition includes:

16. The display device of claim 15, wherein, a first portion overlapping the organic film pattern in the plan view; and a second portion spaced apart from the first portion and not overlapping the organic film pattern in the plan view. a horizontal height of an upper surface of the first portion of the partition is higher than a horizontal height of an upper surface of the second portion of the partition.

17. The display device of claim 16, wherein, a first side surface of the partition and a second side surface, opposite the first side surface, contact the connection pattern.

18. The display device of claim 15, wherein, a portion of the connection pattern is disposed along contours of the pixel-defining layer and the organic film pattern.

19. The display device of claim 15, wherein, in the plan view, each of the second electrode and the dummy electrode contacts the connection pattern in an area overlapping the partition.

20. The display device of claim 15, wherein, 21. The display device according to claim 15, further comprising: an auxiliary connection electrode disposed on the auxiliary electrode in the peripheral area and electrically connected to the auxiliary electrode, wherein the auxiliary connection electrode contacts the dummy electrode in the peripheral area.

22. A display device comprising: a substrate including a display area and a peripheral area adjacent to the display area; a pixel driving circuit disposed on the substrate and including a transistor; a first electrode disposed on the substrate in the display area; a connection electrode disposed on the substrate in the display area, spaced apart from the first electrode, and electrically connected to the pixel driving circuit; and an organic film pattern disposed between the pixel-defining layer and the connection pattern and overlapping at least a portion of the partition in a plan view. the partition includes: a first portion overlapping the organic film pattern in the plan view; and a second portion spaced apart from the first portion and not overlapping the organic film pattern in the plan view. a horizontal height of an upper surface of the first portion of the partition is higher than a horizontal height of an upper surface of the second portion of the partition. a first side surface of the partition and a second side surface, opposite the first side surface, contact the connection pattern. a portion of the connection pattern is disposed along contours of the pixel-defining layer and the organic film pattern. in the plan view, each of the second electrode and the dummy electrode contacts the connection pattern in an area overlapping the partition.

21. The display device according to claim 15, further comprising: an auxiliary connection electrode disposed on the auxiliary electrode in the peripheral area and electrically connected to the auxiliary electrode, wherein the auxiliary connection electrode contacts the dummy electrode in the peripheral area.

22. A display device comprising: a substrate including a display area and a peripheral area adjacent to the display area; a pixel driving circuit disposed on the substrate and including a transistor; a first electrode disposed on the substrate in the display area; a connection electrode disposed on the substrate in the display area, spaced apart from the first electrode, and electrically connected to the pixel driving circuit; and a pixel-defining layer arranged on the substrate and defining an opening exposing the first electrode; an electrode layer arranged on the first electrode and electrically connected to the connection electrode; a partition arranged on the pixel-defining layer and separating the electrode layer into a plurality of second electrodes spaced apart from each other in the display area; and an organic film pattern arranged between the pixel-defining layer and the partition in the display area and the peripheral area, and overlapping at least a portion of the partition in the plan view in the display area and the peripheral area.

23. The display device of claim 22, wherein, The partition includes: a first portion overlapping the organic film pattern in the plan view; and a second portion spaced apart from the first portion and not overlapping the organic film pattern in the plan view.

24. The display device of claim 23, wherein, A horizontal height of an upper surface of the first portion of the partition is higher than a horizontal height of an upper surface of the second portion of the partition.

25. The display device according to claim 23, wherein the first portion of the partition covers the organic film pattern in the display area, and a first side surface of the first portion of the partition and a second side surface opposite to the first side surface contact the pixel-defining layer in the display area.

26. The display device according to claim 22, wherein the partition includes: a first extending portion extending in a first direction; a second extending portion extending in a second direction intersecting the first direction; and an intersection portion at which the first extending portion and the second extending portion intersect, and the organic film pattern overlaps the intersection portion of the partition in the plan view.

27. The display device of claim 22, wherein, The organic film pattern and the pixel-defining layer include different materials.

28. The display device of claim 22, wherein, A cross-sectional shape of a portion of the partition is asymmetric in the peripheral area.

29. The display device of claim 28, wherein, In the peripheral area, the organic film pattern overlaps a first side surface of the portion of the partition in the plan view.

30. The display device according to claim 29, wherein the first side surface of the portion of the partition contacts the organic film pattern in the peripheral area, and a second side surface of the portion of the partition opposite to the first side surface contacts the pixel-defining layer in the peripheral area.

31. The display device according to claim 22, further comprising: a connection pattern arranged on the connection electrode and the pixel-defining layer and electrically connected to the connection electrode, wherein the partition overlaps the connection pattern in the plan view.

32. A display device according to claim 31, wherein, The connection pattern exposes at least a portion of the organic film pattern in the display area.

33. The display device according to claim 31, wherein the connection pattern is arranged on the pixel-defining layer in the peripheral area, a cross-sectional shape of a portion of the partition is asymmetric in the peripheral area, a first side surface of the portion of the partition contacts the organic film pattern in the peripheral area, and a second side surface of the portion of the partition opposite to the first side surface contacts the pixel-defining layer in the peripheral area. A second side surface of the portion of the partition opposite the first side surface contacts the connection pattern in the peripheral area.

34. The display device of claim 33, wherein, In the peripheral area, the organic film pattern overlaps the entire area of the partition in the plan view.

35. The display device according to claim 22, wherein The display area includes a first emission area to a third emission area from which light is emitted, and The partition completely surrounds each of the first emission area to the third emission area in the plan view.

36. An electronic device comprising: The display device according to any one of claims 1 to 35; and A processor that transmits an image data signal and an input control signal to the display device, and is communicatively connected to the display device.

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