Semiconductor device, display device, and method of manufacturing semiconductor device

Abstract

The present invention suppresses a reduction in channel resistance of a semiconductor device using an oxide semiconductor. The semiconductor device includes: an oxide semiconductor layer; a gate insulating layer disposed on the oxide semiconductor layer; a metal oxide layer that has an opening overlapping at least a part of the oxide semiconductor layer, and that is in contact with the upper surface of the gate insulating layer in a region not overlapping the oxide semiconductor layer; and a gate electrode disposed over the gate insulating layer in a region overlapping the oxide semiconductor layer.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device using an oxide semiconductor, a display device, and a method for manufacturing a semiconductor device. BACKGROUND

[0002] In recent years, development of semiconductor devices using an oxide semiconductor instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single crystal silicon has been progressing (see Patent Document 1, for example). For example, a transistor including an oxide semiconductor layer as a channel can be manufactured in a simple structure and at a low temperature, like a transistor including an amorphous silicon layer. It is known that a transistor including an oxide semiconductor layer has higher electric field effect mobility than a transistor including an amorphous silicon layer.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENT

[0005] Patent Document 1: Japanese Published Patent Application No. 2018-006730 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] A transistor using an oxide semiconductor layer as a channel tends to have a problem of deterioration in electrical characteristics due to reduction in channel resistance. For example, if hydrogen excessively diffuses into an oxide semiconductor that forms a channel, there is a problem in that the channel resistance is reduced and the transistor unexpectedly operates in a depletion mode.

[0008] One of the objects of one embodiment of the present application is to inhibit reduction in channel resistance of a semiconductor device using an oxide semiconductor.

[0009] MEANS FOR SOLVING PROBLEMS

[0010] A semiconductor device of one embodiment of the present application includes an oxide semiconductor layer, a gate insulating layer provided over the oxide semiconductor layer, a metal oxide layer having an opening portion overlapping with at least part of the oxide semiconductor layer and in contact with an upper surface of the gate insulating layer in a region where the oxide semiconductor layer does not overlap with the gate insulating layer, and a gate electrode provided over the gate insulating layer in a region overlapping with the oxide semiconductor layer.

[0011] The manufacturing method of a semiconductor device of one embodiment of the present application includes the following processes: forming an oxide semiconductor layer over an insulating surface, forming a gate insulating layer over the oxide semiconductor layer, forming a metal oxide layer having an opening portion overlapping at least part of the oxide semiconductor layer and in contact with an upper surface of the gate insulating layer, forming a gate electrode over the gate insulating layer, and adding impurities to the oxide semiconductor layer through the gate insulating layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 FIG. 1 is a schematic top view showing the configuration of a display device including a semiconductor device of one embodiment of the present application.

[0013] Figure 2 FIG. 2 is a schematic circuit diagram showing an equivalent circuit of a pixel including a semiconductor device of one embodiment of the present application.

[0014] Figure 3 FIG. 3 is a schematic cross-sectional view showing the configuration of a pixel including a semiconductor device of one embodiment of the present application.

[0015] Figure 4 FIG. 4 is a flow chart for describing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0016] Figure 5 FIG. 5 is a schematic cross-sectional view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0017] Figure 6 FIG. 6 is a schematic cross-sectional view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0018] Figure 7 FIG. 7 is a schematic cross-sectional view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0019] Figure 8 FIG. 8 is a schematic cross-sectional view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0020] Figure 9A FIG. 9 is a schematic top view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0021] Figure 9B FIG. 10 is a schematic cross-sectional view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0022] Figure 10A FIG. 11 is a schematic top view showing a manufacturing method of a pixel including a semiconductor device of one embodiment of the present application.

[0023] Figure 10B is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0024] Figure 10C is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0025] Figure 11 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0026] Figure 12 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0027] Figure 13 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0028] Figure 14 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0029] Figure 15 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0030] Figure 16 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0031] Figure 17 is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including one embodiment of the present application.

[0032] Figure 18A is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including a modification example of one embodiment of the present application.

[0033] Figure 18B is a schematic plan view showing a manufacturing method of a pixel of a semiconductor device including a modification example of one embodiment of the present application.

[0034] Figure 19A is a schematic cross-sectional view showing a manufacturing method of a pixel of a semiconductor device including a modification example of one embodiment of the present application.

[0035] Figure 19B is a schematic plan view showing a manufacturing method of a pixel of a semiconductor device including a modification example of one embodiment of the present application.

[0036] Figure 20 This is a schematic cross-sectional view showing the configuration of a pixel in a semiconductor device comprising an embodiment of the present invention.

[0037] Figure 21 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0038] Figure 22 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0039] Figure 23 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0040] Figure 24 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0041] Figure 25 This is a schematic cross-sectional view showing the configuration of a pixel in a semiconductor device comprising an embodiment of the present invention.

[0042] Figure 26 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0043] Figure 27 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0044] Figure 28 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0045] Figure 29 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel comprising a semiconductor device according to an embodiment of the present invention.

[0046] Figure 30 This is a schematic cross-sectional view showing the configuration of pixels in a semiconductor device comprising a modified embodiment of the present invention.

[0047] Figure 31 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel of a semiconductor device comprising a modified embodiment of the present invention.

[0048] Figure 32 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel of a semiconductor device comprising a modified embodiment of the present invention.

[0049] Figure 33 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel of a semiconductor device comprising a modified embodiment of the present invention.

[0050] Figure 34 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel of a semiconductor device comprising a modified embodiment of the present invention.

[0051] Explanation of reference numerals in the attached figures

[0052] 10…display device, 11…substrate, 12…display section, 13, 13a…pixel, 14-1…gate drive circuit, 14-2…gate drive circuit, 16…terminal, 17…terminal section, 18…flexible printed circuit, 19…peripheral section, 20…touch sensor, 100…substrate, 110…conductive layer, 120…insulating layer, 130, 130a…oxide semiconductor layer, 140…insulating layer, 145, 145a… 145b, 145c…metal oxide layer, 145-1, 145a-1, 145b-1, 145c-1…opening, 150…conductive layer, 160…insulating layer, 161, 162…contact hole, 181, 182…conductive layer, 190…insulating layer, 191…contact hole, 200…pixel electrode, 210…barrier, 212…opening, 220…light-emitting layer, 230…common electrode, 240…sealing layer Detailed Implementation

[0053] Embodiments of the present invention will now be described with reference to the accompanying drawings. The following disclosure is merely illustrative. Configurations readily conceived by those skilled in the art, while retaining the spirit of the invention, through appropriate modifications to the embodiments, are of course included within the scope of the invention. To make the description clearer, the drawings sometimes schematically represent the width, thickness, and shape of constituent elements compared to the actual embodiments. However, the illustrated shapes are merely examples and do not limit the interpretation of the invention. In this specification, claims, and drawings (hereinafter referred to as "this specification, etc."), the same reference numerals are used for constituent elements that are the same as those described with respect to the foregoing drawings, and detailed descriptions are appropriately omitted.

[0054] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below." While these terms are used for clarity, the vertical relationship between the substrate and the oxide semiconductor layer can be reversed. Furthermore, the phrase "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer; other components may be positioned between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking order in a multi-layered structure. In the case of a pixel electrode above a semiconductor device, it can also refer to a non-overlapping position when viewed from above. Conversely, a pixel electrode vertically above a semiconductor device refers to an overlapping position when viewed from above. It should be noted that "viewing from above" refers to viewing from a direction perpendicular to the surface of the substrate.

[0055] In this specification, multiple elements formed by etching or other processing of a film are sometimes described as elements with different functions or effects. These multiple elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer. That is, when it is stated in this specification that "A and B are the same layer", element A and element B both refer to elements formed by processing a single layer.

[0056] In this specification and other documents, unless otherwise expressly stated, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", or "α includes one of the groups selected from A, B, and C" do not preclude the possibility that α includes multiple combinations of A, B, and C. Furthermore, these expressions do not preclude the possibility that α includes other constituent elements.

[0057] In this specification and the like, "semiconductor device" refers to any device capable of functioning by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are included in one type of semiconductor device. The semiconductor devices of the embodiments shown below can be used, for example, in integrated circuits (ICs) or memory circuits such as display devices, microprocessors (MPUs).

[0058] In this specification and the like, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" sometimes also refers to a display panel that includes an electro-optical layer, or to a structure in which other optical components (such as polarizing components, backlights, touch panels, etc.) are mounted on a display unit. As long as there is no technical inconsistency, "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer. Therefore, regarding the embodiments described later, an organic EL display device including an organic EL layer will be exemplified as a display device, but the structure in this embodiment can be applied to display devices that include the other electro-optical layers mentioned above.

[0059] In this instruction manual and other documents, the terms "membrane" and "layer" may be used interchangeably as appropriate.

[0060] The source and drain of a transistor can sometimes switch their functions in response to the voltage supplied to them. Therefore, in this specification and other documents, the terms "source" and "drain" can be used interchangeably as appropriate.

[0061] It should be noted that the following implementation methods can be combined with each other as long as no technical contradictions arise.

[0062] <First Embodiment>

[0063] (Composition of the display device)

[0064] The following describes a display device 10 according to one embodiment of the present invention. In this embodiment, an organic EL display device is exemplified as the display device 10. An organic EL display device is a display device in which each pixel includes an organic EL element as a light-emitting element and a semiconductor device for driving the light-emitting element.

[0065] Figure 1 This is a schematic top view illustrating the configuration of a display device 10 incorporating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the display device 10 includes a display portion 12 and a peripheral portion 19 disposed on a substrate 11. The display portion 12 has a plurality of pixels 13 arranged in a matrix. Each of the plurality of pixels 13 has a semiconductor device composed of a plurality of transistors and a light-emitting element, which will be described later. A touch sensor 20 is disposed on the display portion 12 and on the display portion 12.

[0066] The peripheral portion 19 is provided in a manner that surrounds the display portion 12. The peripheral portion 19 refers to the portion of the substrate 11 from the display portion 12 to the end of the substrate 11. That is, the peripheral portion 19 refers to the portion of the substrate 11 excluding the portion where the display portion 12 is located (specifically, the portion outside the display portion 12). The peripheral portion 19 has gate drive circuits 14-1 and 14-2 and a terminal portion 17 containing multiple terminals 16. The gate drive circuits 14-1 and 14-2 are provided in a manner that sandwiches the display portion 12. The terminal portion 17 is connected to a flexible printed circuit 18 on which a driver IC 15 is mounted. Multiple wirings (not shown) included in the flexible printed circuit 18 are connected to the driver IC 15 and the terminal portion 17. Figure 1 In the example shown, the source drive circuit is assembled in the driver IC15. However, it is not limited to this example; the source drive circuit can also be formed on the substrate 11 using transistors.

[0067] Driver IC 15 is connected to gate drive circuits 14-1 and 14-2 and multiple image signal lines VL. Gate drive circuit 14-1 or gate drive circuit 14-2 is connected to pixel 13 via selection control line Sg. For example, the selection control lines Sg in odd-numbered rows are connected to gate drive circuit 14-1, and the selection control lines Sg in even-numbered rows are connected to gate drive circuit 14-2. Image signal lines VL are connected to pixel 13. Control signals SG for selecting each pixel 13 are supplied from driver IC 15 to display unit 12 via gate drive circuits 14-1 and 14-2 and selection control lines Sg (see...). Figure 2 Additionally, an image signal Vsig is supplied from the driver IC15 to the display unit 12 via the image signal line VL (see [link]). Figure 2 Based on these signals, the multiple transistors contained in pixel 13 can be driven to display an image corresponding to the image signal Vsig on the display unit 12. The high-potential power line SLa and the low-potential power line SLb connected to pixel 13 are respectively connected to different terminals 16.

[0068] As the substrate 11, a glass substrate, a quartz substrate, a ceramic substrate, a flexible plastic substrate, or a resin substrate can be used. When a flexible plastic substrate or a resin substrate is used as the substrate 11, the substrate 11 can be bent between the display section 12 and the terminal section 17. This reduces the area of ​​the bezel portion of the display device 10.

[0069] (The structure of a pixel circuit)

[0070] Figure 2This is a schematic circuit diagram illustrating the circuit configuration of a pixel 13 comprising a semiconductor device according to an embodiment of the present invention. Each pixel 13 constituting the display device 10 is connected to a high-potential power line SLa, a low-potential power line SLb, a selection control line Sg, and an image signal line VL. The high-potential power line SLa is connected to a high-potential power supply Pvdd. The low-potential power line SLb is connected to a low-potential power supply Pvss. The selection control line Sg is connected to gate drive circuits 14-1 and 14-2. The image signal line VL is connected to a driver IC 15 that supplies the image signal Vsig.

[0071] Each pixel 13 has at least a driving transistor DRT, a selection transistor SST, and a light-emitting element OLED. The anode of the light-emitting element OLED is connected to a high-potential power supply Pvdd via the driving transistor DRT. The cathode of the light-emitting element OLED is connected to a low-potential power supply Pvss. In this embodiment, the anode of the light-emitting element OLED is connected to the pixel electrode 200 (see...). Figure 3 ) connection, cathode and common electrode 230 (see Figure 3 )connect.

[0072] The driving transistor DRT is connected in series with the light-emitting element OLED between the high-potential power line SLa and the low-potential power line SLb. The driving transistor DRT functions as a current control element, controlling the current flowing to the light-emitting element OLED according to the gate-source voltage. The selection transistor SST functions as a switching element, selecting whether the two nodes are on or off, applying a voltage corresponding to the luminous intensity of the light-emitting element OLED to the gate of the driving transistor DRT. A holding capacitor Cs is provided between the gate and source of the driving transistor DRT. The holding capacitor Cs maintains the gate-source voltage of the driving transistor DRT.

[0073] The gate of the select transistor SST is connected to the select control line Sg, one of its source or drain is connected to the image signal line VL, and the other of its source or drain is connected to the gate of the drive transistor DRT and the holding capacitor Cs. The drain of the drive transistor DRT is connected to the high-potential power line SLa, and its source is connected to the holding capacitor Cs and the anode of the OLED. The cathode of the OLED is connected to the low-potential power line SLb. The drive transistor DRT outputs a drive current to the OLED in an amount corresponding to the image signal Vsig.

[0074] Although the illustration is omitted, pixel 13 may also include other transistors such as a correction transistor that corrects the threshold of the driving transistor DRT, a reset transistor that resets the voltage held by the holding capacitor Cs, and so on.

[0075] In this embodiment, oxide semiconductors are used as the semiconductors in the select transistor (SST) and drive transistor (DRT). Transistors using oxide semiconductors have low cutoff leakage current and can achieve low-frequency drive, thus consuming less power. Therefore, by using oxide semiconductors to form pixels, the power consumption of the display device 10 can be reduced. Furthermore, compared to transistors using so-called low-temperature polysilicon, transistors using oxide semiconductors also exhibit no observed kink effect and good saturation characteristics.

[0076] (Pixel structure)

[0077] Figure 3 This is a schematic cross-sectional view illustrating the configuration of pixel 13, which includes a semiconductor device according to one embodiment of the present invention. Figure 3 In pixel 13 shown, a driving transistor DRT, which supplies current to the light-emitting element OLED, is illustrated as a semiconductor device. Additionally, Figure 3 Not shown in the image, but contained in pixel 13. Figure 2 The selection transistor SST is shown. Figure 3 Pixel 13 shown may also contain more transistors in addition to the driving transistor DRT and the selection transistor SST.

[0078] The driving transistor DRT of this embodiment includes a conductive layer 110, an insulating layer 120, an oxide semiconductor layer 130, an insulating layer 140, a metal oxide layer 145, a conductive layer 150, an insulating layer 160, a conductive layer 181, and a conductive layer 182 disposed on a substrate 100 having an insulating surface.

[0079] The substrate 100 is, for example, a glass substrate on which one or more insulating layers are formed, made of a material selected from insulating oxides such as silicon oxide (SiOx) or silicon oxynitride (SiOxNy), or insulating nitrides such as silicon nitride (SiNx) or silicon oxynitride (SiNxOy). Here, silicon oxynitride (SiNxOy) is a silicon oxide in which the oxygen ratio (x > y) is less than the nitrogen ratio. Silicon oxynitride (SiOxNy) is a silicon nitride in which the nitrogen (N) ratio (x > y) is less than the oxygen (O) ratio.

[0080] In this embodiment, a substrate 100 having an insulating surface is formed by sequentially stacking a silicon nitride layer and a silicon oxide layer on a glass substrate from bottom to top. The silicon nitride layer serves as a protective layer to prevent the intrusion of contaminants (e.g., alkaline substances) from the glass substrate. However, this embodiment is not limited to this example; a quartz substrate, ceramic substrate, plastic substrate, or resin substrate may be used instead of a glass substrate. Furthermore, the stacking order of the silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or silicon oxynitride layer is arbitrary.

[0081] A conductive layer 110 is disposed on the substrate 100. The conductive layer 110 functions as the gate electrode on the lower side of the driving transistor DRT. As the material constituting the conductive layer 110, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W) or alloys thereof can be used. In this embodiment, a molybdenum-tungsten alloy is used as the material constituting the conductive layer 110. The conductive layer 110 also functions as a light-shielding layer to reduce light reaching the oxide semiconductor layer 130 from the lower side.

[0082] An insulating layer 120 is disposed above the conductive layer 110. The insulating layer 120 functions as a gate insulating layer on the lower side of the driving transistor DRT. One or more layers selected from silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride can be used as the insulating layer 120. In this embodiment, an insulating layer consisting of a silicon nitride layer and a silicon oxide layer stacked sequentially from bottom to top is used as the insulating layer 120. As will be described later, since an oxide semiconductor layer 130 is provided above the insulating layer 120, it is preferable that the surface of the insulating layer 120 in contact with the oxide semiconductor layer 130 is a silicon oxide layer.

[0083] The thickness of the insulating layer 120 is not particularly limited. In this embodiment, the thickness of the insulating layer 120 is set to 200 nm or more and 600 nm or less (preferably 300 nm or more and 500 nm or less, and more preferably 350 nm or more and 450 nm or less). In this embodiment, the insulating layer 120 is a laminated structure consisting of a silicon nitride layer with a thickness of 100 nm and a silicon oxide layer with a thickness of 200 nm.

[0084] An oxide semiconductor layer 130 is disposed on the insulating layer 120. The oxide semiconductor layer 130 functions as the active layer in the driving transistor DRT. As the material constituting the oxide semiconductor layer 130, an amorphous oxide semiconductor (e.g., IGZO) can be used. The thickness of the oxide semiconductor layer 130 can be set to 10 nm or more and 100 nm or less (preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 40 nm or less).

[0085] As detailed below, the oxide semiconductor layer 130 can be formed using a sputtering method. The composition of the oxide semiconductor layer 130 formed using the sputtering method depends on the composition of the sputtering target.

[0086] In addition, such as Figure 3As shown, the oxide semiconductor layer 130 is divided into a channel region CR, a source region SR, and a drain region DR. The channel region CR is the region overlapping with the conductive layer 150, which functions as a gate electrode, and forms a channel when a gate voltage is applied to the conductive layer 150. The source region SR and the drain region DR are regions with lower resistance compared to the channel region CR, and function as conductive regions. That is, the source region SR and the drain region DR have a higher conductivity than the channel region CR. In other words, the source region SR and the drain region DR have the properties of conductors, and the channel region has the properties of a semiconductor. As described later, the source region SR and the drain region DR are formed by adding impurities to the oxide semiconductor layer 130 using methods such as ion implantation.

[0087] An insulating layer 140 is disposed on the oxide semiconductor layer 130. The insulating layer 140 functions as the gate insulating layer on the upper side of the driving transistor DRT. One or more layers selected from silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride can be used as the insulating layer 140. In this embodiment, a silicon oxide layer is used as the insulating layer 140. Preferably, the insulating layer 140 has a composition with few defects and a close stoichiometry. Specifically, it is preferable that no defects are observed in the insulating layer 140 when evaluated by the electron spin resonance (ESR) method. The thickness of the insulating layer 140 is not particularly limited. In this embodiment, the thickness of the insulating layer 140 is set to 50 nm or more and 300 nm or less (preferably 60 nm or more and 200 nm or less, more preferably 70 nm or more and 150 nm or less).

[0088] The metal oxide layer 145 is a layer composed of an oxide insulating material containing metal, formed by sputtering as described later. In this embodiment, an aluminum-based metal oxide is used as the metal oxide layer 145. For example, inorganic insulating layers such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum oxynitride (AlNxOy), and aluminum nitride (AlNx) are used as the metal oxide layer 145. The description "aluminum-based metal oxide layer" means that the proportion of aluminum contained in the metal oxide layer 145 is 1% or more of the entire metal oxide layer 145. The proportion of aluminum contained in the metal oxide layer 145 may also be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer 145. The above proportions can be mass ratios or weight ratios. In this embodiment, the thickness of the metal oxide layer 145 is 20 nm or less (preferably 15 nm or less, more preferably 10 nm or less).

[0089] In this embodiment, the metal oxide layer 145 has an opening 145-1. As described later, the opening 145-1 is configured to overlap with at least a portion of the oxide semiconductor layer 130. That is, the metal oxide layer 145 is provided with the opening 145-1 so that the entire or substantially the entire oxide semiconductor layer 130 is exposed when viewed from above (i.e., the metal oxide layer 145 does not overlap with the oxide semiconductor layer 130). Therefore, the metal oxide layer 145 can also be referred to as a metal oxide pattern.

[0090] A conductive layer 150 is disposed on top of the insulating layer 140. The conductive layer 150 functions as the gate electrode on the upper side of the driving transistor DRT. As the material constituting the conductive layer 150, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W) or alloys thereof can be used. In this embodiment, a molybdenum-tungsten alloy is used as the material constituting the conductive layer 150. The conductive layer 150 also functions as a light-shielding layer to reduce light reaching the oxide semiconductor layer 130 from the upper side.

[0091] As described above, the conductive layer 150 functions as the gate electrode on the upper side of the driving transistor DRT, but also functions as a gate wiring. In other words, the conductive layer 150 functions as a gate wiring, and the portion of the gate wiring that overlaps with the oxide semiconductor layer, which functions as the active layer of the transistor, functions as the gate electrode. Therefore, in this specification, for ease of explanation, the gate electrode and the gate wiring are sometimes described separately, but they are sometimes integral components.

[0092] An insulating layer 160 is disposed on the conductive layer 150. The insulating layer 160 functions as an interlayer insulating layer in a driving transistor DRT. As the insulating layer 160, one or more layers selected from silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride can be used. In this embodiment, a stacked structure including a silicon oxide layer and a silicon nitride layer is used as the insulating layer 160.

[0093] Conductive layers 181 and 182 are disposed on the insulating layer 160. Conductive layer 181 is connected to the source region SR of the oxide semiconductor layer 130 via a contact hole 161 disposed in the insulating layer 160, and functions as the source electrode in the driving transistor DRT. Conductive layer 182 is connected to the drain region DR of the oxide semiconductor layer 130 via a contact hole 162 disposed in the insulating layer 160, and functions as the drain electrode in the driving transistor DRT. In other words, conductive layers 181 and 182 respectively function as terminal electrodes in the driving transistor DRT.

[0094] Materials constituting conductive layers 181 and 182 can include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W) or alloys thereof. In this embodiment, a laminated structure comprising a titanium layer and an aluminum layer is used as the materials constituting conductive layers 181 and 182.

[0095] As explained above, the driving transistor DRT in this embodiment is a dual-gate transistor comprising a lower-side gate electrode (conductive layer 110) facing the oxide semiconductor layer 130 separated by an insulating layer 120, and an upper-side gate electrode (conductive layer 150) facing the oxide semiconductor layer 130 separated by an insulating layer 140. However, it is not limited to this example; the driving transistor DRT can also be a top-gate transistor. For example, in the case of… Figure 3 When a fixed voltage is applied to the conductive layer 110, and the conductive layer 110 is not used as a gate electrode, the driving transistor DRT functions as a top-gate transistor.

[0096] An insulating layer 190 is provided above the driving transistor DRT as a planarization layer made of resin material. The pixel electrode 200 is connected to the conductive layer 181 (i.e., the source electrode of the driving transistor DRT) via a contact hole 191 provided in the insulating layer 190. In this embodiment, the pixel electrode 200 is constructed using a stacked structure of a layer containing silver (Ag) and a layer containing a metal oxide (e.g., ITO), but is not limited thereto.

[0097] A septum 210 made of resin material is provided above the pixel electrode 200. The septum 210 is also referred to as a partition or rib. The septum 210 is provided in such a way that it covers a portion of the pixel electrode 200. That is, the septum 210 has an opening 212 at the location where it overlaps with the pixel electrode 200. The area of ​​the pixel electrode 200 not covered by the septum 210 (exposed area) functions as the light-emitting area of ​​the pixel 13. A light-emitting layer 220 made of organic EL (electroluminescent) material is provided in such a way that it covers the exposed area of ​​the pixel electrode 200.

[0098] In addition, a common electrode 230 is provided in such a way that it covers the dike 210 and the light-emitting layer 220. Figure 3 Not shown in the diagram, but the common electrode 230 is arranged across multiple pixels 13. The pixel electrode 200, the light-emitting layer 220, and the common electrode 230 constitute the light-emitting element OLED. The pixel electrode 200 functions as the anode of the light-emitting element OLED. The common electrode 230 functions as the cathode of the light-emitting element OLED.

[0099] An encapsulation layer 240 is provided on top of the light-emitting element OLED. The encapsulation layer 240 is a protective layer for preventing the intrusion of external moisture and other contaminants. In this embodiment, the encapsulation layer 240 is constructed by sequentially stacking an inorganic insulating layer, an organic insulating layer, and another inorganic insulating layer from the bottom layer. For example, a silicon nitride layer can be used as the inorganic insulating layer. For example, an organic resin layer (e.g., a resin layer made of polyimide or acrylic acid) can be used as the organic insulating layer.

[0100] As explained above, pixel 13 includes a driving transistor DRT, but in connection with the manufacturing method described later, a characteristic impurity distribution exists around the driving transistor DRT. This will be explained in detail along with the semiconductor device manufacturing method described below.

[0101] (Methods for manufacturing pixels)

[0102] Figure 4 This is a flowchart illustrating a method for manufacturing a pixel 13 comprising a semiconductor device according to an embodiment of the present invention. Figures 5 to 8 , Figure 9B , Figure 10B , Figure 10C and Figures 11 to 17 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13 comprising a semiconductor device according to an embodiment of the present invention. Figure 9A and Figure 10A This is a schematic top view illustrating a method for manufacturing a pixel 13 comprising a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the semiconductor device manufacturing method of this embodiment includes steps S1010 to S1130. Steps S1010 to S1130 will be described sequentially below, but the order of the steps in the semiconductor device manufacturing method of this embodiment may sometimes be switched. In addition, in the semiconductor device manufacturing method of this embodiment, one or more steps may be omitted, or further steps may be included.

[0103] First, such as Figure 4 and Figure 5 As shown, a conductive layer 110 (first conductive layer) with a predetermined pattern shape is formed on the substrate 100 (step S1010). The patterning of the conductive layer 110 is performed using photolithography. In this embodiment, the conductive layer 110 functions as a light-shielding layer. Additionally, an insulating layer 120 (first insulating layer) is formed to cover the conductive layer 110. The insulating layer 120 is formed using chemical vapor deposition (CVD). In this embodiment, the insulating layer 120 uses a stacked structure consisting of a 100 nm thick silicon nitride layer and a 200 nm thick silicon oxide layer.

[0104] Next, as Figure 4 and Figure 6 As shown, an oxide semiconductor layer 130 with a predetermined pattern shape is formed on the insulating layer 120 (step S1020). The oxide semiconductor layer 130 is formed in a manner that overlaps with the conductive layer 110. The oxide semiconductor layer 130 is formed by photolithographically patterning an oxide semiconductor film deposited by sputtering into a predetermined shape. The oxide semiconductor film deposited by sputtering has an amorphous structure.

[0105] Oxide semiconductor films with amorphous structures can be easily patterned using photolithography. When etching oxide semiconductor films, either wet etching or dry etching can be used. In the case of wet etching, acidic etching solutions can be used to etch the oxide semiconductor films. For example, oxalic acid solution, PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) solution, sulfuric acid solution, hydrogen peroxide solution, or hydrofluoric acid solution can be used as etching solutions.

[0106] Furthermore, the oxide semiconductor layer 130 having a prescribed pattern shape is subjected to heat treatment. Hereinafter, the heat treatment performed in step S1020 will be referred to as "OS annealing". In OS annealing, the oxide semiconductor layer 130 is held at a prescribed arrival temperature for a prescribed time. The prescribed arrival temperature is 300°C to 500°C (preferably 350°C to 450°C). Furthermore, the holding time at the arrival temperature is 15 minutes to 120 minutes (preferably 30 minutes to 60 minutes).

[0107] Next, as Figure 4 and Figure 7 As shown, an insulating layer 140 (second insulating layer) is formed on the oxide semiconductor layer 130 (step S1030). In this embodiment, a silicon oxide layer with a thickness of 100 nm is used as the insulating layer 140.

[0108] Next, as Figure 4 and Figure 8 As shown, a metal oxide layer 145 is formed on the insulating layer 140 (step S1040). In this embodiment, an aluminum oxide (AlOx) layer with a thickness of 8 nm is formed as the metal oxide layer 145 by sputtering. During the formation of the metal oxide layer 145 by sputtering, a large amount of oxygen enters the interior of the insulating layer 140. The metal oxide layer 145 at this stage is an unprocessed metal oxide layer (a metal oxide layer in a film state) that has not undergone patterning.

[0109] Further heat treatment is performed on the insulating layer 140. Hereinafter, the heat treatment performed in step S1040 will be referred to as "oxidative annealing". Through the formation of the oxide semiconductor layer 130 and the insulating layer 140, a large number of oxygen defects are generated inside the oxide semiconductor layer 130. When oxidative annealing is performed, oxygen is supplied from the insulating layer 140 to the oxide semiconductor layer 130, and the oxygen defects in the oxide semiconductor layer 130 are repaired. In this embodiment, during the formation of the metal oxide layer 145, oxygen is injected into the interior of the insulating layer 140, increasing the oxygen content inside the insulating layer 140. Therefore, a sufficient amount of oxygen can be supplied to the oxide semiconductor layer 130 through oxidative annealing. Furthermore, since the metal oxide layer 145 functions as a barrier layer to prevent oxygen movement, oxygen can be efficiently supplied to the oxide semiconductor layer 130.

[0110] Next, as Figure 4 , Figure 9A and Figure 9B As shown, the metal oxide layer 145 is patterned to form an opening 145-1 (step S1050). In this embodiment, a resist mask (not shown) is formed on the metal oxide layer 145 by photolithography, and the opening 145-1 is formed by etching the metal oxide layer 145 using a wet etching process with an aqueous hydrofluoric acid solution. The metal oxide layer 145 at this stage is a patterned metal oxide layer (patterned metal oxide layer).

[0111] like Figure 9A As shown, the metal oxide layer 145 is formed in a region that does not overlap with the oxide semiconductor layer 130. Specifically, the position of the inner wall of the opening 145-1 coincides with the position of the end of the oxide semiconductor layer 130 in a direction perpendicular to the substrate 100. In other words, as... Figure 9A and Figure 9B As shown, when viewed from above, the shape of the edge of the opening 145-1 in the metal oxide layer 145 is consistent with the shape of the edge of the oxide semiconductor layer 130.

[0112] The term "consistent" here includes not only cases of complete consistency, but also cases where the alignment falls within the error range during the formation of the opening 145-1. For example, even if the position of the edge of the opening 145-1 differs from the position of the edge of the oxide semiconductor layer 130 within a range of 1.5 μm (preferably 1.0 μm, more preferably 0.5 μm), the edge of the opening 145-1 is considered to be consistent with the edge of the oxide semiconductor layer 130.

[0113] In addition, strictly speaking, in Figure 9BThe example shown is that the position of the inner wall of the opening 145-1 is consistent with the position of the end of the upper surface of the oxide semiconductor layer 130 in a direction perpendicular to the substrate 100, but the position of the inner wall of the opening 145-1 and the position of the end of the lower surface of the oxide semiconductor layer 130 may also be consistent in a direction perpendicular to the substrate 100.

[0114] Next, as Figure 4 , Figure 10A , Figure 10B and Figure 10C As shown, a conductive layer 150 (second conductive layer) is formed on the insulating layer 140 and the metal oxide layer 145 (step S1060). In this embodiment, the conductive layer 150 functions as a gate wiring. In this embodiment, the conductive layer 150 is formed by sputtering a metal film made of molybdenum-tungsten alloy and patterning the metal film into a predetermined shape. In this embodiment, the thickness of the conductive layer 150 is set to 300 nm, but it is not limited to this.

[0115] like Figure 10A As shown, the conductive layer 150 is formed in a manner that intersects with the oxide semiconductor layer 130. Specifically, the conductive layer 150 has a length direction that intersects the length direction (channel direction) of the oxide semiconductor layer 130. Figure 10A In the middle, the sectional view cut along the single-dotted line shown as A-A' and Figure 10B Correspondingly, the sectional view cut along the single-dotted line shown as B-B' is... Figure 10C correspond.

[0116] like Figure 10B As shown, in the region where the oxide semiconductor layer 130 and the conductive layer 150 overlap, the oxide semiconductor layer 130 and the conductive layer 150 are opposite each other with an insulating layer 140 between them. The region where the oxide semiconductor layer 130 and the conductive layer 150 overlap is located inside the opening 145-1 of the metal oxide layer 145. Therefore, in the region where the oxide semiconductor layer 130 and the conductive layer 150 overlap, the conductive layer 150 is in contact with the insulating layer 140.

[0117] In addition, such as Figure 10CAs shown, in the region where the oxide semiconductor layer 130 and the conductive layer 150 do not overlap, a metal oxide layer 145 is disposed between the insulating layer 140 and the conductive layer 150. That is, in the region where the oxide semiconductor layer 130 and the conductive layer 150 do not overlap, the conductive layer 150 is in contact with the metal oxide layer 145. In this way, the oxide semiconductor layer 130 is surrounded by the metal oxide layer 145, therefore, a large amount of oxygen remains in the insulating layer 140 located in the region covered by the metal oxide layer 145. As a result, as described later, the amount of hydrogen diffusing from the surrounding area of ​​the oxide semiconductor layer 130 toward the oxide semiconductor layer 130 can be suppressed.

[0118] Next, as Figure 4 and Figure 11 As shown, impurities are implanted into the oxide semiconductor layer 130 via the insulating layer 140 (step S1070). Impurities can be implanted into the oxide semiconductor layer 130, for example, using ion implantation. Examples of impurities include argon (Ar), phosphorus (P), or boron (B). However, this is not limited to this example, and other elements may also be used.

[0119] In this embodiment, since a conductive layer 150 is formed on the oxide semiconductor layer 130, the conductive layer 150 functions as a mask, preventing impurities from being implanted into a portion of the oxide semiconductor layer 130. Therefore, in the oxide semiconductor layer 130, no impurities are implanted in the regions overlapping with the conductive layer 150, and a channel region CR is formed in these regions. Furthermore, in the oxide semiconductor layer 130, a source region SR and a drain region DR are formed in the regions where impurities are implanted because they do not overlap with the conductive layer 150. In the source region SR and drain region DR, oxygen defects are generated inside the oxide semiconductor layer 130 due to impurity implantation, and hydrogen is captured by these oxygen defects. Thus, the source region SR and drain region DR are conductive and have a higher conductivity than the channel region CR.

[0120] Here, the technical meaning of configuring the metal oxide layer 145 in this embodiment will be explained. In this embodiment, impurities are added to the oxide semiconductor layer 130 through the insulating layer 140. In this embodiment, since a silicon oxide layer is used as the insulating layer 140, the Si-O bonds and Si-H bonds contained in the silicon oxide layer are sometimes broken due to collisions with the impurities. As a result, oxygen and hydrogen are generated in the regions through which the impurities pass during ion implantation in the insulating layer 140. In particular, the generated hydrogen readily migrates within the insulating layer 140 when heated in subsequent processes. Such hydrogen diffusion may lead to, for example, a decrease in the resistance of the channel region CR (i.e., a reduction in channel resistance).

[0121] Therefore, in this embodiment, the metal oxide layer 145 is configured to cover the area around the oxide semiconductor layer 130, and the amount of hydrogen diffusing into the interior of the insulating layer 140 is minimized around the oxide semiconductor layer 130.

[0122] In this embodiment, impurities through the insulating layer 140 are implanted into the oxide semiconductor layer 130. On the other hand, around the oxide semiconductor layer 130, impurities through the metal oxide layer 145 are implanted into the insulating layer 140 (or insulating layers 120 and 140). Therefore, regardless of whether it overlaps with the oxide semiconductor layer 130, hydrogen and oxygen are generated inside the insulating layer 140 due to the collision of impurity ions caused by ion implantation.

[0123] However, in the region surrounding the oxide semiconductor layer 130 (i.e., the region where the metal oxide layer 145 is disposed), the metal oxide layer 145 functions as a barrier layer that hinders oxygen movement, thus suppressing the upward (i.e., into the air) diffusion of oxygen originally present inside the insulating layer 140 and oxygen generated by ion implantation. In other words, in the region where the metal oxide layer 145 is disposed, oxygen present inside the insulating layer 140 remains inside the insulating layer 140 and does not diffuse into the air.

[0124] As described above, hydrogen is also generated inside the insulating layer 140 due to ion implantation, but the oxygen present inside the insulating layer 140 functions as a hydrogen trap to capture the hydrogen. In other words, the oxygen present inside the insulating layer 140 suppresses hydrogen diffusion caused by subsequent heating processes. Therefore, in the region surrounding the oxide semiconductor layer 130 (the region where the metal oxide layer 145 is not formed), the oxygen remaining inside the insulating layer 140 functions as a hydrogen trap, effectively suppressing hydrogen diffusion. Here, during ion implantation, the region where the oxide semiconductor layer 130 is not formed occupies a significantly larger area compared to the region where the oxide semiconductor layer 130 is formed. That is, by placing the metal oxide layer 145 around the oxide semiconductor layer 130, the amount of hydrogen generated near the oxide semiconductor layer 130 can be significantly reduced, and the decrease in channel resistance caused by hydrogen diffusion can be effectively suppressed.

[0125] It should be noted that an opening 145-1 is provided above the region in the insulating layer 140 that overlaps with the oxide semiconductor layer 130, but no metal oxide layer 145 is disposed there. Therefore, oxygen is difficult to escape from the region located in the insulating layer 140. Figure 11 The insulating layer 140 above the source region SR and drain region DR is released into the air. As a result, hydrogen readily diffuses into the insulating layer 140 above the source region SR and drain region DR, and this hydrogen diffusion contributes significantly to the reduction of resistance in the source region SR and drain region DR.

[0126] As described above, in this embodiment, when impurities are added to the oxide semiconductor layer 130 to form the source region SR and drain region DR, by disposing the metal oxide layer 145 around the oxide semiconductor layer 130, a large amount of oxygen can be retained inside the insulating layer 140 located directly below the metal oxide layer 145. Therefore, hydrogen diffusion inside the insulating layer 140 located directly below the metal oxide layer 145 can be efficiently suppressed using oxygen. As a result, according to this embodiment, the decrease in channel resistance caused by hydrogen diffusion can be suppressed, and a highly reliable semiconductor device can be manufactured.

[0127] Next, as Figure 4 and Figure 12 As shown, a third insulating layer (insulating layer 160) is formed to cover the conductive layer 150 (step S1080). In this embodiment, the insulating layer 160 is formed by plasma CVD, having a stacked structure in which silicon oxide and silicon nitride layers are sequentially stacked from the bottom layer. Furthermore, contact holes 161 and 162 are formed in the portions of the insulating layers 140 and 160 that overlap with the source region SR and drain region DR of the oxide semiconductor layer 130, respectively.

[0128] Next, as Figure 4 and Figure 13 As shown, a third conductive layer (conductive layers 181 and 182) is formed on the insulating layer 160 (step S1090). Specifically, a three-layer metal layer consisting of a titanium layer, an aluminum layer, and another titanium layer is formed by sputtering, and conductive layers 181 and 182 are formed by patterning the metal layer into a predetermined shape. Conductive layers 181 and 182 are electrically connected to the oxide semiconductor layer 130 via contact holes 161 and 162, respectively. That is, conductive layer 181 is connected to the source region SR and functions as a source electrode, and conductive layer 182 is connected to the drain region DR and functions as a drain electrode.

[0129] Next, as Figure 4 and Figure 14 As shown, a fourth insulating layer (insulating layer 190) is formed by covering conductive layers 181 and 182 (step S1100). In this embodiment, the insulating layer 190 is formed by applying a resin material (e.g., acrylic or polyimide) using a solution coating method. In this embodiment, a photosensitive acrylic material is used as the insulating layer 190. By exposing and photosensitive the material to light, an insulating layer 190 having contact holes 191 can be formed. In this embodiment, contact holes 191 are formed in the portion of the insulating layer 190 that overlaps with the conductive layer 181.

[0130] In this embodiment, an example of forming the insulating layer 190 by solution coating is shown, but it is not limited to this example and can also be formed by other methods such as printing. The insulating layer 190 functions as a planarization layer. Therefore, it is preferable that the thickness of the insulating layer 190 is 1 μm or more and 4 μm or less (preferably 2 μm or more and 3 μm or less).

[0131] Next, as Figure 4 and Figure 15 As shown, a pixel electrode 200 is formed on the insulating layer 190 (step S1110). Specifically, a transparent conductive film (metal oxide film) is formed on the insulating layer 190 by sputtering and patterned into a predetermined pattern shape, thereby forming the pixel electrode 200. In this embodiment, ITO (indium tin oxide) is used as the material constituting the pixel electrode 200. The pixel electrode 200 is electrically connected to the conductive layer 181, which functions as a source electrode, via a contact hole 191.

[0132] Next, as Figure 4 and Figure 16 As shown, a septum 210 is formed on the pixel electrode 200 (step S1120). A resin material (e.g., a photosensitive acrylic material) can be used as the material constituting the septum 210. Specifically, after applying a resin material by a solution coating method or similar means, exposure and development are performed to form the septum 210, which includes the opening 212. Figure 16 As shown, the opening 212 provided in the partition 210 exposes most of the upper surface of the pixel electrode 200.

[0133] After the partition 210 is formed, a light-emitting layer 220 made of organic EL material is formed, overlapping with the opening 212. In this embodiment, the light-emitting layer 220 is formed by vapor deposition of an organic EL material that emits red, green, or blue light. The light-emitting layer 220 is formed to differentiate the emission color according to the pixel 13. That is, the pixel 13 emitting red light uses an organic EL material that emits red light, the pixel 13 emitting green light uses an organic EL material that emits green light, and the pixel 13 emitting blue light uses an organic EL material that emits blue light. In addition to the light-emitting layer made of luminescent material, the light-emitting layer 220 may also include an electron injection layer, an electron transport layer, an electron blocking layer, a hole injection layer, a hole transport layer, or a hole blocking layer as a functional layer made of functional material.

[0134] A common electrode 230 is formed on the light-emitting layer 220. In this embodiment, the common electrode 230 is formed by vapor deposition of a layer containing magnesium and silver. The common electrode 230 may also be disposed across multiple pixels. By forming the common electrode 230, a light-emitting element OLED consisting of pixel electrode 200, light-emitting layer 220 and common electrode 230 is formed.

[0135] Finally, as Figure 4 and Figure 17 As shown, an encapsulation layer 240 is formed to cover the light-emitting element OLED (step S1130). Although not shown in the figure, the encapsulation layer 240 has a stacked structure in which a silicon nitride layer, an organic resin layer (e.g., an acrylic layer), and a silicon nitride layer are stacked sequentially from the bottom layer. However, it is not limited to this example; a silicon oxide layer and an amorphous silicon layer may also be provided between the silicon nitride layer and the organic resin layer. By providing these layers, the adhesion between the silicon nitride layer and the organic resin layer can be improved. In addition, in this embodiment, a touch sensor 20 (see [reference]) is provided on the encapsulation layer 240. Figure 1 Therefore, an outer coating layer can also be applied on top of the sealing layer 240 for planarization.

[0136] According to the process described above, a pixel 13 comprising a driving transistor DRT as a semiconductor device is completed. In this embodiment, oxygen generated inside the insulating layer 140 during ion implantation can be retained around the oxide semiconductor layer 130. As a result, hydrogen generated inside the insulating layer 140 during ion implantation can be effectively suppressed from diffusing due to subsequent heating processes. Therefore, hydrogen diffusion into the channel region CR after ion implantation can be effectively suppressed, enabling the fabrication of a highly reliable semiconductor device that suppresses channel resistance reduction.

[0137] (Modification 1 of the first embodiment)

[0138] like Figure 9A and Figure 9B As shown, in this embodiment, the position of the inner wall of the opening 145-1 of the metal oxide layer 145 is aligned with the position of the end of the oxide semiconductor layer 130 in a direction perpendicular to the substrate 100. However, this is not limited to this example; the size of the opening 145-1 may be larger or smaller than the size of the oxide semiconductor layer 130.

[0139] Figure 18A This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13 of a semiconductor device comprising a modified embodiment of the present invention. Figure 18B This is a schematic top view illustrating a method for manufacturing a pixel 13 of a semiconductor device comprising a modified embodiment of the present invention. In this modified embodiment, the metal oxide layer 145 is arranged to overlap the end of the oxide semiconductor layer 130 by a predetermined distance (here, L1). Specifically, as Figure 18B As shown, the metal oxide layer 145 is arranged along the outer periphery of the oxide semiconductor layer 130 with an overlap width L1. The acceptable range of distance L1 is not particularly limited, but it is desirable to be 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less).

[0140] If the distance L1 is too large, the oxide semiconductor layer 130 may become highly resistive due to oxygen in the region where the metal oxide layer 145 overlaps with the oxide semiconductor layer 130. That is, the effective area of ​​the source region SR and the drain region DR may sometimes be reduced. Furthermore, if the metal oxide layer 145 is present in the region where the source region SR connects to the source electrode (conductive layer 181) or the region where the drain region DR connects to the drain electrode (conductive layer 182), poor etching may occur during the formation of contact holes. If the metal oxide layer 145 and the oxide semiconductor layer 130 overlap excessively, poor connections between the source electrode, the drain electrode, and the oxide semiconductor layer 130 may result.

[0141] Furthermore, if the distance L1 is too small, and a positional shift occurs when forming the opening 145-1 of the metal oxide layer 145, sometimes overlapping and non-overlapping portions of the oxide semiconductor layer 130 and the metal oxide layer 145 may occur, which may lead to deviations in the characteristics of the semiconductor device.

[0142] As described above, in the case of Modification 1, the size of the opening 145-1 of the metal oxide layer 145 is smaller than the size of the oxide semiconductor layer 130. That is, when viewed from above, the outline of the edge of the oxide semiconductor layer 130 includes the outline of the edge of the opening 145-1. With this configuration, the area of ​​oxygen residue in the insulating layer 140 can be maximized. Therefore, the amount of hydrogen diffusing from the periphery of the oxide semiconductor layer 130 toward the channel region CR can be significantly suppressed.

[0143] Next, Figure 19A This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13 of a semiconductor device comprising a modified embodiment of the present invention. Figure 19B This is a schematic top view illustrating a method for manufacturing a pixel 13 of a semiconductor device comprising a modified embodiment of the present invention. In this modified embodiment, the metal oxide layer 145 is arranged such that it is separated from the end of the oxide semiconductor layer 130 by a predetermined distance (here, L2). Specifically, as Figure 19B As shown, the metal oxide layer 145 is disposed along the outer periphery of the oxide semiconductor layer 130 with a separation width L2 from the oxide semiconductor layer 130. The acceptable range of the distance L2 is not particularly limited, but it is desirable to be 0.3 μm or more and 1.2 μm or less (preferably 0.5 μm or more and 1.0 μm or less).

[0144] If the distance L2 is too large, the exposed area of ​​the insulating layer 140 increases, which may lead to an increase in the amount of hydrogen reaching the channel region CR. Conversely, if the distance L2 is too small, in the event of a positional shift during the formation of the opening 145-1 of the metal oxide layer 145, the oxide semiconductor layer 130 may overlap with the metal oxide layer 145, potentially reducing the effective area of ​​the source region SR or the drain region DR. If the oxide semiconductor layer 130 overlaps with the metal oxide layer 145 in this way, as described above, it may lead to poor connections between the source electrode, the drain electrode, and the oxide semiconductor layer 130.

[0145] As described above, in Modification 2, the size of the opening 145-1 of the metal oxide layer 145 is larger than the size of the oxide semiconductor layer 130. That is, when viewed from above, the outline of the edge of the opening 145-1 includes the outline of the edge of the oxide semiconductor layer 130. With this configuration, the metal oxide layer 145 does not overlap with the oxide semiconductor layer 130 (especially the source region SR and the drain region DR), thus preventing problems such as poor contact between the conductive layer 181 and the source region SR or between the conductive layer 182 and the drain region DR.

[0146] (Modification 2 of the first embodiment)

[0147] In the first embodiment, it is shown that... Figure 4 The example shown is of a metal oxide layer 145 formed in step S1040 being patterned so that it remains around the oxide semiconductor layer 130, but it is not limited to this example. The metal oxide layer may also be formed after the conductive layer 150 is formed.

[0148] For example, the metal oxide layer 145 formed in step S1040 above is completely removed after oxidation annealing. Then, after forming the conductive layer 150 on the insulating layer 140, a metal oxide layer having an opening overlapping the oxide semiconductor layer 130 can be formed. In this case, the metal oxide layer is disposed around the oxide semiconductor layer 130, and the upper surface and side surfaces of the conductive layer 150 are covered around the oxide semiconductor layer 130 (i.e., the area that does not overlap with the oxide semiconductor layer 130).

[0149] <Second Implementation>

[0150] In the first embodiment, an example in which a channel region CR, a source region SR, and a drain region DR are provided in the oxide semiconductor layer 130 is described. However, in this embodiment, an example in which a low-resistance region HRR is further provided in addition to these regions is described. In the description of this embodiment, elements that are the same as those in the first embodiment are sometimes labeled with the same reference numerals in the drawings and are omitted from the description.

[0151] (Pixel structure)

[0152] Figure 20 This is a schematic cross-sectional view showing the configuration of a pixel 13a comprising a semiconductor device according to an embodiment of the present invention. Figure 20 Basic structure and Figure 3 The pixel 13 shown is the same, but the structure of the oxide semiconductor layer 130a, which functions as the active layer of the semiconductor device, is different. Specifically, the oxide semiconductor layer 130a has low-resistance regions HRR between the channel region CR and the source region SR, and between the channel region CR and the drain region DR.

[0153] The low-resistance region (HRR) is a region with relatively low resistance compared to the channel region (CR). However, the resistance of the HRR is higher than that of the source region (SR) and the drain region (DR). The HRR functions as a buffer region to suppress the movement velocity of charge carriers from the channel region (CR) towards the source region (SR) or the drain region (DR). That is, functionally, it is similar to the region commonly referred to as the LDD region.

[0154] Furthermore, in this embodiment, a metal oxide layer 145a is provided to cover the conductive layer 150. Specifically, a metal oxide layer 145a is provided that covers the upper surface and side surfaces of the conductive layer 150 and a portion of the upper surface of the insulating layer 140. As a result, in the first embodiment, a transistor has one opening 145-1 in the metal oxide layer 145, while in this embodiment, a transistor has two openings 145a-1 in the metal oxide layer 145a. Figure 20 As shown, the two openings 145a-1 overlap with the source region SR and drain region DR disposed in the oxide semiconductor layer 130a, respectively. At this time, the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the upper surface of the insulating layer 140 overlaps with the low resistance region HRR of the oxide semiconductor layer 130a.

[0155] (Methods for manufacturing pixels)

[0156] Figures 21 to 24 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13a comprising a semiconductor device according to an embodiment of the present invention.

[0157] First, implementation in the first embodiment Figure 4Steps S1010 to S1040, as shown, complete the oxidation annealing of the oxide semiconductor layer 130a. Then, the entire metal oxide layer 145 disposed above the insulating layer 140 is removed, and a conductive layer 150 (the second conductive layer) is formed at the position overlapping with the oxide semiconductor layer 130a. Thus, a... Figure 21 The state shown.

[0158] Next, as Figure 22 As shown, a metal oxide layer 145a is formed on the insulating layer 140 and the conductive layer 150. The metal oxide layer 145a can be formed using the same material and film-forming conditions as the metal oxide layer 145 described in the first embodiment. In this embodiment, an aluminum oxide (AlOx) layer with a thickness of 8 nm is formed as the metal oxide layer 145a by sputtering.

[0159] After forming the metal oxide layer 145a, the metal oxide layer 145a is patterned to form openings 145a-1. Specifically, a resist mask (not shown) is formed on the metal oxide layer 145a by photolithography, and the metal oxide layer 145a is etched using a wet etching process with hydrofluoric acid to form two openings 145a-1. At this time, the metal oxide layer 145a remains on the conductive layer 150 to cover the conductive layer 150.

[0160] like Figure 22 As shown, a portion of the metal oxide layer 145a, configured to cover the conductive layer 150, is in contact with the upper surface of the insulating layer 140. Specifically, a portion of the metal oxide layer 145a covering the conductive layer 150 is configured to overlap the insulating layer 140 by a predetermined distance (here, L3). In other words, in Figure 22 In the conductive layer 150, the opening 145a-1 is separated from the end by a predetermined distance L3. The acceptable range of distance L3 is not particularly limited, but it is desirable to be 0.5 μm to 3.0 μm (preferably 1.0 μm to 2.0 μm, more preferably 1.5 μm to 2.0 μm). The opening 145a-1 is formed to overlap with the region in the oxide semiconductor layer 130a that subsequently functions as the source region SR and the drain region DR.

[0161] Next, as Figure 23 As shown, impurities are implanted into the oxide semiconductor layer 130a. The impurity implantation process is similar to that in... Figure 4The process described in step S1070 is the same. By performing an impurity implantation process, a channel region CR, a source region SR, and a drain region DR are formed in the oxide semiconductor layer 130a. In this embodiment, the region directly below the conductive layer 150 is called the channel region CR (the region without impurities). Furthermore, the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140 does not function as a mask during the impurity implantation process. Therefore, impurities are added to the oxide semiconductor layer 130a located directly below the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140.

[0162] Then, by following the first embodiment Figure 4 Steps S1080 and S1090 shown form an insulating layer 160, a conductive layer 181, and a conductive layer 182, thereby obtaining... Figure 24 The state shown.

[0163] Upon reaching Figure 24 During the state shown, the oxide semiconductor layer 130 and the insulating layer 140 are heated during the formation of the insulating layer 160, conductive layer 181, and conductive layer 182. In this embodiment, a large amount of oxygen remains directly below the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140, and its diffusion is suppressed by the metal oxide layer 145a. Therefore, through the heating during the formation of the insulating layer 160, conductive layer 181, and conductive layer 182, the oxygen remaining inside the insulating layer 140 diffuses into the oxide semiconductor layer 130. As a result, the oxygen vacancies formed on the oxide semiconductor layer 130 by the impurity implantation process are repaired by oxygen again, and the resistance of the oxide semiconductor layer 130 increases. That is, the resistance value of the oxide semiconductor layer 130 located directly below the portion of the metal oxide layer 145a covering the conductive layer 150 that is in contact with the insulating layer 140 increases.

[0164] As described above, in this embodiment, a low-resistance region HRR is formed between the channel region CR and the source region SR, and between the channel region CR and the drain region DR. This low-resistance region HRR has a lower resistance than the channel region CR but a higher resistance than the source region SR and the drain region DR. Thus, in this embodiment, the channel region CR and the low-resistance region HRR are formed in a self-aligned manner. In this embodiment, the width of the low-resistance region HRR in the channel direction is L3.

[0165] In this embodiment, similar to the first embodiment, when impurities are implanted into the oxide semiconductor layer 130, the metal oxide layer 145a is disposed around the oxide semiconductor layer 130, thus suppressing hydrogen diffusion caused by subsequent heating processes. Therefore, according to this embodiment, the decrease in channel resistance caused by hydrogen diffusion can be effectively suppressed.

[0166] <Third Implementation>

[0167] In this embodiment, an example of manufacturing a semiconductor device using a method different from that of the first embodiment will be described. Specifically, in this embodiment, a metal oxide layer 145b remains between the insulating layer 140 and the conductive layer 150. In the description of this embodiment, sometimes the same reference numerals are used in the drawings as in the first embodiment, and the description is omitted.

[0168] Figure 25 This is a schematic cross-sectional view showing the configuration of pixel 13b of a semiconductor device comprising an embodiment of the present invention. Figure 25 Basic structure and Figure 3 The pixel 13 shown is the same, but the difference is that a metal oxide layer 145b is sandwiched between the insulating layer 140 and the conductive layer 150.

[0169] Figures 26 to 29 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13b comprising a semiconductor device according to an embodiment of the present invention.

[0170] First, it is implemented in the first embodiment. Figure 4 Steps S1010 to S1040 are shown, and the oxide semiconductor layer 130 is oxidized and annealed. Then, a conductive layer 150 (second conductive layer) is formed on the metal oxide layer 145b at the location overlapping with the oxide semiconductor layer 130. This results in... Figure 26 The state shown.

[0171] In this embodiment, a molybdenum-tungsten alloy is used as the constituent material of the conductive layer 150, and aluminum oxide is used as the constituent material of the metal oxide layer 145b. In this case, by employing a dry etching process using fluorine-based gases in the patterning process for forming the conductive layer 150, the selectivity between the conductive layer 150 and the metal oxide layer 145b can be ensured.

[0172] Next, as Figure 27As shown, a photoresist mask RM is formed on the metal oxide layer 145b. The photoresist mask RM has an opening RM1 at a location where it overlaps with the oxide semiconductor layer 130. In other words, the photoresist mask RM is formed in a region that does not overlap with the oxide semiconductor layer 130. Specifically, the position of the inner wall of the opening RM1 coincides with the position of the end of the oxide semiconductor layer 130 in a direction perpendicular to the substrate 100. That is, when viewed from above, the shape of the edge of the opening RM1 matches the shape of the edge of the oxide semiconductor layer 130.

[0173] Next, as Figure 28 As shown, the metal oxide layer 145b is etched using the resist mask RM and the conductive layer 150 as masks to form two openings 145b-1. The etching process is performed using a wet etching process with hydrofluoric acid. By using hydrofluoric acid as the etchant, not only the resist mask RM but also the conductive layer 150 can be used as a mask. Furthermore, in this embodiment, since the thickness of the metal oxide layer 145b is less than 10 nm, the etching is completed in a very short time. Therefore, by controlling the etching time, over-etching of the insulating layer 140 exposed after etching the metal oxide layer 145b can be minimized.

[0174] Next, as Figure 29 As shown, after removing the resist mask RM, impurities are added to the oxide semiconductor layer 130 using ion implantation. This forms the channel region CR, source region SR, and drain region DR in the oxide semiconductor layer 130.

[0175] Figure 29 The processes following the impurity implantation shown are the same as in the first embodiment, so repeated descriptions are omitted. Furthermore, in this embodiment, the function of the metal oxide layer 145b disposed around the oxide semiconductor layer 130 is also the same as in the first embodiment, so descriptions are omitted. According to this embodiment, the amount of hydrogen generated near the oxide semiconductor layer 130 can be significantly reduced, and the decrease in channel resistance caused by hydrogen diffusion can be effectively suppressed. Therefore, the decrease in channel resistance caused by hydrogen diffusion can be suppressed, resulting in the manufacture of highly reliable semiconductor devices.

[0176] (A variation of the third embodiment)

[0177] Figure 30 This is a schematic cross-sectional view showing the configuration of a pixel 13c of a semiconductor device comprising a modified embodiment of the present invention. Figure 30 Basic structure and Figure 25The pixel 13 shown is the same, but the structure of the oxide semiconductor layer 130c, which functions as the active layer of the semiconductor device, is different. Specifically, the oxide semiconductor layer 130c has low-resistance regions HRR between the channel region CR and the source region SR, and between the channel region CR and the drain region DR.

[0178] Figures 31 to 34 This is a schematic cross-sectional view illustrating a method for manufacturing a pixel 13c of a semiconductor device comprising a modified embodiment of the present invention.

[0179] First, after the above Figure 26 After the state shown, as Figure 31 As shown, a photoresist mask RM is formed on the metal oxide layer 145c. The photoresist mask RM is formed not only in the region that does not overlap with the oxide semiconductor layer 130, but also on the conductive layer 150. Specifically, in Figure 31 In addition, it is not only set up in Figure 27 The resist mask RM at the indicated location also includes a resist mask RM covering the upper and side surfaces of the conductive layer 150 and a portion of the upper surface of the insulating layer 140. As a result, in Figure 31 In a transistor, two openings RM1 are provided on the resist mask RM.

[0180] At this point, a portion of the resist mask RM covering the conductive layer 150 is configured to overlap the insulating layer 140 by a specified distance (here, L3). In other words, in Figure 31 In the conductive layer 150, the opening RM1 is separated from the end by a predetermined distance L3. The acceptable range of distance L3 is not particularly limited, but it is desirable to be 0.5 μm to 3.0 μm (preferably 1.0 μm to 2.0 μm, more preferably 1.5 μm to 2.0 μm). The opening RM1 is formed in a manner that overlaps with the region in the oxide semiconductor layer 130a that subsequently functions as the source region SR and the drain region DR.

[0181] Next, as Figure 32 As shown, the metal oxide layer 145c is etched using a resist mask RM to form two openings 145c-1. The etching process is performed using a wet etching process with hydrofluoric acid. However, it is not limited to this example; either wet or dry etching processes can be used as long as the metal oxide layer 145c can be etched. However, it is desirable to minimize over-etching of the insulating layer 140 exposed after etching the metal oxide layer 145c.

[0182] pass Figure 32The process shown leaves a metal oxide layer 145c between the insulating layer 140 and the conductive layer 150. For example... Figure 32 As shown, the width of the metal oxide layer 145c disposed between the insulating layer 140 and the conductive layer 150 in the channel direction is twice the width of the conductive layer 150 in the channel direction by a predetermined distance L3. That is, the portion of the metal oxide layer 145c located between the insulating layer 140 and the conductive layer 150 that does not overlap with the conductive layer 150 (hereinafter referred to as the "non-overlapping portion of the metal oxide layer 145c") protrudes from the conductive layer 150 in the channel direction and covers the insulating layer 140.

[0183] Next, after removing the resist mask RM, as follows Figure 33 As shown, impurities are implanted into the oxide semiconductor layer 130c. The impurity implantation process is similar to that in... Figure 4 The process described in step S1070 is the same. By performing an impurity implantation process, a channel region CR, a source region SR, and a drain region DR are formed in the oxide semiconductor layer 130c. In this modified example, the region directly below the conductive layer 150 becomes the channel region CR (the region without impurities). Furthermore, the non-overlapping portion of the metal oxide layer 145c does not function as a mask during the impurity implantation process. Therefore, the oxide semiconductor layer 130c located directly below the non-overlapping portion of the metal oxide layer 145c is impurized.

[0184] Then, according to the first embodiment Figure 4 Steps S1080 and S1090 shown form the third insulating layer 160, conductive layer 181, and conductive layer 182, thereby obtaining Figure 34 The state shown.

[0185] Upon reaching Figure 34 During the state shown, the oxide semiconductor layer 130 and the insulating layer 140 are heated during the formation of the third insulating layer 160, conductive layer 181, and conductive layer 182. In this embodiment, a large amount of oxygen remains directly below the non-overlapping portion of the metal oxide layer 145c, and its diffusion is suppressed by the metal oxide layer 145c. Therefore, through the heating during the formation of the aforementioned third insulating layer 160, conductive layer 181, and conductive layer 182, the oxygen remaining inside the insulating layer 140 diffuses into the oxide semiconductor layer 130. As a result, the oxygen vacancies formed in the oxide semiconductor layer 130 by the impurity implantation process are repaired by oxygen again, and the resistance of the oxide semiconductor layer 130 increases. That is, the resistance value of the oxide semiconductor layer 130 located directly below the non-overlapping portion of the metal oxide layer 145c increases.

[0186] As described above, in this embodiment, a region with a resistance lower than that of the channel region CR and the source region SR, and a region with a resistance higher than that of the source region SR and the drain region DR, namely a low-resistance region HRR, is formed between the channel region CR and the source region SR and the drain region DR. In this embodiment, the width of the low-resistance region HRR in the channel direction is L3.

[0187] In this embodiment, similar to the first embodiment, when impurities are implanted into the oxide semiconductor layer 130c, the metal oxide layer 145c is disposed around the oxide semiconductor layer 130c, thus suppressing hydrogen diffusion caused by subsequent heating processes. Therefore, according to this embodiment, the decrease in channel resistance caused by hydrogen diffusion can be effectively suppressed.

[0188] As embodiments of the present invention, the above-described embodiments (modifications) can be appropriately combined and implemented as long as they do not contradict each other. Furthermore, any methods described above obtained by those skilled in the art based on appropriate additions, deletions, design changes, or additions, omissions, or changes in processes or conditions, provided they capture the essence of the present invention, are also included within the scope of the present invention.

[0189] Even if other effects are different from those of the embodiments described above, effects that are known from the description in this specification or that can be easily predicted by those skilled in the art should be considered as effects brought about by the present invention.

Claims

1. A semiconductor device, characterized by, Comprise: an oxide semiconductor layer; a gate insulating layer provided over the oxide semiconductor layer; a metal oxide layer having an opening portion overlapping at least part of the oxide semiconductor layer, and in a region not overlapping with the oxide semiconductor layer, an upper surface of the gate insulating layer; and a gate electrode provided over the gate insulating layer in a region overlapping with the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein an outline of an edge of the opening portion coincides with an outline of an edge of the oxide semiconductor layer when viewed in plan.

3. The semiconductor device according to claim 1, wherein an outline of an edge of the oxide semiconductor layer includes an outline of an edge of the opening portion when viewed in plan.

4. The semiconductor device according to claim 3, wherein the metal oxide layer overlaps with a part of the oxide semiconductor layer along an edge of the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein an outline of an edge of the opening portion includes an outline of an edge of the oxide semiconductor layer when viewed in plan.

6. The semiconductor device according to claim 5, wherein a distance from an edge of the opening portion to an edge of the oxide semiconductor layer is 0.3 μm or more and 1.2 μm or less.

7. The semiconductor device according to claim 1, wherein the gate electrode is in contact with the metal oxide layer in a region not overlapping with the oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein the opening portion has a first opening portion overlapping with a source region of the oxide semiconductor layer and a second opening portion overlapping with a drain region of the oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein a part of the metal oxide layer covers an upper surface and side surfaces of the gate electrode and is in contact with the gate insulating layer in a region overlapping with the oxide semiconductor layer.

10. The semiconductor device according to claim 8, wherein a part of the metal oxide layer is arranged between the gate insulating layer and the gate electrode in a region overlapping with the oxide semiconductor layer.

11. The semiconductor device according to claim 1, wherein the metal oxide layer includes aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride (AlNxOy), or aluminum nitride (AlNx).

12. The semiconductor device according to claim 1, wherein a thickness of the metal oxide layer is 20 nm or less.

13. A display device, comprising: the semiconductor device according to any one of claims 1 to 12.

14. A method of manufacturing a semiconductor device, characterized by comprising the following processes: forming an oxide semiconductor layer over an insulating surface, forming a gate insulating layer over the oxide semiconductor layer, forming a metal oxide layer having an opening portion overlapping at least part of the oxide semiconductor layer and in contact with an upper surface of the gate insulating layer, a gate electrode is formed over the gate insulating layer, an impurity is added to the oxide semiconductor layer through the gate insulating layer.

15. The method according to claim 14, wherein the metal oxide layer is formed by a sputtering method.

16. The method according to claim 14, wherein the metal oxide layer contains aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride (AlNxOy), or aluminum nitride (AlNx).

17. The method according to claim 14, wherein the thickness of the metal oxide layer is 20 nm or less.

18. The method according to claim 14, wherein the shape of the edge of the opening portion coincides with the shape of the edge of the oxide semiconductor layer when viewed in plan view.

19. The method according to claim 14, wherein the shape of the edge of the oxide semiconductor layer includes the shape of the edge of the opening portion when viewed in plan view.

20. The method according to claim 14, wherein the shape of the edge of the opening portion includes the shape of the edge of the oxide semiconductor layer when viewed in plan view.

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