Display device, method of manufacturing the same, and electronic device including the same

Abstract

A display device, a method of manufacturing the same, and an electronic device including the same are provided, in which the display device includes: a substrate including a display area and a peripheral area around the display area, the display area including sub-pixels; a horizontal power voltage line disposed in the display area and extending in a first direction; a vertical power voltage line disposed in the display area, located in a different layer from the horizontal power voltage line, extending in the second direction, and electrically connected to the horizontal power voltage line; and a test line disposed in the peripheral region at a different layer than the vertical power voltage line, positioned closer to the substrate than the vertical power voltage line, extending in the second direction, and electrically connected to the horizontal power voltage line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0119645, filed on September 4, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments disclosed relate to a display device and a method of manufacturing the display device. BACKGROUND

[0003] Generally, in a display device such as an organic light emitting display device, a transistor, a connection electrode, and an interconnection are provided in each sub-pixel to control the brightness or the like of each sub-pixel. SUMMARY

[0004] Embodiments disclosed can provide a display device in which defects in a transistor, a connection electrode, and an interconnection are tested, and a method of manufacturing the display device.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings or can be learned by practice of the presented embodiments of the disclosure.

[0006] Embodiments disclosed can provide a display device including a substrate including a display area and a peripheral area around the display area, the display area including a sub-pixel; horizontal power voltage lines disposed in the display area and extending in a first direction; vertical power voltage lines disposed in the display area, located at different layers from the horizontal power voltage lines, extending in a second direction crossing the first direction, and electrically connected to the horizontal power voltage lines; and a test line disposed in the peripheral area, located at different layers from the vertical power voltage lines, positioned closer to the substrate than the vertical power voltage lines, extending in the second direction, and electrically connected to the horizontal power voltage lines.

[0007] In this embodiment, the display device can further include a semiconductor layer on an insulating layer, the insulating layer covering at least one of the horizontal power voltage lines.

[0008] In an embodiment, the semiconductor layer can include an oxide semiconductor material.

[0009] In an embodiment, the test line can be on an insulating layer covering the semiconductor layer.

[0010] In an embodiment, the sub-pixel can include a transistor, and the test line and a gate electrode of the transistor can be formed as the same layer.

[0011] In an embodiment, at least one of the horizontal power voltage lines and the test line can be located at the same layer.

[0012] In an embodiment, the sub-pixel can include a capacitor, and the test line and an electrode of the capacitor can be located on the same layer.

[0013] In an embodiment, the vertical power voltage line can be located on an insulating layer covering the test line.

[0014] In an embodiment, the sub-pixel can include a transistor, and the test line and a source electrode and a drain electrode of the transistor can be located on the same layer.

[0015] In an embodiment, the test line can include a plurality of test lines, the horizontal power voltage line can include a plurality of horizontal power voltage lines, each of the plurality of test lines can be electrically connected to a corresponding horizontal power voltage line of the plurality of horizontal power voltage lines, and the plurality of test lines can be located on the same layer.

[0016] In an embodiment, the test line can include a plurality of test lines, the horizontal power voltage line can include a plurality of horizontal power voltage lines, each of the plurality of test lines can be electrically connected to a corresponding horizontal power voltage line of the plurality of horizontal power voltage lines, and the plurality of test lines can be located on different layers.

[0017] In an embodiment, the test line can be electrically connected to the horizontal power voltage line through a connection interconnect.

[0018] In an embodiment, the sub-pixel can include a transistor, the horizontal power voltage line can include a horizontal first power line electrically connected to the transistor and extending in a first direction, the vertical power voltage line can include a vertical first power line crossing the sub-pixel in a second direction and electrically connected to the horizontal first power line, and the test line can include a first power test line electrically connected to the horizontal first power line.

[0019] In an embodiment, the horizontal power voltage line can include a horizontal second power line crossing the sub-pixel and extending in the first direction, the vertical power voltage line can include a vertical second power line crossing another sub-pixel of a pixel including the sub-pixel in the second direction and electrically connected to the horizontal second power line, the horizontal second power line and the vertical second power line can be electrically connected to a display element, and the test line can include a second power test line electrically connected to the horizontal second power line.

[0020] In an embodiment, the sub-pixel can include an initialization transistor, the horizontal power voltage line can include a horizontal initialization voltage line electrically connected to the initialization transistor and crossing the sub-pixel to extend in a first direction, the vertical power voltage line can include a vertical initialization voltage line crossing the sub-pixel in a second direction and electrically connected to the horizontal initialization voltage line, and the test line can include an initialization voltage test line electrically connected to the horizontal initialization voltage line.

[0021] In an embodiment, a sub-pixel may include a reference voltage transistor, a horizontal power voltage line may include a horizontal first reference voltage line electrically connected to the reference voltage transistor and traversing the sub-pixel to extend in a first direction, a vertical power voltage line may include a vertical first reference voltage line traversing the sub-pixel and adjacent sub-pixels in a second direction and electrically connected to the horizontal first reference voltage line, and a test line may include a first reference voltage test line electrically connected to the horizontal first reference voltage line.

[0022] In an embodiment, a sub-pixel may include a capacitor, a horizontal power voltage line may include a horizontal second reference voltage line electrically connected to the capacitor, a vertical power voltage line may include a vertical second reference voltage line, the vertical second reference voltage line traverses the sub-pixel and adjacent sub-pixels in a second direction and is electrically connected to the horizontal second reference voltage line, and a test line may include a second reference voltage test line electrically connected to the horizontal second reference voltage line.

[0023] In an embodiment, other horizontal power voltage lines besides the horizontal second reference voltage line may be located on an insulating layer covering the horizontal second reference voltage line.

[0024] In an embodiment, a sub-pixel may include a switching transistor, a driving circuit that transmits a write signal to the switching transistor may be located in the peripheral area, and a test line may be located between the driving circuit and the display area.

[0025] In an embodiment, a sub-pixel may include an emission control transistor, a driving circuit that transmits emission control signals to the emission control transistor may be located in the peripheral area, and a test line may be located between the driving circuit and the display area.

[0026] Another disclosed embodiment provides a method for manufacturing a display device, the method comprising the steps of: preparing a substrate, the substrate including a display area and a peripheral area outside the display area, the display area including sub-pixels; forming horizontal power voltage lines disposed in the display area and extending in a first direction; forming test lines disposed in the peripheral area, extending in a second direction intersecting the first direction, and electrically connected to the horizontal power voltage lines; and forming vertical power voltage lines disposed in the display area, located on a different layer from the horizontal power voltage lines and the test lines, extending in the second direction, and electrically connected to the horizontal power voltage lines.

[0027] In an embodiment, at least one of the horizontal power voltage lines and the test line may be formed on the same layer.

[0028] In an embodiment, the method may further include the following steps: after the step of forming horizontal power voltage lines, forming a semiconductor layer on an insulating layer, the insulating layer covering at least one of the horizontal power voltage lines, wherein the test line is located on the insulating layer covering the semiconductor layer.

[0029] In an embodiment, the step of forming a vertical power voltage line may include: forming an insulating layer covering the test line; and forming a vertical power voltage line located on the insulating layer.

[0030] Another embodiment of this disclosure provides an electronic device including a display device, wherein the display device includes: a substrate including a display area and a peripheral area outside the display area, the display area including sub-pixels; a horizontal power voltage line disposed in the display area and extending in a first direction; a vertical power voltage line disposed in the display area, located at a different layer from the horizontal power voltage line, extending in a second direction intersecting the first direction, and electrically connected to the horizontal power voltage line; and a test line disposed in the peripheral area, located at a different layer from the vertical power voltage line, positioned closer to the substrate than the vertical power voltage line, extending in the second direction, and electrically connected to the horizontal power voltage line.

[0031] The electronic device may be at least one of the following: smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (PMP), navigation system, and ultra-mobile computer.

[0032] Other aspects, features, and advantages of the disclosure will be better understood through the accompanying drawings, claims, and detailed descriptions. Attached Figure Description

[0033] The above and other aspects, features and advantages of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic plan view illustrating a display device according to a disclosed embodiment; Figure 2 yes Figure 1 An enlarged schematic diagram of part A; Figure 3 Is included Figure 1 A schematic diagram of the equivalent circuit of a sub-pixel in a display device; Figure 4 It is shown that it includes Figure 1 A schematic layout of the positions of transistors, capacitors, etc. in pixels of a display device; Figures 5 to 10 It is shown for each layer. Figure 4 A schematic layout of components such as transistors and capacitors in the display device shown; Figure 11 It shows along Figure 4 A schematic cross-sectional view of the display device shown, taken along line B-B'; Figure 12 It shows along Figure 2 A schematic cross-sectional view of the display device shown, taken by the discontinuous line C-C'. Figures 13 to 16 This illustrates along another embodiment according to the disclosure. Figure 2 A schematic cross-sectional view of the display device shown, taken by the discontinuous line C-C'. Figure 17 This is a schematic block diagram illustrating a display system according to a disclosed embodiment; and Figure 18 This is a schematic diagram illustrating an example of a smartwatch including a display device according to a disclosed embodiment. Detailed Implementation

[0034] Referring now to embodiments in detail, examples of which are shown in the accompanying drawings, in which the same reference numerals consistently denote the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below solely by reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” following a list of elements modify the entire list of elements, without modifying any individual element within that list.

[0035] Because the disclosure can be applied in various variations and has various embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the specific implementation. The effects and features of the disclosure, as well as the methods of implementing it, will become apparent from the following detailed description of the embodiments taken in conjunction with the accompanying drawings. However, the disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0036] In the following embodiments, the terms first, second, etc., are not intended to be limiting, but are used to distinguish one component from another.

[0037] In the following embodiments, unless the context clearly indicates otherwise, expressions used in the singular (such as “a,” “an,” and “the”) are intended to include the plural as well.

[0038] In the following embodiments, it will be understood that terms such as “comprising,” “including,” and “having” indicate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0039] In the following embodiments, when a unit, region, or component is located on or above another part, the disclosure includes not only the case where the unit, region, or component is directly above the other part, but also the case where other units, other regions, or other components may be located therebetween.

[0040] In the following embodiments, unless the terms “connection” or “joining” are clearly different in the context, the terms “connection” or “joining” do not necessarily mean a direct connection (or joining) and / or a fixed connection (or joining) between two components, but do not exclude a component located between the two components.

[0041] In the accompanying drawings, the dimensions of components may be enlarged or reduced for ease of description. For example, the dimensions and / or thicknesses of the various components shown in the drawings are arbitrarily illustrated for ease of description, and therefore one or more embodiments are not necessarily limited thereto.

[0042] In the following examples, it will be understood that when a component such as a layer, membrane, region, or plate is referred to as being "on" another component, the component may be directly on the other component, or an intermediary component may be present on it.

[0043] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes in a Cartesian coordinate system, but can be interpreted in a general sense that includes these three axes. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0044] In the following embodiments, the term "line" may refer to "interconnector". This also applies to the embodiments and variations thereof described below.

[0045] In the following embodiments, the term "horizontal" refers to a target line extending in the first direction in the same manner as a reference line extending in the first direction (or x-axis direction). The term "vertical" refers to a target line extending in the second direction (or y-axis direction) that intersects with the reference line extending in the first direction (or x-axis direction).

[0046] In the following, the disclosed exemplary embodiments will be described in detail with reference to the accompanying drawings, in which the same reference numerals refer to the same or corresponding components throughout the drawings, and redundant descriptions thereof will be omitted.

[0047] Figure 1 This is a schematic plan view showing a display device 10 according to a disclosed embodiment.Figure 2 yes Figure 1 An enlarged schematic diagram of part A. Figure 3 Is included Figure 1 A schematic diagram of the equivalent circuit of a sub-pixel SP in the display device 10.

[0048] Reference Figures 1 to 3 The display device 10 according to the embodiment can be one of various products such as a smartphone, tablet computer, laptop computer, television or billboard.

[0049] The display device 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA may be a portion in which an image is displayed, and multiple pixels may be disposed in the display area DA. When viewed in a direction perpendicular to a plane parallel to the display device 10, the display area DA may have various shapes, such as circular, elliptical, polygonal, and shapes of specific graphics.

[0050] The peripheral region PA can be located outside the display region DA. Various types of driving circuits can be located in the peripheral region PA. For example, the scan driving circuit 11 that generates scan signals and transmit control signals can be located in the peripheral region PA on both sides of the display region DA in the first direction (or x-axis direction). According to an optional embodiment, the scan driving circuit 11 that generates scan signals and the transmit control driving circuit that generates transmit control signals can be arranged separately. For example, the scan driving circuit 11 and the transmit control driving circuit can be located in the peripheral region PA on both sides of the display region DA in the first direction (or x-axis direction), respectively.

[0051] An integrated circuit 12 for driving the display device 10 may be disposed in the peripheral region PA of the display device 10. Such an integrated circuit 12 may include a data driving circuit 121 that generates data signals, and may further include a controller 122 that generates control signals for controlling the scan driving circuit 11, the transmit control driving circuit, and the data driving circuit 121. The integrated circuit 12 may also include a power supply 123 that converts an input voltage (e.g., battery voltage and system voltage) into an electrical voltage. For example, the electrical voltage may include an initialization voltage Vint, a first reference voltage Vref1, a second reference voltage Vref2, a first electrical voltage ELVDD, and a second electrical voltage ELVSS. For example, the integrated circuit 12 may be located in the peripheral region PA of the display area DA at its lower end in the second direction (or the y-axis direction).

[0052] Since the display device 10 includes a substrate 100 (see...) Figure 11Therefore, it is conceivable that the substrate 100 may have a display area DA and a peripheral area PA as described above. Hereinafter, for convenience, it will be described that the substrate 100 may have a display area DA and a peripheral area PA. Various components included in the display device 10 may be located on the substrate 100. The substrate 100 may include glass, metal, or polymer resin.

[0053] In the following description, the display device 10 according to the disclosed embodiments will be described as an example of an organic light-emitting display device. However, the disclosed display device 10 is not limited thereto. As another embodiment, the disclosed display device 10 may be a display device such as an inorganic light-emitting display device, an inorganic electroluminescent (EL) display device, or a quantum dot light-emitting display device. For example, the emitting layer of the display element included in the display device may comprise an organic or inorganic material. The display device may have an emitting layer and a quantum dot layer located in the path of light emitted from the emitting layer.

[0054] Multiple pixels can be located in the display area DA. Each pixel can include multiple subpixels SP, and each subpixel SP can include a display element such as an organic light-emitting diode (OLED). The subpixel SP can emit, for example, red, green, blue, or white light.

[0055] The sub-pixel SP can be electrically connected to peripheral circuitry located in the peripheral region PA. Scan drive circuitry 11 and integrated circuit 12, etc., can also be located in the peripheral region PA.

[0056] The scan drive circuit 11 can provide scan signals to the pixels via scan lines SL, such as write signal line GWL, reference voltage signal line GRL, initialization signal line GIL, first transmit control line EML, and second transmit control line EMBL. The scan lines SL can extend in the display area DA in a first direction (or x-axis direction) to be commonly connected to a plurality of sub-pixels SP disposed in each row.

[0057] Integrated circuit 12 may include data driving circuit 121, controller 122, and power supply 123, and may be in the form of a driver chip to transmit various signals or power to the driving circuit or pixels. Data signals generated in data driving circuit 121 can be transmitted to pixels via data line DL, and control signals generated in controller 122 can be transmitted to each of the driving circuits. Additionally, power voltage from power supply 123 can be transmitted to power voltage lines 200 in display area DA via each of power voltage supply interconnects 20. Power voltage supply interconnects 20 may be disposed in peripheral area PA and electrically connected to power supply 123 via power voltage lines 200 in display area DA.

[0058] According to the disclosed embodiments, the power voltage lines 200 in the display area DA can be formed in a grid pattern. The power voltage lines 200 may include horizontal power voltage lines (first direction power voltage lines) 210 extending in a first direction (or x-axis direction) and vertical power voltage lines (second direction power voltage lines) 220 extending in a second direction (or y-axis direction) intersecting the first direction (or x-axis direction).

[0059] Refer to together Figure 1 and Figure 3 The power voltage line 200 may include a first power line PL2 to which a first power voltage ELVDD is supplied, a second power line to which a second power voltage ELVSS is supplied, an initialization voltage line VL to which an initialization voltage Vint is supplied, and reference voltage lines to which a first reference voltage Vref1 and a second reference voltage Vref2 are respectively supplied. The following will refer to... Figure 3 The circuit diagram of the pixel circuit describes the specific details of each power voltage line 200.

[0060] Although not in Figure 1 As shown, however, the power supply interconnect 20 may include a first power interconnect, a second power interconnect, an initialization voltage supply interconnect, and a reference voltage supply interconnect. Power supply 123 can provide a first power voltage (drive voltage) ELVDD to the first power line PL2 via the first power interconnect, and a second power voltage (common voltage) ELVSS to the second power line via the second power interconnect. Power supply 123 can provide an initialization voltage Vint to the initialization voltage line VL via the initialization voltage supply interconnect, and can provide a first reference voltage Vref1 and a second reference voltage Vref2 to the reference voltage line via the reference voltage supply interconnect.

[0061] A first power interconnect can transmit a first power voltage ELVDD to a sub-pixel SP via a first power line PL2. The first power interconnect can be disposed in a peripheral region PA between integrated circuit 12 and display region DA. The first power interconnect can be electrically connected to the first power line PL2, which is disposed in a grid pattern in display region DA. The first power line PL2 can include a horizontal first power line extending in a first direction (or x-axis direction) and a vertical first power line extending in a second direction (or y-axis direction). The horizontal and vertical first power lines can be located on different layers. For example, the layer where the horizontal first power lines are positioned can be a layer closer to the substrate 100 than the layer where the vertical first power lines are positioned. For example, the horizontal first power lines can be formed first, and then the vertical first power lines can be formed. The horizontal and vertical first power lines can be electrically connected to each other via contact holes at least where they intersect each other. The first power line PL2 can be electrically connected to the sub-pixel SP. The first power line PL2 can be electrically connected to at least a transistor included in the sub-pixel SP. Therefore, the sub-pixel SP can be electrically connected to the first power interconnect to receive a first power voltage ELVDD as a driving voltage from the power supply 123. Simultaneously, through the first power line PL2 having a grid-like structure, the first power line PL2 can have a uniform potential in its various portions.

[0062] The second power interconnect supplies the second power voltage ELVSS to the counter electrode 530 of the organic light-emitting diode OLED (see...). Figure 11 The second power interconnect can be disposed in the peripheral region PA between the integrated circuit 12 and the display region DA. However, one or more embodiments are not limited thereto, and the second power interconnect can be disposed in the peripheral region PA and can have an annular shape with one side open. The second power interconnect can be electrically connected to second power lines arranged in a grid in the display region DA. The second power lines can include horizontal second power lines extending in a first direction (or x-axis direction) and vertical second power lines extending in a second direction (or y-axis direction). The horizontal second power lines and the vertical second power lines can be located in different layers. For example, the layer where the horizontal second power lines are positioned can be a layer closer to the substrate 100 than the layer where the vertical second power lines are positioned. For example, the horizontal second power lines can be formed first, and then the vertical second power lines can be formed. The horizontal second power lines and the vertical second power lines can be electrically connected through contact holes at least at the points where the horizontal second power lines and the vertical second power lines intersect each other. The organic light-emitting diode (OLED) can be electrically connected to the second power lines. For example, the counter electrode 530 of the organic light-emitting diode (OLED) (see Figure 11The counter electrode 530 can be electrically connected to a second power line outside the display area DA. Therefore, the counter electrode 530 can receive a second power voltage ELVSS from the power supply 123. The second power line, having a grid-like structure, can prevent or minimize deviations in the second power voltage ELVSS applied to the counter electrode 530 in the display area DA.

[0063] The initialization voltage line VL can transmit the initialization voltage Vint, which is transmitted from the power supply 123 via the initialization voltage supply interconnect, to each of the sub-pixels SP. The initialization voltage line VL can also be arranged in a grid pattern in the display area DA. The initialization voltage line VL can include a horizontal initialization voltage line extending in a first direction (or the x-axis direction) and a vertical initialization voltage line extending in a second direction (or the y-axis direction). The horizontal and vertical initialization voltage lines can be located on different layers. For example, the layer where the horizontal initialization voltage lines are located can be a layer closer to the substrate 100 than the layer where the vertical initialization voltage lines are located. For example, the horizontal initialization voltage lines can be formed first, and then the vertical initialization voltage lines can be formed. The horizontal and vertical initialization voltage lines can be electrically connected via contact holes at least at the points where they intersect each other. The horizontal initialization voltage lines can be electrically connected to the initialization transistor T4 (see...). Figure 3 Therefore, with the initialization transistor T4 turned on, an initialization voltage Vint can be supplied to initialize the organic light-emitting diode (OLED).

[0064] The reference voltage lines can transmit a first reference voltage Vref1 and a second reference voltage Vref2, which are transmitted from the power supply 123 via the reference voltage supply interconnect, to each sub-pixel SP. The reference voltage lines can also be arranged in a grid pattern within the display area DA. The reference voltage lines can include a horizontal reference voltage line extending in a first direction (or the x-axis direction) and a vertical reference voltage line extending in a second direction (or the y-axis direction). Simultaneously, the reference voltage lines can include a first reference voltage line RL1 and a second reference voltage line RL2, and the first reference voltage line RL1 and the second reference voltage line RL2 can respectively transmit the first reference voltage Vref1 and the second reference voltage Vref2 to each sub-pixel SP.

[0065] The first reference voltage line RL1 may include a horizontal first reference voltage line extending in a first direction (or the x-axis direction) and a vertical first reference voltage line extending in a second direction (or the y-axis direction). The horizontal and vertical first reference voltage lines may be located on different layers. For example, the layer where the horizontal first reference voltage line is positioned may be a layer closer to the substrate 100 than the layer where the vertical first reference voltage line is positioned. For example, the horizontal first reference voltage line may be formed first, and then the vertical first reference voltage line may be formed. The horizontal and vertical first reference voltage lines may be electrically connected at least at the point where they intersect each other. The horizontal first reference voltage line may be electrically connected to the reference voltage transistor T3 (see...). Figure 3 Therefore, when the reference voltage transistor T3 is turned on, a first reference voltage Vref1 can be supplied to compensate the drive transistor T1 (see...). Figure 3 The threshold voltage of ).

[0066] The second reference voltage line RL2 may include a horizontal second reference voltage line arranged to extend in a first direction (or the x-axis direction) and a vertical second reference voltage line arranged to extend in a second direction (or the y-axis direction). The horizontal and vertical second reference voltage lines may be located on different layers. For example, the layer where the horizontal second reference voltage line is located may be closer to the substrate 100 than the layer where the vertical second reference voltage line is located. For example, the horizontal second reference voltage line may be formed first, and then the vertical second reference voltage line may be formed. Simultaneously, the horizontal second reference voltage line may be located on a layer closer to the substrate 100 than the layer where the remaining horizontal power voltage line 210 described above is located. For example, after the horizontal second reference voltage line is formed first, the remaining horizontal power voltage line 210 may be formed, and then the vertical power voltage line 220 may be formed. The horizontal and vertical second reference voltage lines may be electrically connected via contact holes at least where they intersect each other. The horizontal second reference voltage line may be electrically connected to a capacitor. Therefore, the capacitor may store charge based on the second reference voltage Vref2.

[0067] Reference Figure 3 The circuit diagram of the pixel circuit. Figures 4 to 10 The pixel circuit planar diagram for each layer and Figure 11 The cross-sectional view of the pixel circuit describes the positional relationships between the various interconnects in more detail.

[0068] Simultaneously, the data drive circuit 121 can generate a data signal DT (see... Figure 3The generated data signal DT can be transmitted to the sub-pixel SP via the data line DL. The data line DL can extend in the display area DA in the second direction (or the y-axis direction) and can be commonly connected to multiple sub-pixels SP set in each column.

[0069] According to the disclosed embodiments, the test line 30 may be located in a peripheral region PA. The test line 30 may be located in at least one peripheral region PA on both sides of the display region DA in a first direction (or x-axis direction). The test line 30 may be located in a corresponding peripheral region PA between the scan driving circuit 11 and the display region DA. The test line 30 may be located in a corresponding peripheral region PA between the emission control driving circuit and the display region DA. The test line 30 may have a shape extending substantially in a second direction (or y-axis direction).

[0070] Refer again Figures 1 to 3 Test line 30 can be electrically connected to power voltage line 200 disposed in display area DA. Test line 30 can include multiple lines, and therefore can be electrically connected to each of power voltage lines 200. Test line 30 can include: a first power test line 301, electrically connected to a first power line PL2 to which a first power voltage ELVDD is supplied (see...). Figure 3 ); Second power test line 302, electrically connected to the second power line supplied with the second power voltage ELVSS; Initialization voltage test line 303, connected to the initialization voltage line VL supplied with the initialization voltage Vint (see Figure 3 ); The first reference voltage test line 304 is connected to the first reference voltage line RL1 to which the first reference voltage Vref1 is supplied (see Figure 3 ); and the second reference voltage test line 305, connected to the second reference voltage line RL2 to which the second reference voltage Vref2 is supplied (see Figure 3 ).

[0071] Test line 30 can be electrically connected to power voltage line 200 via interconnect 31. Interconnect 31 is disposed in peripheral area PA. Interconnect 31 is disposed between test line 30 and display area DA and can extend in a first direction (or x-axis direction). Interconnect 31 may include multiple interconnects to electrically connect each of power voltage lines 200 to test line 30. The interconnecting element 31 may include: a first interconnecting element 311 for electrically connecting a first power line PL2 to which a first power voltage ELVDD is supplied to a first power test line 301; a second interconnecting element 312 for electrically connecting a second power line to which a second power voltage ELVSS is supplied to a second power test line 302; a third interconnecting element 313 for electrically connecting an initialization voltage line VL to which an initialization voltage Vint is supplied to an initialization voltage test line 303; a fourth interconnecting element 314 for electrically connecting a first reference voltage line RL1 to which a first reference voltage Vref1 is supplied to a first reference voltage test line 304; and a fifth interconnecting element 315 for electrically connecting a second reference voltage line RL2 to which a second reference voltage Vref2 is supplied to a second reference voltage test line 305.

[0072] The interconnecting element 31 may be located on a different layer from the test line 30 and / or the power voltage line 200. For example, the interconnecting element 31 may be electrically connected to the test line 30 and the power voltage line 200 through contact holes at both end portions of the interconnecting element 31. However, the disclosure is not limited thereto, and the interconnecting element 31 may be located on the same layer as the test line 30. For example, the interconnecting element 31 may be integrally formed with the test line 30.

[0073] Test line 30 may be located on a different layer than at least one of the power voltage lines 200. As described above, the power voltage lines 200 may include horizontal power voltage lines 210 and vertical power voltage lines 220. The horizontal power voltage lines 210 and vertical power voltage lines 220 may be located on different layers and may be electrically connected to each other through contact holes. For example, test line 30 may be located on a different layer than the vertical power voltage line 220. Test line 30 may be located on a layer closer to the substrate 100 than the layer where the vertical power voltage line 220 is located. For example, test line 30 may be formed before the vertical power voltage line 220 is formed.

[0074] Test lead 30 can be electrically connected to power supply 123 to receive the power or voltage required for testing. However, the disclosure is not limited thereto, and test lead 30 can be electrically connected to power supply 123 for testing to receive the power or voltage required for testing. In another embodiment, the end portion of test lead 30 can be exposed in the form of terminals to receive the power or voltage required for testing from an external power supply 123.

[0075] According to the disclosed embodiments, to achieve high-resolution pixels, power voltage lines 200 are implemented in a grid pattern within the display area DA. Horizontal power voltage lines 210 and vertical power voltage lines 220 may be located on different layers, and specifically, the vertical power voltage lines 220 are formed after the horizontal power voltage lines 210 are formed. For example, it is impossible to test the fine contact area (FCA) to test for defects in the transistors in the pixel circuitry before the vertical power voltage lines 220 are formed. This is because it is difficult to drive the entire display area DA before the vertical power voltage lines 220 are formed. According to the disclosed embodiments, even before the vertical power voltage lines 220 are formed, the entire display area DA can be driven by test lines 30. Test lines 30 are formed before the vertical power voltage lines 220 and can be electrically connected to the horizontal power voltage lines 210. Test lines 30 extend in a direction intersecting the horizontal power voltage lines 210 and are formed in the peripheral area PA. Therefore, test lines 30 and horizontal power voltage lines 210 are implemented in a global grid pattern. Therefore, the entire display area DA can be driven even before the vertical power voltage line 220 is formed, thus enabling the execution of FCA testing. Furthermore, since defects can be repaired before the vertical power voltage line 220 is formed, repair is easier.

[0076] In the following text, reference will be made to Figure 3 Detailed description Figure 1 Subpixels SP. For example... Figure 3 As shown, the sub-pixel SP may include pixel circuitry PC and an organic light-emitting diode (OLED) electrically connected thereto.

[0077] The pixel circuit PC may include multiple transistors T1 to T6, a storage capacitor Cst, and a holding capacitor Chold. The multiple transistors T1 to T6, the storage capacitor Cst, and the holding capacitor Chold may be electrically connected to signal lines GWL, GRL, GIL, EML, DL, and EMBL, initialization voltage line VL, first reference voltage line RL1, second reference voltage line RL2, and first power line PL2.

[0078] The multiple transistors T1 to T6 may include a driving transistor T1, a switching transistor T2, a reference voltage transistor T3, an initialization transistor T4, a first emitter control transistor T5, and a second emitter control transistor T6.

[0079] Organic light-emitting diodes (OLEDs) may include pixel electrodes (anodes) 510 (see...) Figure 11 ) and counter electrode (cathode) 530 (see Figure 11The pixel electrode 510 of the organic light-emitting diode (OLED) can be electrically connected to the driving transistor T1 via the second emission control transistor T6 to receive a driving current, and its counter electrode 530 can receive a second electrical voltage ELVSS. The OLED can produce light with a brightness corresponding to the driving current.

[0080] The plurality of transistors T1 to T6 may be n-channel metal-oxide-semiconductor (NMOS) (n-channel metal-oxide-semiconductor silicon field-effect transistor (MOSFET)). Each of the plurality of transistors T1 to T6 may include an oxide semiconductor layer. For example, the oxide semiconductor layer may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor layer may include InSnZnO (ITZO) or InGaZnO (IGZO), etc.

[0081] The signal lines may include a write signal line GWL for transmitting the write signal (scan signal) GW, a reference voltage signal line GRL for transmitting the reference voltage signal GR, an initialization signal line GIL for transmitting the initialization signal GI, a first transmit control line EML for transmitting the first transmit control signal EM, a second transmit control line EMBL for transmitting the second transmit control signal EMB, and a data line DL that crosses the write signal line GWL and transmits the data signal DT.

[0082] The power voltage line 200 may include an initialization voltage line VL, a first reference voltage line RL1, a second reference voltage line RL2, a first power line PL2, and a counter electrode 530 electrically connected to an organic light-emitting diode (OLED) (see [link to OLED documentation]). Figure 11 The second power line. The initialization voltage line VL can transmit the initialization voltage Vint used to initialize the pixel electrodes of the organic light-emitting diode (OLED), and the first reference voltage line RL1 can transmit the first reference voltage Vref1 to the driving gate electrode G1 of the driving transistor T1 (see...). Figure 8 The second reference voltage line RL2 can transmit the second reference voltage Vref2 to one end of the holding capacitor Chold, and the first power line PL2 can transmit the first power voltage ELVDD, which serves as the driving voltage, to the driving transistor T1.

[0083] The driving gate electrode G1 of the driving transistor T1 can be electrically connected to the storage capacitor Cst through the first node N1. The drain region D of the driving transistor T1 can be electrically connected to the first power line PL2 through the first emitter control transistor T5. The source region of the driving transistor T1 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED) through the second emitter control transistor T6. The driving transistor T1 can receive the data signal DT according to the switching operation of the switching transistor T2, and can supply driving current to the OLED. For example, the driving transistor T1 can control the amount of current flowing to the OLED in response to the voltage applied to the first node N1 and changing according to the data signal DT.

[0084] The switching gate electrode G2 of the switching transistor T2 (see...) Figure 8 The switching transistor T2 can be electrically connected to the write signal line GWL, which transmits the write signal GW. Either the source or drain region of the switching transistor T2 can be electrically connected to the data line DL, and the other of the source and drain regions of the switching transistor T2 can be electrically connected to the drive gate electrode G1 of the driving transistor T1 via the first node N1. The switching transistor T2 can transmit the data signal DT from the data line DL to the first node N1 in response to a voltage applied to the write signal line GWL. For example, the switching transistor T2 can be turned on according to the write signal GW received via the write signal line GWL to perform a switching operation that transmits the data signal DT transmitted via the data line DL to the driving transistor T1 via the first node N1.

[0085] The reference voltage gate electrode G3 of the reference voltage transistor T3 (see) Figure 8 The reference voltage transistor T3 can be electrically connected to the reference voltage signal line GRL, which transmits the reference voltage signal GR. Either the source or drain region of the reference voltage transistor T3 can be electrically connected to the first reference voltage line RL1, and the other of the source and drain regions of the reference voltage transistor T3 can be electrically connected to the driving gate electrode G1 of the driving transistor T1 through the first node N1. The reference voltage transistor T3 can transmit the first reference voltage Vref1 from the first reference voltage line RL1 to the first node N1 in response to the reference voltage signal GR applied to the reference voltage signal line GRL. If desired, the reference voltage signal line GRL can be a write signal line GWL in a sub-pixel belonging to the previous row and adjacent to sub-pixel SP and electrically connected to the same data line DL. For example, the reference voltage signal GR can be referred to as the previous write signal (previous scan signal) GW.

[0086] Initialize the gate electrode G4 of transistor T4 (see Initialize Gate Electrode G4) Figure 8The initialization transistor T4 can be electrically connected to the initialization signal line GIL. Either the source or drain region of the initialization transistor T4 can be electrically connected to the pixel electrode of the OLED via a third node N3, and the other of the source and drain regions of the initialization transistor T4 can be electrically connected to the initialization voltage line VL to receive the initialization voltage Vint. The initialization transistor T4 can be turned on according to the initialization signal GI received via the initialization signal line GIL to initialize the pixel electrode of the OLED. If desired, the initialization signal line GIL can be the write signal line GWL in a sub-pixel belonging to the next row and adjacent to sub-pixel SP and electrically connected to the same data line DL. For example, the initialization signal GI can be referred to as the next write signal (next scan signal) GW.

[0087] The first emitter control gate electrode G5 of the first emitter control transistor T5 (see...) Figure 8 The first emitter control transistor T5 can be electrically connected to the first emitter control line EML. Either the source or drain region of the first emitter control transistor T5 can be electrically connected to the first power line PL2, and the other of the source and drain regions of the first emitter control transistor T5 can be electrically connected to the drain region of the driving transistor T1. The first emitter control transistor T5 is turned on according to the first emitter control signal EM received through the first emitter control line EML, causing the first power voltage (driving voltage) ELVDD to be transmitted to the organic light-emitting diode OLED, thereby allowing driving current to flow to the organic light-emitting diode OLED.

[0088] The second emitter control gate electrode G6 of the second emitter control transistor T6 (see...) Figure 8 The first emission control transistor T5 can be electrically connected to the second emission control line EMBL. Either the source or drain region of the second emission control transistor T6 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED), and the other of the source and drain regions of the second emission control transistor T6 can be electrically connected to the source region of the driving transistor T1. The second emission control transistor T6 can be turned on according to the second emission control signal EMB received via the second emission control line EMBL to connect the source region of the driving transistor T1 to the pixel electrode of the organic light-emitting diode (OLED). Although the first emission control transistor T5 and the second emission control transistor T6 are... Figure 3 The diagram shows operation in response to different control signals EM and EMB, but the disclosure is not limited thereto, and the first emitter control transistor T5 and the second emitter control transistor T6 can operate in response to the same control signal.

[0089] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 of the storage capacitor Cst is electrically connected to the driving gate electrode G1 of the driving transistor T1 through a first node N1, and the second capacitor electrode CE2 of the storage capacitor Cst is electrically connected to the source region of the driving transistor T1 through a second node N2. The storage capacitor Cst can store the charge corresponding to the difference between the driving gate electrode voltage of the driving transistor T1 and the initialization voltage Vint.

[0090] The holding capacitor Chold may include a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 of the holding capacitor Chold may be electrically connected to the source region of the driving transistor T1 through the second node N2, and the fourth capacitor electrode CE4 of the holding capacitor Chold may be electrically connected to the second reference voltage line RL2. A compensation voltage for compensating the threshold voltage of the driving transistor T1 may be stored in the holding capacitor Chold.

[0091] The specific operation of each sub-pixel SP according to the embodiment is as follows.

[0092] During the initialization period, with the initialization signal GI supplied via the initialization signal line GIL, the initialization transistor T4 is turned on, and the pixel electrodes of the OLED are initialized by the initialization voltage Vint supplied from the initialization voltage line VL. As described above, the initialization signal line GIL can be the write signal line GWL in a sub-pixel belonging to the next row and adjacent to sub-pixel SP and electrically connected to the same data line DL. For example, the initialization signal GI can be referred to as the next write signal (next scan signal) GW.

[0093] During the compensation period, when a reference voltage signal GR is supplied via the reference voltage signal line GRL, the reference voltage transistor T3 is turned on, and the first reference voltage Vref1 supplied from the first reference voltage line RL1 is transmitted to the drive gate electrode G1 of the drive transistor T1 to compensate for the threshold voltage of the drive transistor T1. The compensation voltage used to compensate for the threshold voltage of the drive transistor T1 can be stored in the holding capacitor Chold. As described above, if necessary, the reference voltage signal line GRL can be the write signal line GWL in a sub-pixel that belongs to the previous row and is adjacent to the sub-pixel SP and electrically connected to the same data line DL. For example, the reference voltage signal GR can be referred to as the previous write signal (previous scan signal) GW.

[0094] During the data programming period, when a write signal GW is supplied via the write signal line GWL, the switching transistor T2 can be turned on in response to the write signal GW. Then, a voltage corresponding to the data signal DT supplied from the data line DL can be applied to the drive gate electrode G1 of the drive transistor T1. Since the first capacitor electrode CE1 of the storage capacitor Cst is electrically connected to the drive gate electrode G1 of the drive transistor T1 via the first node N1, and the second capacitor electrode CE2 of the storage capacitor Cst is electrically connected via the second node N2 to the third capacitor electrode CE3 of the holding capacitor Chold, which stores a compensation voltage that compensates for the threshold voltage of the drive transistor T1, the storage capacitor Cst stores the data voltage that compensates for the threshold voltage of the drive transistor T1.

[0095] During the emission period, the first emission control transistor T5 can be turned on by the first emission control signal EM supplied from the first emission control line EML. Similarly, the second emission control transistor T6 can also be turned on by the second emission control signal EMB supplied from the second emission control line EMBL. Since the first capacitor electrode CE1 of the storage capacitor Cst is electrically connected to the driving gate electrode G1 of the driving transistor T1 through the first node N1, and the second capacitor electrode CE2 of the storage capacitor Cst is electrically connected to the source region of the driving transistor T1 through the second node N2, the driving current corresponding to the data signal DT flows to the organic light-emitting diode OLED through the data voltage stored in the storage capacitor Cst (which compensates for the threshold voltage of the driving transistor T1), regardless of the threshold voltage of the driving transistor T1.

[0096] As described above, the multiple transistors T1 to T6 may comprise oxide semiconductor materials. Since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even when the operating time may be long. For example, in the case of oxide semiconductors, even during low-frequency driving, the color change of the image due to the voltage drop is not significant, thus low-frequency driving is possible. Therefore, the multiple transistors T1 to T6 may comprise oxide semiconductor materials, thereby realizing a display device 10 in which leakage current is prevented and power consumption is reduced simultaneously.

[0097] Pixel circuit PC in Figure 3 The diagram shows six transistors and two capacitors, but the disclosure is not limited thereto. In another embodiment, the pixel circuit PC may include five transistors and two capacitors. In yet another embodiment, the pixel circuit PC may include seven transistors and two capacitors. For example, the pixel circuit PC may include more or fewer than six transistors and more or fewer than two capacitors.

[0098] Figure 4 It is shown that it includesFigure 1 A schematic layout of the positions of transistors T1 to T6, storage capacitor Cst, and holding capacitor Chold in the pixels of the display device 10. Figures 5 to 10 It is shown for each layer according to the manufacturing process sequence. Figure 4 The schematic layout of components such as transistors T1 to T6, storage capacitor Cst, and holding capacitor Chold of the display device 10 shown is shown. Figure 11 It shows along Figure 4 A schematic cross-sectional view of the display device 10 shown, taken along a continuous line B-B'. Meanwhile, Figure 8 It shows Figure 2 The layout of the test line 30 and the pixel components shown. Figure 12 It shows along Figure 2 A schematic cross-sectional view of the display device 10 shown, taken along the discontinuous line C-C'. Referring below... Figures 4 to 12 A detailed description of the display device 10 according to the disclosed embodiments. Figure 11 and Figure 12 The sectional view schematically illustrates the components by modifying them to better show their characteristics.

[0099] The display device 10 may include pixels, and the pixels may be located in a display area DA. Each pixel may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, the first sub-pixel SP1 may be a red sub-pixel emitting red light, the second sub-pixel SP2 may be a green sub-pixel emitting green light, and the third sub-pixel SP3 may be a blue sub-pixel emitting blue light. The disclosure is not limited thereto, and a pixel may include fewer or more sub-pixels.

[0100] Figures 4 to 10 The pixels shown can be repeated in the first direction (or the x-axis direction). Figures 4 to 10 The pixels shown can also be repeated in a second direction (or the y-axis direction) that intersects the first direction.

[0101] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include pixel circuitry. In the following description, for ease of description, some components will be described based on the pixel circuitry of the first sub-pixel SP1; however, these components may also be disposed in the pixel circuitry of each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0102] A barrier layer 111, comprising silicon oxide, silicon nitride, or silicon oxynitride, may be located on the substrate 100. The barrier layer 111 may planarize the upper surface of the substrate 100.

[0103] ReferenceFigure 5 The lower metal layer 1100 (BML0) may be disposed on the barrier layer 111. The lower metal layer 1100 may include some horizontal power voltage lines 210 (see...). Figure 1 The lower metal layer 1100 may include a horizontal second reference voltage line 1110, a first capacitor electrode 1121, a fourth capacitor electrode 1131, and a horizontal repair line 1140. Among these, the horizontal second reference voltage line 1110 may be electrically connected to the fourth capacitor electrode 1131 and may extend substantially in a first direction (or the x-axis direction).

[0104] The horizontal second reference voltage line 1110 can be electrically connected via a contact hole to the vertical second reference voltage line 1640, which will be described below (see...). Figure 10 The vertical second reference voltage line 1640 is located on the horizontal second reference voltage line 1110 and extends in a second direction (or y-axis direction) intersecting the first direction (or x-axis direction). The horizontal second reference voltage line 1110 may include a protrusion 1112p protruding from the horizontal second reference voltage line 1110 toward the horizontal repair line 1140 in the second direction (or y-axis direction) in the region of the second sub-pixel SP2. The horizontal second reference voltage line 1110 may be electrically connected to the vertical second reference voltage line 1640 thereon through contact holes at the corresponding protrusion 1112p (see...). Figure 10 ). Horizontal second reference voltage line 1110 and vertical second reference voltage line 1640 (see Figure 10 This can be the second reference voltage line RL2 (see...) Figure 3 ) components.

[0105] The horizontal repair line 1140 can extend in the first direction (or the x-axis direction) and can be used in subsequent pixel repair processes.

[0106] The first capacitor electrode 1121 may have an isolated shape. The first capacitor electrode 1121 is Figure 3 The first capacitor electrode CE1 of the storage capacitor Cst. The first capacitor electrode 1121 can be electrically connected to the drive gate electrode G1 of the drive transistor T1 located thereon through a contact hole (see... Figure 8 ).

[0107] The fourth capacitor electrode 1131 can be electrically connected to the horizontal second reference voltage line 1110. The fourth capacitor electrode 1131 and the horizontal second reference voltage line 1110 are arranged alternately in a first direction (or the x-axis direction). The fourth capacitor electrode 1131 can be connected in a third direction (or the z-axis direction) to the third capacitor electrode 1241b located thereon (see...). Figure 6 The fourth capacitor electrode 1131 and the third capacitor electrode 1241b are stacked. Figure 6These are the two electrodes of the holding capacitor Chold. Therefore, the holding capacitor Chold can have a fourth capacitor electrode 1131 including a lower metal layer 1100 and an upper metal layer 1200, which will be described below (see [link to documentation]). Figure 6 The third capacitor electrode 1241b (see) Figure 6 This is a single capacitor structure with two electrodes. The fourth capacitor electrode 1131 can be connected to the drive gate electrode G1, which will be described below (see...). Figure 8 ) and drive active region A1 (see Figure 7 The electrodes are stacked. Therefore, external light incident on the driving active region A1 can be prevented or minimized. The fourth capacitor electrode 1131 can correspond to... Figure 3 The fourth capacitor electrode CE4.

[0108] The lower metal layer 1100 may include metals, alloys, or conductive metal oxides. For example, the lower metal layer 1100 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). The lower metal layer 1100 may have a multilayer structure. For example, the lower metal layer 1100 may have a two-layer structure, which includes an aluminum layer with a thickness of 3500 angstroms and a titanium layer with a thickness of 300 angstroms.

[0109] First buffer layer 113 (see Figure 11 The first buffer layer 113 may cover the lower metal layer 1100 and may be disposed on the barrier layer 111. The first buffer layer 113 may include an insulating material. For example, the first buffer layer 113 may include silicon oxide, silicon nitride, or silicon oxynitride. The first buffer layer 113 is used to insulate the lower metal layer 1100 from the upper metal layer 1200. The first buffer layer 113 can prevent metal atoms or impurities from the substrate 100, etc., from diffusing into the semiconductor layer 1300 located thereon.

[0110] like Figure 6 The upper metal layer 1200 (BML) shown can be disposed on the first buffer layer 113 in a third direction (or z-axis direction). Figure 6 In the diagram, for ease of description, the lower metal layer 1100 is shown together with the upper metal layer 1200. The upper metal layer 1200 may include all horizontal power voltage lines 210 except for the horizontal second reference voltage line 1110 (see [link to diagram]). Figure 1The upper metal layer 1200 may include a write signal line 1220, a horizontal first reference voltage line 1230, a common capacitor electrode 1241, a horizontal first power line 1250, a horizontal second power line 1270, and a horizontal initialization voltage line 1260. Among these, the write signal line 1220, the horizontal first reference voltage line 1230, the horizontal first power line 1250, the horizontal initialization voltage line 1260, and the horizontal second power line 1270 may extend in a first direction (or the x-axis direction).

[0111] Write signal line 1220 can be an interconnect that applies the write signal GW to the switching transistor T2, and can correspond to Figure 3 The write signal line GWL. The write signal line 1220 can be connected to the first connection electrode 1511 of the second conductive layer (first source / drain layer) 1500, which will be described below (see below). Figure 9 Electrically connected to the switching gate electrode G2 of switching transistor T2 (see...) Figure 8 The write signal line 1220 may include a protrusion projecting toward the horizontal first reference voltage line 1230 in a second direction (or the y-axis direction) and for connecting the write signal line 1220 to the switch gate electrode G2 (see [link to documentation]). Figure 8 The first connecting electrode 1511 (see) Figure 9 The contact hole can be formed in the protrusion.

[0112] The first horizontal reference voltage line 1230 can be passed through the contact hole ( Figure 10 (Not shown in the image) Electrically connected to the vertical first reference voltage line 1630, which will be described below (see image). Figure 10 The vertical first reference voltage line 1630 is located on the horizontal first reference voltage line 1230 and extends in a second direction (or y-axis direction) that intersects the first direction (or x-axis direction). The horizontal first reference voltage line 1230 and the vertical first reference voltage line 1630 (see...) Figure 10 () can be a component of the first reference voltage line. For example, the first reference voltage line corresponds to Figure 3 The first reference voltage line RL1. The horizontal first reference voltage line 1230 can belong to... Figure 1 The components of the horizontal power voltage line 210 shown.

[0113] The horizontal first electric field line 1250 can be electrically connected via a contact hole to the vertical first electric field line 1610, which will be described below (see...). Figure 10 The vertical first electric field line 1610 lies on the horizontal first electric field line 1250 and extends in a second direction (or y-axis direction) that intersects the first direction (or x-axis direction). The horizontal first electric field line 1250 and the vertical first electric field line 1610 (see...) Figure 10This can be a component of the first electric field line that supplies the driving voltage ELVDD to an organic light-emitting diode (OLED). For example, the first electric field line corresponds to... Figure 3 The first power line PL2. The horizontal first power line 1250 can belong to... Figure 1 The components of the horizontal power voltage line 210 shown.

[0114] The horizontal initialization voltage line 1260 can be electrically connected via a contact hole to the vertical initialization voltage line 1620, which will be described below (see...). Figure 10 The vertical initialization voltage line 1620 is located on the horizontal initialization voltage line 1260 and extends in a second direction (or y-axis direction) intersecting the first direction (or x-axis direction). The horizontal initialization voltage line 1260 and the vertical initialization voltage line 1620 (see...) Figure 10 (This can be a component for initializing voltage lines.) Initializing voltage lines can correspond to... Figure 3 The initialization voltage line VL. The horizontal initialization voltage line 1260 can belong to... Figure 1 The components of the horizontal power voltage line 210 shown.

[0115] The horizontal second power line 1270 can be electrically connected via a contact hole to the vertical second power line 1650, which will be described below (see...). Figure 10 The vertical second electric field line 1650 lies on the horizontal second electric field line 1270 and extends in a second direction (or y-axis direction) that intersects the first direction (or x-axis direction). The horizontal second electric field line 1270 and the vertical second electric field line 1650 (see...) Figure 10 This can be a component of a second power line, which can be electrically connected to an organic light-emitting diode (OLED) to supply a common voltage ELVSS. The horizontal second power line 1270 can be a component belonging to... Figure 1 The components of the horizontal power voltage line 210 shown.

[0116] The common capacitor electrode 1241 can have an isolated shape. The common capacitor electrode 1241 can be... Figure 3 The third capacitor electrode CE3 of the holding capacitor Chold can also be a 2-1 capacitor electrode 1241a, which is part of the second capacitor electrode CE2 of the storage capacitor Cst. Within the region of the common capacitor electrode 1241, the portion near the horizontal first reference voltage line 1230 corresponding to the upper part in the second direction (or the y-axis direction) can be the 2-1 capacitor electrode 1241a, and the portion near the horizontal first electric field line 1250 corresponding to the lower part in the second direction (or the y-axis direction) can be the third capacitor electrode 1241b. For example, the second capacitor electrode CE2 of the storage capacitor Cst and the third capacitor electrode CE3 of the holding capacitor Chold can be an integral conductive layer.

[0117] The common capacitor electrode 1241 may include an opening 1240-op. Through the opening 1240-op, the lower metal layer 1100 and the first conductive layer (gate layer) 1400, described below, can be electrically connected to each other via a contact hole. The first capacitor electrode 1121 of the storage capacitor Cst of the lower metal layer 1100 can be electrically connected via the opening 1240-op to the driving gate electrode G1 of the driving transistor T1 of the first conductive layer 1400 (see...). Figure 8 The common capacitor electrode 1241 can be connected to the drive gate electrode G1 of the first conductive layer 1400, which will be described below (see...). Figure 8 ) and the driving active region A1 of semiconductor layer 1300 (see Figure 7 The common capacitor electrode 1241 is stacked. Therefore, the common capacitor electrode 1241 can prevent or minimize external light incident on the driving active region A1 (see Figure 7 )superior.

[0118] The upper metal layer 1200 may include metals, alloys, or conductive metal oxides. For example, the upper metal layer 1200 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). The upper metal layer 1200 may have a multilayer structure. For example, the upper metal layer 1200 may have a two-layer structure, which includes an aluminum layer with a thickness of 3500 angstroms and a titanium layer with a thickness of 300 angstroms.

[0119] Second buffer layer 114 (see) Figure 11 The upper metal layer 1200 can be covered, and the second buffer layer 114 can be disposed on the first buffer layer 113 in a third direction (or z-axis direction). The second buffer layer 114 can include an insulating material. For example, the second buffer layer 114 can include silicon oxide, silicon nitride, or silicon oxynitride. The second buffer layer 114 is used to insulate the upper metal layer 1200 from the semiconductor layer 1300. The second buffer layer 114 can prevent metal atoms or impurities from the substrate 100, etc., from diffusing into the semiconductor layer 1300 located thereon.

[0120] like Figure 7 The semiconductor layer 1300 shown can be disposed on the second buffer layer 114 in a third direction (or z-axis direction). As described above, the semiconductor layer 1300 can include an oxide semiconductor material. For example, the semiconductor layer 1300 can include indium tin gallium zinc oxide (ITGZO) having a thickness of about 300 angstroms. Figure 7 As shown, Figure 3The driving transistor T1, the switching transistor T2, the reference voltage transistor T3, the initialization transistor T4, the first emitter control transistor T5, and the second emitter control transistor T6 can be positioned along the semiconductor layer 1300. Figure 7 The semiconductor layer 1300 is shown to include a first portion, a second portion, and a third portion spaced apart from each other. The switching active region A2 of the switching transistor T2 and the reference voltage active region A3 of the reference voltage transistor T3 are located in the first portion. The driving active region A1 of the driving transistor T1 and the first emission control active region A5 of the first emitter control transistor T5 are located in the second portion. The initialization active region A4 of the initialization transistor T4 and the second emission control active region A6 of the second emitter control transistor T6 are shown as being located in the third portion.

[0121] Gate insulating layer 115 (see Figure 11 The gate insulating layer 115 may cover the semiconductor layer 1300 and may be disposed on the second buffer layer 114. The gate insulating layer 115 may include an insulating material. For example, the gate insulating layer 115 may include an inorganic insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0122] like Figure 8 The first conductive layer 1400 shown can be located on the gate insulating layer 115 in a third direction (or z-axis direction). Figure 8 For ease of description, the first conductive layer 1400 may be shown together with the semiconductor layer 1300. The first conductive layer 1400 may include a reference voltage signal line 1410 containing a reference voltage gate electrode G3, a first emission control line 1420 containing a first emission control gate electrode G5, a second emission control line 1430 containing a second emission control gate electrode G6, an initialization signal line 1440 containing an initialization gate electrode G4, a switching gate electrode layer 1470, and a common gate electrode layer 1450. According to the disclosed embodiments, the first conductive layer 1400 may also include a test line 30 in the peripheral region PA.

[0123] Reference voltage signal line 1410 can correspond to Figure 3 The reference voltage signal line GRL. The portion of the reference voltage signal line 1410 that is superimposed on the semiconductor layer 1300 can be the reference voltage gate electrode G3 of the reference voltage transistor T3. Figure 8 The reference voltage signal line 1410 is shown to include a protrusion, and the protrusion may be the reference voltage gate electrode G3.

[0124] The first launch control line 1420 can correspond to Figure 3 The first emitter control line EML. The portion of the first emitter control line 1420 that is superimposed on the semiconductor layer 1300 in the third direction (or z-axis direction) may be the first emitter control gate electrode G5 of the first emitter control transistor T5.Figure 8 The first transmit control line 1420 is shown to include a protrusion, and the protrusion may be the first transmit control gate electrode G5.

[0125] The second launch control line 1430 can correspond to Figure 3 The second emitter control line EMBL. The portion of the second emitter control line 1430 that is superimposed on the semiconductor layer 1300 in the third direction (or z-axis direction) can be the second emitter control gate electrode G6 of the second emitter control transistor T6. Figure 8 The second transmit control line 1430 is shown to include a protrusion, and the protrusion may be the second transmit control gate electrode G6.

[0126] Initialization signal line 1440 can correspond to Figure 3 The initialization signal line GIL. The portion of the initialization signal line 1440 that overlaps with the semiconductor layer 1300 in the third direction (or z-axis direction) can be the initialization gate electrode G4 of the initialization transistor T4. Figure 8 The initialization signal line 1440 is shown to include a protrusion, and the protrusion may be the initialization gate electrode G4.

[0127] The switch gate electrode layer 1470 may have an isolated shape. A portion of the switch gate electrode layer 1470 may be stacked with the underlying semiconductor layer 1300. The portion of the switch gate electrode layer 1470 that is stacked with the semiconductor layer 1300 in a third direction (or z-axis direction) (e.g., the portion that is stacked with the switching active region A2 of the semiconductor layer 1300) may be referred to as the switch gate electrode G2. The switch gate electrode G2 may be electrically connected to the write signal line 1220 via the first connection electrode 1511 of the second conductive layer 1500, which will be described below.

[0128] The common-gate electrode layer 1450 can have an isolated shape. A portion of the common-gate electrode layer 1450 can be stacked with the underlying semiconductor layer 1300. The portion of the common-gate electrode layer 1450 stacked with the semiconductor layer 1300 (e.g., the portion stacked with the driving active region A1 of the semiconductor layer 1300) can be the driving gate electrode G1. Meanwhile, another portion of the common-gate electrode layer 1450 can be not stacked with the semiconductor layer 1300, but can be stacked with the upper metal layer 1200. The portion of the common-gate electrode layer 1450 not stacked with the semiconductor layer 1300 but stacked with the upper metal layer 1200 can be the capacitor electrode of the storage capacitor Cst. For example, Figure 3The driving gate electrode G1 of the driving transistor T1 and the capacitor electrode of the storage capacitor Cst can be an integral conductive layer. The portion of the common gate electrode layer 1450 corresponding to the capacitor electrode can be a 2-2 capacitor electrode 1451, which is part of the second capacitor electrode CE2 of the storage capacitor Cst and can be electrically connected to the first capacitor electrode 1121 through the contact hole 1450CNT. Therefore, the storage capacitor Cst can have a dual capacitor structure by including a first capacitor electrode 1121 formed by the lower metal layer 1100, a 2-1 capacitor electrode 1241a formed by the upper metal layer 1200, and a 2-2 capacitor electrode 1451 formed by the first conductive layer 1400.

[0129] Simultaneously, the driving gate electrode G1 of the driving transistor T1 and the first capacitor electrode 1121 of the storage capacitor Cst can be electrically connected to each other through a contact hole. (Refer to the above...) Figure 6 The common capacitor electrode 1241 of the upper metal layer 1200 may include an opening 1240-op. Through the opening 1240-op, the first capacitor electrode 1121 of the lower metal layer 1100 and the driving gate electrode G1 of the first conductive layer 1400 can be electrically connected to each other through a contact hole.

[0130] At the same time, Figure 8 middle, Figure 1 The test line 30 is positioned in the peripheral region PA, shown as being to the left of the display region DA, in which pixels are shown together with the display region DA. The first conductive layer 1400 may also include the test line 30. For example, the test line 30 may be located in the gate layer. The test line 30 may extend substantially in a second direction (or the y-axis direction). Figure 8 The test lines 30 shown can correspond to respectively Figure 2 The diagram shows a first power test line 301, a second power test line 302, an initialization voltage test line 303, a first reference voltage test line 304, and a second reference voltage test line 305. The width W1 of each of the test lines 30 in the first direction (or x-axis direction) can be greater than the width W2 of each of the signal lines in the display area DA in the second direction (or y-axis direction). The test lines 30 can be interconnects supplying power voltage, and therefore can have a width wider than the signal lines supplying signals, thereby preventing voltage drop.

[0131] According to the disclosed embodiments, a vertical power voltage line 220 (see...) can be formed. Figure 1Test lines 30 are formed before the vertical power voltage line 220 and can be electrically connected to the horizontal power voltage line 210. Therefore, test lines 30 and the horizontal power voltage line 210 can form a global grid pattern throughout the entire area of ​​the display device 10. Due to this global grid pattern, the display device 10 can undergo FCA testing even before the vertical power voltage line 220 is formed.

[0132] The first conductive layer 1400 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the first conductive layer 1400 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first conductive layer 1400 may have a multilayer structure. For example, the first conductive layer 1400 may have a two-layer structure, comprising a titanium layer with a thickness of 300 angstroms and a molybdenum layer with a thickness of 2500 angstroms. The first conductive layer 1400 may also be referred to as a gate layer.

[0133] Interlayer insulation layer 116 (see) Figure 11 The interlayer insulating layer 116 may cover the first conductive layer 1400 and may be located on the gate insulating layer 115 in a third direction (or z-axis direction). The interlayer insulating layer 116 may include an insulating material. For example, the interlayer insulating layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0134] like Figure 9 The second conductive layer 1500 shown can be located on the interlayer insulating layer 116 in the third direction (or z-axis direction). The second conductive layer 1500 may include data lines 1591R, 1592G and 1593B, a first connection electrode 1511, a second connection electrode 1521, a third connection electrode 1531, a fourth connection electrode 1541, a fifth connection electrode 1551, a sixth connection electrode 1561, a seventh connection electrode 1571 and a common source / drain electrode layer 1581. The second conductive layer 1500 may also be referred to as the first source / drain layer.

[0135] At least one of the data cables 1591R, 1592G, and 1593B can correspond to Figure 3The data lines DL. Data lines 1591R, 1592G, and 1593B can extend in the second direction (or the y-axis direction). Data lines 1591R, 1592G, and 1593B are provided for each sub-pixel. The R data line 1591R, which transmits the data signal for emitting red light, is located in the first sub-pixel SP1; the G data line 1592G, which transmits the data signal for emitting green light, is located in the second sub-pixel SP2; and the B data line 1593B, which transmits the data signal for emitting blue light, can be located in the third sub-pixel SP3. The data lines can be electrically connected to one side of the switching active region A2 of the underlying semiconductor layer 1300 via contact holes.

[0136] Each of the first connecting electrode 1511, the second connecting electrode 1521, the third connecting electrode 1531, the fourth connecting electrode 1541, the fifth connecting electrode 1551, and the sixth connecting electrode 1561 may have an isolated shape. The first connecting electrode 1511, the second connecting electrode 1521, the third connecting electrode 1531, the fourth connecting electrode 1541, the fifth connecting electrode 1551, and the sixth connecting electrode 1561 are connected to other components on or under them via contact holes.

[0137] The first connection electrode 1511 can be electrically connected to the switching active region A2 of the underlying semiconductor layer 1300 through contact hole 1511CNTb. The first connection electrode 1511 can also be electrically connected to the write signal line 1220 of the upper metal layer 1200 through contact hole 1511CNTa. The first connection electrode 1511 is used to... Figure 3 The write signal line GWL is connected to the switching transistor T2.

[0138] The second connection electrode 1521 can be electrically connected to the reference voltage active region A3 of the semiconductor layer 1300 through contact hole 1521CNTa. The second connection electrode 1521 can also be electrically connected to the horizontal first reference voltage line 1230 of the upper metal layer 1200 through contact hole 1521CNTb. The second connection electrode 1521 is used to... Figure 3 The reference voltage signal line GRL is connected to the reference voltage transistor T3.

[0139] The third connection electrode 1531 can be electrically connected via contact hole 1531CNTa to the portion between the switching active region A2 and the reference voltage active region A3 of the semiconductor layer 1300. The third connection electrode 1531 can also be electrically connected via contact hole 1531CNTb to the driving gate electrode G1 of the driving transistor T1. For example, the third connection electrode 1531, which electrically connects the switching transistor T2, the reference voltage transistor T3, and the driving transistor T1, can be understood as serving as… Figure 3 The first node N1.

[0140] The fourth connection electrode 1541 can be electrically connected to the first emitter control active region A5 of the semiconductor layer 1300 through contact hole 1541CNTa. The fourth connection electrode 1541 can also be electrically connected to the horizontal first electric field line 1250 of the upper metal layer 1200 through contact hole 1541CNTb. The fourth connection electrode 1541 is used to... Figure 3 The first power line PL2 is connected to the first emitter control transistor T5.

[0141] The fifth connection electrode 1551 can be electrically connected to the second emitter control active region A6 and the initialization active region A4 of the semiconductor layer 1300 through contact hole 1551CNT. For example, connecting the second emitter control transistor T6 to the fifth connection electrode 1551 of the initialization transistor T4 can be understood as serving as... Figure 3 The third node N3.

[0142] The sixth connection electrode 1561 can be electrically connected to the initialization active region A4 of the semiconductor layer 1300 through contact hole 1561CNTb. The sixth connection electrode 1561 can also be electrically connected to the horizontal initialization voltage line 1260 of the upper metal layer 1200 through contact hole 1561CNTa. The sixth connection electrode 1561 is used to... Figure 3 The initialization signal line GIL is connected to the initialization transistor T4.

[0143] The common-source / drain electrode layer 1581 can have an isolated shape. The common-source / drain electrode layer 1581 can be stacked with the common-gate electrode layer 1450 of the first conductive layer 1400 below it. The common-source / drain electrode layer 1581 can also be stacked with the common capacitor electrode 1241 of the upper metal layer 1200 below it, and can be electrically connected to the common capacitor electrode 1241 of the upper metal layer 1200 through contact hole 1581CNTa. The common-source / drain electrode layer 1581 can also be stacked with the first capacitor electrode 1121 of the lower metal layer 1100 below it. The common-source / drain electrode layer 1581 can be a 2-3 capacitor electrode 1581a, which is part of the second capacitor electrode CE2 of the storage capacitor Cst. Therefore, by including a first capacitor electrode 1121 composed of a lower metal layer 1100, a 2-1 capacitor electrode 1241a composed of an upper metal layer 1200, a 2-2 capacitor electrode 1451 composed of a first conductive layer 1400, and a 2-3 capacitor electrode 1581a composed of a second conductive layer 1500, the storage capacitor Cst can have a triple capacitor structure. The common source / drain electrode layer 1581 can be electrically connected to the driving active region A1 of the semiconductor layer 1300 through contact holes 1581CNTb. The common source / drain electrode layer 1581 may include protrusions and can be electrically connected to the second emitter control active region A6 of the semiconductor layer 1300 through contact holes 1581CNTc of the protrusions. For example, the common source / drain electrode layer 1581, which electrically connects the second emitter control transistor T6, the driving transistor T1, and the storage capacitor Cst, can be understood as serving as... Figure 3 The second node N2.

[0144] Simultaneously, a seventh connection electrode 1571 is provided on the second sub-pixel SP2 adjacent to the first sub-pixel SP1. The seventh connection electrode 1571 may also have an isolated shape. The seventh connection electrode 1571 electrically connects the horizontal second reference voltage line 1110 of the lower metal layer 1100 to the subsequent third conductive layer 1600 (see...). Figure 10 The vertical second reference voltage line 1640 (see second source / drain layer) Figure 10 The seventh connecting electrode 1571 can be electrically connected to the contact hole 1571CNT via... Figure 8 The eighth connecting electrode 1460 of the first conductive layer 1400. Figure 8 The eighth connection electrode 1460 of the first conductive layer 1400 can be electrically connected to the protrusion 1112p of the horizontal second reference voltage line 1110 of the lower metal layer 1100 through the contact hole 1460CNT. Figure 10 The third conductive layer 1600 (see Figure 10 The vertical second reference voltage line 1640 of the second source / drain layer can be electrically connected to the second conductive layer 1500 (see contact hole 1640CNT) through the contact hole 1640CNT.Figure 9 The seventh connection electrode 1571 (of the first source / drain layer). For example, the seventh connection electrode 1571 is used to electrically connect the horizontal second reference voltage line 1110 to the vertical second reference voltage line 1640.

[0145] At the same time, refer to Figure 1 , Figure 2 and Figure 12 The second conductive layer 1500 may further include a connecting interconnect 31. The connecting interconnect 31 is disposed in the peripheral region PA, may extend in a first direction (or x-axis direction), and electrically connects the test line 30 to the horizontal power voltage line 210.

[0146] The interconnecting element 31 can be located on a different layer from the test line 30. For example, one end of the interconnecting element 31 in the second conductive layer 1500 is connected to the test line 30 corresponding to the interconnecting element 31 through contact holes. For example, the first interconnecting element 311 can be electrically connected to the first power test line 301 through contact holes. The second interconnecting element 312 can be electrically connected to the second power test line 302 through contact holes. The third interconnecting element 313 can be electrically connected to the initialization voltage test line 303 through contact holes. The fourth interconnecting element 314 can be electrically connected to the first reference voltage test line 304 through contact holes. The fifth interconnecting element 315 can be electrically connected to the second reference voltage test line 305 through contact holes. The other end of the interconnecting element 31 in the second conductive layer 1500 is connected to the horizontal power voltage line 210 through contact holes. For example, the first interconnecting element 311 can be electrically connected to the horizontal first power line 1250 of the upper metal layer 1200 through contact holes. The second interconnecting element 312 can be electrically connected to the horizontal second power line 1270 of the upper metal layer 1200 through contact holes. The third interconnect 313 can be electrically connected via a contact hole to the horizontal initialization voltage line 1260 of the upper metal layer 1200. The fourth interconnect 314 can be electrically connected via a contact hole to the horizontal first reference voltage line 1230 of the upper metal layer 1200. The fifth interconnect 315 can be electrically connected via a contact hole to the horizontal second reference voltage line 1110 of the lower metal layer 1100.

[0147] The interconnect 31 can be located on the same layer as the test line 30. For example, the interconnect 31 can be integrally formed with the test line 30 without needing to be electrically connected to the test line 30 through a contact hole.

[0148] Meanwhile, multiple interconnects 31 can be located in different layers. For example, the first interconnect 311 and the second interconnect 312 can be located in the first conductive layer 1400, while the third interconnect 313 to the fifth interconnect 315 can be located in the second conductive layer 1500. The position and shape of each of the interconnects 31 can vary in various ways.

[0149] The second conductive layer 1500 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the second conductive layer 1500 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), ITO, or IZO. For example, the second conductive layer 1500 may have a multilayer structure, which includes a titanium layer with a thickness of 700 angstroms, an aluminum layer with a thickness of 6000 angstroms, and a titanium layer with a thickness of 300 angstroms.

[0150] First planarization layer 117 (see...) Figure 11 The first planarization layer 117 may cover the second conductive layer 1500 and may be located on the interlayer insulating layer 116. The first planarization layer 117 may include an insulating material. For example, the first planarization layer 117 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0151] like Figure 10 The third conductive layer 1600 shown may be located on the first planarization layer 117. The third conductive layer 1600 may include vertical electric voltage lines 220. The vertical electric voltage lines 220 may include a vertical first electric voltage line 1610, a vertical initialization voltage line 1620, a vertical first reference voltage line 1630, a vertical second reference voltage line 1640, a vertical second electric voltage line 1650, and a tenth connecting electrode 1660. Each of the vertical first electric voltage line 1610, vertical initialization voltage line 1620, vertical first reference voltage line 1630, vertical second reference voltage line 1640, and vertical second electric voltage line 1650 may have a shape that approximately extends in the second direction (or the y-axis direction).

[0152] A vertical first electric field line 1610 traverses the first sub-pixel SP1 in a second direction (or the y-axis direction). The vertical first electric field line 1610 can be electrically connected to the fourth connection electrode 1541 of the underlying second conductive layer 1500 via contact hole 1610CNT. The fourth connection electrode 1541 can be electrically connected to the horizontal first electric field line 1250 of the upper metal layer 1200 via contact hole 1541CNTb. For example, the vertical first electric field line 1610 of the third conductive layer 1600 can be electrically connected to the horizontal first electric field line 1250 of the upper metal layer 1200. The vertical first electric field line 1610 and the horizontal first electric field line 1250 electrically connected to each other can form a first electric field line. The structure of the first electric field line can be applied to all of a plurality of pixels arranged in a matrix in the display area DA. Therefore, the first electric field line can be implemented in a grid form in the display area DA. The first electric field line can supply a first electric voltage ELVDD to the pixel.

[0153] A vertical initialization voltage line 1620 traverses the first sub-pixel SP1 in the second direction (or the y-axis direction). The vertical initialization voltage line 1620 is electrically connected to the sixth connection electrode 1561 of the second conductive layer 1500 below it via contact hole 1620CNT. The sixth connection electrode 1561 is electrically connected to the horizontal initialization voltage line 1260 of the upper metal layer 1200 via contact hole 1561CNTa. For example, the vertical initialization voltage line 1620 of the third conductive layer 1600 can be electrically connected to the horizontal initialization voltage line 1260 of the upper metal layer 1200. The vertical initialization voltage line 1620 and the horizontal initialization voltage line 1260 electrically connected to each other can form an initialization voltage line. The structure of the initialization voltage line can be applied to all of a plurality of pixels arranged in a matrix in the display area DA. Therefore, the initialization voltage line can be implemented in a grid form in the display area DA. The initialization voltage line supplies an initialization voltage Vint to the pixel.

[0154] The vertical first reference voltage line 1630 crosses the second sub-pixel SP2 adjacent to the first sub-pixel SP1 in the second direction (or the y-axis direction). Although Figure 10Although not shown, the vertical first reference voltage line 1630 can be electrically connected to the horizontal first reference voltage line 1230 of the upper metal layer 1200 below it via a contact hole (not shown). For example, the vertical first reference voltage line 1630 of the third conductive layer 1600 can be electrically connected to the horizontal first reference voltage line 1230 of the upper metal layer 1200. The vertical first reference voltage line 1630 and the horizontal first reference voltage line 1230 electrically connected to each other can form a first reference voltage line. The structure of the first reference voltage line can be applied to all of a plurality of pixels arranged in a matrix in the display area DA. Therefore, the first reference voltage line can be implemented in a grid in the display area DA. The first reference voltage line can supply a first reference voltage Vref1 to the pixel.

[0155] The vertical second reference voltage line 1640 traverses the second sub-pixel SP2 adjacent to the first sub-pixel SP1 in the second direction (or the y-axis direction). The vertical second reference voltage line 1640 may include a protrusion and can be electrically connected to the seventh connection electrode 1571 of the underlying second conductive layer 1500 through a contact hole 1640CNT of the protrusion. The seventh connection electrode 1571 can be electrically connected to... Figure 8 The eighth connecting electrode 1460 of the first conductive layer 1400. Figure 8 The eighth connection electrode 1460 can be electrically connected to the protrusion of the horizontal second reference voltage line 1110 of the lower metal layer 1100 through the contact hole 1460CNT. For example, the vertical second reference voltage line 1640 of the third conductive layer 1600 can be electrically connected to the horizontal second reference voltage line 1110 of the lower metal layer 1100. The vertical second reference voltage line 1640 and the horizontal second reference voltage line 1110 electrically connected to each other can form a second reference voltage line. The structure of the second reference voltage line can be applied to all of the multiple pixels arranged in a matrix in the display area DA. Therefore, the second reference voltage line can be implemented in a grid form in the display area DA. The second reference voltage line can supply a second reference voltage Vref2 to the pixel.

[0156] A vertical second electric field line 1650 traverses a third sub-pixel SP3 adjacent to the second sub-pixel SP2 in a second direction (or the y-axis direction). The vertical second electric field line 1650 may include a protrusion and can be electrically connected to a ninth connection electrode 1591 of the second conductive layer 1500 below it via a contact hole 1650CNT of the protrusion. The ninth connection electrode 1591 can be electrically connected to a horizontal second electric field line 1270 of the upper metal layer 1200 via a contact hole 1591CNT. For example, the vertical second electric field line 1650 of the third conductive layer 1600 can be electrically connected to the horizontal second electric field line 1270 of the upper metal layer 1200. The vertical second electric field line 1650 and the horizontal second electric field line 1270 electrically connected to each other can form a second electric field line. The structure of the second electric field line can be applied to all of a plurality of pixels arranged in a matrix in the display area DA. Therefore, the second electric field line can be implemented in a grid form in the display area DA. The second electric field line can be electrically connected to the counter electrode 530 of the organic light-emitting diode OLED (see [reference]) outside the display area DA. Figure 11 And it can supply a second power voltage, ELVSS, to organic light-emitting diodes (OLEDs).

[0157] The third conductive layer 1600 may further include a tenth connecting electrode 1660. The tenth connecting electrode 1660 may have an isolated shape. The tenth connecting electrode 1660 may be disposed in each sub-pixel. The tenth connecting electrode 1660 may be electrically connected to the fifth connecting electrode 1551 of the second conductive layer 1500 below it via a contact hole 1660CNT. The fifth connecting electrode 1551 may be electrically connected to the second emission control active region A6 and the initialization active region A4 of the semiconductor layer 1300 below it via a contact hole 1551CNT. Simultaneously, the tenth connecting electrode 1660 may be electrically connected to the pixel electrode 510 (see...) via a via (not shown). Figure 11 ), pixel electrode 510 is formed on an insulating layer (second planarization layer, see) covering the third conductive layer 1600. Figure 11 (118) on.

[0158] The third conductive layer 1600 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the third conductive layer 1600 may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), ITO, or IZO. For example, the third conductive layer 1600 may have a multilayer structure, including a titanium layer with a thickness of 700 angstroms, an aluminum layer with a thickness of 6000 angstroms, and a titanium layer with a thickness of 300 angstroms. The third conductive layer 1600 may also be referred to as a second source / drain layer.

[0159] The second planarization layer 118 may cover the third conductive layer 1600 and may be located on the first planarization layer 117 in a third direction (or z-axis direction). The second planarization layer 118 may include an organic insulating material. For example, the second planarization layer 118 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof. For example, the second planarization layer 118 may include a polyimide layer having a thickness of about 1.6 μm.

[0160] The organic light-emitting diode (OLED) can be located on the second planarization layer 118. The OLED may include a pixel electrode 510, an intermediate layer 520 including an emission layer, and a counter electrode 530.

[0161] The pixel electrode 510 can be a (semi-)transparent electrode or a reflective electrode. For example, the pixel electrode 510 may include a reflective layer comprising at least one selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and their compounds or mixtures thereof, and a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of ITO, IZO, zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, the pixel electrode 510 may have a three-layer structure of ITO / Ag / ITO.

[0162] The pixel defining film 119 can be disposed on the second planarization layer 118 in a third direction (or z-axis direction). The pixel defining film 119 can increase the distance between the edge of the pixel electrode 510 and the counter electrode 530 above the pixel electrode 510, thereby preventing arcing or the like at the edge of the pixel electrode 510. The pixel defining film 119 can be formed using at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin by a method including spin coating.

[0163] At least a portion of the intermediate layer 520 of the organic light-emitting diode (OLED) can be located within an opening formed by the pixel defining film 119. The emission region of the OLED can be defined by the opening.

[0164] The intermediate layer 520 may include an emission layer. The emission layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may include low-molecular-weight or high-molecular-weight organic materials, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may optionally be disposed below and above the emission layer.

[0165] The emission layer may have a patterned shape corresponding to each of the pixel electrodes 510. The layers included in the intermediate layer 520, other than the emission layer, may be modified in various ways, such as being integrally formed on the multiple pixel electrodes 510.

[0166] The counter electrode 530 can be a transparent electrode or a reflective electrode. For example, the counter electrode 530 can be a transparent or translucent electrode and can include a metal thin film with low work function, comprising at least one of Li, Ca, LiF, Al, Ag, Mg and their compounds (such as LiF). The counter electrode 530 may also include a transparent conductive oxide (TCO) film located on the metal thin film and made of ITO, IZO, ZnO or In2O3. The counter electrode 530 can be integrally formed on the entire surface of the display area DA and disposed on the intermediate layer 520 and the pixel defining film 119.

[0167] So far, a description has been provided based on the construction of the first sub-pixel SP1, but this description can also be applied to the second sub-pixel SP2 and / or the third sub-pixel SP3.

[0168] The display device 10 according to an embodiment may include a horizontal power voltage line 210 and a vertical power voltage line 220. The horizontal power voltage line 210 is disposed in the display area DA, located in the lower metal layer 1100 or the upper metal layer 1200, and extends in a first direction (or the x-axis direction). The vertical power voltage line 220 is disposed in the display area DA, located in the third conductive layer 1600, and extends in a second direction (or the y-axis direction) intersecting the first direction (or the x-axis direction). For example, the horizontal power voltage line 210 and the vertical power voltage line 220 may be electrically connected to each other, such that the power voltage lines 200 form a grid pattern in the display area DA. The display device 10 may include a test line 30 disposed in the peripheral area PA, located in a different layer from the vertical power voltage line 220, in a layer closer to the substrate 100 than the layer in which the vertical power voltage line 220 is located, and extends in a second direction. For example, the test line 30 may be electrically connected to the horizontal power voltage line 210 to form a global grid pattern in the peripheral area PA. Test lines 30 are formed before the vertical power voltage lines 220 are formed. Therefore, the entire display area DA can be driven even before the vertical power voltage lines 220 are formed. Due to the test lines 30, defects in the pixel circuitry can be tested before the third conductive layer 1600 is formed.

[0169] Horizontal power voltage lines 210 are formed on a lower metal layer 1100 or an upper metal layer 1200 located below the semiconductor layer 1300. The horizontal power voltage lines 210 are formed before the semiconductor layer 1300, thereby allowing for free interconnect design. The semiconductor layer 1300 may comprise an oxide semiconductor material. Oxide semiconductors can be photosensitive, so the current and other quantities can vary due to external light. Therefore, with the metal layer located below the oxide semiconductor, the metal layer can absorb or reflect external light. For this purpose, capacitor electrodes are formed using the lower metal layer 1100 and the upper metal layer 1200, and the capacitor electrodes can be configured to be stacked with the semiconductor layer driving the transistor.

[0170] In the method of manufacturing the display device 10 according to the embodiment, in operation (a), a substrate including a display area DA and a peripheral area PA can be prepared. In operation (b), a horizontal power voltage line 210 disposed in the display area DA and extending in a first direction (or the x-axis direction) can be formed. Next, in operation (c), a test line 30 can be formed, disposed in the peripheral area PA, extending in a second direction (or the y-axis direction), and electrically connected to the horizontal power voltage line 210. Subsequently, in operation (d), a vertical power voltage line 220 can be formed, thereby manufacturing the display device 10. The vertical power voltage line 220 is disposed in the display area DA, located on a different layer from the horizontal power voltage line 210 and the test line 30, extending in the second direction (or the y-axis direction), and electrically connected to the horizontal power voltage line 210.

[0171] For example, operation (c) can be performed after operation (b). For example, if the horizontal power voltage line 210 and the test line 30 are located on different layers, and the horizontal power voltage line 210 is located on a layer closer to the substrate 100 than the test line 30, operation (c) can be performed after operation (b).

[0172] For example, operations (b) and (c) can be performed simultaneously. For example, if at least one of the horizontal power voltage line 210 and the test line 30 is located on the same layer, operations (b) and (c) can be performed simultaneously.

[0173] For example, operation (b) can be performed after operation (c). For example, if the horizontal power voltage line 210 and the test line 30 are located on different layers, and the test line 30 is located on a layer closer to the substrate 100 than at least one of the horizontal power voltage lines 210, operation (b) can be performed after operation (c).

[0174] according to Figures 4 to 12 In this embodiment, the test line 30 can be located in the first conductive layer 1400. For example, the test line 30 can be located in the gate layer.

[0175] Figures 13 to 16 This illustrates along another embodiment according to the disclosure. Figure 2 A schematic cross-sectional view of the display device shown, taken by the discontinuous line C-C'.

[0176] Test line 30 may be located on the same layer as at least one of the horizontal power voltage lines 210. For example, refer to Figure 13Test line 30, including a second power test line 302a, a first reference voltage test line 304a, a second reference voltage test line 305a, a first power test line 301a, and an initialization voltage test line 303a, can be located on the upper metal layer 1200. For example, test line 30 can be located on the same layer as the horizontal first power line 1250, write signal line 1220, horizontal first reference voltage line 1230, horizontal second power line 1270, and horizontal initialization voltage line 1260 located on the upper metal layer 1200. The second power test line 302a, the first reference voltage test line 304a, the second reference voltage test line 305a, the first power test line 301a, and the initialization voltage test line 303a can be connected to the second interconnect 312a, the fourth interconnect 314a, the fifth interconnect 315a, the first interconnect 311a, and the third interconnect 313a, respectively, through contact holes. (Refer to...) Figure 14 Test line 30, comprising a second power test line 302b, a first reference voltage test line 304b, a second reference voltage test line 305b, a first power test line 301b, and an initialization voltage test line 303b, can be located in the lower metal layer 1100. For example, test line 30 can be located in the same layer as the horizontal second reference voltage line 1110 located in the lower metal layer 1100. The second power test line 302b, the first reference voltage test line 304b, the second reference voltage test line 305b, the first power test line 301b, and the initialization voltage test line 303b can be connected to the second interconnect 312b, the fourth interconnect 314b, the fifth interconnect 315b, the first interconnect 311b, and the third interconnect 313b, respectively, via contact holes.

[0177] In another embodiment, the test lead 30 may be located directly below the vertical power voltage line 220, with an insulation layer placed therebetween. For example, see reference... Figure 15 Test line 30, including second power test line 302d, first reference voltage test line 304d, second reference voltage test line 305d, first power test line 301d, and initialization voltage test line 303d, can be located in the second conductive layer 1500. For example, test line 30 can be located in the same layer as data lines and source / drain electrodes of transistors.

[0178] As described above, the test lead 30 may include multiple test leads 30 connected to correspond to each of the multiple horizontal power voltage lines 210. Figures 12 to 15 As shown, multiple test lines 30 can be located on the same layer. However, the disclosure is not limited to this, and as... Figure 16As shown, multiple test lines 30, including a second power test line 302c, a first reference voltage test line 304c, a second reference voltage test line 305c, a first power test line 301c, and an initialization voltage test line 303c, can be located on different layers. For example, referring to... Figure 16 The second power test line 302c can be located on the upper metal layer 1200, the first reference voltage test line 304c can be located on the first conductive layer 1400, the second reference voltage test line 305c can be located on the lower metal layer 1100, the first power test line 301c can be located on the first conductive layer 1400, and the initialization voltage test line 303c can be located on the upper metal layer 1200. The second power test line 302c, the first reference voltage test line 304c, the second reference voltage test line 305c, the first power test line 301c, and the initialization voltage test line 303c can be connected to the second interconnecting member 312c, the fourth interconnecting member 314c, the fifth interconnecting member 315c, the first interconnecting member 311c, and the third interconnecting member 313c respectively through contact holes. However... Figure 16 It can be an example, and it can be modified and made public in various ways.

[0179] Figure 17 This is a schematic block diagram illustrating a display system 1000 according to a disclosed embodiment, and Figure 18 This is a schematic diagram illustrating an example of a smartwatch 2000 including a display device according to a disclosed embodiment. (See also...) Figure 17 The display system 1000 may include a processor 1010 and a display device 1020.

[0180] The processor 1010 can perform various tasks and calculations. The processor 1010 may include an application processor, graphics processor, microprocessor, and central processing unit (CPU), etc. The processor 1010 can be electrically connected to other components of the display system 1000 via a bus system to control these other components.

[0181] The processor 1010 can transmit image data IMG and control signal CTRL to the display device 1020. The display device 1020 can display an image based on the image data IMG and control signal CTRL. The display device 1020 can be compared with a reference... Figure 1 The described display device 10 is constructed similarly.

[0182] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation devices (or navigation systems), and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0183] Reference Figure 18 , Figure 17 The display system 1000 can be applied to a smartwatch 2000, which includes a display unit 2100 and a belt unit 2200.

[0184] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 can have a structure in which the strap unit 2200 is mounted on the user's wrist. Here, the display system 1000 and / or display device 1020 can be applied to the display unit 2100, and image data including time information can be provided to the user.

[0185] Each of the above embodiments can be implemented independently, but the structure of each embodiment can be combined and applied to other embodiments.

[0186] Although the disclosure has been described with reference to the embodiments shown in the accompanying drawings, it is merely illustrative. It will be understood that various equivalent modifications and variations can be made to the embodiments by those skilled in the art without departing from the spirit and scope of the disclosure. Therefore, the true scope of protection of the disclosure should be determined by the technical spirit of the appended claims.

[0187] The specific implementations described in the embodiments are examples and do not limit the scope of the embodiments in any way. Furthermore, unless specifically mentioned as "necessary," "important," etc., they may not be essential components of the publicly disclosed application.

[0188] In the description of the embodiments (particularly in the claims), the use of the term "the (described)" and similar descriptive terms may correspond to both singular and plural. Where a scope is described in the embodiments, since it includes the disclosure of individual values ​​belonging to that scope, it is identical to the description of the individual values ​​constituting the scope in the detailed description, unless otherwise stated. Finally, in the absence of an explicit or contradictory description of the operations constituting the method according to the embodiments, the operations may be performed in a suitable order. The embodiments are not necessarily limited to the order in which the operations are described. The use of all example or exemplary terms in the embodiments is merely for the purpose of describing the embodiments in detail. Therefore, the scope of the embodiments may not be limited by example or exemplary terms, unless limited by the claims. Furthermore, those skilled in the art will recognize that various modifications, combinations, and changes can be constructed within the scope of the appended claims or their equivalents, depending on design conditions and factors.

[0189] The display device according to the disclosed embodiments can provide a display device with good quality. The scope of the disclosure is not limited by its effects.

[0190] It should be understood that the embodiments described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device comprising: a substrate including a display region and a peripheral region around the display region, the display region including a subpixel; a horizontal power voltage line provided in the display region and extending in a first direction; a vertical power voltage line provided in the display region, located at a different layer from the horizontal power voltage line, extending in a second direction intersecting the first direction, and electrically connected to the horizontal power voltage line; and a test line provided in the peripheral region, located at a different layer from the vertical power voltage line, positioned closer to the substrate than the vertical power voltage line, extending in the second direction, and electrically connected to the horizontal power voltage line.

2. The display device according to claim 1, further comprising a semiconductor layer over an insulating layer covering at least one of the horizontal power voltage lines. The semiconductor layer includes an oxide semiconductor material.

3. The display device of claim 2, wherein, The test line is over an insulating layer covering the semiconductor layer.

4. The display device of claim 2, wherein, The subpixel includes a transistor, and 5. The display device of claim 4, wherein, The test line and a gate electrode of the transistor are formed in the same layer. At least one of the horizontal power voltage lines and the test line are in the same layer.

6. The display device of claim 1, wherein, The subpixel includes a capacitor, and 7. The display device of claim 6, wherein, The test line and an electrode of the capacitor are in the same layer. The vertical power voltage line is over an insulating layer covering the test line.

8. The display device of claim 1, wherein, The subpixel includes a transistor, and 9. The display device of claim 8, wherein, The test line and a source electrode and a drain electrode of the transistor are in the same layer. The test line includes a plurality of test lines, the horizontal power voltage line includes a plurality of horizontal power voltage lines, each of the plurality of test lines is electrically connected to a corresponding horizontal power voltage line among the plurality of horizontal power voltage lines, and 10. The display device of claim 1, wherein, The plurality of test lines are in the same layer. The test line includes a plurality of test lines, the horizontal power voltage line includes a plurality of horizontal power voltage lines, each of the plurality of test lines is electrically connected to a corresponding horizontal power voltage line among the plurality of horizontal power voltage lines, and 11. The display device of claim 1, wherein, The plurality of test lines are in different layers. The test line is electrically connected to the horizontal power voltage line by a connection interconnect.

12. The display device of claim 1, wherein, The subpixel includes a transistor, 13. The display device of claim 1, wherein, The horizontal power voltage line includes a horizontal first power line electrically connected to the transistor and extending in the first direction, The vertical power voltage line includes a vertical first power line crossing the subpixel in the second direction and electrically connected to the horizontal first power line, and The test line includes a first power test line electrically connected to the horizontal first power line. The horizontal power voltage line includes a horizontal second power line crossing the subpixel and extending in the first direction, 14. The display device of claim 1, wherein, The vertical power voltage line includes a vertical second power line crossing another subpixel of a pixel including the subpixel in the second direction, and electrically connected to the horizontal second power line, The horizontal second power line and the vertical second power line are electrically connected to a display element, and The test line includes a first power test line electrically connected to the horizontal first power line. The test line includes a second power test line electrically connected to the horizontal second power line.

15. A method of manufacturing a display device, the method comprising the steps of: preparing a substrate including a display region and a peripheral region outside the display region, the display region including sub-pixels; forming horizontal power voltage lines provided in the display region and extending in a first direction; forming a test line provided in the peripheral region, extending in a second direction intersecting the first direction, and electrically connected to the horizontal power voltage lines; and forming vertical power voltage lines provided in the display region, located in different layers from the horizontal power voltage lines and the test line, extending in the second direction, and electrically connected to the horizontal power voltage lines.

16. The method of claim 15, wherein, At least one of the horizontal power voltage lines and the test line are formed in the same layer.

17. The method of claim 15, further comprising the step of: After the step of forming the horizontal power voltage lines, a semiconductor layer is formed on an insulating layer covering at least one of the horizontal power voltage lines, wherein the test line is located on an insulating layer covering the semiconductor layer.

18. The method of claim 15, wherein, The step of forming the vertical power voltage lines includes forming an insulating layer covering the test line, and forming the vertical power voltage lines on the insulating layer.

19. An electronic device, the electronic device comprising: a display device, wherein the display device comprises: a substrate including a display region and a peripheral region outside the display region, the display region including sub-pixels; horizontal power voltage lines provided in the display region and extending in a first direction; vertical power voltage lines provided in the display region, located in different layers from the horizontal power voltage lines, extending in a second direction intersecting the first direction, and electrically connected to the horizontal power voltage lines; and a test line provided in the peripheral region, located in different layers from the vertical power voltage lines, positioned closer to the substrate than the vertical power voltage lines, extending in the second direction, and electrically connected to the horizontal power voltage lines.

20. The electronic device of claim 19, wherein, The electronic device is at least one of a smart watch, a mobile phone, a smartphone, a portable computer, a tablet personal computer, a watch phone, a car display, smart glasses, a portable multimedia player, a navigation system, an ultra-mobile computer, a head-mounted display device, a virtual reality device, a mixed reality device, and an augmented reality device.

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